PPC32 ARM ASM SHA-256: SPE impl, tidy up original

Implement using SPE instructions that allow for 64-bit registers as a
vector of 2 32-bit values.
Tidy up original implementation to not use stack.

configure.ac

@@ -3564,6 +3564,9 @@ then
       small)
         ENABLED_PPC32_ASM_SMALL=yes
         ;;
+      spe)
+        ENABLED_PPC32_ASM_SPE=yes
+        ;;
       *)
         AC_MSG_ERROR([Invalid RISC-V option [yes,inline,small]: $ENABLED_PPC32_ASM.])
         break
@@ -3584,6 +3587,10 @@ if test "$ENABLED_PPC32_ASM_SMALL" = "yes"; then
     AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_SMALL"
     AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM_SMALL"
 fi
+if test "$ENABLED_PPC32_ASM_SPE" = "yes"; then
+    AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_SPE"
+    AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM_SPE"
+fi
 
 # Xilinx hardened crypto
 AC_ARG_ENABLE([xilinx],