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SP ARM 32: Fixes to get building for armv7-a

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Change ldrd to either have even first register or change over to ldm
with even first register.
Ensure shift value in ORR instruction has a hash before it.
Don't index loads and stores by 256 or more - make them post-index.
div2 for P521 simplified.
This commit is contained in:
Sean Parkinson
2022-05-20 12:15:58 +10:00
parent 4a3ff40eb3
commit bc5262a5d0
2 changed files with 3750 additions and 5084 deletions
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2
configure.ac
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@ -6254,7 +6254,7 @@ do
;;
*)
AC_MSG_ERROR([Invalid choice of Single Precision length in bits [256, 2048, 3072]: $ENABLED_SP.])
AC_MSG_ERROR([Invalid choice of Single Precision length in bits [256, 384, 521, 1024, 2048, 3072, 4096]: $ENABLED_SP.])
break;;
esac
done

8832
wolfcrypt/src/sp_arm32.c
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