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Aarch64 ASM: missing push and pop of vector regs
Generated code wasn't pushing and poping vector registers when they were 64-bit. Generation code fixed and SHA-256 ASM code fixed.
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@@ -120,12 +120,14 @@ Transform_Sha256_Len_neon:
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.p2align 2
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_Transform_Sha256_Len_neon:
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#endif /* __APPLE__ */
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stp x29, x30, [sp, #-80]!
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stp x29, x30, [sp, #-112]!
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add x29, sp, #0
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stp x17, x19, [x29, #24]
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stp x20, x21, [x29, #40]
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stp x22, x23, [x29, #56]
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str x24, [x29, #72]
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stp d8, d9, [x29, #80]
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stp d10, d11, [x29, #96]
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#ifndef __APPLE__
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adrp x3, L_SHA256_transform_neon_len_k
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add x3, x3, :lo12:L_SHA256_transform_neon_len_k
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@@ -1089,7 +1091,9 @@ L_sha256_len_neon_start:
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ldp x20, x21, [x29, #40]
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ldp x22, x23, [x29, #56]
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ldr x24, [x29, #72]
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ldp x29, x30, [sp], #0x50
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ldp d8, d9, [x29, #80]
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ldp d10, d11, [x29, #96]
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ldp x29, x30, [sp], #0x70
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ret
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#ifndef __APPLE__
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.size Transform_Sha256_Len_neon,.-Transform_Sha256_Len_neon
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