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fix slli

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This commit is contained in:
Shawn Hoffman
2021-05-03 23:40:30 -07:00
committed by Sebastian Schmidt
parent 94c353ae9d
commit e4823d14bb
2 changed files with 6 additions and 3 deletions
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4
data/languages/xtensa.sinc
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@@ -169,6 +169,10 @@ s5_12.15_oex: tmp is u4_12.15 [ tmp = (2 << u4_12.15) * -1; ] { export *[c
n_s4_4.7_nozero: tmp is n_u4_4.7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; }
n_s4_4.7_nozero: tmp is n_u4_4.7 [ tmp = n_u4_4.7+0; ] { export *[const]:4 tmp; }
# imm stored in sa for slli is 32-shift.
# TODO why can't we use subtable output for this instead of repeating u5_4.7_20 calc?
u5_4.7_20_slli: tmp is u1_20 & u4_4.7 [ tmp = 32 - ((u1_20 << 4) | u4_4.7); ] { export *[const]:1 tmp; }
# B4CONST(ar) (Branch Immediate) encodings, pg. 41 f.
r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; }
r_b4const: tmp is ar = 1 [ tmp = 0x1; ] { export *[const]:4 tmp; }

5
data/languages/xtensaInstructions.sinc
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@@ -1090,9 +1090,8 @@ macro extract_bit(val, bit, result) {
}
# SLLI - Shift Left Logical Immediate, pg. 525.
:slli ar, as, u5_4.7_20 is u3_21.23 = 0 & u5_4.7_20 & op1 = 0b0001 & ar & as & op0 = 0 {
local sa:1 = 32 - u5_4.7_20;
ar = as << sa;
:slli ar, as, u5_4.7_20_slli is u3_21.23 = 0 & u5_4.7_20_slli & op1 = 0b0001 & ar & as & op0 = 0 {
ar = as << u5_4.7_20_slli;
}
# SRA - Shift Right Arithmetic, pg. 526.