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feat(etm): support etm on esp32-h4

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This commit is contained in:
laokaiyao
2025-06-09 15:28:02 +08:00
parent 3992f734bf
commit 026370e5b3
10 changed files with 341 additions and 727 deletions
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119
components/hal/esp32h4/include/hal/etm_ll.h Normal file
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@@ -0,0 +1,119 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task
/**
* @brief Enable the clock for ETM register
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Reset the ETM register
*
* @param group_id Group ID
*/
static inline void etm_ll_reset_register(int group_id)
{
(void)group_id;
PCR.etm_conf.etm_rst_en = 1;
PCR.etm_conf.etm_rst_en = 0;
}
/**
* @brief Enable ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
*/
static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
hw->etm_ch_ena_ad0_set.val = 1 << chan;
} else {
hw->etm_ch_ena_ad1_set.val = 1 << (chan - 32);
}
}
/**
* @brief Disable ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
*/
static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
hw->etm_ch_ena_ad0_clr.val = 1 << chan;
} else {
hw->etm_ch_ena_ad1_clr.val = 1 << (chan - 32);
}
}
/**
* @brief Check whether the ETM channel is enabled or not
*
* @param hw ETM register base address
* @param chan Channel ID
* @return true if the channel is enabled, false otherwise
*/
static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
return hw->etm_ch_ena_ad0.val & (1 << chan);
} else {
return hw->etm_ch_ena_ad1.val & (1 << (chan - 32));
}
}
/**
* @brief Set the input event for the ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
* @param event Event ID
*/
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, etm_chn_evt_id, event);
}
/**
* @brief Set the output task for the ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
* @param task Task ID
*/
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, etm_chn_task_id, task);
}
#ifdef __cplusplus
}
#endif

136
components/hal/esp32h4/include/hal/gpio_etm_ll.h Normal file
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@@ -0,0 +1,136 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/gpio_ext_struct.h"
#include "soc/soc_etm_source.h"
#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch))
#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch))
#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch))
#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8
#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set which GPIO to be bound to the event channel
*
* @note Different channels can be bound to one GPIO
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @param gpio_num GPIO number
*/
static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
{
dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel = gpio_num;
}
/**
* @brief Whether to enable the event channel
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
{
dev->etm_event_chn_cfg[chan].ext_etm_chn_event_en = enable;
}
/**
* @brief Get which GPIO is bound to the event channel
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @return GPIO number
*/
static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
{
return dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel;
}
/**
* @brief Set which GPIO to be bound to the task channel
*
* @note One channel can be bound to multiple different GPIOs
*
* @param dev Register base address
* @param chan GPIO ETM Task channel number
* @param gpio_num GPIO number
*/
static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x07 << (g_idx * 6));
reg_val |= ((chan & 0x07) << (g_idx * 6));
dev->etm_task_pn_cfg[g_p].val = reg_val;
}
/**
* @brief Whether to enable the GPIO to be managed by the task channel
*
* @param dev Register base address
* @param gpio_num GPIO number
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x01 << (g_idx * 6 + 5));
reg_val |= ((enable & 0x01) << (g_idx * 6 + 5));
dev->etm_task_pn_cfg[g_p].val = reg_val;
}
/**
* @brief Check whether a GPIO has been enabled and managed by a task channel
*
* @param dev Register base address
* @param gpio_num GPIO number
* @return True if enabled, false otherwise
*/
static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5));
}
/**
* @brief Get the channel number that the GPIO is bound to
*
* @param dev Register base address
* @param gpio_num GPIO number
* @return GPIO ETM Task channel number
*/
static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07;
}
#ifdef __cplusplus
}
#endif

10
components/soc/esp32h4/etm_periph.c Normal file
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@@ -0,0 +1,10 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
// TODO: [ESP32H4] IDF-12356 Support sleep retention

40
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
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@@ -19,6 +19,10 @@ config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_ETM_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -203,6 +207,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 5
config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
@@ -211,6 +219,14 @@ config SOC_AHB_GDMA_SUPPORT_PSRAM
bool
default y
config SOC_ETM_GROUPS
int
default 1
config SOC_ETM_CHANNELS_PER_GROUP
int
default 50
config SOC_GPIO_PORT
int
default 1
@@ -227,6 +243,18 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 39
config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_ETM_EVENTS_PER_GROUP
int
default 8
config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
@@ -303,6 +331,10 @@ config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_ETM_SYNC
bool
default y
@@ -467,6 +499,14 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_SYSTIMER_SUPPORT_ETM
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_TIMER_SUPPORT_SLEEP_RETENTION
bool
default y

20
components/soc/esp32h4/include/soc/soc_caps.h
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@@ -41,7 +41,7 @@
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12338
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12352
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12355
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
@@ -191,13 +191,14 @@
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 5
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
/*-------------------------- ETM CAPS --------------------------------------*/
// #define SOC_ETM_GROUPS 1U // Number of ETM groups
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
#define SOC_ETM_GROUPS 1U // Number of ETM groups
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12356 Support sleep retention
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-H4 has 1 GPIO peripheral
@@ -212,9 +213,9 @@
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 // TODO: [ESP32H4] IDF-12391
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1 // TODO: [ESP32H4] IDF-12394
// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8
#define SOC_GPIO_SUPPORT_ETM 1
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has the full LP IO subsystem
// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
@@ -270,7 +271,7 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
// #define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_ETM_SYNC (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F96M (1)
@@ -438,7 +439,7 @@
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
@@ -446,6 +447,7 @@
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
// #define SOC_TIMER_SUPPORT_ETM (1) // TODO: [ESP32H4] IDF-12355
#define SOC_TIMER_SUPPORT_ETM (1)
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/

1
components/soc/esp32h4/ld/esp32h4.peripherals.ld
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@@ -43,6 +43,7 @@ PROVIDE ( TIMERG1 = 0x60091000 );
PROVIDE ( IO_MUX = 0x60092000 );
PROVIDE ( GPIO = 0x60093000 );
PROVIDE ( GPIO_EXT = 0x60093E00 );
PROVIDE ( GPIO_ETM = 0x60093F18 );
PROVIDE ( PCR = 0x60094000 );
PROVIDE ( SPIMEM0 = 0x60098000 );
PROVIDE ( SPIMEM1 = 0x60099000 );

622
components/soc/esp32h4/register/soc/gpio_ext_struct.h
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@@ -117,7 +117,7 @@ typedef union {
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of ext_etm_task_p0_cfg register
/** Type of ext_etm_task_pn_cfg register
* GPIO selection register 0 for ETM
*/
typedef union {
@@ -200,602 +200,7 @@ typedef union {
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p0_cfg_reg_t;
/** Type of ext_etm_task_p1_cfg register
* GPIO selection register 1 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO5.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio5_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO5 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio5_en:1;
/** ext_etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO6.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio6_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO6 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio6_en:1;
/** ext_etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO7.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio7_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO7 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio7_en:1;
/** ext_etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO8.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio8_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO8 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio8_en:1;
/** ext_etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO9.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio9_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO9 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio9_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p1_cfg_reg_t;
/** Type of ext_etm_task_p2_cfg register
* GPIO selection register 2 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO10.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio10_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO10 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio10_en:1;
/** ext_etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO11.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio11_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO11 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio11_en:1;
/** ext_etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO12.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio12_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO12 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio12_en:1;
/** ext_etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO13.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio13_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO13 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio13_en:1;
/** ext_etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO14.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio14_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO14 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio14_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p2_cfg_reg_t;
/** Type of ext_etm_task_p3_cfg register
* GPIO selection register 3 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO15.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio15_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO15 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio15_en:1;
/** ext_etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO16.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio16_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO16 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio16_en:1;
/** ext_etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO17.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio17_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO17 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio17_en:1;
/** ext_etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO18.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio18_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO18 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio18_en:1;
/** ext_etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO19.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio19_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO19 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio19_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p3_cfg_reg_t;
/** Type of ext_etm_task_p4_cfg register
* GPIO selection register 4 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO20.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio20_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO20 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio20_en:1;
/** ext_etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO21.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio21_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO21 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio21_en:1;
/** ext_etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO22.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio22_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO22 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio22_en:1;
/** ext_etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO23.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio23_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO23 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio23_en:1;
/** ext_etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO24.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio24_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO24 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio24_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p4_cfg_reg_t;
/** Type of ext_etm_task_p5_cfg register
* GPIO selection register 5 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO25.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio25_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO25 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio25_en:1;
/** ext_etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO26.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio26_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO26 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio26_en:1;
/** ext_etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO27.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio27_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO27 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio27_en:1;
/** ext_etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO28.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio28_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO28 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio28_en:1;
/** ext_etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO29.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio29_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio29_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO29 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio29_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p5_cfg_reg_t;
/** Type of ext_etm_task_p6_cfg register
* GPIO selection register 6 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio30_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO30.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio30_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio30_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO30 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio30_en:1;
/** ext_etm_task_gpio31_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO31.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio31_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio31_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO31 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio31_en:1;
/** ext_etm_task_gpio32_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO32.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio32_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio32_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO32 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio32_en:1;
/** ext_etm_task_gpio33_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO33.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio33_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio33_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO33 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio33_en:1;
/** ext_etm_task_gpio34_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO34.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio34_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio34_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO34 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio34_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p6_cfg_reg_t;
/** Type of ext_etm_task_p7_cfg register
* GPIO selection register 7 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio35_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO35.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio35_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio35_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO35 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio35_en:1;
/** ext_etm_task_gpio36_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO36.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio36_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio36_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO36 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio36_en:1;
/** ext_etm_task_gpio37_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO37.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio37_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio37_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO37 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio37_en:1;
/** ext_etm_task_gpio38_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO38.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio38_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio38_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO38 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio38_en:1;
/** ext_etm_task_gpio39_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO39.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio39_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio39_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO39 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio39_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p7_cfg_reg_t;
} gpio_ext_etm_task_pn_cfg_reg_t;
/** Group: Version Register */
@@ -813,6 +218,11 @@ typedef union {
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct gpio_etm_dev_t {
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[8];
} gpio_etm_dev_t;
typedef struct {
uint32_t reserved_000;
@@ -821,24 +231,16 @@ typedef struct {
uint32_t reserved_018[48];
volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8];
uint32_t reserved_0f8[8];
volatile gpio_ext_etm_event_chn_cfg_reg_t ext_etm_event_chn_cfg[8];
uint32_t reserved_138[8];
volatile gpio_ext_etm_task_p0_cfg_reg_t ext_etm_task_p0_cfg;
volatile gpio_ext_etm_task_p1_cfg_reg_t ext_etm_task_p1_cfg;
volatile gpio_ext_etm_task_p2_cfg_reg_t ext_etm_task_p2_cfg;
volatile gpio_ext_etm_task_p3_cfg_reg_t ext_etm_task_p3_cfg;
volatile gpio_ext_etm_task_p4_cfg_reg_t ext_etm_task_p4_cfg;
volatile gpio_ext_etm_task_p5_cfg_reg_t ext_etm_task_p5_cfg;
volatile gpio_ext_etm_task_p6_cfg_reg_t ext_etm_task_p6_cfg;
volatile gpio_ext_etm_task_p7_cfg_reg_t ext_etm_task_p7_cfg;
volatile gpio_etm_dev_t etm;
uint32_t reserved_178[33];
volatile gpio_ext_version_reg_t ext_version;
} gpio_dev_t;
} gpio_ext_dev_t;
extern gpio_dev_t GPIO_EXT;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x200, "Invalid size of gpio_dev_t structure");
_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus

4
components/soc/esp32h4/register/soc/i2s_struct.h
View File

@@ -829,7 +829,7 @@ typedef union {
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
* I2S signal data register
* I2S single data register
*/
typedef union {
struct {
@@ -839,7 +839,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */

112
components/soc/esp32h4/register/soc/soc_etm_struct.h
View File

@@ -5985,113 +5985,17 @@ typedef union {
} soc_etm_date_reg_t;
typedef struct {
typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad0_reg_t etm_ch_ena_ad0;
volatile soc_etm_ch_ena_ad0_set_reg_t etm_ch_ena_ad0_set;
volatile soc_etm_ch_ena_ad0_clr_reg_t etm_ch_ena_ad0_clr;
volatile soc_etm_ch_ena_ad1_reg_t etm_ch_ena_ad1;
volatile soc_etm_ch_ena_ad1_set_reg_t etm_ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t etm_ch_ena_ad1_clr;
volatile soc_etm_chn_evt_id_reg_t etm_ch0_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch0_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch1_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch1_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch2_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch2_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch3_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch3_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch4_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch4_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch5_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch5_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch6_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch6_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch7_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch7_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch8_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch8_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch9_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch9_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch10_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch10_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch11_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch11_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch12_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch12_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch13_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch13_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch14_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch14_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch15_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch15_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch16_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch16_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch17_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch17_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch18_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch18_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch19_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch19_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch20_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch20_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch21_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch21_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch22_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch22_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch23_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch23_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch24_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch24_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch25_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch25_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch26_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch26_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch27_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch27_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch28_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch28_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch29_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch29_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch30_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch30_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch31_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch31_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch32_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch32_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch33_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch33_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch34_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch34_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch35_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch35_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch36_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch36_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch37_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch37_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch38_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch38_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch39_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch39_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch40_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch40_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch41_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch41_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch42_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch42_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch43_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch43_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch44_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch44_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch45_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch45_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch46_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch46_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch47_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch47_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch48_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch48_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch49_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch49_task_id;
volatile struct {
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_evt_st0_reg_t etm_evt_st0;
volatile soc_etm_evt_st0_clr_reg_t etm_evt_st0_clr;
volatile soc_etm_evt_st1_reg_t etm_evt_st1;
@@ -6120,12 +6024,12 @@ typedef struct {
volatile soc_etm_task_st5_clr_reg_t etm_task_st5_clr;
volatile soc_etm_clk_en_reg_t etm_clk_en;
volatile soc_etm_date_reg_t etm_date;
} soc_dev_t;
} soc_etm_dev_t;
extern soc_dev_t SOC_ETM;
extern soc_etm_dev_t SOC_ETM;
#ifndef __cplusplus
_Static_assert(sizeof(soc_dev_t) == 0x218, "Invalid size of soc_dev_t structure");
_Static_assert(sizeof(soc_etm_dev_t) == 0x218, "Invalid size of soc_etm_dev_t structure");
#endif
#ifdef __cplusplus

4
examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 |
| ----------------- | -------- | -------- | --------- | -------- | -------- | -------- |
# HC-SR04 Example based on GPTimer Capture and ETM