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feat(cache): supported cache panic driver on h21

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This commit is contained in:
armando
2025-05-14 11:36:50 +08:00
parent acda9a7a7e
commit 0c6aeecde4
2 changed files with 22 additions and 7 deletions
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11
components/esp_system/port/soc/esp32h21/cache_err_int.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -19,8 +19,6 @@
#include "hal/cache_ll.h" #include "hal/cache_ll.h"
#include "esp_private/cache_err_int.h" #include "esp_private/cache_err_int.h"
// TODO: [ESP32H21] IDF-11524
static const char *TAG = "CACHE_ERR"; static const char *TAG = "CACHE_ERR";
const char cache_error_msg[] = "Cache access error"; const char cache_error_msg[] = "Cache access error";
@ -64,6 +62,13 @@ void esp_cache_err_int_init(void)
esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/**
* Here we
* 1. enable the cache fail tracer to take cache error interrupt into effect.
* 2. clear potential cache error interrupt raw bits
* 3. enable cache error interrupt en bits
*/
cache_ll_l1_enable_fail_tracer(0, true);
/* On the hardware side, start by clearing all the bits responsible for cache access error */ /* On the hardware side, start by clearing all the bits responsible for cache access error */
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Then enable cache access error interrupts. */ /* Then enable cache access error interrupts. */

18
components/hal/esp32h21/include/hal/cache_ll.h
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@ -273,6 +273,17 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
return valid; return valid;
} }
/**
* Enable the Cache fail tracer
*
* @param cache_id cache ID
* @param en enable / disable
*/
static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
{
CACHE.trace_ena.l1_cache_trace_ena = en;
}
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Interrupt * Interrupt
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
@ -284,7 +295,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
*/ */
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
{ {
//TODO: [ESP32H21] IDF-11525 CACHE.l1_cache_acs_fail_int_ena.val |= mask;
} }
/** /**
@ -295,7 +306,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3
*/ */
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
{ {
//TODO: [ESP32H21] IDF-11525 CACHE.l1_cache_acs_fail_int_clr.val = mask;
} }
/** /**
@ -308,8 +319,7 @@ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32
*/ */
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
{ {
//TODO: [ESP32H21] IDF-11525 return CACHE.l1_cache_acs_fail_int_st.val & mask;
return 0;
} }
#ifdef __cplusplus #ifdef __cplusplus