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Merge branch 'feature/add_esp32c5_beta3_soc_header_files' into 'master'
feat(esp32c5): add esp32c5 soc header files (stage 2, part 1) See merge request espressif/esp-idf!27492
This commit is contained in:
Kevin (Lao Kaiyao)
813
components/soc/esp32c5/include/soc/apb_saradc_reg.h
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813
components/soc/esp32c5/include/soc/apb_saradc_reg.h
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@@ -0,0 +1,813 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** APB_SARADC_CTRL_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0)
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/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
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* select software enable saradc sample
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*/
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#define APB_SARADC_SARADC_START_FORCE (BIT(0))
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#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
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#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
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#define APB_SARADC_SARADC_START_FORCE_S 0
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/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
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* software enable saradc sample
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*/
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#define APB_SARADC_SARADC_START (BIT(1))
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#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
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#define APB_SARADC_SARADC_START_V 0x00000001U
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#define APB_SARADC_SARADC_START_S 1
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/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
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* SAR clock gated
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*/
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#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
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#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
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#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
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#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
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/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
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* SAR clock divider
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*/
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#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
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#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
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#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
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#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
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/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
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* 0 ~ 15 means length 1 ~ 16
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*/
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#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
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#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
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#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
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#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
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/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
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* clear the pointer of pattern table for DIG ADC1 CTRL
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*/
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#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
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#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
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#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
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#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
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/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
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* force option to xpd sar blocks
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*/
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#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
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#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
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#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
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#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
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/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
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* enable saradc2 power detect driven func.
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*/
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#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
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#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
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#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
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#define APB_SARADC_SARADC2_PWDET_DRV_S 29
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/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
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* wait arbit signal stable after sar_done
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*/
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#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
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#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
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#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
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#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
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/** APB_SARADC_CTRL2_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4)
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/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
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* enable max meas num
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*/
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#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
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#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
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#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
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#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
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/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
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* max conversion number
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*/
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#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
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#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
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#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
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#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
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/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
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* 1: data to DIG ADC1 CTRL is inverted, otherwise not
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*/
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#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
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#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
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#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
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#define APB_SARADC_SARADC_SAR1_INV_S 9
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/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
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* 1: data to DIG ADC2 CTRL is inverted, otherwise not
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*/
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#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
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#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
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#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
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#define APB_SARADC_SARADC_SAR2_INV_S 10
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/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
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* to set saradc timer target
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*/
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#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
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#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
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#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
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#define APB_SARADC_SARADC_TIMER_TARGET_S 12
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/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
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* to enable saradc timer trigger
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*/
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#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
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#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
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#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
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#define APB_SARADC_SARADC_TIMER_EN_S 24
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/** APB_SARADC_FILTER_CTRL1_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8)
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/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
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* Factor of saradc filter1
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*/
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
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/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
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* Factor of saradc filter0
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*/
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
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#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
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/** APB_SARADC_SAR_PATT_TAB1_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18)
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/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
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* item 0 ~ 3 for pattern table 1 (each item one byte)
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*/
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#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
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#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
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#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
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#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
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/** APB_SARADC_SAR_PATT_TAB2_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c)
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/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
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* Item 4 ~ 7 for pattern table 1 (each item one byte)
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*/
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#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
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#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
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#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
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#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
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/** APB_SARADC_ONETIME_SAMPLE_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20)
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/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
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* configure onetime atten
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*/
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#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
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#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
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#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
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#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
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/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
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* configure onetime channel
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*/
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#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
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#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
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#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
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#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
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/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
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* trigger adc onetime sample
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*/
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#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
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#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
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#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
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#define APB_SARADC_SARADC_ONETIME_START_S 29
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/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
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* enable adc2 onetime sample
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*/
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#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
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#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
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#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
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#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
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/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
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* enable adc1 onetime sample
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*/
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#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
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#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
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#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
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#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
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/** APB_SARADC_ARB_CTRL_REG register
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* digital saradc configure register
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*/
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#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24)
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/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
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* adc2 arbiter force to enableapb controller
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*/
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#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
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#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
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#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
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#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
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/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
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* adc2 arbiter force to enable rtc controller
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*/
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#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
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#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
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#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
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#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
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/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
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* adc2 arbiter force to enable wifi controller
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*/
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#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
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#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
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#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
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#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
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/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
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* adc2 arbiter force grant
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*/
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#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
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#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
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#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
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#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
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/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
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* Set adc2 arbiterapb priority
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*/
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#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
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#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
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#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
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#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
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/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
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* Set adc2 arbiter rtc priority
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*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
|
||||
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
|
||||
* Set adc2 arbiter wifi priority
|
||||
*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
|
||||
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
|
||||
* adc2 arbiter uses fixed priority
|
||||
*/
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
|
||||
|
||||
/** APB_SARADC_FILTER_CTRL0_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28)
|
||||
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
|
||||
* configure filter1 to adc channel
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
|
||||
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
|
||||
* configure filter0 to adc channel
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
|
||||
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc1_filter
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
|
||||
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
|
||||
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
|
||||
|
||||
/** APB_SARADC_SAR1DATA_STATUS_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c)
|
||||
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc1 data
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
|
||||
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
|
||||
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
|
||||
#define APB_SARADC_APB_SARADC1_DATA_S 0
|
||||
|
||||
/** APB_SARADC_SAR2DATA_STATUS_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30)
|
||||
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc2 data
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
|
||||
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
|
||||
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
|
||||
#define APB_SARADC_APB_SARADC2_DATA_S 0
|
||||
|
||||
/** APB_SARADC_THRES0_CTRL_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34)
|
||||
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres0 to adc channel
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
|
||||
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
|
||||
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
|
||||
|
||||
/** APB_SARADC_THRES1_CTRL_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38)
|
||||
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres1 to adc channel
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
|
||||
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
|
||||
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
|
||||
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
|
||||
|
||||
/** APB_SARADC_THRES_CTRL_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c)
|
||||
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* enable thres to all channel
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
|
||||
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
|
||||
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
|
||||
* enable thres1
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
|
||||
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
|
||||
* enable thres0
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
|
||||
|
||||
/** APB_SARADC_INT_ENA_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40)
|
||||
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
|
||||
* tsens low interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
|
||||
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
|
||||
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
|
||||
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
|
||||
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
|
||||
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
|
||||
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt enable
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
|
||||
|
||||
/** APB_SARADC_INT_RAW_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44)
|
||||
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
|
||||
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
|
||||
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
|
||||
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
|
||||
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
|
||||
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
|
||||
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt raw
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
|
||||
|
||||
/** APB_SARADC_INT_ST_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48)
|
||||
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
|
||||
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
|
||||
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
|
||||
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
|
||||
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
|
||||
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
|
||||
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt state
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
|
||||
|
||||
/** APB_SARADC_INT_CLR_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c)
|
||||
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
|
||||
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
|
||||
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
|
||||
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
|
||||
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
|
||||
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
|
||||
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt clear
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
|
||||
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
|
||||
|
||||
/** APB_SARADC_DMA_CONF_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50)
|
||||
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
|
||||
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
|
||||
*/
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
|
||||
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
|
||||
* reset_apb_adc_state
|
||||
*/
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
|
||||
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc use spi_dma
|
||||
*/
|
||||
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
|
||||
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
|
||||
#define APB_SARADC_APB_ADC_TRANS_S 31
|
||||
|
||||
/** APB_SARADC_CLKM_CONF_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54)
|
||||
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
|
||||
* Integral I2S clock divider value
|
||||
*/
|
||||
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
|
||||
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
|
||||
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
|
||||
#define APB_SARADC_CLKM_DIV_NUM_S 0
|
||||
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
|
||||
* Fractional clock divider numerator value
|
||||
*/
|
||||
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
|
||||
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
|
||||
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
|
||||
#define APB_SARADC_CLKM_DIV_B_S 8
|
||||
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
|
||||
* Fractional clock divider denominator value
|
||||
*/
|
||||
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
|
||||
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
|
||||
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
|
||||
#define APB_SARADC_CLKM_DIV_A_S 14
|
||||
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
|
||||
* reg clk en
|
||||
*/
|
||||
#define APB_SARADC_CLK_EN (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
|
||||
#define APB_SARADC_CLK_EN_V 0x00000001U
|
||||
#define APB_SARADC_CLK_EN_S 20
|
||||
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
|
||||
* Set this bit to enable clk_apll
|
||||
*/
|
||||
#define APB_SARADC_CLK_SEL 0x00000003U
|
||||
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
|
||||
#define APB_SARADC_CLK_SEL_V 0x00000003U
|
||||
#define APB_SARADC_CLK_SEL_S 21
|
||||
|
||||
/** APB_SARADC_APB_TSENS_CTRL_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58)
|
||||
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
|
||||
* temperature sensor data out
|
||||
*/
|
||||
#define APB_SARADC_TSENS_OUT 0x000000FFU
|
||||
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
|
||||
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
|
||||
#define APB_SARADC_TSENS_OUT_S 0
|
||||
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
|
||||
* invert temperature sensor data
|
||||
*/
|
||||
#define APB_SARADC_TSENS_IN_INV (BIT(13))
|
||||
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
|
||||
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
|
||||
#define APB_SARADC_TSENS_IN_INV_S 13
|
||||
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
|
||||
* temperature sensor clock divider
|
||||
*/
|
||||
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
|
||||
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
|
||||
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
|
||||
#define APB_SARADC_TSENS_CLK_DIV_S 14
|
||||
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
|
||||
* temperature sensor power up
|
||||
*/
|
||||
#define APB_SARADC_TSENS_PU (BIT(22))
|
||||
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
|
||||
#define APB_SARADC_TSENS_PU_V 0x00000001U
|
||||
#define APB_SARADC_TSENS_PU_S 22
|
||||
|
||||
/** APB_SARADC_TSENS_CTRL2_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c)
|
||||
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
|
||||
* tsens clk select
|
||||
*/
|
||||
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
|
||||
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
|
||||
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
|
||||
#define APB_SARADC_TSENS_CLK_SEL_S 15
|
||||
|
||||
/** APB_SARADC_CALI_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60)
|
||||
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
|
||||
* saradc cali factor
|
||||
*/
|
||||
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
|
||||
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
|
||||
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
|
||||
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
|
||||
|
||||
/** APB_TSENS_WAKE_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64)
|
||||
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
|
||||
* reg_wakeup_th_low
|
||||
*/
|
||||
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
|
||||
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
|
||||
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
|
||||
#define APB_SARADC_WAKEUP_TH_LOW_S 0
|
||||
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
|
||||
* reg_wakeup_th_high
|
||||
*/
|
||||
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
|
||||
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
|
||||
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
|
||||
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
|
||||
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
|
||||
* reg_wakeup_over_upper_th
|
||||
*/
|
||||
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
|
||||
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
|
||||
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
|
||||
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
|
||||
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
|
||||
* reg_wakeup_mode
|
||||
*/
|
||||
#define APB_SARADC_WAKEUP_MODE (BIT(17))
|
||||
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
|
||||
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
|
||||
#define APB_SARADC_WAKEUP_MODE_S 17
|
||||
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
|
||||
* reg_wakeup_en
|
||||
*/
|
||||
#define APB_SARADC_WAKEUP_EN (BIT(18))
|
||||
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
|
||||
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
|
||||
#define APB_SARADC_WAKEUP_EN_S 18
|
||||
|
||||
/** APB_TSENS_SAMPLE_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68)
|
||||
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
|
||||
* HW sample rate
|
||||
*/
|
||||
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
|
||||
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
|
||||
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
|
||||
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
|
||||
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
|
||||
* HW sample en
|
||||
*/
|
||||
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
|
||||
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
|
||||
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
|
||||
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
|
||||
|
||||
/** APB_SARADC_CTRL_DATE_REG register
|
||||
* version
|
||||
*/
|
||||
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc)
|
||||
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
|
||||
* version
|
||||
*/
|
||||
#define APB_SARADC_DATE 0xFFFFFFFFU
|
||||
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
|
||||
#define APB_SARADC_DATE_V 0xFFFFFFFFU
|
||||
#define APB_SARADC_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
696
components/soc/esp32c5/include/soc/apb_saradc_struct.h
Normal file
696
components/soc/esp32c5/include/soc/apb_saradc_struct.h
Normal file
@@ -0,0 +1,696 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configure Register */
|
||||
/** Type of saradc_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
|
||||
* select software enable saradc sample
|
||||
*/
|
||||
uint32_t saradc_saradc_start_force:1;
|
||||
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
|
||||
* software enable saradc sample
|
||||
*/
|
||||
uint32_t saradc_saradc_start:1;
|
||||
uint32_t reserved_2:4;
|
||||
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
|
||||
* SAR clock gated
|
||||
*/
|
||||
uint32_t saradc_saradc_sar_clk_gated:1;
|
||||
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
|
||||
* SAR clock divider
|
||||
*/
|
||||
uint32_t saradc_saradc_sar_clk_div:8;
|
||||
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
|
||||
* 0 ~ 15 means length 1 ~ 16
|
||||
*/
|
||||
uint32_t saradc_saradc_sar_patt_len:3;
|
||||
uint32_t reserved_18:5;
|
||||
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
|
||||
* clear the pointer of pattern table for DIG ADC1 CTRL
|
||||
*/
|
||||
uint32_t saradc_saradc_sar_patt_p_clear:1;
|
||||
uint32_t reserved_24:3;
|
||||
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
|
||||
* force option to xpd sar blocks
|
||||
*/
|
||||
uint32_t saradc_saradc_xpd_sar_force:2;
|
||||
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
|
||||
* enable saradc2 power detect driven func.
|
||||
*/
|
||||
uint32_t saradc_saradc2_pwdet_drv:1;
|
||||
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
|
||||
* wait arbit signal stable after sar_done
|
||||
*/
|
||||
uint32_t saradc_saradc_wait_arb_cycle:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_ctrl2 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
|
||||
* enable max meas num
|
||||
*/
|
||||
uint32_t saradc_saradc_meas_num_limit:1;
|
||||
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
|
||||
* max conversion number
|
||||
*/
|
||||
uint32_t saradc_saradc_max_meas_num:8;
|
||||
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
|
||||
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
|
||||
*/
|
||||
uint32_t saradc_saradc_sar1_inv:1;
|
||||
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
|
||||
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
|
||||
*/
|
||||
uint32_t saradc_saradc_sar2_inv:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
|
||||
* to set saradc timer target
|
||||
*/
|
||||
uint32_t saradc_saradc_timer_target:12;
|
||||
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
|
||||
* to enable saradc timer trigger
|
||||
*/
|
||||
uint32_t saradc_saradc_timer_en:1;
|
||||
uint32_t reserved_25:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_ctrl2_reg_t;
|
||||
|
||||
/** Type of saradc_filter_ctrl1 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:26;
|
||||
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
|
||||
* Factor of saradc filter1
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_filter_factor1:3;
|
||||
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
|
||||
* Factor of saradc filter0
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_filter_factor0:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_filter_ctrl1_reg_t;
|
||||
|
||||
/** Type of saradc_sar_patt_tab1 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
|
||||
* item 0 ~ 3 for pattern table 1 (each item one byte)
|
||||
*/
|
||||
uint32_t saradc_saradc_sar_patt_tab1:24;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_sar_patt_tab1_reg_t;
|
||||
|
||||
/** Type of saradc_sar_patt_tab2 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
|
||||
* Item 4 ~ 7 for pattern table 1 (each item one byte)
|
||||
*/
|
||||
uint32_t saradc_saradc_sar_patt_tab2:24;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_sar_patt_tab2_reg_t;
|
||||
|
||||
/** Type of saradc_onetime_sample register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:23;
|
||||
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
|
||||
* configure onetime atten
|
||||
*/
|
||||
uint32_t saradc_saradc_onetime_atten:2;
|
||||
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
|
||||
* configure onetime channel
|
||||
*/
|
||||
uint32_t saradc_saradc_onetime_channel:4;
|
||||
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
|
||||
* trigger adc onetime sample
|
||||
*/
|
||||
uint32_t saradc_saradc_onetime_start:1;
|
||||
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
|
||||
* enable adc2 onetime sample
|
||||
*/
|
||||
uint32_t saradc_saradc2_onetime_sample:1;
|
||||
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
|
||||
* enable adc1 onetime sample
|
||||
*/
|
||||
uint32_t saradc_saradc1_onetime_sample:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_onetime_sample_reg_t;
|
||||
|
||||
/** Type of saradc_arb_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:2;
|
||||
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
|
||||
* adc2 arbiter force to enableapb controller
|
||||
*/
|
||||
uint32_t saradc_adc_arb_apb_force:1;
|
||||
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
|
||||
* adc2 arbiter force to enable rtc controller
|
||||
*/
|
||||
uint32_t saradc_adc_arb_rtc_force:1;
|
||||
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
|
||||
* adc2 arbiter force to enable wifi controller
|
||||
*/
|
||||
uint32_t saradc_adc_arb_wifi_force:1;
|
||||
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
|
||||
* adc2 arbiter force grant
|
||||
*/
|
||||
uint32_t saradc_adc_arb_grant_force:1;
|
||||
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
|
||||
* Set adc2 arbiterapb priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_apb_priority:2;
|
||||
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
|
||||
* Set adc2 arbiter rtc priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_rtc_priority:2;
|
||||
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
|
||||
* Set adc2 arbiter wifi priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_wifi_priority:2;
|
||||
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
|
||||
* adc2 arbiter uses fixed priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_fix_priority:1;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_arb_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_filter_ctrl0 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:18;
|
||||
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
|
||||
* configure filter1 to adc channel
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_filter_channel1:4;
|
||||
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
|
||||
* configure filter0 to adc channel
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_filter_channel0:4;
|
||||
uint32_t reserved_26:5;
|
||||
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc1_filter
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_filter_reset:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_filter_ctrl0_reg_t;
|
||||
|
||||
/** Type of saradc_sar1data_status register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc1 data
|
||||
*/
|
||||
uint32_t saradc_apb_saradc1_data:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_sar1data_status_reg_t;
|
||||
|
||||
/** Type of saradc_sar2data_status register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc2 data
|
||||
*/
|
||||
uint32_t saradc_apb_saradc2_data:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_sar2data_status_reg_t;
|
||||
|
||||
/** Type of saradc_thres0_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres0 to adc channel
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_channel:4;
|
||||
uint32_t reserved_4:1;
|
||||
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_high:13;
|
||||
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_low:13;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_thres0_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_thres1_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres1 to adc channel
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_channel:4;
|
||||
uint32_t reserved_4:1;
|
||||
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_high:13;
|
||||
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_low:13;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_thres1_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_thres_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:27;
|
||||
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
|
||||
* enable thres to all channel
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres_all_en:1;
|
||||
uint32_t reserved_28:2;
|
||||
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
|
||||
* enable thres1
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_en:1;
|
||||
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
|
||||
* enable thres0
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_thres_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_int_ena register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
|
||||
* tsens low interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_tsens_int_ena:1;
|
||||
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
|
||||
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
|
||||
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
|
||||
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
|
||||
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc2_done_int_ena:1;
|
||||
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt enable
|
||||
*/
|
||||
uint32_t saradc_apb_saradc1_done_int_ena:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_int_ena_reg_t;
|
||||
|
||||
/** Type of saradc_int_raw register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_tsens_int_raw:1;
|
||||
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
|
||||
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
|
||||
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
|
||||
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
|
||||
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc2_done_int_raw:1;
|
||||
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt raw
|
||||
*/
|
||||
uint32_t saradc_apb_saradc1_done_int_raw:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_int_raw_reg_t;
|
||||
|
||||
/** Type of saradc_int_st register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_tsens_int_st:1;
|
||||
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
|
||||
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
|
||||
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
|
||||
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
|
||||
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc2_done_int_st:1;
|
||||
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt state
|
||||
*/
|
||||
uint32_t saradc_apb_saradc1_done_int_st:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_int_st_reg_t;
|
||||
|
||||
/** Type of saradc_int_clr register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_tsens_int_clr:1;
|
||||
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
|
||||
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
|
||||
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
|
||||
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
|
||||
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc2_done_int_clr:1;
|
||||
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt clear
|
||||
*/
|
||||
uint32_t saradc_apb_saradc1_done_int_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_int_clr_reg_t;
|
||||
|
||||
/** Type of saradc_dma_conf register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
|
||||
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
|
||||
*/
|
||||
uint32_t saradc_apb_adc_eof_num:16;
|
||||
uint32_t reserved_16:14;
|
||||
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
|
||||
* reset_apb_adc_state
|
||||
*/
|
||||
uint32_t saradc_apb_adc_reset_fsm:1;
|
||||
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc use spi_dma
|
||||
*/
|
||||
uint32_t saradc_apb_adc_trans:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_dma_conf_reg_t;
|
||||
|
||||
/** Type of saradc_clkm_conf register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
|
||||
* Integral I2S clock divider value
|
||||
*/
|
||||
uint32_t saradc_clkm_div_num:8;
|
||||
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
|
||||
* Fractional clock divider numerator value
|
||||
*/
|
||||
uint32_t saradc_clkm_div_b:6;
|
||||
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
|
||||
* Fractional clock divider denominator value
|
||||
*/
|
||||
uint32_t saradc_clkm_div_a:6;
|
||||
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
|
||||
* reg clk en
|
||||
*/
|
||||
uint32_t saradc_clk_en:1;
|
||||
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
|
||||
* Set this bit to enable clk_apll
|
||||
*/
|
||||
uint32_t saradc_clk_sel:2;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_clkm_conf_reg_t;
|
||||
|
||||
/** Type of saradc_apb_tsens_ctrl register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
|
||||
* temperature sensor data out
|
||||
*/
|
||||
uint32_t saradc_tsens_out:8;
|
||||
uint32_t reserved_8:5;
|
||||
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
|
||||
* invert temperature sensor data
|
||||
*/
|
||||
uint32_t saradc_tsens_in_inv:1;
|
||||
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
|
||||
* temperature sensor clock divider
|
||||
*/
|
||||
uint32_t saradc_tsens_clk_div:8;
|
||||
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
|
||||
* temperature sensor power up
|
||||
*/
|
||||
uint32_t saradc_tsens_pu:1;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_apb_tsens_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_tsens_ctrl2 register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:15;
|
||||
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
|
||||
* tsens clk select
|
||||
*/
|
||||
uint32_t saradc_tsens_clk_sel:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_tsens_ctrl2_reg_t;
|
||||
|
||||
/** Type of saradc_cali register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
|
||||
* saradc cali factor
|
||||
*/
|
||||
uint32_t saradc_apb_saradc_cali_cfg:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_cali_reg_t;
|
||||
|
||||
/** Type of tsens_wake register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
|
||||
* reg_wakeup_th_low
|
||||
*/
|
||||
uint32_t saradc_wakeup_th_low:8;
|
||||
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
|
||||
* reg_wakeup_th_high
|
||||
*/
|
||||
uint32_t saradc_wakeup_th_high:8;
|
||||
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
|
||||
* reg_wakeup_over_upper_th
|
||||
*/
|
||||
uint32_t saradc_wakeup_over_upper_th:1;
|
||||
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
|
||||
* reg_wakeup_mode
|
||||
*/
|
||||
uint32_t saradc_wakeup_mode:1;
|
||||
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
|
||||
* reg_wakeup_en
|
||||
*/
|
||||
uint32_t saradc_wakeup_en:1;
|
||||
uint32_t reserved_19:13;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_tsens_wake_reg_t;
|
||||
|
||||
/** Type of tsens_sample register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
|
||||
* HW sample rate
|
||||
*/
|
||||
uint32_t saradc_tsens_sample_rate:16;
|
||||
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
|
||||
* HW sample en
|
||||
*/
|
||||
uint32_t saradc_tsens_sample_en:1;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_tsens_sample_reg_t;
|
||||
|
||||
/** Type of saradc_ctrl_date register
|
||||
* version
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
|
||||
* version
|
||||
*/
|
||||
uint32_t saradc_date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc_ctrl_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
|
||||
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
|
||||
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
|
||||
uint32_t reserved_00c[3];
|
||||
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
|
||||
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
|
||||
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
|
||||
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
|
||||
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
|
||||
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
|
||||
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
|
||||
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
|
||||
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
|
||||
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
|
||||
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
|
||||
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
|
||||
volatile apb_saradc_int_st_reg_t saradc_int_st;
|
||||
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
|
||||
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
|
||||
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
|
||||
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
|
||||
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
|
||||
volatile apb_saradc_cali_reg_t saradc_cali;
|
||||
volatile apb_tsens_wake_reg_t tsens_wake;
|
||||
volatile apb_tsens_sample_reg_t tsens_sample;
|
||||
uint32_t reserved_06c[228];
|
||||
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
|
||||
} apb_dev_t;
|
||||
|
||||
extern apb_dev_t APB_SARADC;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
582
components/soc/esp32c5/include/soc/assist_debug_reg.h
Normal file
582
components/soc/esp32c5/include/soc/assist_debug_reg.h
Normal file
@@ -0,0 +1,582 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
|
||||
* core0 monitor enable configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
|
||||
* core0 monitor interrupt status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
|
||||
* core0 monitor interrupt enable register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt enable
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
|
||||
* core0 monitor interrupt clr register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt clr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
|
||||
* core0 dram0 region0 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 dram0 region0 start addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
|
||||
* core0 dram0 region0 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 dram0 region0 end addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
|
||||
* core0 dram0 region1 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 dram0 region1 start addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
|
||||
* core0 dram0 region1 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 dram0 region1 end addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
|
||||
* core0 PIF region0 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 PIF region0 start addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
|
||||
* core0 PIF region0 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 PIF region0 end addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
|
||||
* core0 PIF region1 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 PIF region1 start addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
|
||||
* core0 PIF region1 addr configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 PIF region1 end addr
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
|
||||
* core0 area pc status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* the stackpointer when first touch region monitor interrupt
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
|
||||
* core0 area sp status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
|
||||
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
|
||||
* the PC when first touch region monitor interrupt
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
|
||||
* stack min value
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
* core0 sp region configuration regsiter
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
|
||||
* stack max value
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* core0 sp pc status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
|
||||
* stack monitor pc status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* This regsiter stores the PC when trigger stack monitor.
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
|
||||
* record enable configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
|
||||
* Set 1 to enable record PC
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
|
||||
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
|
||||
* record status regsiter
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
|
||||
* recorded PC
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
|
||||
* record status regsiter
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
|
||||
* recorded sp
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
|
||||
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
|
||||
* cpu's lastpc before exception
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
|
||||
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
|
||||
* cpu debug mode status, 1 means cpu enter debug mode.
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
|
||||
* cpu debug_module active status
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
|
||||
/** ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
|
||||
* need desc
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_M (ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V << ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S)
|
||||
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CLOCK_GATE_REG register
|
||||
* clock register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c)
|
||||
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Set 1 force on the clock gate
|
||||
*/
|
||||
#define ASSIST_DEBUG_CLK_EN (BIT(0))
|
||||
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
|
||||
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CLK_EN_S 0
|
||||
|
||||
/** ASSIST_DEBUG_DATE_REG register
|
||||
* version register
|
||||
*/
|
||||
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
|
||||
/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35725648;
|
||||
* version register
|
||||
*/
|
||||
#define ASSIST_DEBUG_DATE 0x0FFFFFFFU
|
||||
#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
|
||||
#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
|
||||
#define ASSIST_DEBUG_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
548
components/soc/esp32c5/include/soc/assist_debug_struct.h
Normal file
548
components/soc/esp32c5/include/soc/assist_debug_struct.h
Normal file
@@ -0,0 +1,548 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: monitor configuration registers */
|
||||
/** Type of core_0_montr_ena register
|
||||
* core0 monitor enable configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_rd_ena:1;
|
||||
/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_wr_ena:1;
|
||||
/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_rd_ena:1;
|
||||
/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_wr_ena:1;
|
||||
/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_rd_ena:1;
|
||||
/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_wr_ena:1;
|
||||
/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_rd_ena:1;
|
||||
/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_wr_ena:1;
|
||||
/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor enable
|
||||
*/
|
||||
uint32_t core_0_sp_spill_min_ena:1;
|
||||
/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor enable
|
||||
*/
|
||||
uint32_t core_0_sp_spill_max_ena:1;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_montr_ena_reg_t;
|
||||
|
||||
/** Type of core_0_area_dram0_0_min register
|
||||
* core0 dram0 region0 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 dram0 region0 start addr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_min:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_dram0_0_min_reg_t;
|
||||
|
||||
/** Type of core_0_area_dram0_0_max register
|
||||
* core0 dram0 region0 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 dram0 region0 end addr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_dram0_0_max_reg_t;
|
||||
|
||||
/** Type of core_0_area_dram0_1_min register
|
||||
* core0 dram0 region1 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 dram0 region1 start addr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_min:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_dram0_1_min_reg_t;
|
||||
|
||||
/** Type of core_0_area_dram0_1_max register
|
||||
* core0 dram0 region1 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 dram0 region1 end addr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_dram0_1_max_reg_t;
|
||||
|
||||
/** Type of core_0_area_pif_0_min register
|
||||
* core0 PIF region0 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 PIF region0 start addr
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_min:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_pif_0_min_reg_t;
|
||||
|
||||
/** Type of core_0_area_pif_0_max register
|
||||
* core0 PIF region0 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 PIF region0 end addr
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_pif_0_max_reg_t;
|
||||
|
||||
/** Type of core_0_area_pif_1_min register
|
||||
* core0 PIF region1 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Core0 PIF region1 start addr
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_min:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_pif_1_min_reg_t;
|
||||
|
||||
/** Type of core_0_area_pif_1_max register
|
||||
* core0 PIF region1 addr configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
|
||||
* Core0 PIF region1 end addr
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_pif_1_max_reg_t;
|
||||
|
||||
/** Type of core_0_area_pc register
|
||||
* core0 area pc status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
|
||||
* the stackpointer when first touch region monitor interrupt
|
||||
*/
|
||||
uint32_t core_0_area_pc:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_pc_reg_t;
|
||||
|
||||
/** Type of core_0_area_sp register
|
||||
* core0 area sp status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
|
||||
* the PC when first touch region monitor interrupt
|
||||
*/
|
||||
uint32_t core_0_area_sp:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_area_sp_reg_t;
|
||||
|
||||
/** Type of core_0_sp_min register
|
||||
* stack min value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
|
||||
* core0 sp region configuration regsiter
|
||||
*/
|
||||
uint32_t core_0_sp_min:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_sp_min_reg_t;
|
||||
|
||||
/** Type of core_0_sp_max register
|
||||
* stack max value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* core0 sp pc status register
|
||||
*/
|
||||
uint32_t core_0_sp_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_sp_max_reg_t;
|
||||
|
||||
/** Type of core_0_sp_pc register
|
||||
* stack monitor pc status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
|
||||
* This regsiter stores the PC when trigger stack monitor.
|
||||
*/
|
||||
uint32_t core_0_sp_pc:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_sp_pc_reg_t;
|
||||
|
||||
|
||||
/** Group: interrupt configuration register */
|
||||
/** Type of core_0_intr_raw register
|
||||
* core0 monitor interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_rd_raw:1;
|
||||
/** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_wr_raw:1;
|
||||
/** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_rd_raw:1;
|
||||
/** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_wr_raw:1;
|
||||
/** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_rd_raw:1;
|
||||
/** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_wr_raw:1;
|
||||
/** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_rd_raw:1;
|
||||
/** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_wr_raw:1;
|
||||
/** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_sp_spill_min_raw:1;
|
||||
/** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt status
|
||||
*/
|
||||
uint32_t core_0_sp_spill_max_raw:1;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_intr_raw_reg_t;
|
||||
|
||||
/** Type of core_0_intr_ena register
|
||||
* core0 monitor interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_rd_intr_ena:1;
|
||||
/** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_wr_intr_ena:1;
|
||||
/** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_rd_intr_ena:1;
|
||||
/** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_wr_intr_ena:1;
|
||||
/** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_rd_intr_ena:1;
|
||||
/** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_wr_intr_ena:1;
|
||||
/** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_rd_intr_ena:1;
|
||||
/** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_wr_intr_ena:1;
|
||||
/** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_sp_spill_min_intr_ena:1;
|
||||
/** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_sp_spill_max_intr_ena:1;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_intr_ena_reg_t;
|
||||
|
||||
/** Type of core_0_intr_clr register
|
||||
* core0 monitor interrupt clr register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_rd_clr:1;
|
||||
/** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
|
||||
* Core0 dram0 area0 write monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_wr_clr:1;
|
||||
/** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
|
||||
* Core0 dram0 area1 read monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_rd_clr:1;
|
||||
/** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
|
||||
* Core0 dram0 area1 write monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_wr_clr:1;
|
||||
/** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
|
||||
* Core0 PIF area0 read monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_rd_clr:1;
|
||||
/** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
|
||||
* Core0 PIF area0 write monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_wr_clr:1;
|
||||
/** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_rd_clr:1;
|
||||
/** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_wr_clr:1;
|
||||
/** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_sp_spill_min_clr:1;
|
||||
/** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_sp_spill_max_clr:1;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_intr_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: pc reording configuration register */
|
||||
/** Type of core_0_rcd_en register
|
||||
* record enable configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
|
||||
* Set 1 to enable record PC
|
||||
*/
|
||||
uint32_t core_0_rcd_recorden:1;
|
||||
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
|
||||
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
|
||||
*/
|
||||
uint32_t core_0_rcd_pdebugen:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_rcd_en_reg_t;
|
||||
|
||||
|
||||
/** Group: pc reording status register */
|
||||
/** Type of core_0_rcd_pdebugpc register
|
||||
* record status regsiter
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
|
||||
* recorded PC
|
||||
*/
|
||||
uint32_t core_0_rcd_pdebugpc:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_rcd_pdebugpc_reg_t;
|
||||
|
||||
/** Type of core_0_rcd_pdebugsp register
|
||||
* record status regsiter
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
|
||||
* recorded sp
|
||||
*/
|
||||
uint32_t core_0_rcd_pdebugsp:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_rcd_pdebugsp_reg_t;
|
||||
|
||||
|
||||
/** Group: cpu status registers */
|
||||
/** Type of core_0_lastpc_before_exception register
|
||||
* cpu status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
|
||||
* cpu's lastpc before exception
|
||||
*/
|
||||
uint32_t core_0_lastpc_before_exc:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_lastpc_before_exception_reg_t;
|
||||
|
||||
/** Type of core_0_debug_mode register
|
||||
* cpu status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
|
||||
* cpu debug mode status, 1 means cpu enter debug mode.
|
||||
*/
|
||||
uint32_t core_0_debug_mode:1;
|
||||
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
|
||||
* cpu debug_module active status
|
||||
*/
|
||||
uint32_t core_0_debug_module_active:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_debug_mode_reg_t;
|
||||
|
||||
/** Type of core_0_dmactive_mode register
|
||||
* cpu status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dmactive_lpcore : RO; bitpos: [0]; default: 0;
|
||||
* need desc
|
||||
*/
|
||||
uint32_t core_0_dmactive_lpcore:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dmactive_mode_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration Registers */
|
||||
/** Type of clock_gate register
|
||||
* clock register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* Set 1 force on the clock gate
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_clock_gate_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* version register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 35725648;
|
||||
* version register
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
|
||||
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
|
||||
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
|
||||
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
|
||||
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
|
||||
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
|
||||
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
|
||||
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
|
||||
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
|
||||
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
|
||||
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
|
||||
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
|
||||
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
|
||||
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
|
||||
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
|
||||
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
|
||||
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
|
||||
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
|
||||
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
|
||||
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
|
||||
uint32_t reserved_050[8];
|
||||
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
|
||||
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
|
||||
volatile assist_debug_core_0_dmactive_mode_reg_t core_0_dmactive_mode;
|
||||
volatile assist_debug_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_080[223];
|
||||
volatile assist_debug_date_reg_t date;
|
||||
} assist_debug_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
481
components/soc/esp32c5/include/soc/bitscrambler_reg.h
Normal file
481
components/soc/esp32c5/include/soc/bitscrambler_reg.h
Normal file
@@ -0,0 +1,481 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** BITSCRAMBLER_TX_INST_CFG0_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
|
||||
/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
|
||||
* write this bits to specify the one of 8 instruction
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_INST_IDX 0x00000007U
|
||||
#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
|
||||
#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U
|
||||
#define BITSCRAMBLER_TX_INST_IDX_S 0
|
||||
/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
|
||||
* write this bits to specify the bit position of 257 bit instruction which in units
|
||||
* of 32 bits
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_INST_POS 0x0000000FU
|
||||
#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
|
||||
#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU
|
||||
#define BITSCRAMBLER_TX_INST_POS_S 3
|
||||
|
||||
/** BITSCRAMBLER_TX_INST_CFG1_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
|
||||
/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
|
||||
* write this bits to update instruction which specified by
|
||||
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
|
||||
* BITSCRAMBLER_TX_INST_CFG0_REG
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
|
||||
#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_TX_INST_S 0
|
||||
|
||||
/** BITSCRAMBLER_RX_INST_CFG0_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
|
||||
/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
|
||||
* write this bits to specify the one of 8 instruction
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_INST_IDX 0x00000007U
|
||||
#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
|
||||
#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U
|
||||
#define BITSCRAMBLER_RX_INST_IDX_S 0
|
||||
/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
|
||||
* write this bits to specify the bit position of 257 bit instruction which in units
|
||||
* of 32 bits
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_INST_POS 0x0000000FU
|
||||
#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
|
||||
#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU
|
||||
#define BITSCRAMBLER_RX_INST_POS_S 3
|
||||
|
||||
/** BITSCRAMBLER_RX_INST_CFG1_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
|
||||
/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
|
||||
* write this bits to update instruction which specified by
|
||||
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
|
||||
* BITSCRAMBLER_RX_INST_CFG0_REG
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
|
||||
#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_RX_INST_S 0
|
||||
|
||||
/** BITSCRAMBLER_TX_LUT_CFG0_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
|
||||
/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
|
||||
* write this bits to specify the bytes position of LUT RAM based on
|
||||
* reg_bitscrambler_tx_lut_mode
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU
|
||||
#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
|
||||
#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU
|
||||
#define BITSCRAMBLER_TX_LUT_IDX_S 0
|
||||
/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
|
||||
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
|
||||
* bytes
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U
|
||||
#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
|
||||
#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U
|
||||
#define BITSCRAMBLER_TX_LUT_MODE_S 11
|
||||
|
||||
/** BITSCRAMBLER_TX_LUT_CFG1_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
|
||||
/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
|
||||
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
|
||||
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
|
||||
#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_TX_LUT_S 0
|
||||
|
||||
/** BITSCRAMBLER_RX_LUT_CFG0_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
|
||||
/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
|
||||
* write this bits to specify the bytes position of LUT RAM based on
|
||||
* reg_bitscrambler_rx_lut_mode
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU
|
||||
#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
|
||||
#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU
|
||||
#define BITSCRAMBLER_RX_LUT_IDX_S 0
|
||||
/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
|
||||
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
|
||||
* bytes
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U
|
||||
#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
|
||||
#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U
|
||||
#define BITSCRAMBLER_RX_LUT_MODE_S 11
|
||||
|
||||
/** BITSCRAMBLER_RX_LUT_CFG1_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
|
||||
/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
|
||||
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
|
||||
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
|
||||
#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU
|
||||
#define BITSCRAMBLER_RX_LUT_S 0
|
||||
|
||||
/** BITSCRAMBLER_TX_TAILING_BITS_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
|
||||
/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
|
||||
* write this bits to specify the extra data bit length after getting EOF
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU
|
||||
#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
|
||||
#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU
|
||||
#define BITSCRAMBLER_TX_TAILING_BITS_S 0
|
||||
|
||||
/** BITSCRAMBLER_RX_TAILING_BITS_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
|
||||
/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
|
||||
* write this bits to specify the extra data bit length after getting EOF
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU
|
||||
#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
|
||||
#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU
|
||||
#define BITSCRAMBLER_RX_TAILING_BITS_S 0
|
||||
|
||||
/** BITSCRAMBLER_TX_CTRL_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
|
||||
/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* write this bit to enable the bitscrambler tx
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_ENA (BIT(0))
|
||||
#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
|
||||
#define BITSCRAMBLER_TX_ENA_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_ENA_S 0
|
||||
/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
|
||||
* write this bit to pause the bitscrambler tx core
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_PAUSE (BIT(1))
|
||||
#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
|
||||
#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_PAUSE_S 1
|
||||
/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
|
||||
* write this bit to halt the bitscrambler tx core
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_HALT (BIT(2))
|
||||
#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
|
||||
#define BITSCRAMBLER_TX_HALT_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_HALT_S 2
|
||||
/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
|
||||
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
|
||||
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
|
||||
* counter by write peripheral buffer
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_EOF_MODE (BIT(3))
|
||||
#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
|
||||
#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_EOF_MODE_S 3
|
||||
/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
|
||||
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
|
||||
* core, 0: use the little than operator to get the condition, 1: use not equal
|
||||
* operator to get the condition
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_COND_MODE (BIT(4))
|
||||
#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
|
||||
#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_COND_MODE_S 4
|
||||
/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
|
||||
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
|
||||
* by reset, 1: fetch by instrutions
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5))
|
||||
#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
|
||||
#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_FETCH_MODE_S 5
|
||||
/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
|
||||
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
|
||||
* wait write data back done, , 1: ignore write data back
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_HALT_MODE (BIT(6))
|
||||
#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
|
||||
#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_HALT_MODE_S 6
|
||||
/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
|
||||
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
|
||||
* wait read data, 1: ignore read data
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7))
|
||||
#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
|
||||
#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_RD_DUMMY_S 7
|
||||
/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
|
||||
* write this bit to reset the bitscrambler tx fifo
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_FIFO_RST (BIT(8))
|
||||
#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
|
||||
#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_FIFO_RST_S 8
|
||||
|
||||
/** BITSCRAMBLER_RX_CTRL_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
|
||||
/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* write this bit to enable the bitscrambler rx
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_ENA (BIT(0))
|
||||
#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
|
||||
#define BITSCRAMBLER_RX_ENA_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_ENA_S 0
|
||||
/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
|
||||
* write this bit to pause the bitscrambler rx core
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_PAUSE (BIT(1))
|
||||
#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
|
||||
#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_PAUSE_S 1
|
||||
/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
|
||||
* write this bit to halt the bitscrambler rx core
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_HALT (BIT(2))
|
||||
#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
|
||||
#define BITSCRAMBLER_RX_HALT_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_HALT_S 2
|
||||
/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
|
||||
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
|
||||
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
|
||||
* buffer, 0 counter by write dma fifo
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_EOF_MODE (BIT(3))
|
||||
#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
|
||||
#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_EOF_MODE_S 3
|
||||
/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
|
||||
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
|
||||
* core, 0: use the little than operator to get the condition, 1: use not equal
|
||||
* operator to get the condition
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_COND_MODE (BIT(4))
|
||||
#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
|
||||
#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_COND_MODE_S 4
|
||||
/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
|
||||
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
|
||||
* by reset, 1: fetch by instrutions
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5))
|
||||
#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
|
||||
#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_FETCH_MODE_S 5
|
||||
/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
|
||||
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
|
||||
* wait write data back done, , 1: ignore write data back
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_HALT_MODE (BIT(6))
|
||||
#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
|
||||
#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_HALT_MODE_S 6
|
||||
/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
|
||||
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
|
||||
* wait read data, 1: ignore read data
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7))
|
||||
#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
|
||||
#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_RD_DUMMY_S 7
|
||||
/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
|
||||
* write this bit to reset the bitscrambler rx fifo
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_FIFO_RST (BIT(8))
|
||||
#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
|
||||
#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_FIFO_RST_S 8
|
||||
|
||||
/** BITSCRAMBLER_TX_STATE_REG register
|
||||
* Status registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
|
||||
/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
|
||||
* represents the bitscrambler tx core in halt mode
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_IN_IDLE (BIT(0))
|
||||
#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
|
||||
#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_IN_IDLE_S 0
|
||||
/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
|
||||
* represents the bitscrambler tx core in run mode
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_IN_RUN (BIT(1))
|
||||
#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
|
||||
#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_IN_RUN_S 1
|
||||
/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
|
||||
* represents the bitscrambler tx core in wait mode to wait write back done
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_IN_WAIT (BIT(2))
|
||||
#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
|
||||
#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_IN_WAIT_S 2
|
||||
/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
|
||||
* represents the bitscrambler tx core in pause mode
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3))
|
||||
#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
|
||||
#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_IN_PAUSE_S 3
|
||||
/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
|
||||
* represents the bitscrambler tx fifo in empty state
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4))
|
||||
#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
|
||||
#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4
|
||||
/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
|
||||
* represents the bytes numbers of bitscrambler tx core when get EOF
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU
|
||||
#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
|
||||
#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU
|
||||
#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16
|
||||
/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
|
||||
* represents the some EOFs will be lost for bitscrambler tx core
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30))
|
||||
#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
|
||||
#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30
|
||||
/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
|
||||
* write this bit to clear reg_bitscrambler_tx_eof_overload and
|
||||
* reg_bitscrambler_tx_eof_get_cnt registers
|
||||
*/
|
||||
#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31))
|
||||
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
|
||||
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U
|
||||
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31
|
||||
|
||||
/** BITSCRAMBLER_RX_STATE_REG register
|
||||
* Status registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
|
||||
/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
|
||||
* represents the bitscrambler rx core in halt mode
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_IN_IDLE (BIT(0))
|
||||
#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
|
||||
#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_IN_IDLE_S 0
|
||||
/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
|
||||
* represents the bitscrambler rx core in run mode
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_IN_RUN (BIT(1))
|
||||
#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
|
||||
#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_IN_RUN_S 1
|
||||
/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
|
||||
* represents the bitscrambler rx core in wait mode to wait write back done
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_IN_WAIT (BIT(2))
|
||||
#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
|
||||
#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_IN_WAIT_S 2
|
||||
/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
|
||||
* represents the bitscrambler rx core in pause mode
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3))
|
||||
#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
|
||||
#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_IN_PAUSE_S 3
|
||||
/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
|
||||
* represents the bitscrambler rx fifo in full state
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4))
|
||||
#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
|
||||
#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_FIFO_FULL_S 4
|
||||
/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
|
||||
* represents the bytes numbers of bitscrambler rx core when get EOF
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU
|
||||
#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
|
||||
#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU
|
||||
#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16
|
||||
/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
|
||||
* represents the some EOFs will be lost for bitscrambler rx core
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30))
|
||||
#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
|
||||
#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30
|
||||
/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
|
||||
* write this bit to clear reg_bitscrambler_rx_eof_overload and
|
||||
* reg_bitscrambler_rx_eof_get_cnt registers
|
||||
*/
|
||||
#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31))
|
||||
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
|
||||
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U
|
||||
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31
|
||||
|
||||
/** BITSCRAMBLER_SYS_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
|
||||
/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
|
||||
* write this bit to set the bitscrambler tx loop back to DMA rx
|
||||
*/
|
||||
#define BITSCRAMBLER_LOOP_MODE (BIT(0))
|
||||
#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
|
||||
#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U
|
||||
#define BITSCRAMBLER_LOOP_MODE_S 0
|
||||
/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define BITSCRAMBLER_CLK_EN (BIT(31))
|
||||
#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
|
||||
#define BITSCRAMBLER_CLK_EN_V 0x00000001U
|
||||
#define BITSCRAMBLER_CLK_EN_S 31
|
||||
|
||||
/** BITSCRAMBLER_VERSION_REG register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
|
||||
/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
|
||||
* Reserved
|
||||
*/
|
||||
#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU
|
||||
#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
|
||||
#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU
|
||||
#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
436
components/soc/esp32c5/include/soc/bitscrambler_struct.h
Normal file
436
components/soc/esp32c5/include/soc/bitscrambler_struct.h
Normal file
@@ -0,0 +1,436 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Control and configuration registers */
|
||||
/** Type of tx_inst_cfg0 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
|
||||
* write this bits to specify the one of 8 instruction
|
||||
*/
|
||||
uint32_t tx_inst_idx:3;
|
||||
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
|
||||
* write this bits to specify the bit position of 257 bit instruction which in units
|
||||
* of 32 bits
|
||||
*/
|
||||
uint32_t tx_inst_pos:4;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_inst_cfg0_reg_t;
|
||||
|
||||
/** Type of tx_inst_cfg1 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
|
||||
* write this bits to update instruction which specified by
|
||||
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
|
||||
* BITSCRAMBLER_TX_INST_CFG0_REG
|
||||
*/
|
||||
uint32_t tx_inst:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_inst_cfg1_reg_t;
|
||||
|
||||
/** Type of rx_inst_cfg0 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
|
||||
* write this bits to specify the one of 8 instruction
|
||||
*/
|
||||
uint32_t rx_inst_idx:3;
|
||||
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
|
||||
* write this bits to specify the bit position of 257 bit instruction which in units
|
||||
* of 32 bits
|
||||
*/
|
||||
uint32_t rx_inst_pos:4;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_inst_cfg0_reg_t;
|
||||
|
||||
/** Type of rx_inst_cfg1 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
|
||||
* write this bits to update instruction which specified by
|
||||
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
|
||||
* BITSCRAMBLER_RX_INST_CFG0_REG
|
||||
*/
|
||||
uint32_t rx_inst:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_inst_cfg1_reg_t;
|
||||
|
||||
/** Type of tx_lut_cfg0 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
|
||||
* write this bits to specify the bytes position of LUT RAM based on
|
||||
* reg_bitscrambler_tx_lut_mode
|
||||
*/
|
||||
uint32_t tx_lut_idx:11;
|
||||
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
|
||||
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
|
||||
* bytes
|
||||
*/
|
||||
uint32_t tx_lut_mode:2;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_lut_cfg0_reg_t;
|
||||
|
||||
/** Type of tx_lut_cfg1 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
|
||||
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
|
||||
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
|
||||
*/
|
||||
uint32_t tx_lut:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_lut_cfg1_reg_t;
|
||||
|
||||
/** Type of rx_lut_cfg0 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
|
||||
* write this bits to specify the bytes position of LUT RAM based on
|
||||
* reg_bitscrambler_rx_lut_mode
|
||||
*/
|
||||
uint32_t rx_lut_idx:11;
|
||||
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
|
||||
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
|
||||
* bytes
|
||||
*/
|
||||
uint32_t rx_lut_mode:2;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_lut_cfg0_reg_t;
|
||||
|
||||
/** Type of rx_lut_cfg1 register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
|
||||
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
|
||||
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
|
||||
*/
|
||||
uint32_t rx_lut:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_lut_cfg1_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of tx_tailing_bits register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
|
||||
* write this bits to specify the extra data bit length after getting EOF
|
||||
*/
|
||||
uint32_t tx_tailing_bits:16;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_tailing_bits_reg_t;
|
||||
|
||||
/** Type of rx_tailing_bits register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
|
||||
* write this bits to specify the extra data bit length after getting EOF
|
||||
*/
|
||||
uint32_t rx_tailing_bits:16;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_tailing_bits_reg_t;
|
||||
|
||||
/** Type of tx_ctrl register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_ena : R/W; bitpos: [0]; default: 0;
|
||||
* write this bit to enable the bitscrambler tx
|
||||
*/
|
||||
uint32_t tx_ena:1;
|
||||
/** tx_pause : R/W; bitpos: [1]; default: 0;
|
||||
* write this bit to pause the bitscrambler tx core
|
||||
*/
|
||||
uint32_t tx_pause:1;
|
||||
/** tx_halt : R/W; bitpos: [2]; default: 1;
|
||||
* write this bit to halt the bitscrambler tx core
|
||||
*/
|
||||
uint32_t tx_halt:1;
|
||||
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
|
||||
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
|
||||
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
|
||||
* counter by write peripheral buffer
|
||||
*/
|
||||
uint32_t tx_eof_mode:1;
|
||||
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
|
||||
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
|
||||
* core, 0: use the little than operator to get the condition, 1: use not equal
|
||||
* operator to get the condition
|
||||
*/
|
||||
uint32_t tx_cond_mode:1;
|
||||
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
|
||||
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
|
||||
* by reset, 1: fetch by instrutions
|
||||
*/
|
||||
uint32_t tx_fetch_mode:1;
|
||||
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
|
||||
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
|
||||
* wait write data back done, , 1: ignore write data back
|
||||
*/
|
||||
uint32_t tx_halt_mode:1;
|
||||
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
|
||||
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
|
||||
* wait read data, 1: ignore read data
|
||||
*/
|
||||
uint32_t tx_rd_dummy:1;
|
||||
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
|
||||
* write this bit to reset the bitscrambler tx fifo
|
||||
*/
|
||||
uint32_t tx_fifo_rst:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_ctrl_reg_t;
|
||||
|
||||
/** Type of rx_ctrl register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_ena : R/W; bitpos: [0]; default: 0;
|
||||
* write this bit to enable the bitscrambler rx
|
||||
*/
|
||||
uint32_t rx_ena:1;
|
||||
/** rx_pause : R/W; bitpos: [1]; default: 0;
|
||||
* write this bit to pause the bitscrambler rx core
|
||||
*/
|
||||
uint32_t rx_pause:1;
|
||||
/** rx_halt : R/W; bitpos: [2]; default: 1;
|
||||
* write this bit to halt the bitscrambler rx core
|
||||
*/
|
||||
uint32_t rx_halt:1;
|
||||
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
|
||||
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
|
||||
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
|
||||
* buffer, 0 counter by write dma fifo
|
||||
*/
|
||||
uint32_t rx_eof_mode:1;
|
||||
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
|
||||
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
|
||||
* core, 0: use the little than operator to get the condition, 1: use not equal
|
||||
* operator to get the condition
|
||||
*/
|
||||
uint32_t rx_cond_mode:1;
|
||||
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
|
||||
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
|
||||
* by reset, 1: fetch by instrutions
|
||||
*/
|
||||
uint32_t rx_fetch_mode:1;
|
||||
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
|
||||
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
|
||||
* wait write data back done, , 1: ignore write data back
|
||||
*/
|
||||
uint32_t rx_halt_mode:1;
|
||||
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
|
||||
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
|
||||
* wait read data, 1: ignore read data
|
||||
*/
|
||||
uint32_t rx_rd_dummy:1;
|
||||
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
|
||||
* write this bit to reset the bitscrambler rx fifo
|
||||
*/
|
||||
uint32_t rx_fifo_rst:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_ctrl_reg_t;
|
||||
|
||||
/** Type of sys register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** loop_mode : R/W; bitpos: [0]; default: 0;
|
||||
* write this bit to set the bitscrambler tx loop back to DMA rx
|
||||
*/
|
||||
uint32_t loop_mode:1;
|
||||
uint32_t reserved_1:30;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_sys_reg_t;
|
||||
|
||||
|
||||
/** Group: Status registers */
|
||||
/** Type of tx_state register
|
||||
* Status registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_in_idle : RO; bitpos: [0]; default: 1;
|
||||
* represents the bitscrambler tx core in halt mode
|
||||
*/
|
||||
uint32_t tx_in_idle:1;
|
||||
/** tx_in_run : RO; bitpos: [1]; default: 0;
|
||||
* represents the bitscrambler tx core in run mode
|
||||
*/
|
||||
uint32_t tx_in_run:1;
|
||||
/** tx_in_wait : RO; bitpos: [2]; default: 0;
|
||||
* represents the bitscrambler tx core in wait mode to wait write back done
|
||||
*/
|
||||
uint32_t tx_in_wait:1;
|
||||
/** tx_in_pause : RO; bitpos: [3]; default: 0;
|
||||
* represents the bitscrambler tx core in pause mode
|
||||
*/
|
||||
uint32_t tx_in_pause:1;
|
||||
/** tx_fifo_empty : RO; bitpos: [4]; default: 0;
|
||||
* represents the bitscrambler tx fifo in empty state
|
||||
*/
|
||||
uint32_t tx_fifo_empty:1;
|
||||
uint32_t reserved_5:11;
|
||||
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
|
||||
* represents the bytes numbers of bitscrambler tx core when get EOF
|
||||
*/
|
||||
uint32_t tx_eof_get_cnt:14;
|
||||
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
|
||||
* represents the some EOFs will be lost for bitscrambler tx core
|
||||
*/
|
||||
uint32_t tx_eof_overload:1;
|
||||
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
|
||||
* write this bit to clear reg_bitscrambler_tx_eof_overload and
|
||||
* reg_bitscrambler_tx_eof_get_cnt registers
|
||||
*/
|
||||
uint32_t tx_eof_trace_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_tx_state_reg_t;
|
||||
|
||||
/** Type of rx_state register
|
||||
* Status registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_in_idle : RO; bitpos: [0]; default: 1;
|
||||
* represents the bitscrambler rx core in halt mode
|
||||
*/
|
||||
uint32_t rx_in_idle:1;
|
||||
/** rx_in_run : RO; bitpos: [1]; default: 0;
|
||||
* represents the bitscrambler rx core in run mode
|
||||
*/
|
||||
uint32_t rx_in_run:1;
|
||||
/** rx_in_wait : RO; bitpos: [2]; default: 0;
|
||||
* represents the bitscrambler rx core in wait mode to wait write back done
|
||||
*/
|
||||
uint32_t rx_in_wait:1;
|
||||
/** rx_in_pause : RO; bitpos: [3]; default: 0;
|
||||
* represents the bitscrambler rx core in pause mode
|
||||
*/
|
||||
uint32_t rx_in_pause:1;
|
||||
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
|
||||
* represents the bitscrambler rx fifo in full state
|
||||
*/
|
||||
uint32_t rx_fifo_full:1;
|
||||
uint32_t reserved_5:11;
|
||||
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
|
||||
* represents the bytes numbers of bitscrambler rx core when get EOF
|
||||
*/
|
||||
uint32_t rx_eof_get_cnt:14;
|
||||
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
|
||||
* represents the some EOFs will be lost for bitscrambler rx core
|
||||
*/
|
||||
uint32_t rx_eof_overload:1;
|
||||
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
|
||||
* write this bit to clear reg_bitscrambler_rx_eof_overload and
|
||||
* reg_bitscrambler_rx_eof_get_cnt registers
|
||||
*/
|
||||
uint32_t rx_eof_trace_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_rx_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of version register
|
||||
* Control and configuration registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t bitscrambler_ver:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} bitscrambler_version_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
|
||||
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
|
||||
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
|
||||
volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
|
||||
volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
|
||||
volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
|
||||
volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
|
||||
volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
|
||||
volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
|
||||
volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
|
||||
volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
|
||||
volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
|
||||
volatile bitscrambler_tx_state_reg_t tx_state;
|
||||
volatile bitscrambler_rx_state_reg_t rx_state;
|
||||
uint32_t reserved_038[48];
|
||||
volatile bitscrambler_sys_reg_t sys;
|
||||
volatile bitscrambler_version_reg_t version;
|
||||
} bitscrambler_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
167
components/soc/esp32c5/include/soc/ecc_mult_reg.h
Normal file
167
components/soc/esp32c5/include/soc/ecc_mult_reg.h
Normal file
@@ -0,0 +1,167 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** ECC_MULT_INT_RAW_REG register
|
||||
* ECC interrupt raw register, valid in level.
|
||||
*/
|
||||
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
|
||||
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecc_calc_done_int interrupt
|
||||
*/
|
||||
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
|
||||
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
|
||||
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
|
||||
|
||||
/** ECC_MULT_INT_ST_REG register
|
||||
* ECC interrupt status register.
|
||||
*/
|
||||
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
|
||||
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecc_calc_done_int interrupt
|
||||
*/
|
||||
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
|
||||
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
|
||||
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
|
||||
#define ECC_MULT_CALC_DONE_INT_ST_S 0
|
||||
|
||||
/** ECC_MULT_INT_ENA_REG register
|
||||
* ECC interrupt enable register.
|
||||
*/
|
||||
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
|
||||
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecc_calc_done_int interrupt
|
||||
*/
|
||||
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
|
||||
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
|
||||
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
|
||||
|
||||
/** ECC_MULT_INT_CLR_REG register
|
||||
* ECC interrupt clear register.
|
||||
*/
|
||||
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
|
||||
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecc_calc_done_int interrupt
|
||||
*/
|
||||
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
|
||||
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
|
||||
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
|
||||
|
||||
/** ECC_MULT_CONF_REG register
|
||||
* ECC configure register
|
||||
*/
|
||||
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
|
||||
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
|
||||
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
|
||||
* the caculatrion is done.
|
||||
*/
|
||||
#define ECC_MULT_START (BIT(0))
|
||||
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
|
||||
#define ECC_MULT_START_V 0x00000001U
|
||||
#define ECC_MULT_START_S 0
|
||||
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to reset ECC Accelerator.
|
||||
*/
|
||||
#define ECC_MULT_RESET (BIT(1))
|
||||
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
|
||||
#define ECC_MULT_RESET_V 0x00000001U
|
||||
#define ECC_MULT_RESET_S 1
|
||||
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
|
||||
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
#define ECC_MULT_KEY_LENGTH (BIT(2))
|
||||
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
|
||||
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
|
||||
#define ECC_MULT_KEY_LENGTH_S 2
|
||||
/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
|
||||
* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
|
||||
* 1: p(mod base of curve)
|
||||
*/
|
||||
#define ECC_MULT_MOD_BASE (BIT(3))
|
||||
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
|
||||
#define ECC_MULT_MOD_BASE_V 0x00000001U
|
||||
#define ECC_MULT_MOD_BASE_S 3
|
||||
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
|
||||
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
|
||||
* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
|
||||
* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
|
||||
* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
|
||||
*/
|
||||
#define ECC_MULT_WORK_MODE 0x0000000FU
|
||||
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
|
||||
#define ECC_MULT_WORK_MODE_V 0x0000000FU
|
||||
#define ECC_MULT_WORK_MODE_S 4
|
||||
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define ECC_MULT_SECURITY_MODE (BIT(8))
|
||||
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
|
||||
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
|
||||
#define ECC_MULT_SECURITY_MODE_S 8
|
||||
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
|
||||
* The verification result bit of ECC Accelerator, only valid when calculation is done.
|
||||
*/
|
||||
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
|
||||
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
|
||||
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
|
||||
#define ECC_MULT_VERIFICATION_RESULT_S 29
|
||||
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
#define ECC_MULT_CLK_EN (BIT(30))
|
||||
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
|
||||
#define ECC_MULT_CLK_EN_V 0x00000001U
|
||||
#define ECC_MULT_CLK_EN_S 30
|
||||
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
|
||||
* ECC memory clock gate force on register
|
||||
*/
|
||||
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
|
||||
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
|
||||
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
|
||||
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
|
||||
|
||||
/** ECC_MULT_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
|
||||
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
|
||||
* ECC mult version control register
|
||||
*/
|
||||
#define ECC_MULT_DATE 0x0FFFFFFFU
|
||||
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
|
||||
#define ECC_MULT_DATE_V 0x0FFFFFFFU
|
||||
#define ECC_MULT_DATE_S 0
|
||||
|
||||
/** ECC_MULT_K_MEM register
|
||||
* The memory that stores k.
|
||||
*/
|
||||
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
|
||||
#define ECC_MULT_K_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECC_MULT_PX_MEM register
|
||||
* The memory that stores Px.
|
||||
*/
|
||||
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
|
||||
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECC_MULT_PY_MEM register
|
||||
* The memory that stores Py.
|
||||
*/
|
||||
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
|
||||
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
164
components/soc/esp32c5/include/soc/ecc_mult_struct.h
Normal file
164
components/soc/esp32c5/include/soc/ecc_mult_struct.h
Normal file
@@ -0,0 +1,164 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Memory data */
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* ECC interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecc_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_raw:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_mult_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* ECC interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecc_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_st:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_mult_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* ECC interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecc_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_ena:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_mult_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* ECC interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecc_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_clr:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_mult_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: RX Control and configuration registers */
|
||||
/** Type of conf register
|
||||
* ECC configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : R/W/SC; bitpos: [0]; default: 0;
|
||||
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
|
||||
* the caculatrion is done.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** reset : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to reset ECC Accelerator.
|
||||
*/
|
||||
uint32_t reset:1;
|
||||
/** key_length : R/W; bitpos: [2]; default: 0;
|
||||
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
uint32_t key_length:1;
|
||||
/** mod_base : R/W; bitpos: [3]; default: 0;
|
||||
* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
|
||||
* 1: p(mod base of curve)
|
||||
*/
|
||||
uint32_t mod_base:1;
|
||||
/** work_mode : R/W; bitpos: [7:4]; default: 0;
|
||||
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
|
||||
* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
|
||||
* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
|
||||
* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
|
||||
*/
|
||||
uint32_t work_mode:4;
|
||||
/** security_mode : R/W; bitpos: [8]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t security_mode:1;
|
||||
uint32_t reserved_9:20;
|
||||
/** verification_result : RO/SS; bitpos: [29]; default: 0;
|
||||
* The verification result bit of ECC Accelerator, only valid when calculation is done.
|
||||
*/
|
||||
uint32_t verification_result:1;
|
||||
/** clk_en : R/W; bitpos: [30]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
|
||||
* ECC memory clock gate force on register
|
||||
*/
|
||||
uint32_t mem_clock_gate_force_on:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_mult_conf_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36720704;
|
||||
* ECC mult version control register
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_mult_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000[3];
|
||||
volatile ecc_mult_int_raw_reg_t int_raw;
|
||||
volatile ecc_mult_int_st_reg_t int_st;
|
||||
volatile ecc_mult_int_ena_reg_t int_ena;
|
||||
volatile ecc_mult_int_clr_reg_t int_clr;
|
||||
volatile ecc_mult_conf_reg_t conf;
|
||||
uint32_t reserved_020[55];
|
||||
volatile ecc_mult_date_reg_t date;
|
||||
volatile uint32_t k[8];
|
||||
volatile uint32_t px[8];
|
||||
volatile uint32_t py[8];
|
||||
} ecc_mult_dev_t;
|
||||
|
||||
extern ecc_mult_dev_t ECC;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
318
components/soc/esp32c5/include/soc/ecdsa_reg.h
Normal file
318
components/soc/esp32c5/include/soc/ecdsa_reg.h
Normal file
@@ -0,0 +1,318 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** ECDSA_CONF_REG register
|
||||
* ECDSA configure register
|
||||
*/
|
||||
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
|
||||
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
|
||||
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
|
||||
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
|
||||
*/
|
||||
#define ECDSA_WORK_MODE 0x00000003U
|
||||
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
|
||||
#define ECDSA_WORK_MODE_V 0x00000003U
|
||||
#define ECDSA_WORK_MODE_S 0
|
||||
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
#define ECDSA_ECC_CURVE (BIT(2))
|
||||
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
|
||||
#define ECDSA_ECC_CURVE_V 0x00000001U
|
||||
#define ECDSA_ECC_CURVE_S 2
|
||||
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
|
||||
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
|
||||
* written by software.
|
||||
*/
|
||||
#define ECDSA_SOFTWARE_SET_K (BIT(3))
|
||||
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
|
||||
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
|
||||
#define ECDSA_SOFTWARE_SET_K_S 3
|
||||
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
|
||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
|
||||
* software.
|
||||
*/
|
||||
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
|
||||
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
|
||||
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
|
||||
#define ECDSA_SOFTWARE_SET_Z_S 4
|
||||
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
|
||||
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
|
||||
* deterministic derivation algorithm.
|
||||
*/
|
||||
#define ECDSA_DETERMINISTIC_K (BIT(5))
|
||||
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
|
||||
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
|
||||
#define ECDSA_DETERMINISTIC_K_S 5
|
||||
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
|
||||
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
|
||||
*/
|
||||
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
|
||||
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
|
||||
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
|
||||
#define ECDSA_DETERMINISTIC_LOOP_S 6
|
||||
|
||||
/** ECDSA_CLK_REG register
|
||||
* ECDSA clock gate register
|
||||
*/
|
||||
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
|
||||
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
|
||||
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
|
||||
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
|
||||
#define ECDSA_CLK_GATE_FORCE_ON_S 0
|
||||
|
||||
/** ECDSA_INT_RAW_REG register
|
||||
* ECDSA interrupt raw register, valid in level.
|
||||
*/
|
||||
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
|
||||
/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
|
||||
#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_RAW_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_S 1
|
||||
|
||||
/** ECDSA_INT_ST_REG register
|
||||
* ECDSA interrupt status register.
|
||||
*/
|
||||
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
|
||||
/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_ST (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
|
||||
#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_ST_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_S 1
|
||||
|
||||
/** ECDSA_INT_ENA_REG register
|
||||
* ECDSA interrupt enable register.
|
||||
*/
|
||||
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
|
||||
/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
|
||||
#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_ENA_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_S 1
|
||||
|
||||
/** ECDSA_INT_CLR_REG register
|
||||
* ECDSA interrupt clear register.
|
||||
*/
|
||||
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
|
||||
/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
|
||||
#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_CLR_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_S 1
|
||||
|
||||
/** ECDSA_START_REG register
|
||||
* ECDSA start register
|
||||
*/
|
||||
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
|
||||
/** ECDSA_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
|
||||
* after configuration.
|
||||
*/
|
||||
#define ECDSA_START (BIT(0))
|
||||
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
|
||||
#define ECDSA_START_V 0x00000001U
|
||||
#define ECDSA_START_S 0
|
||||
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_LOAD_DONE (BIT(1))
|
||||
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
|
||||
#define ECDSA_LOAD_DONE_V 0x00000001U
|
||||
#define ECDSA_LOAD_DONE_S 1
|
||||
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_GET_DONE (BIT(2))
|
||||
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
|
||||
#define ECDSA_GET_DONE_V 0x00000001U
|
||||
#define ECDSA_GET_DONE_S 2
|
||||
|
||||
/** ECDSA_STATE_REG register
|
||||
* ECDSA status register
|
||||
*/
|
||||
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
|
||||
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
|
||||
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
#define ECDSA_BUSY 0x00000003U
|
||||
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
|
||||
#define ECDSA_BUSY_V 0x00000003U
|
||||
#define ECDSA_BUSY_S 0
|
||||
|
||||
/** ECDSA_RESULT_REG register
|
||||
* ECDSA result register
|
||||
*/
|
||||
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
|
||||
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
|
||||
* done.
|
||||
*/
|
||||
#define ECDSA_OPERATION_RESULT (BIT(0))
|
||||
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
|
||||
#define ECDSA_OPERATION_RESULT_V 0x00000001U
|
||||
#define ECDSA_OPERATION_RESULT_S 0
|
||||
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
|
||||
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
|
||||
* curve order, then actually taken k = k mod n.
|
||||
*/
|
||||
#define ECDSA_K_VALUE_WARNING (BIT(1))
|
||||
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
|
||||
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
|
||||
#define ECDSA_K_VALUE_WARNING_S 1
|
||||
|
||||
/** ECDSA_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
|
||||
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
#define ECDSA_DATE 0x0FFFFFFFU
|
||||
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
|
||||
#define ECDSA_DATE_V 0x0FFFFFFFU
|
||||
#define ECDSA_DATE_S 0
|
||||
|
||||
/** ECDSA_SHA_MODE_REG register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
|
||||
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
*/
|
||||
#define ECDSA_SHA_MODE 0x00000007U
|
||||
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
|
||||
#define ECDSA_SHA_MODE_V 0x00000007U
|
||||
#define ECDSA_SHA_MODE_S 0
|
||||
|
||||
/** ECDSA_SHA_START_REG register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
|
||||
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_SHA_START (BIT(0))
|
||||
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
|
||||
#define ECDSA_SHA_START_V 0x00000001U
|
||||
#define ECDSA_SHA_START_S 0
|
||||
|
||||
/** ECDSA_SHA_CONTINUE_REG register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
|
||||
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_SHA_CONTINUE (BIT(0))
|
||||
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
|
||||
#define ECDSA_SHA_CONTINUE_V 0x00000001U
|
||||
#define ECDSA_SHA_CONTINUE_S 0
|
||||
|
||||
/** ECDSA_SHA_BUSY_REG register
|
||||
* ECDSA status register
|
||||
*/
|
||||
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
|
||||
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
*/
|
||||
#define ECDSA_SHA_BUSY (BIT(0))
|
||||
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
|
||||
#define ECDSA_SHA_BUSY_V 0x00000001U
|
||||
#define ECDSA_SHA_BUSY_S 0
|
||||
|
||||
/** ECDSA_MESSAGE_MEM register
|
||||
* The memory that stores message.
|
||||
*/
|
||||
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
|
||||
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_R_MEM register
|
||||
* The memory that stores r.
|
||||
*/
|
||||
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
|
||||
#define ECDSA_R_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_S_MEM register
|
||||
* The memory that stores s.
|
||||
*/
|
||||
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
|
||||
#define ECDSA_S_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_Z_MEM register
|
||||
* The memory that stores software written z.
|
||||
*/
|
||||
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
|
||||
#define ECDSA_Z_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_QAX_MEM register
|
||||
* The memory that stores x coordinates of QA or software written k.
|
||||
*/
|
||||
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
|
||||
#define ECDSA_QAX_MEM_SIZE_BYTES 32
|
||||
|
||||
/** ECDSA_QAY_MEM register
|
||||
* The memory that stores y coordinates of QA.
|
||||
*/
|
||||
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
|
||||
#define ECDSA_QAY_MEM_SIZE_BYTES 32
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
323
components/soc/esp32c5/include/soc/ecdsa_struct.h
Normal file
323
components/soc/esp32c5/include/soc/ecdsa_struct.h
Normal file
@@ -0,0 +1,323 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Data Memory */
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of conf register
|
||||
* ECDSA configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** work_mode : R/W; bitpos: [1:0]; default: 0;
|
||||
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
|
||||
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
|
||||
*/
|
||||
uint32_t work_mode:2;
|
||||
/** ecc_curve : R/W; bitpos: [2]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
|
||||
*/
|
||||
uint32_t ecc_curve:1;
|
||||
/** software_set_k : R/W; bitpos: [3]; default: 0;
|
||||
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
|
||||
* written by software.
|
||||
*/
|
||||
uint32_t software_set_k:1;
|
||||
/** software_set_z : R/W; bitpos: [4]; default: 0;
|
||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
|
||||
* software.
|
||||
*/
|
||||
uint32_t software_set_z:1;
|
||||
/** deterministic_k : R/W; bitpos: [5]; default: 0;
|
||||
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
|
||||
* deterministic derivation algorithm.
|
||||
*/
|
||||
uint32_t deterministic_k:1;
|
||||
/** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
|
||||
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
|
||||
*/
|
||||
uint32_t deterministic_loop:16;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_conf_reg_t;
|
||||
|
||||
/** Type of start register
|
||||
* ECDSA start register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
|
||||
* after configuration.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** load_done : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t load_done:1;
|
||||
/** get_done : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
|
||||
* self-cleared after configuration.
|
||||
*/
|
||||
uint32_t get_done:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_start_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock and reset registers */
|
||||
/** Type of clk register
|
||||
* ECDSA clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t clk_gate_force_on:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* ECDSA interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_raw:1;
|
||||
/** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* ECDSA interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_st:1;
|
||||
/** sha_release_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_st:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* ECDSA interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_ena:1;
|
||||
/** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* ECDSA interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_calc_done_int interrupt
|
||||
*/
|
||||
uint32_t calc_done_int_clr:1;
|
||||
/** sha_release_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
uint32_t sha_release_int_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Status registers */
|
||||
/** Type of state register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** busy : RO; bitpos: [1:0]; default: 0;
|
||||
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
uint32_t busy:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Result registers */
|
||||
/** Type of result register
|
||||
* ECDSA result register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** operation_result : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
|
||||
* done.
|
||||
*/
|
||||
uint32_t operation_result:1;
|
||||
/** k_value_warning : RO/SS; bitpos: [1]; default: 0;
|
||||
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
|
||||
* curve order, then actually taken k = k mod n.
|
||||
*/
|
||||
uint32_t k_value_warning:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_result_reg_t;
|
||||
|
||||
|
||||
/** Group: SHA register */
|
||||
/** Type of sha_mode register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
*/
|
||||
uint32_t sha_mode:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_mode_reg_t;
|
||||
|
||||
/** Type of sha_start register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_start:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_start_reg_t;
|
||||
|
||||
/** Type of sha_continue register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_continue : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
uint32_t sha_continue:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_continue_reg_t;
|
||||
|
||||
/** Type of sha_busy register
|
||||
* ECDSA status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sha_busy : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
*/
|
||||
uint32_t sha_busy:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_sha_busy_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36716656;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} ecdsa_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000;
|
||||
volatile ecdsa_conf_reg_t conf;
|
||||
volatile ecdsa_clk_reg_t clk;
|
||||
volatile ecdsa_int_raw_reg_t int_raw;
|
||||
volatile ecdsa_int_st_reg_t int_st;
|
||||
volatile ecdsa_int_ena_reg_t int_ena;
|
||||
volatile ecdsa_int_clr_reg_t int_clr;
|
||||
volatile ecdsa_start_reg_t start;
|
||||
volatile ecdsa_state_reg_t state;
|
||||
volatile ecdsa_result_reg_t result;
|
||||
uint32_t reserved_028[53];
|
||||
volatile ecdsa_date_reg_t date;
|
||||
uint32_t reserved_100[64];
|
||||
volatile ecdsa_sha_mode_reg_t sha_mode;
|
||||
uint32_t reserved_204[3];
|
||||
volatile ecdsa_sha_start_reg_t sha_start;
|
||||
volatile ecdsa_sha_continue_reg_t sha_continue;
|
||||
volatile ecdsa_sha_busy_reg_t sha_busy;
|
||||
uint32_t reserved_21c[25];
|
||||
volatile uint32_t message[8];
|
||||
uint32_t reserved_2a0[472];
|
||||
volatile uint32_t r[8];
|
||||
volatile uint32_t s[8];
|
||||
volatile uint32_t z[8];
|
||||
volatile uint32_t qax[8];
|
||||
volatile uint32_t qay[8];
|
||||
} ecdsa_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
340
components/soc/esp32c5/include/soc/gpio_ext_struct.h
Normal file
340
components/soc/esp32c5/include/soc/gpio_ext_struct.h
Normal file
@@ -0,0 +1,340 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: SDM Configure Registers */
|
||||
/** Type of sigmadeltan register
|
||||
* Duty Cycle Configure Register of SDMn
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sdn_in : R/W; bitpos: [7:0]; default: 0;
|
||||
* This field is used to configure the duty cycle of sigma delta modulation output.
|
||||
*/
|
||||
uint32_t sdn_in:8;
|
||||
/** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
|
||||
* This field is used to set a divider value to divide APB clock.
|
||||
*/
|
||||
uint32_t sdn_prescale:8;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_sigmadeltan_reg_t;
|
||||
|
||||
/** Type of sigmadelta_misc register
|
||||
* MISC Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** function_clk_en : R/W; bitpos: [30]; default: 0;
|
||||
* Clock enable bit of sigma delta modulation.
|
||||
*/
|
||||
uint32_t function_clk_en:1;
|
||||
/** spi_swap : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved.
|
||||
*/
|
||||
uint32_t spi_swap:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_sigmadelta_misc_reg_t;
|
||||
|
||||
|
||||
/** Group: Configure Registers */
|
||||
/** Type of pad_comp_config register
|
||||
* PAD Compare configure Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** xpd_comp : R/W; bitpos: [0]; default: 0;
|
||||
* Pad compare enable bit.
|
||||
*/
|
||||
uint32_t xpd_comp:1;
|
||||
/** mode_comp : R/W; bitpos: [1]; default: 0;
|
||||
* 1 to enable external reference from PAD[0]. 0 to enable internal reference,
|
||||
* meanwhile PAD[0] can be used as a regular GPIO.
|
||||
*/
|
||||
uint32_t mode_comp:1;
|
||||
/** dref_comp : R/W; bitpos: [4:2]; default: 0;
|
||||
* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
|
||||
*/
|
||||
uint32_t dref_comp:3;
|
||||
/** zero_det_mode : R/W; bitpos: [6:5]; default: 0;
|
||||
* Zero Detect mode select.
|
||||
*/
|
||||
uint32_t zero_det_mode:2;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_pad_comp_config_reg_t;
|
||||
|
||||
/** Type of pad_comp_filter register
|
||||
* Zero Detect filter Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0;
|
||||
* Zero Detect filter cycle length
|
||||
*/
|
||||
uint32_t zero_det_filter_cnt:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_pad_comp_filter_reg_t;
|
||||
|
||||
|
||||
/** Group: Glitch filter Configure Registers */
|
||||
/** Type of glitch_filter_chn register
|
||||
* Glitch Filter Configure Register of Channeln
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
|
||||
* Glitch Filter channel enable bit.
|
||||
*/
|
||||
uint32_t filter_ch0_en:1;
|
||||
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
|
||||
* Glitch Filter input io number.
|
||||
*/
|
||||
uint32_t filter_ch0_input_io_num:6;
|
||||
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
|
||||
* Glitch Filter window threshold.
|
||||
*/
|
||||
uint32_t filter_ch0_window_thres:6;
|
||||
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
|
||||
* Glitch Filter window width.
|
||||
*/
|
||||
uint32_t filter_ch0_window_width:6;
|
||||
uint32_t reserved_19:13;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_glitch_filter_chn_reg_t;
|
||||
|
||||
|
||||
/** Group: Etm Configure Registers */
|
||||
/** Type of etm_event_chn_cfg register
|
||||
* Etm Config register of Channeln
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
|
||||
* Etm event channel select gpio.
|
||||
*/
|
||||
uint32_t etm_ch0_event_sel:5;
|
||||
uint32_t reserved_5:2;
|
||||
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
|
||||
* Etm event send enable bit.
|
||||
*/
|
||||
uint32_t etm_ch0_event_en:1;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_event_chn_cfg_reg_t;
|
||||
|
||||
/** Type of etm_task_pn_cfg register
|
||||
* Etm Configure Register to decide which GPIO been chosen
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
|
||||
* Enable bit of GPIO response etm task.
|
||||
*/
|
||||
uint32_t etm_task_gpio0_en:1;
|
||||
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
|
||||
* GPIO choose a etm task channel.
|
||||
*/
|
||||
uint32_t etm_task_gpio0_sel:3;
|
||||
uint32_t reserved_4:4;
|
||||
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
|
||||
* Enable bit of GPIO response etm task.
|
||||
*/
|
||||
uint32_t etm_task_gpio1_en:1;
|
||||
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
|
||||
* GPIO choose a etm task channel.
|
||||
*/
|
||||
uint32_t etm_task_gpio1_sel:3;
|
||||
uint32_t reserved_12:4;
|
||||
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
|
||||
* Enable bit of GPIO response etm task.
|
||||
*/
|
||||
uint32_t etm_task_gpio2_en:1;
|
||||
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
|
||||
* GPIO choose a etm task channel.
|
||||
*/
|
||||
uint32_t etm_task_gpio2_sel:3;
|
||||
uint32_t reserved_20:4;
|
||||
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
|
||||
* Enable bit of GPIO response etm task.
|
||||
*/
|
||||
uint32_t etm_task_gpio3_en:1;
|
||||
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
|
||||
* GPIO choose a etm task channel.
|
||||
*/
|
||||
uint32_t etm_task_gpio3_sel:3;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_task_pn_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Registers */
|
||||
/** Type of int_raw register
|
||||
* GPIOSD interrupt raw register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp0_neg_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt raw
|
||||
*/
|
||||
uint32_t comp0_neg_int_raw:1;
|
||||
/** comp0_pos_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt raw
|
||||
*/
|
||||
uint32_t comp0_pos_int_raw:1;
|
||||
/** comp0_all_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt raw
|
||||
*/
|
||||
uint32_t comp0_all_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* GPIOSD interrupt masked register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt status
|
||||
*/
|
||||
uint32_t comp0_neg_int_st:1;
|
||||
/** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt status
|
||||
*/
|
||||
uint32_t comp0_pos_int_st:1;
|
||||
/** comp0_all_int_st : RO; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt status
|
||||
*/
|
||||
uint32_t comp0_all_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* GPIOSD interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
|
||||
* analog comparator pos edge interrupt enable
|
||||
*/
|
||||
uint32_t comp0_neg_int_ena:1;
|
||||
/** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
|
||||
* analog comparator neg edge interrupt enable
|
||||
*/
|
||||
uint32_t comp0_pos_int_ena:1;
|
||||
/** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
|
||||
* analog comparator neg or pos edge interrupt enable
|
||||
*/
|
||||
uint32_t comp0_all_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* GPIOSD interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt clear
|
||||
*/
|
||||
uint32_t comp0_neg_int_clr:1;
|
||||
/** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt clear
|
||||
*/
|
||||
uint32_t comp0_pos_int_clr:1;
|
||||
/** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt clear
|
||||
*/
|
||||
uint32_t comp0_all_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of version register
|
||||
* Version Control Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 36704513;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t gpio_sd_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_version_reg_t;
|
||||
|
||||
|
||||
typedef struct gpio_sd_dev_t {
|
||||
volatile gpio_ext_sigmadeltan_reg_t channel[4];
|
||||
uint32_t reserved_010[5];
|
||||
volatile gpio_ext_sigmadelta_misc_reg_t misc;
|
||||
} gpio_sd_dev_t;
|
||||
|
||||
typedef struct gpio_ana_cmpr_dev_t {
|
||||
volatile gpio_ext_pad_comp_config_reg_t pad_comp_config;
|
||||
volatile gpio_ext_pad_comp_filter_reg_t pad_comp_filter;
|
||||
} gpio_ana_cmpr_dev_t;
|
||||
|
||||
typedef struct {
|
||||
volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
|
||||
} gpio_glitch_filter_dev_t;
|
||||
|
||||
typedef struct gpio_etm_dev_t {
|
||||
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
|
||||
uint32_t reserved_080[8];
|
||||
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7];
|
||||
} gpio_etm_dev_t;
|
||||
|
||||
typedef struct gpio_ext_dev_t {
|
||||
volatile gpio_sd_dev_t sigma_delta;
|
||||
volatile gpio_ana_cmpr_dev_t ana_cmpr;
|
||||
volatile gpio_glitch_filter_dev_t glitch_filter;
|
||||
uint32_t reserved_050[4];
|
||||
volatile gpio_etm_dev_t etm;
|
||||
uint32_t reserved_0bc[9];
|
||||
volatile gpio_ext_int_raw_reg_t int_raw;
|
||||
volatile gpio_ext_int_st_reg_t int_st;
|
||||
volatile gpio_ext_int_ena_reg_t int_ena;
|
||||
volatile gpio_ext_int_clr_reg_t int_clr;
|
||||
uint32_t reserved_0f0[3];
|
||||
volatile gpio_ext_version_reg_t version;
|
||||
} gpio_ext_dev_t;
|
||||
|
||||
extern gpio_sd_dev_t SDM;
|
||||
extern gpio_glitch_filter_dev_t GLITCH_FILTER;
|
||||
extern gpio_etm_dev_t GPIO_ETM;
|
||||
extern gpio_ext_dev_t GPIO_EXT;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
5727
components/soc/esp32c5/include/soc/gpio_reg.h
Normal file
5727
components/soc/esp32c5/include/soc/gpio_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1950
components/soc/esp32c5/include/soc/hp_apm_reg.h
Normal file
1950
components/soc/esp32c5/include/soc/hp_apm_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1734
components/soc/esp32c5/include/soc/hp_apm_struct.h
Normal file
1734
components/soc/esp32c5/include/soc/hp_apm_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
222
components/soc/esp32c5/include/soc/huk_reg.h
Normal file
222
components/soc/esp32c5/include/soc/huk_reg.h
Normal file
@@ -0,0 +1,222 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** HUK_CLK_REG register
|
||||
* HUK Generator clock gate control register
|
||||
*/
|
||||
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
|
||||
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
#define HUK_CLK_EN (BIT(0))
|
||||
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
|
||||
#define HUK_CLK_EN_V 0x00000001U
|
||||
#define HUK_CLK_EN_S 0
|
||||
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to force on memory clock gate.
|
||||
*/
|
||||
#define HUK_MEM_CG_FORCE_ON (BIT(1))
|
||||
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
|
||||
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
|
||||
#define HUK_MEM_CG_FORCE_ON_S 1
|
||||
|
||||
/** HUK_INT_RAW_REG register
|
||||
* HUK Generator interrupt raw register, valid in level.
|
||||
*/
|
||||
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
|
||||
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the huk_prep_done_int interrupt
|
||||
*/
|
||||
#define HUK_PREP_DONE_INT_RAW (BIT(0))
|
||||
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
|
||||
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
|
||||
#define HUK_PREP_DONE_INT_RAW_S 0
|
||||
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the huk_proc_done_int interrupt
|
||||
*/
|
||||
#define HUK_PROC_DONE_INT_RAW (BIT(1))
|
||||
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
|
||||
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
|
||||
#define HUK_PROC_DONE_INT_RAW_S 1
|
||||
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the huk_post_done_int interrupt
|
||||
*/
|
||||
#define HUK_POST_DONE_INT_RAW (BIT(2))
|
||||
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
|
||||
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
|
||||
#define HUK_POST_DONE_INT_RAW_S 2
|
||||
|
||||
/** HUK_INT_ST_REG register
|
||||
* HUK Generator interrupt status register.
|
||||
*/
|
||||
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
|
||||
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the huk_prep_done_int interrupt
|
||||
*/
|
||||
#define HUK_PREP_DONE_INT_ST (BIT(0))
|
||||
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
|
||||
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
|
||||
#define HUK_PREP_DONE_INT_ST_S 0
|
||||
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the huk_proc_done_int interrupt
|
||||
*/
|
||||
#define HUK_PROC_DONE_INT_ST (BIT(1))
|
||||
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
|
||||
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
|
||||
#define HUK_PROC_DONE_INT_ST_S 1
|
||||
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the huk_post_done_int interrupt
|
||||
*/
|
||||
#define HUK_POST_DONE_INT_ST (BIT(2))
|
||||
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
|
||||
#define HUK_POST_DONE_INT_ST_V 0x00000001U
|
||||
#define HUK_POST_DONE_INT_ST_S 2
|
||||
|
||||
/** HUK_INT_ENA_REG register
|
||||
* HUK Generator interrupt enable register.
|
||||
*/
|
||||
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
|
||||
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the huk_prep_done_int interrupt
|
||||
*/
|
||||
#define HUK_PREP_DONE_INT_ENA (BIT(0))
|
||||
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
|
||||
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
|
||||
#define HUK_PREP_DONE_INT_ENA_S 0
|
||||
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the huk_proc_done_int interrupt
|
||||
*/
|
||||
#define HUK_PROC_DONE_INT_ENA (BIT(1))
|
||||
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
|
||||
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
|
||||
#define HUK_PROC_DONE_INT_ENA_S 1
|
||||
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the huk_post_done_int interrupt
|
||||
*/
|
||||
#define HUK_POST_DONE_INT_ENA (BIT(2))
|
||||
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
|
||||
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
|
||||
#define HUK_POST_DONE_INT_ENA_S 2
|
||||
|
||||
/** HUK_INT_CLR_REG register
|
||||
* HUK Generator interrupt clear register.
|
||||
*/
|
||||
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
|
||||
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the huk_prep_done_int interrupt
|
||||
*/
|
||||
#define HUK_PREP_DONE_INT_CLR (BIT(0))
|
||||
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
|
||||
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
|
||||
#define HUK_PREP_DONE_INT_CLR_S 0
|
||||
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the huk_proc_done_int interrupt
|
||||
*/
|
||||
#define HUK_PROC_DONE_INT_CLR (BIT(1))
|
||||
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
|
||||
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
|
||||
#define HUK_PROC_DONE_INT_CLR_S 1
|
||||
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the huk_post_done_int interrupt
|
||||
*/
|
||||
#define HUK_POST_DONE_INT_CLR (BIT(2))
|
||||
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
|
||||
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
|
||||
#define HUK_POST_DONE_INT_CLR_S 2
|
||||
|
||||
/** HUK_CONF_REG register
|
||||
* HUK Generator configuration register
|
||||
*/
|
||||
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
|
||||
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
|
||||
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
|
||||
* huk recovery mode.
|
||||
*/
|
||||
#define HUK_MODE (BIT(0))
|
||||
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
|
||||
#define HUK_MODE_V 0x00000001U
|
||||
#define HUK_MODE_S 0
|
||||
|
||||
/** HUK_START_REG register
|
||||
* HUK Generator control register
|
||||
*/
|
||||
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
|
||||
/** HUK_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
|
||||
*/
|
||||
#define HUK_START (BIT(0))
|
||||
#define HUK_START_M (HUK_START_V << HUK_START_S)
|
||||
#define HUK_START_V 0x00000001U
|
||||
#define HUK_START_S 0
|
||||
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to start HUK Generator at IDLE state.
|
||||
*/
|
||||
#define HUK_CONTINUE (BIT(1))
|
||||
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
|
||||
#define HUK_CONTINUE_V 0x00000001U
|
||||
#define HUK_CONTINUE_S 1
|
||||
|
||||
/** HUK_STATE_REG register
|
||||
* HUK Generator state register
|
||||
*/
|
||||
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
|
||||
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
|
||||
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
|
||||
*/
|
||||
#define HUK_STATE 0x00000003U
|
||||
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
|
||||
#define HUK_STATE_V 0x00000003U
|
||||
#define HUK_STATE_S 0
|
||||
|
||||
/** HUK_STATUS_REG register
|
||||
* HUK Generator HUK status register
|
||||
*/
|
||||
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
|
||||
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
|
||||
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
|
||||
* 2: HUK is generated but invalid. 3: reserved.
|
||||
*/
|
||||
#define HUK_STATUS 0x00000003U
|
||||
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
|
||||
#define HUK_STATUS_V 0x00000003U
|
||||
#define HUK_STATUS_S 0
|
||||
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
|
||||
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
|
||||
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
|
||||
*/
|
||||
#define HUK_RISK_LEVEL 0x00000007U
|
||||
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
|
||||
#define HUK_RISK_LEVEL_V 0x00000007U
|
||||
#define HUK_RISK_LEVEL_S 2
|
||||
|
||||
/** HUK_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
|
||||
/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
|
||||
* HUK Generator version control register.
|
||||
*/
|
||||
#define HUK_DATE 0x0FFFFFFFU
|
||||
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
|
||||
#define HUK_DATE_V 0x0FFFFFFFU
|
||||
#define HUK_DATE_S 0
|
||||
|
||||
/** HUK_INFO_MEM register
|
||||
* The memory that stores HUK info.
|
||||
*/
|
||||
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
|
||||
#define HUK_INFO_MEM_SIZE_BYTES 384
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
241
components/soc/esp32c5/include/soc/huk_struct.h
Normal file
241
components/soc/esp32c5/include/soc/huk_struct.h
Normal file
@@ -0,0 +1,241 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Memory data */
|
||||
|
||||
/** Group: Clock gate register */
|
||||
/** Type of clk register
|
||||
* HUK Generator clock gate control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to force on memory clock gate.
|
||||
*/
|
||||
uint32_t mem_cg_force_on:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* HUK Generator interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the huk_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_raw:1;
|
||||
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the huk_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_raw:1;
|
||||
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the huk_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* HUK Generator interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the huk_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_st:1;
|
||||
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the huk_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_st:1;
|
||||
/** post_done_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the huk_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* HUK Generator interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the huk_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_ena:1;
|
||||
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the huk_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_ena:1;
|
||||
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the huk_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* HUK Generator interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the huk_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_clr:1;
|
||||
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the huk_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_clr:1;
|
||||
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the huk_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of conf register
|
||||
* HUK Generator configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mode : R/W; bitpos: [0]; default: 0;
|
||||
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
|
||||
* huk recovery mode.
|
||||
*/
|
||||
uint32_t mode:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_conf_reg_t;
|
||||
|
||||
|
||||
/** Group: Control registers */
|
||||
/** Type of start register
|
||||
* HUK Generator control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** continue : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to start HUK Generator at IDLE state.
|
||||
*/
|
||||
uint32_t continue:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_start_reg_t;
|
||||
|
||||
|
||||
/** Group: State registers */
|
||||
/** Type of state register
|
||||
* HUK Generator state register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** state : RO; bitpos: [1:0]; default: 0;
|
||||
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
|
||||
*/
|
||||
uint32_t state:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Result registers */
|
||||
/** Type of status register
|
||||
* HUK Generator HUK status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** status : RO; bitpos: [1:0]; default: 0;
|
||||
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
|
||||
* 2: HUK is generated but invalid. 3: reserved.
|
||||
*/
|
||||
uint32_t status:2;
|
||||
/** risk_level : RO; bitpos: [4:2]; default: 0;
|
||||
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
|
||||
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
|
||||
*/
|
||||
uint32_t risk_level:3;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_status_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36720704;
|
||||
* HUK Generator version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} huk_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000;
|
||||
volatile huk_clk_reg_t clk;
|
||||
volatile huk_int_raw_reg_t int_raw;
|
||||
volatile huk_int_st_reg_t int_st;
|
||||
volatile huk_int_ena_reg_t int_ena;
|
||||
volatile huk_int_clr_reg_t int_clr;
|
||||
uint32_t reserved_018[2];
|
||||
volatile huk_conf_reg_t conf;
|
||||
volatile huk_start_reg_t start;
|
||||
volatile huk_state_reg_t state;
|
||||
uint32_t reserved_02c[2];
|
||||
volatile huk_status_reg_t status;
|
||||
uint32_t reserved_038[49];
|
||||
volatile huk_date_reg_t date;
|
||||
volatile uint32_t info[96];
|
||||
} huk_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1521
components/soc/esp32c5/include/soc/i2c_reg.h
Normal file
1521
components/soc/esp32c5/include/soc/i2c_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1277
components/soc/esp32c5/include/soc/i2c_struct.h
Normal file
1277
components/soc/esp32c5/include/soc/i2c_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
1268
components/soc/esp32c5/include/soc/i2s_reg.h
Normal file
1268
components/soc/esp32c5/include/soc/i2s_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1007
components/soc/esp32c5/include/soc/i2s_struct.h
Normal file
1007
components/soc/esp32c5/include/soc/i2s_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
135
components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h
Normal file
135
components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h
Normal file
@@ -0,0 +1,135 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
|
||||
/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
|
||||
#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C0_CTRL_S 0
|
||||
/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25))
|
||||
#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
|
||||
#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
|
||||
#define LP_I2C_ANA_MST_I2C0_BUSY_S 25
|
||||
|
||||
/** LP_I2C_ANA_MST_I2C0_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
|
||||
/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
|
||||
#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C0_CONF_S 0
|
||||
/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
|
||||
* reserved
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU
|
||||
#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
|
||||
#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
|
||||
#define LP_I2C_ANA_MST_I2C0_STATUS_S 24
|
||||
|
||||
/** LP_I2C_ANA_MST_I2C0_DATA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
|
||||
/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU
|
||||
#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
|
||||
#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU
|
||||
#define LP_I2C_ANA_MST_I2C0_RDATA_S 0
|
||||
/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U
|
||||
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
|
||||
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U
|
||||
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8
|
||||
/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
|
||||
* need des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11))
|
||||
#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
|
||||
#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U
|
||||
#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11
|
||||
|
||||
/** LP_I2C_ANA_MST_ANA_CONF1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
|
||||
/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
|
||||
#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
|
||||
#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
|
||||
#define LP_I2C_ANA_MST_ANA_CONF1_S 0
|
||||
|
||||
/** LP_I2C_ANA_MST_NOUSE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
|
||||
/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
|
||||
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0
|
||||
|
||||
/** LP_I2C_ANA_MST_DEVICE_EN_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
|
||||
/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU
|
||||
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
|
||||
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU
|
||||
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0
|
||||
|
||||
/** LP_I2C_ANA_MST_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
|
||||
/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0
|
||||
/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28))
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U
|
||||
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
150
components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
Normal file
150
components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: configure_register */
|
||||
/** Type of i2c0_ctrl register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c0_ctrl:25;
|
||||
/** i2c0_busy : RO; bitpos: [25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c0_busy:1;
|
||||
uint32_t reserved_26:6;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
|
||||
|
||||
/** Type of i2c0_conf register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c0_conf:24;
|
||||
/** i2c0_status : RO; bitpos: [31:24]; default: 7;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t i2c0_status:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_i2c0_conf_reg_t;
|
||||
|
||||
/** Type of i2c0_data register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c0_rdata:8;
|
||||
/** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c0_clk_sel:3;
|
||||
/** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
|
||||
* need des
|
||||
*/
|
||||
uint32_t i2c_mst_sel:1;
|
||||
uint32_t reserved_12:20;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_i2c0_data_reg_t;
|
||||
|
||||
/** Type of ana_conf1 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t ana_conf1:24;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_ana_conf1_reg_t;
|
||||
|
||||
/** Type of nouse register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c_mst_nouse:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_nouse_reg_t;
|
||||
|
||||
/** Type of device_en register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c_device_en:12;
|
||||
uint32_t reserved_12:20;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_device_en_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c_mat_date:28;
|
||||
/** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t i2c_mat_clk_en:1;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_i2c_ana_mst_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
|
||||
volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
|
||||
volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
|
||||
volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
|
||||
volatile lp_i2c_ana_mst_nouse_reg_t nouse;
|
||||
volatile lp_i2c_ana_mst_device_en_reg_t device_en;
|
||||
uint32_t reserved_018[249];
|
||||
volatile lp_i2c_ana_mst_date_reg_t date;
|
||||
} lp_i2c_ana_mst_dev_t;
|
||||
|
||||
extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
324
components/soc/esp32c5/include/soc/lp_wdt_reg.h
Normal file
324
components/soc/esp32c5/include/soc/lp_wdt_reg.h
Normal file
@@ -0,0 +1,324 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** LP_WDT_CONFIG0_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
|
||||
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
|
||||
/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
|
||||
/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
|
||||
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
|
||||
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
|
||||
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
|
||||
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG3 0x00000007U
|
||||
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
|
||||
#define LP_WDT_WDT_STG3_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG3_S 19
|
||||
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG2 0x00000007U
|
||||
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
|
||||
#define LP_WDT_WDT_STG2_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG2_S 22
|
||||
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG1 0x00000007U
|
||||
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
|
||||
#define LP_WDT_WDT_STG1_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG1_S 25
|
||||
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG0 0x00000007U
|
||||
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
|
||||
#define LP_WDT_WDT_STG0_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG0_S 28
|
||||
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_EN (BIT(31))
|
||||
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
|
||||
#define LP_WDT_WDT_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_EN_S 31
|
||||
|
||||
/** LP_WDT_CONFIG1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
|
||||
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
|
||||
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** LP_WDT_CONFIG2_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
|
||||
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
|
||||
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** LP_WDT_CONFIG3_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
|
||||
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
|
||||
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** LP_WDT_CONFIG4_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
|
||||
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
|
||||
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** LP_WDT_FEED_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
|
||||
/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_RTC_WDT_FEED (BIT(31))
|
||||
#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
|
||||
#define LP_WDT_RTC_WDT_FEED_V 0x00000001U
|
||||
#define LP_WDT_RTC_WDT_FEED_S 31
|
||||
|
||||
/** LP_WDT_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
|
||||
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
|
||||
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_WKEY_S 0
|
||||
|
||||
/** LP_WDT_SWD_CONFIG_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
|
||||
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
|
||||
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
|
||||
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
|
||||
#define LP_WDT_SWD_RESET_FLAG_S 0
|
||||
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
|
||||
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
|
||||
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
|
||||
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_DISABLE (BIT(30))
|
||||
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
|
||||
#define LP_WDT_SWD_DISABLE_V 0x00000001U
|
||||
#define LP_WDT_SWD_DISABLE_S 30
|
||||
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_FEED (BIT(31))
|
||||
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
|
||||
#define LP_WDT_SWD_FEED_V 0x00000001U
|
||||
#define LP_WDT_SWD_FEED_S 31
|
||||
|
||||
/** LP_WDT_SWD_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
|
||||
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
|
||||
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
|
||||
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
|
||||
#define LP_WDT_SWD_WKEY_S 0
|
||||
|
||||
/** LP_WDT_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
|
||||
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
|
||||
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
|
||||
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_RAW_S 31
|
||||
|
||||
/** LP_WDT_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
|
||||
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_S 30
|
||||
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
|
||||
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_ST_S 31
|
||||
|
||||
/** LP_WDT_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
|
||||
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
|
||||
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
|
||||
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_ENA_S 31
|
||||
|
||||
/** LP_WDT_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
|
||||
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
|
||||
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
|
||||
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_CLR_S 31
|
||||
|
||||
/** LP_WDT_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
|
||||
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
|
||||
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
|
||||
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
|
||||
#define LP_WDT_LP_WDT_DATE_S 0
|
||||
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CLK_EN (BIT(31))
|
||||
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
|
||||
#define LP_WDT_CLK_EN_V 0x00000001U
|
||||
#define LP_WDT_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
309
components/soc/esp32c5/include/soc/lp_wdt_struct.h
Normal file
309
components/soc/esp32c5/include/soc/lp_wdt_struct.h
Normal file
@@ -0,0 +1,309 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: configure_register */
|
||||
/** Type of config0 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_pause_in_slp:1;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en:1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en:1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en:1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length:3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length:3;
|
||||
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg3:3;
|
||||
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg2:3;
|
||||
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg1:3;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg0:3;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config0_reg_t;
|
||||
|
||||
/** Type of config1 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config1_reg_t;
|
||||
|
||||
/** Type of config2 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config2_reg_t;
|
||||
|
||||
/** Type of config3 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config3_reg_t;
|
||||
|
||||
/** Type of config4 register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config4_reg_t;
|
||||
|
||||
/** Type of feed register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** rtc_wdt_feed : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t rtc_wdt_feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_feed_reg_t;
|
||||
|
||||
/** Type of wprotect register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_wprotect_reg_t;
|
||||
|
||||
/** Type of swd_config register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_reset_flag:1;
|
||||
uint32_t reserved_1:17;
|
||||
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_auto_feed_en:1;
|
||||
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_rst_flag_clr:1;
|
||||
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_signal_width:10;
|
||||
/** swd_disable : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_disable:1;
|
||||
/** swd_feed : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_swd_config_reg_t;
|
||||
|
||||
/** Type of swd_wprotect register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t swd_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_swd_wprotect_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_raw:1;
|
||||
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_raw:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_st:1;
|
||||
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_st:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_ena:1;
|
||||
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_ena:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t super_wdt_int_clr:1;
|
||||
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_int_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_clr_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t lp_wdt_date:31;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile lp_wdt_config0_reg_t config0;
|
||||
volatile lp_wdt_config1_reg_t config1;
|
||||
volatile lp_wdt_config2_reg_t config2;
|
||||
volatile lp_wdt_config3_reg_t config3;
|
||||
volatile lp_wdt_config4_reg_t config4;
|
||||
volatile lp_wdt_feed_reg_t feed;
|
||||
volatile lp_wdt_wprotect_reg_t wprotect;
|
||||
volatile lp_wdt_swd_config_reg_t swd_config;
|
||||
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
|
||||
volatile lp_wdt_int_raw_reg_t int_raw;
|
||||
volatile lp_wdt_int_st_reg_t int_st;
|
||||
volatile lp_wdt_int_ena_reg_t int_ena;
|
||||
volatile lp_wdt_int_clr_reg_t int_clr;
|
||||
uint32_t reserved_034[242];
|
||||
volatile lp_wdt_date_reg_t date;
|
||||
} lp_wdt_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
4514
components/soc/esp32c5/include/soc/mcpwm_reg.h
Normal file
4514
components/soc/esp32c5/include/soc/mcpwm_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
2031
components/soc/esp32c5/include/soc/mcpwm_struct.h
Normal file
2031
components/soc/esp32c5/include/soc/mcpwm_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
480
components/soc/esp32c5/include/soc/parl_io_reg.h
Normal file
480
components/soc/esp32c5/include/soc/parl_io_reg.h
Normal file
@@ -0,0 +1,480 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** PARL_IO_RX_MODE_CFG_REG register
|
||||
* Parallel RX Sampling mode configuration register.
|
||||
*/
|
||||
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
|
||||
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
|
||||
* Configures rx external enable signal selection from IO PAD.
|
||||
*/
|
||||
#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
|
||||
#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
|
||||
#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
|
||||
#define PARL_IO_RX_EXT_EN_SEL_S 21
|
||||
/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
|
||||
* Set this bit to enable data sampling by software.
|
||||
*/
|
||||
#define PARL_IO_RX_SW_EN (BIT(25))
|
||||
#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
|
||||
#define PARL_IO_RX_SW_EN_V 0x00000001U
|
||||
#define PARL_IO_RX_SW_EN_S 25
|
||||
/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
|
||||
* Set this bit to invert the external enable signal.
|
||||
*/
|
||||
#define PARL_IO_RX_EXT_EN_INV (BIT(26))
|
||||
#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
|
||||
#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U
|
||||
#define PARL_IO_RX_EXT_EN_INV_S 26
|
||||
/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
|
||||
* Configures the rxd pulse sampling submode.
|
||||
* 4'd0: positive pulse start(data bit included) && positive pulse end(data bit
|
||||
* included)
|
||||
* 4'd1: positive pulse start(data bit included) && positive pulse end (data bit
|
||||
* excluded)
|
||||
* 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
|
||||
* included)
|
||||
* 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
|
||||
* excluded)
|
||||
* 4'd4: positive pulse start(data bit included) && length end
|
||||
* 4'd5: positive pulse start(data bit excluded) && length end
|
||||
*/
|
||||
#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U
|
||||
#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
|
||||
#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U
|
||||
#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27
|
||||
/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
|
||||
* Configures the rxd sampling mode.
|
||||
* 2'b00: external level enable mode
|
||||
* 2'b01: external pulse enable mode
|
||||
* 2'b10: internal software enable mode
|
||||
*/
|
||||
#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
|
||||
#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
|
||||
#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
|
||||
#define PARL_IO_RX_SMP_MODE_SEL_S 30
|
||||
|
||||
/** PARL_IO_RX_DATA_CFG_REG register
|
||||
* Parallel RX data configuration register.
|
||||
*/
|
||||
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
|
||||
/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
|
||||
* Configures expected byte number of received data.
|
||||
*/
|
||||
#define PARL_IO_RX_BITLEN 0x0007FFFFU
|
||||
#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
|
||||
#define PARL_IO_RX_BITLEN_V 0x0007FFFFU
|
||||
#define PARL_IO_RX_BITLEN_S 9
|
||||
/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
|
||||
* Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
|
||||
*/
|
||||
#define PARL_IO_RX_DATA_ORDER_INV (BIT(28))
|
||||
#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
|
||||
#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U
|
||||
#define PARL_IO_RX_DATA_ORDER_INV_S 28
|
||||
/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
|
||||
* Configures the rxd bus width.
|
||||
* 3'd0: bus width is 1.
|
||||
* 3'd1: bus width is 2.
|
||||
* 3'd2: bus width is 4.
|
||||
* 3'd3: bus width is 8.
|
||||
*/
|
||||
#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
|
||||
#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
|
||||
#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
|
||||
#define PARL_IO_RX_BUS_WID_SEL_S 29
|
||||
|
||||
/** PARL_IO_RX_GENRL_CFG_REG register
|
||||
* Parallel RX general configuration register.
|
||||
*/
|
||||
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
|
||||
/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
|
||||
* Set this bit to enable the clock gating of output rx clock.
|
||||
*/
|
||||
#define PARL_IO_RX_GATING_EN (BIT(12))
|
||||
#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
|
||||
#define PARL_IO_RX_GATING_EN_V 0x00000001U
|
||||
#define PARL_IO_RX_GATING_EN_S 12
|
||||
/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
|
||||
* Configures threshold of timeout counter.
|
||||
*/
|
||||
#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU
|
||||
#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
|
||||
#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU
|
||||
#define PARL_IO_RX_TIMEOUT_THRES_S 13
|
||||
/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
|
||||
* Set this bit to enable timeout function to generate error eof.
|
||||
*/
|
||||
#define PARL_IO_RX_TIMEOUT_EN (BIT(29))
|
||||
#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
|
||||
#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
|
||||
#define PARL_IO_RX_TIMEOUT_EN_S 29
|
||||
/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
|
||||
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
|
||||
* 1'b1: eof generated by external enable signal.
|
||||
*/
|
||||
#define PARL_IO_RX_EOF_GEN_SEL (BIT(30))
|
||||
#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
|
||||
#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
|
||||
#define PARL_IO_RX_EOF_GEN_SEL_S 30
|
||||
|
||||
/** PARL_IO_RX_START_CFG_REG register
|
||||
* Parallel RX Start configuration register.
|
||||
*/
|
||||
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
|
||||
/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start rx data sampling.
|
||||
*/
|
||||
#define PARL_IO_RX_START (BIT(31))
|
||||
#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
|
||||
#define PARL_IO_RX_START_V 0x00000001U
|
||||
#define PARL_IO_RX_START_S 31
|
||||
|
||||
/** PARL_IO_TX_DATA_CFG_REG register
|
||||
* Parallel TX data configuration register.
|
||||
*/
|
||||
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
|
||||
/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
|
||||
* Configures expected byte number of sent data.
|
||||
*/
|
||||
#define PARL_IO_TX_BITLEN 0x0007FFFFU
|
||||
#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
|
||||
#define PARL_IO_TX_BITLEN_V 0x0007FFFFU
|
||||
#define PARL_IO_TX_BITLEN_S 9
|
||||
/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
|
||||
* Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
|
||||
*/
|
||||
#define PARL_IO_TX_DATA_ORDER_INV (BIT(28))
|
||||
#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
|
||||
#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U
|
||||
#define PARL_IO_TX_DATA_ORDER_INV_S 28
|
||||
/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
|
||||
* Configures the txd bus width.
|
||||
* 3'd0: bus width is 1.
|
||||
* 3'd1: bus width is 2.
|
||||
* 3'd2: bus width is 4.
|
||||
* 3'd3: bus width is 8.
|
||||
*/
|
||||
#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
|
||||
#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
|
||||
#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
|
||||
#define PARL_IO_TX_BUS_WID_SEL_S 29
|
||||
|
||||
/** PARL_IO_TX_START_CFG_REG register
|
||||
* Parallel TX Start configuration register.
|
||||
*/
|
||||
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
|
||||
/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start tx data transmit.
|
||||
*/
|
||||
#define PARL_IO_TX_START (BIT(31))
|
||||
#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
|
||||
#define PARL_IO_TX_START_V 0x00000001U
|
||||
#define PARL_IO_TX_START_S 31
|
||||
|
||||
/** PARL_IO_TX_GENRL_CFG_REG register
|
||||
* Parallel TX general configuration register.
|
||||
*/
|
||||
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
|
||||
/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
|
||||
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
|
||||
* 1'b1: eof generated by DMA eof.
|
||||
*/
|
||||
#define PARL_IO_TX_EOF_GEN_SEL (BIT(13))
|
||||
#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
|
||||
#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U
|
||||
#define PARL_IO_TX_EOF_GEN_SEL_S 13
|
||||
/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
|
||||
* Configures bus value of transmitter in IDLE state.
|
||||
*/
|
||||
#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
|
||||
#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
|
||||
#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
|
||||
#define PARL_IO_TX_IDLE_VALUE_S 14
|
||||
/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to enable the clock gating of output tx clock.
|
||||
*/
|
||||
#define PARL_IO_TX_GATING_EN (BIT(30))
|
||||
#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
|
||||
#define PARL_IO_TX_GATING_EN_V 0x00000001U
|
||||
#define PARL_IO_TX_GATING_EN_S 30
|
||||
/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to enable the output of tx data valid signal.
|
||||
*/
|
||||
#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31))
|
||||
#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
|
||||
#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U
|
||||
#define PARL_IO_TX_VALID_OUTPUT_EN_S 31
|
||||
|
||||
/** PARL_IO_FIFO_CFG_REG register
|
||||
* Parallel IO FIFO configuration register.
|
||||
*/
|
||||
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
|
||||
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to reset async fifo in tx module.
|
||||
*/
|
||||
#define PARL_IO_TX_FIFO_SRST (BIT(30))
|
||||
#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
|
||||
#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
|
||||
#define PARL_IO_TX_FIFO_SRST_S 30
|
||||
/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to reset async fifo in rx module.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_SRST (BIT(31))
|
||||
#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
|
||||
#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
|
||||
#define PARL_IO_RX_FIFO_SRST_S 31
|
||||
|
||||
/** PARL_IO_REG_UPDATE_REG register
|
||||
* Parallel IO FIFO configuration register.
|
||||
*/
|
||||
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
|
||||
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
|
||||
* Set this bit to update rx register configuration.
|
||||
*/
|
||||
#define PARL_IO_RX_REG_UPDATE (BIT(31))
|
||||
#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
|
||||
#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
|
||||
#define PARL_IO_RX_REG_UPDATE_S 31
|
||||
|
||||
/** PARL_IO_ST_REG register
|
||||
* Parallel IO module status register0.
|
||||
*/
|
||||
#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
|
||||
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
|
||||
* Represents the status that tx is ready to transmit.
|
||||
*/
|
||||
#define PARL_IO_TX_READY (BIT(31))
|
||||
#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
|
||||
#define PARL_IO_TX_READY_V 0x00000001U
|
||||
#define PARL_IO_TX_READY_S 31
|
||||
|
||||
/** PARL_IO_INT_ENA_REG register
|
||||
* Parallel IO interrupt enable singal configuration register.
|
||||
*/
|
||||
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
|
||||
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
|
||||
/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Set this bit to enable RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1))
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1
|
||||
/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to enable TX_EOF_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
|
||||
#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
|
||||
#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
|
||||
#define PARL_IO_TX_EOF_INT_ENA_S 2
|
||||
|
||||
/** PARL_IO_INT_RAW_REG register
|
||||
* Parallel IO interrupt raw singal status register.
|
||||
*/
|
||||
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
|
||||
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
|
||||
/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status of RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1))
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1
|
||||
/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status of TX_EOF_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
|
||||
#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
|
||||
#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
|
||||
#define PARL_IO_TX_EOF_INT_RAW_S 2
|
||||
|
||||
/** PARL_IO_INT_ST_REG register
|
||||
* Parallel IO interrupt singal status register.
|
||||
*/
|
||||
#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
|
||||
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status of TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
|
||||
/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status of RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1))
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1
|
||||
/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status of TX_EOF_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_EOF_INT_ST (BIT(2))
|
||||
#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
|
||||
#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
|
||||
#define PARL_IO_TX_EOF_INT_ST_S 2
|
||||
|
||||
/** PARL_IO_INT_CLR_REG register
|
||||
* Parallel IO interrupt clear singal configuration register.
|
||||
*/
|
||||
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
|
||||
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
|
||||
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
|
||||
/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1))
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U
|
||||
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1
|
||||
/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear TX_EOF_INT.
|
||||
*/
|
||||
#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
|
||||
#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
|
||||
#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
|
||||
#define PARL_IO_TX_EOF_INT_CLR_S 2
|
||||
|
||||
/** PARL_IO_RX_ST0_REG register
|
||||
* Parallel IO RX status register0
|
||||
*/
|
||||
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
|
||||
/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
|
||||
* Indicates the cycle number of reading Rx FIFO.
|
||||
*/
|
||||
#define PARL_IO_RX_CNT 0x0000001FU
|
||||
#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
|
||||
#define PARL_IO_RX_CNT_V 0x0000001FU
|
||||
#define PARL_IO_RX_CNT_S 8
|
||||
/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
|
||||
* Indicates the current written bit number into Rx FIFO.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU
|
||||
#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
|
||||
#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU
|
||||
#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13
|
||||
|
||||
/** PARL_IO_RX_ST1_REG register
|
||||
* Parallel IO RX status register1
|
||||
*/
|
||||
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
|
||||
/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
|
||||
* Indicates the current read bit number from Rx FIFO.
|
||||
*/
|
||||
#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU
|
||||
#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
|
||||
#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
|
||||
#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13
|
||||
|
||||
/** PARL_IO_TX_ST0_REG register
|
||||
* Parallel IO TX status register0
|
||||
*/
|
||||
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
|
||||
/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
|
||||
* Indicates the cycle number of reading Tx FIFO.
|
||||
*/
|
||||
#define PARL_IO_TX_CNT 0x0000007FU
|
||||
#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
|
||||
#define PARL_IO_TX_CNT_V 0x0000007FU
|
||||
#define PARL_IO_TX_CNT_S 6
|
||||
/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
|
||||
* Indicates the current read bit number from Tx FIFO.
|
||||
*/
|
||||
#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU
|
||||
#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
|
||||
#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
|
||||
#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13
|
||||
|
||||
/** PARL_IO_RX_CLK_CFG_REG register
|
||||
* Parallel IO RX clk configuration register
|
||||
*/
|
||||
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
|
||||
/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to invert the input Rx core clock.
|
||||
*/
|
||||
#define PARL_IO_RX_CLK_I_INV (BIT(30))
|
||||
#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
|
||||
#define PARL_IO_RX_CLK_I_INV_V 0x00000001U
|
||||
#define PARL_IO_RX_CLK_I_INV_S 30
|
||||
/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to invert the output Rx core clock.
|
||||
*/
|
||||
#define PARL_IO_RX_CLK_O_INV (BIT(31))
|
||||
#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
|
||||
#define PARL_IO_RX_CLK_O_INV_V 0x00000001U
|
||||
#define PARL_IO_RX_CLK_O_INV_S 31
|
||||
|
||||
/** PARL_IO_TX_CLK_CFG_REG register
|
||||
* Parallel IO TX clk configuration register
|
||||
*/
|
||||
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
|
||||
/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to invert the input Tx core clock.
|
||||
*/
|
||||
#define PARL_IO_TX_CLK_I_INV (BIT(30))
|
||||
#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
|
||||
#define PARL_IO_TX_CLK_I_INV_V 0x00000001U
|
||||
#define PARL_IO_TX_CLK_I_INV_S 30
|
||||
/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to invert the output Tx core clock.
|
||||
*/
|
||||
#define PARL_IO_TX_CLK_O_INV (BIT(31))
|
||||
#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
|
||||
#define PARL_IO_TX_CLK_O_INV_V 0x00000001U
|
||||
#define PARL_IO_TX_CLK_O_INV_S 31
|
||||
|
||||
/** PARL_IO_CLK_REG register
|
||||
* Parallel IO clk configuration register
|
||||
*/
|
||||
#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
|
||||
/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Force clock on for this register file
|
||||
*/
|
||||
#define PARL_IO_CLK_EN (BIT(31))
|
||||
#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
|
||||
#define PARL_IO_CLK_EN_V 0x00000001U
|
||||
#define PARL_IO_CLK_EN_S 31
|
||||
|
||||
/** PARL_IO_VERSION_REG register
|
||||
* Version register.
|
||||
*/
|
||||
#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
|
||||
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
|
||||
* Version of this register file
|
||||
*/
|
||||
#define PARL_IO_DATE 0x0FFFFFFFU
|
||||
#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
|
||||
#define PARL_IO_DATE_V 0x0FFFFFFFU
|
||||
#define PARL_IO_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
509
components/soc/esp32c5/include/soc/parl_io_struct.h
Normal file
509
components/soc/esp32c5/include/soc/parl_io_struct.h
Normal file
@@ -0,0 +1,509 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: PARL_IO RX Mode Configuration */
|
||||
/** Type of rx_mode_cfg register
|
||||
* Parallel RX Sampling mode configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:21;
|
||||
/** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
|
||||
* Configures rx external enable signal selection from IO PAD.
|
||||
*/
|
||||
uint32_t rx_ext_en_sel:4;
|
||||
/** rx_sw_en : R/W; bitpos: [25]; default: 0;
|
||||
* Set this bit to enable data sampling by software.
|
||||
*/
|
||||
uint32_t rx_sw_en:1;
|
||||
/** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
|
||||
* Set this bit to invert the external enable signal.
|
||||
*/
|
||||
uint32_t rx_ext_en_inv:1;
|
||||
/** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
|
||||
* Configures the rxd pulse sampling submode.
|
||||
* 4'd0: positive pulse start(data bit included) && positive pulse end(data bit
|
||||
* included)
|
||||
* 4'd1: positive pulse start(data bit included) && positive pulse end (data bit
|
||||
* excluded)
|
||||
* 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
|
||||
* included)
|
||||
* 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
|
||||
* excluded)
|
||||
* 4'd4: positive pulse start(data bit included) && length end
|
||||
* 4'd5: positive pulse start(data bit excluded) && length end
|
||||
*/
|
||||
uint32_t rx_pulse_submode_sel:3;
|
||||
/** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
|
||||
* Configures the rxd sampling mode.
|
||||
* 2'b00: external level enable mode
|
||||
* 2'b01: external pulse enable mode
|
||||
* 2'b10: internal software enable mode
|
||||
*/
|
||||
uint32_t rx_smp_mode_sel:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_mode_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO RX Data Configuration */
|
||||
/** Type of rx_data_cfg register
|
||||
* Parallel RX data configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
|
||||
* Configures expected byte number of received data.
|
||||
*/
|
||||
uint32_t rx_bitlen:19;
|
||||
/** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
|
||||
* Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
|
||||
*/
|
||||
uint32_t rx_data_order_inv:1;
|
||||
/** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
|
||||
* Configures the rxd bus width.
|
||||
* 3'd0: bus width is 1.
|
||||
* 3'd1: bus width is 2.
|
||||
* 3'd2: bus width is 4.
|
||||
* 3'd3: bus width is 8.
|
||||
*/
|
||||
uint32_t rx_bus_wid_sel:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_data_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO RX General Configuration */
|
||||
/** Type of rx_genrl_cfg register
|
||||
* Parallel RX general configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** rx_gating_en : R/W; bitpos: [12]; default: 0;
|
||||
* Set this bit to enable the clock gating of output rx clock.
|
||||
*/
|
||||
uint32_t rx_gating_en:1;
|
||||
/** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
|
||||
* Configures threshold of timeout counter.
|
||||
*/
|
||||
uint32_t rx_timeout_thres:16;
|
||||
/** rx_timeout_en : R/W; bitpos: [29]; default: 1;
|
||||
* Set this bit to enable timeout function to generate error eof.
|
||||
*/
|
||||
uint32_t rx_timeout_en:1;
|
||||
/** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
|
||||
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
|
||||
* 1'b1: eof generated by external enable signal.
|
||||
*/
|
||||
uint32_t rx_eof_gen_sel:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_genrl_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO RX Start Configuration */
|
||||
/** Type of rx_start_cfg register
|
||||
* Parallel RX Start configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** rx_start : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start rx data sampling.
|
||||
*/
|
||||
uint32_t rx_start:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_start_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO TX Data Configuration */
|
||||
/** Type of tx_data_cfg register
|
||||
* Parallel TX data configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
|
||||
* Configures expected byte number of sent data.
|
||||
*/
|
||||
uint32_t tx_bitlen:19;
|
||||
/** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
|
||||
* Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
|
||||
*/
|
||||
uint32_t tx_data_order_inv:1;
|
||||
/** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
|
||||
* Configures the txd bus width.
|
||||
* 3'd0: bus width is 1.
|
||||
* 3'd1: bus width is 2.
|
||||
* 3'd2: bus width is 4.
|
||||
* 3'd3: bus width is 8.
|
||||
*/
|
||||
uint32_t tx_bus_wid_sel:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_tx_data_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO TX Start Configuration */
|
||||
/** Type of tx_start_cfg register
|
||||
* Parallel TX Start configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_start : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start tx data transmit.
|
||||
*/
|
||||
uint32_t tx_start:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_tx_start_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO TX General Configuration */
|
||||
/** Type of tx_genrl_cfg register
|
||||
* Parallel TX general configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:13;
|
||||
/** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
|
||||
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
|
||||
* 1'b1: eof generated by DMA eof.
|
||||
*/
|
||||
uint32_t tx_eof_gen_sel:1;
|
||||
/** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
|
||||
* Configures bus value of transmitter in IDLE state.
|
||||
*/
|
||||
uint32_t tx_idle_value:16;
|
||||
/** tx_gating_en : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to enable the clock gating of output tx clock.
|
||||
*/
|
||||
uint32_t tx_gating_en:1;
|
||||
/** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to enable the output of tx data valid signal.
|
||||
*/
|
||||
uint32_t tx_valid_output_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_tx_genrl_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO FIFO Configuration */
|
||||
/** Type of fifo_cfg register
|
||||
* Parallel IO FIFO configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to reset async fifo in tx module.
|
||||
*/
|
||||
uint32_t tx_fifo_srst:1;
|
||||
/** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to reset async fifo in rx module.
|
||||
*/
|
||||
uint32_t rx_fifo_srst:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_fifo_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Register Update Configuration */
|
||||
/** Type of reg_update register
|
||||
* Parallel IO FIFO configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** rx_reg_update : WT; bitpos: [31]; default: 0;
|
||||
* Set this bit to update rx register configuration.
|
||||
*/
|
||||
uint32_t rx_reg_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_reg_update_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Status */
|
||||
/** Type of st register
|
||||
* Parallel IO module status register0.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_ready : RO; bitpos: [31]; default: 0;
|
||||
* Represents the status that tx is ready to transmit.
|
||||
*/
|
||||
uint32_t tx_ready:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_st_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Interrupt Configuration and Status */
|
||||
/** Type of int_ena register
|
||||
* Parallel IO interrupt enable singal configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
uint32_t tx_fifo_rempty_int_ena:1;
|
||||
/** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Set this bit to enable RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
uint32_t rx_fifo_wovf_int_ena:1;
|
||||
/** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to enable TX_EOF_INT.
|
||||
*/
|
||||
uint32_t tx_eof_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* Parallel IO interrupt raw singal status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
uint32_t tx_fifo_rempty_int_raw:1;
|
||||
/** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status of RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
uint32_t rx_fifo_wovf_int_raw:1;
|
||||
/** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status of TX_EOF_INT.
|
||||
*/
|
||||
uint32_t tx_eof_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* Parallel IO interrupt singal status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status of TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
uint32_t tx_fifo_rempty_int_st:1;
|
||||
/** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status of RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
uint32_t rx_fifo_wovf_int_st:1;
|
||||
/** tx_eof_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status of TX_EOF_INT.
|
||||
*/
|
||||
uint32_t tx_eof_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_int_st_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Parallel IO interrupt clear singal configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear TX_FIFO_REMPTY_INT.
|
||||
*/
|
||||
uint32_t tx_fifo_rempty_int_clr:1;
|
||||
/** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear RX_FIFO_WOVF_INT.
|
||||
*/
|
||||
uint32_t rx_fifo_wovf_int_clr:1;
|
||||
/** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear TX_EOF_INT.
|
||||
*/
|
||||
uint32_t tx_eof_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Rx Status0 */
|
||||
/** Type of rx_st0 register
|
||||
* Parallel IO RX status register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:8;
|
||||
/** rx_cnt : RO; bitpos: [12:8]; default: 0;
|
||||
* Indicates the cycle number of reading Rx FIFO.
|
||||
*/
|
||||
uint32_t rx_cnt:5;
|
||||
/** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
|
||||
* Indicates the current written bit number into Rx FIFO.
|
||||
*/
|
||||
uint32_t rx_fifo_wr_bit_cnt:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_st0_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Rx Status1 */
|
||||
/** Type of rx_st1 register
|
||||
* Parallel IO RX status register1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:13;
|
||||
/** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
|
||||
* Indicates the current read bit number from Rx FIFO.
|
||||
*/
|
||||
uint32_t rx_fifo_rd_bit_cnt:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_st1_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Tx Status0 */
|
||||
/** Type of tx_st0 register
|
||||
* Parallel IO TX status register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:6;
|
||||
/** tx_cnt : RO; bitpos: [12:6]; default: 0;
|
||||
* Indicates the cycle number of reading Tx FIFO.
|
||||
*/
|
||||
uint32_t tx_cnt:7;
|
||||
/** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
|
||||
* Indicates the current read bit number from Tx FIFO.
|
||||
*/
|
||||
uint32_t tx_fifo_rd_bit_cnt:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_tx_st0_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Rx Clock Configuration */
|
||||
/** Type of rx_clk_cfg register
|
||||
* Parallel IO RX clk configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to invert the input Rx core clock.
|
||||
*/
|
||||
uint32_t rx_clk_i_inv:1;
|
||||
/** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to invert the output Rx core clock.
|
||||
*/
|
||||
uint32_t rx_clk_o_inv:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_rx_clk_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Tx Clock Configuration */
|
||||
/** Type of tx_clk_cfg register
|
||||
* Parallel IO TX clk configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:30;
|
||||
/** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
|
||||
* Set this bit to invert the input Tx core clock.
|
||||
*/
|
||||
uint32_t tx_clk_i_inv:1;
|
||||
/** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to invert the output Tx core clock.
|
||||
*/
|
||||
uint32_t tx_clk_o_inv:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_tx_clk_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Clock Configuration */
|
||||
/** Type of clk register
|
||||
* Parallel IO clk configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Force clock on for this register file
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: PARL_IO Version Register */
|
||||
/** Type of version register
|
||||
* Version register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 35725920;
|
||||
* Version of this register file
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} parl_io_version_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
|
||||
volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
|
||||
volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
|
||||
volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
|
||||
volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
|
||||
volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
|
||||
volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
|
||||
volatile parl_io_fifo_cfg_reg_t fifo_cfg;
|
||||
volatile parl_io_reg_update_reg_t reg_update;
|
||||
volatile parl_io_st_reg_t st;
|
||||
volatile parl_io_int_ena_reg_t int_ena;
|
||||
volatile parl_io_int_raw_reg_t int_raw;
|
||||
volatile parl_io_int_st_reg_t int_st;
|
||||
volatile parl_io_int_clr_reg_t int_clr;
|
||||
volatile parl_io_rx_st0_reg_t rx_st0;
|
||||
volatile parl_io_rx_st1_reg_t rx_st1;
|
||||
volatile parl_io_tx_st0_reg_t tx_st0;
|
||||
volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
|
||||
volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
|
||||
uint32_t reserved_04c[53];
|
||||
volatile parl_io_clk_reg_t clk;
|
||||
uint32_t reserved_124[182];
|
||||
volatile parl_io_version_reg_t version;
|
||||
} parl_io_dev_t;
|
||||
|
||||
extern parl_io_dev_t PARL_IO;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
233
components/soc/esp32c5/include/soc/rsa_reg.h
Normal file
233
components/soc/esp32c5/include/soc/rsa_reg.h
Normal file
@@ -0,0 +1,233 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** RSA_M_MEM register
|
||||
* Represents M
|
||||
*/
|
||||
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
|
||||
#define RSA_M_MEM_SIZE_BYTES 16
|
||||
|
||||
/** RSA_Z_MEM register
|
||||
* Represents Z
|
||||
*/
|
||||
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
|
||||
#define RSA_Z_MEM_SIZE_BYTES 16
|
||||
|
||||
/** RSA_Y_MEM register
|
||||
* Represents Y
|
||||
*/
|
||||
#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
|
||||
#define RSA_Y_MEM_SIZE_BYTES 16
|
||||
|
||||
/** RSA_X_MEM register
|
||||
* Represents X
|
||||
*/
|
||||
#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
|
||||
#define RSA_X_MEM_SIZE_BYTES 16
|
||||
|
||||
/** RSA_M_PRIME_REG register
|
||||
* Represents M’
|
||||
*/
|
||||
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
|
||||
/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
|
||||
* Represents M’
|
||||
*/
|
||||
#define RSA_M_PRIME 0xFFFFFFFFU
|
||||
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
|
||||
#define RSA_M_PRIME_V 0xFFFFFFFFU
|
||||
#define RSA_M_PRIME_S 0
|
||||
|
||||
/** RSA_MODE_REG register
|
||||
* Configures RSA length
|
||||
*/
|
||||
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
|
||||
/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
|
||||
* Configures the RSA length.
|
||||
*/
|
||||
#define RSA_MODE 0x0000007FU
|
||||
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
|
||||
#define RSA_MODE_V 0x0000007FU
|
||||
#define RSA_MODE_S 0
|
||||
|
||||
/** RSA_QUERY_CLEAN_REG register
|
||||
* RSA clean register
|
||||
*/
|
||||
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
|
||||
/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether or not the RSA memory completes initialization.
|
||||
*
|
||||
* 0: Not complete
|
||||
*
|
||||
* 1: Completed
|
||||
*
|
||||
*/
|
||||
#define RSA_QUERY_CLEAN (BIT(0))
|
||||
#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
|
||||
#define RSA_QUERY_CLEAN_V 0x00000001U
|
||||
#define RSA_QUERY_CLEAN_S 0
|
||||
|
||||
/** RSA_SET_START_MODEXP_REG register
|
||||
* Starts modular exponentiation
|
||||
*/
|
||||
#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
|
||||
/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not to start the modular exponentiation.
|
||||
*
|
||||
* 0: No effect
|
||||
*
|
||||
* 1: Start
|
||||
*
|
||||
*/
|
||||
#define RSA_SET_START_MODEXP (BIT(0))
|
||||
#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
|
||||
#define RSA_SET_START_MODEXP_V 0x00000001U
|
||||
#define RSA_SET_START_MODEXP_S 0
|
||||
|
||||
/** RSA_SET_START_MODMULT_REG register
|
||||
* Starts modular multiplication
|
||||
*/
|
||||
#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
|
||||
/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not to start the modular multiplication.
|
||||
*
|
||||
* 0: No effect
|
||||
*
|
||||
* 1: Start
|
||||
*
|
||||
*/
|
||||
#define RSA_SET_START_MODMULT (BIT(0))
|
||||
#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
|
||||
#define RSA_SET_START_MODMULT_V 0x00000001U
|
||||
#define RSA_SET_START_MODMULT_S 0
|
||||
|
||||
/** RSA_SET_START_MULT_REG register
|
||||
* Starts multiplication
|
||||
*/
|
||||
#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
|
||||
/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not to start the multiplication.
|
||||
*
|
||||
* 0: No effect
|
||||
*
|
||||
* 1: Start
|
||||
*
|
||||
*/
|
||||
#define RSA_SET_START_MULT (BIT(0))
|
||||
#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
|
||||
#define RSA_SET_START_MULT_V 0x00000001U
|
||||
#define RSA_SET_START_MULT_S 0
|
||||
|
||||
/** RSA_QUERY_IDLE_REG register
|
||||
* Represents the RSA status
|
||||
*/
|
||||
#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
|
||||
/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
|
||||
* Represents the RSA status.
|
||||
*
|
||||
* 0: Busy
|
||||
*
|
||||
* 1: Idle
|
||||
*
|
||||
*/
|
||||
#define RSA_QUERY_IDLE (BIT(0))
|
||||
#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
|
||||
#define RSA_QUERY_IDLE_V 0x00000001U
|
||||
#define RSA_QUERY_IDLE_S 0
|
||||
|
||||
/** RSA_INT_CLR_REG register
|
||||
* Clears RSA interrupt
|
||||
*/
|
||||
#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
|
||||
/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear the RSA interrupt.
|
||||
*/
|
||||
#define RSA_CLEAR_INTERRUPT (BIT(0))
|
||||
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
|
||||
#define RSA_CLEAR_INTERRUPT_V 0x00000001U
|
||||
#define RSA_CLEAR_INTERRUPT_S 0
|
||||
|
||||
/** RSA_CONSTANT_TIME_REG register
|
||||
* Configures the constant_time option
|
||||
*/
|
||||
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
|
||||
/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
|
||||
* Configures the constant_time option.
|
||||
*
|
||||
* 0: Acceleration
|
||||
*
|
||||
* 1: No acceleration (default)
|
||||
*
|
||||
*/
|
||||
#define RSA_CONSTANT_TIME (BIT(0))
|
||||
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
|
||||
#define RSA_CONSTANT_TIME_V 0x00000001U
|
||||
#define RSA_CONSTANT_TIME_S 0
|
||||
|
||||
/** RSA_SEARCH_ENABLE_REG register
|
||||
* Configures the search option
|
||||
*/
|
||||
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
|
||||
/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
|
||||
* Configure the search option.
|
||||
*
|
||||
* 0: No acceleration (default)
|
||||
*
|
||||
* 1: Acceleration
|
||||
*
|
||||
* This option should be used together with RSA_SEARCH_POS.
|
||||
*/
|
||||
#define RSA_SEARCH_ENABLE (BIT(0))
|
||||
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
|
||||
#define RSA_SEARCH_ENABLE_V 0x00000001U
|
||||
#define RSA_SEARCH_ENABLE_S 0
|
||||
|
||||
/** RSA_SEARCH_POS_REG register
|
||||
* Configures the search position
|
||||
*/
|
||||
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
|
||||
/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
|
||||
* Configures the starting address to start search. This field should be used together
|
||||
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
|
||||
*/
|
||||
#define RSA_SEARCH_POS 0x00000FFFU
|
||||
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
|
||||
#define RSA_SEARCH_POS_V 0x00000FFFU
|
||||
#define RSA_SEARCH_POS_S 0
|
||||
|
||||
/** RSA_INT_ENA_REG register
|
||||
* Enables the RSA interrupt
|
||||
*/
|
||||
#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
|
||||
/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable the RSA interrupt.
|
||||
*/
|
||||
#define RSA_INT_ENA (BIT(0))
|
||||
#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S)
|
||||
#define RSA_INT_ENA_V 0x00000001U
|
||||
#define RSA_INT_ENA_S 0
|
||||
|
||||
/** RSA_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
|
||||
/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
|
||||
* Version control register.
|
||||
*/
|
||||
#define RSA_DATE 0x3FFFFFFFU
|
||||
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
|
||||
#define RSA_DATE_V 0x3FFFFFFFU
|
||||
#define RSA_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
273
components/soc/esp32c5/include/soc/rsa_struct.h
Normal file
273
components/soc/esp32c5/include/soc/rsa_struct.h
Normal file
@@ -0,0 +1,273 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Memory */
|
||||
|
||||
/** Group: Control / Configuration Registers */
|
||||
/** Type of m_prime register
|
||||
* Represents M’
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** m_prime : R/W; bitpos: [31:0]; default: 0;
|
||||
* Represents M’
|
||||
*/
|
||||
uint32_t m_prime:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_m_prime_reg_t;
|
||||
|
||||
/** Type of mode register
|
||||
* Configures RSA length
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mode : R/W; bitpos: [6:0]; default: 0;
|
||||
* Configures the RSA length.
|
||||
*/
|
||||
uint32_t mode:7;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_mode_reg_t;
|
||||
|
||||
/** Type of set_start_modexp register
|
||||
* Starts modular exponentiation
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** set_start_modexp : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not to start the modular exponentiation.
|
||||
*
|
||||
* 0: No effect
|
||||
*
|
||||
* 1: Start
|
||||
*
|
||||
*/
|
||||
uint32_t set_start_modexp:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_set_start_modexp_reg_t;
|
||||
|
||||
/** Type of set_start_modmult register
|
||||
* Starts modular multiplication
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** set_start_modmult : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not to start the modular multiplication.
|
||||
*
|
||||
* 0: No effect
|
||||
*
|
||||
* 1: Start
|
||||
*
|
||||
*/
|
||||
uint32_t set_start_modmult:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_set_start_modmult_reg_t;
|
||||
|
||||
/** Type of set_start_mult register
|
||||
* Starts multiplication
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** set_start_mult : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not to start the multiplication.
|
||||
*
|
||||
* 0: No effect
|
||||
*
|
||||
* 1: Start
|
||||
*
|
||||
*/
|
||||
uint32_t set_start_mult:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_set_start_mult_reg_t;
|
||||
|
||||
/** Type of query_idle register
|
||||
* Represents the RSA status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** query_idle : RO; bitpos: [0]; default: 0;
|
||||
* Represents the RSA status.
|
||||
*
|
||||
* 0: Busy
|
||||
*
|
||||
* 1: Idle
|
||||
*
|
||||
*/
|
||||
uint32_t query_idle:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_query_idle_reg_t;
|
||||
|
||||
/** Type of constant_time register
|
||||
* Configures the constant_time option
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** constant_time : R/W; bitpos: [0]; default: 1;
|
||||
* Configures the constant_time option.
|
||||
*
|
||||
* 0: Acceleration
|
||||
*
|
||||
* 1: No acceleration (default)
|
||||
*
|
||||
*/
|
||||
uint32_t constant_time:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_constant_time_reg_t;
|
||||
|
||||
/** Type of search_enable register
|
||||
* Configures the search option
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** search_enable : R/W; bitpos: [0]; default: 0;
|
||||
* Configure the search option.
|
||||
*
|
||||
* 0: No acceleration (default)
|
||||
*
|
||||
* 1: Acceleration
|
||||
*
|
||||
* This option should be used together with RSA_SEARCH_POS.
|
||||
*/
|
||||
uint32_t search_enable:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_search_enable_reg_t;
|
||||
|
||||
/** Type of search_pos register
|
||||
* Configures the search position
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** search_pos : R/W; bitpos: [11:0]; default: 0;
|
||||
* Configures the starting address to start search. This field should be used together
|
||||
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
|
||||
*/
|
||||
uint32_t search_pos:12;
|
||||
uint32_t reserved_12:20;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_search_pos_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Register */
|
||||
/** Type of query_clean register
|
||||
* RSA clean register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** query_clean : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether or not the RSA memory completes initialization.
|
||||
*
|
||||
* 0: Not complete
|
||||
*
|
||||
* 1: Completed
|
||||
*
|
||||
*/
|
||||
uint32_t query_clean:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_query_clean_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Registers */
|
||||
/** Type of int_clr register
|
||||
* Clears RSA interrupt
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clear_interrupt : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear the RSA interrupt.
|
||||
*/
|
||||
uint32_t clear_interrupt:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_int_clr_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* Enables the RSA interrupt
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable the RSA interrupt.
|
||||
*/
|
||||
uint32_t int_ena:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_int_ena_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Control Register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [29:0]; default: 538969624;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:30;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} rsa_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t m[4];
|
||||
uint32_t reserved_010[124];
|
||||
volatile uint32_t z[4];
|
||||
uint32_t reserved_210[124];
|
||||
volatile uint32_t y[4];
|
||||
uint32_t reserved_410[124];
|
||||
volatile uint32_t x[4];
|
||||
uint32_t reserved_610[124];
|
||||
volatile rsa_m_prime_reg_t m_prime;
|
||||
volatile rsa_mode_reg_t mode;
|
||||
volatile rsa_query_clean_reg_t query_clean;
|
||||
volatile rsa_set_start_modexp_reg_t set_start_modexp;
|
||||
volatile rsa_set_start_modmult_reg_t set_start_modmult;
|
||||
volatile rsa_set_start_mult_reg_t set_start_mult;
|
||||
volatile rsa_query_idle_reg_t query_idle;
|
||||
volatile rsa_int_clr_reg_t int_clr;
|
||||
volatile rsa_constant_time_reg_t constant_time;
|
||||
volatile rsa_search_enable_reg_t search_enable;
|
||||
volatile rsa_search_pos_reg_t search_pos;
|
||||
volatile rsa_int_ena_reg_t int_ena;
|
||||
volatile rsa_date_reg_t date;
|
||||
} rsa_dev_t;
|
||||
|
||||
extern rsa_dev_t RSA;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
148
components/soc/esp32c5/include/soc/sha_reg.h
Normal file
148
components/soc/esp32c5/include/soc/sha_reg.h
Normal file
@@ -0,0 +1,148 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SHA_MODE_REG register
|
||||
* Initial configuration register.
|
||||
*/
|
||||
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
|
||||
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* Sha mode.
|
||||
*/
|
||||
#define SHA_MODE 0x00000007U
|
||||
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
|
||||
#define SHA_MODE_V 0x00000007U
|
||||
#define SHA_MODE_S 0
|
||||
|
||||
/** SHA_DMA_BLOCK_NUM_REG register
|
||||
* DMA configuration register 0.
|
||||
*/
|
||||
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
|
||||
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
|
||||
* Dma-sha block number.
|
||||
*/
|
||||
#define SHA_DMA_BLOCK_NUM 0x0000003FU
|
||||
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
|
||||
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
|
||||
#define SHA_DMA_BLOCK_NUM_S 0
|
||||
|
||||
/** SHA_START_REG register
|
||||
* Typical SHA configuration register 0.
|
||||
*/
|
||||
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
|
||||
/** SHA_START : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
*/
|
||||
#define SHA_START 0x7FFFFFFFU
|
||||
#define SHA_START_M (SHA_START_V << SHA_START_S)
|
||||
#define SHA_START_V 0x7FFFFFFFU
|
||||
#define SHA_START_S 1
|
||||
|
||||
/** SHA_CONTINUE_REG register
|
||||
* Typical SHA configuration register 1.
|
||||
*/
|
||||
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
|
||||
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
*/
|
||||
#define SHA_CONTINUE 0x7FFFFFFFU
|
||||
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
|
||||
#define SHA_CONTINUE_V 0x7FFFFFFFU
|
||||
#define SHA_CONTINUE_S 1
|
||||
|
||||
/** SHA_BUSY_REG register
|
||||
* Busy register.
|
||||
*/
|
||||
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
|
||||
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
|
||||
* Sha busy state. 1'b0: idle. 1'b1: busy.
|
||||
*/
|
||||
#define SHA_BUSY_STATE (BIT(0))
|
||||
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
|
||||
#define SHA_BUSY_STATE_V 0x00000001U
|
||||
#define SHA_BUSY_STATE_S 0
|
||||
|
||||
/** SHA_DMA_START_REG register
|
||||
* DMA configuration register 1.
|
||||
*/
|
||||
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
|
||||
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
|
||||
* Start dma-sha.
|
||||
*/
|
||||
#define SHA_DMA_START (BIT(0))
|
||||
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
|
||||
#define SHA_DMA_START_V 0x00000001U
|
||||
#define SHA_DMA_START_S 0
|
||||
|
||||
/** SHA_DMA_CONTINUE_REG register
|
||||
* DMA configuration register 2.
|
||||
*/
|
||||
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
|
||||
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
|
||||
* Continue dma-sha.
|
||||
*/
|
||||
#define SHA_DMA_CONTINUE (BIT(0))
|
||||
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
|
||||
#define SHA_DMA_CONTINUE_V 0x00000001U
|
||||
#define SHA_DMA_CONTINUE_S 0
|
||||
|
||||
/** SHA_CLEAR_IRQ_REG register
|
||||
* Interrupt clear register.
|
||||
*/
|
||||
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
|
||||
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
|
||||
* Clear sha interrupt.
|
||||
*/
|
||||
#define SHA_CLEAR_INTERRUPT (BIT(0))
|
||||
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
|
||||
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
|
||||
#define SHA_CLEAR_INTERRUPT_S 0
|
||||
|
||||
/** SHA_IRQ_ENA_REG register
|
||||
* Interrupt enable register.
|
||||
*/
|
||||
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
|
||||
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
|
||||
*/
|
||||
#define SHA_INTERRUPT_ENA (BIT(0))
|
||||
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
|
||||
#define SHA_INTERRUPT_ENA_V 0x00000001U
|
||||
#define SHA_INTERRUPT_ENA_S 0
|
||||
|
||||
/** SHA_DATE_REG register
|
||||
* Date register.
|
||||
*/
|
||||
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
|
||||
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
|
||||
* Sha date information/ sha version information.
|
||||
*/
|
||||
#define SHA_DATE 0x3FFFFFFFU
|
||||
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
|
||||
#define SHA_DATE_V 0x3FFFFFFFU
|
||||
#define SHA_DATE_S 0
|
||||
|
||||
/** SHA_H_MEM register
|
||||
* Sha H memory which contains intermediate hash or finial hash.
|
||||
*/
|
||||
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
|
||||
#define SHA_H_MEM_SIZE_BYTES 64
|
||||
|
||||
/** SHA_M_MEM register
|
||||
* Sha M memory which contains message.
|
||||
*/
|
||||
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
|
||||
#define SHA_M_MEM_SIZE_BYTES 64
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
188
components/soc/esp32c5/include/soc/sha_struct.h
Normal file
188
components/soc/esp32c5/include/soc/sha_struct.h
Normal file
@@ -0,0 +1,188 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration Register */
|
||||
/** Type of mode register
|
||||
* Initial configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mode : R/W; bitpos: [2:0]; default: 0;
|
||||
* Sha mode.
|
||||
*/
|
||||
uint32_t mode:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_mode_reg_t;
|
||||
|
||||
/** Type of dma_block_num register
|
||||
* DMA configuration register 0.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
|
||||
* Dma-sha block number.
|
||||
*/
|
||||
uint32_t dma_block_num:6;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_dma_block_num_reg_t;
|
||||
|
||||
/** Type of start register
|
||||
* Typical SHA configuration register 0.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:1;
|
||||
/** start : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
*/
|
||||
uint32_t start:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_start_reg_t;
|
||||
|
||||
/** Type of continue register
|
||||
* Typical SHA configuration register 1.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:1;
|
||||
/** continue : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
*/
|
||||
uint32_t continue:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_continue_reg_t;
|
||||
|
||||
/** Type of dma_start register
|
||||
* DMA configuration register 1.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_start : WO; bitpos: [0]; default: 0;
|
||||
* Start dma-sha.
|
||||
*/
|
||||
uint32_t dma_start:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_dma_start_reg_t;
|
||||
|
||||
/** Type of dma_continue register
|
||||
* DMA configuration register 2.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_continue : WO; bitpos: [0]; default: 0;
|
||||
* Continue dma-sha.
|
||||
*/
|
||||
uint32_t dma_continue:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_dma_continue_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Register */
|
||||
/** Type of busy register
|
||||
* Busy register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** busy_state : RO; bitpos: [0]; default: 0;
|
||||
* Sha busy state. 1'b0: idle. 1'b1: busy.
|
||||
*/
|
||||
uint32_t busy_state:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_busy_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Register */
|
||||
/** Type of clear_irq register
|
||||
* Interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clear_interrupt : WO; bitpos: [0]; default: 0;
|
||||
* Clear sha interrupt.
|
||||
*/
|
||||
uint32_t clear_interrupt:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_clear_irq_reg_t;
|
||||
|
||||
/** Type of irq_ena register
|
||||
* Interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** interrupt_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
|
||||
*/
|
||||
uint32_t interrupt_ena:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_irq_ena_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* Date register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [29:0]; default: 538972713;
|
||||
* Sha date information/ sha version information.
|
||||
*/
|
||||
uint32_t date:30;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_date_reg_t;
|
||||
|
||||
|
||||
/** Group: memory type */
|
||||
|
||||
typedef struct {
|
||||
volatile sha_mode_reg_t mode;
|
||||
uint32_t reserved_004[2];
|
||||
volatile sha_dma_block_num_reg_t dma_block_num;
|
||||
volatile sha_start_reg_t start;
|
||||
volatile sha_continue_reg_t continue;
|
||||
volatile sha_busy_reg_t busy;
|
||||
volatile sha_dma_start_reg_t dma_start;
|
||||
volatile sha_dma_continue_reg_t dma_continue;
|
||||
volatile sha_clear_irq_reg_t clear_irq;
|
||||
volatile sha_irq_ena_reg_t irq_ena;
|
||||
volatile sha_date_reg_t date;
|
||||
uint32_t reserved_030[4];
|
||||
volatile uint32_t h[16];
|
||||
volatile uint32_t m[16];
|
||||
} sha_dev_t;
|
||||
|
||||
extern sha_dev_t SHA;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
6867
components/soc/esp32c5/include/soc/soc_etm_reg.h
Normal file
6867
components/soc/esp32c5/include/soc/soc_etm_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
5116
components/soc/esp32c5/include/soc/soc_etm_struct.h
Normal file
5116
components/soc/esp32c5/include/soc/soc_etm_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
2116
components/soc/esp32c5/include/soc/spi_reg.h
Normal file
2116
components/soc/esp32c5/include/soc/spi_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1615
components/soc/esp32c5/include/soc/spi_struct.h
Normal file
1615
components/soc/esp32c5/include/soc/spi_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
630
components/soc/esp32c5/include/soc/systimer_reg.h
Normal file
630
components/soc/esp32c5/include/soc/systimer_reg.h
Normal file
@@ -0,0 +1,630 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SYSTIMER_CONF_REG register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
|
||||
/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
|
||||
* enable systimer's etm task and event
|
||||
*/
|
||||
#define SYSTIMER_ETM_EN (BIT(1))
|
||||
#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
|
||||
#define SYSTIMER_ETM_EN_V 0x00000001U
|
||||
#define SYSTIMER_ETM_EN_S 1
|
||||
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_WORK_EN_S 22
|
||||
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_WORK_EN_S 23
|
||||
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_WORK_EN_S 24
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
|
||||
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
|
||||
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
#define SYSTIMER_CLK_EN (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
|
||||
#define SYSTIMER_CLK_EN_V 0x00000001U
|
||||
#define SYSTIMER_CLK_EN_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_OP_REG register
|
||||
* system timer unit0 value update register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT1_OP_REG register
|
||||
* system timer unit1 value update register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer unit1
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_HI_REG register
|
||||
* system timer unit0 value high load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit0 load high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_LO_REG register
|
||||
* system timer unit0 value low load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit0 load low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_HI_REG register
|
||||
* system timer unit1 value high load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit1 load high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_LO_REG register
|
||||
* system timer unit1 value low load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit1 load low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_HI_REG register
|
||||
* system timer comp0 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
|
||||
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget0 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_LO_REG register
|
||||
* system timer comp0 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
|
||||
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget0 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_HI_REG register
|
||||
* system timer comp1 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
|
||||
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget1 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_LO_REG register
|
||||
* system timer comp1 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
|
||||
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget1 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_HI_REG register
|
||||
* system timer comp2 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
|
||||
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget2 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_LO_REG register
|
||||
* system timer comp2 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
|
||||
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget2 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_CONF_REG register
|
||||
* system timer comp0 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
|
||||
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target0 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET0_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target0 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET1_CONF_REG register
|
||||
* system timer comp1 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
|
||||
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target1 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET1_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target1 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET2_CONF_REG register
|
||||
* system timer comp2 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
|
||||
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target2 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET2_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target2 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_HI_REG register
|
||||
* system timer unit0 value high register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_LO_REG register
|
||||
* system timer unit0 value low register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_HI_REG register
|
||||
* system timer unit1 value high register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_LO_REG register
|
||||
* system timer unit1 value low register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_COMP0_LOAD_REG register
|
||||
* system timer comp0 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
|
||||
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp0 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP1_LOAD_REG register
|
||||
* system timer comp1 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
|
||||
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp1 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP2_LOAD_REG register
|
||||
* system timer comp2 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
|
||||
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp2 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_REG register
|
||||
* system timer unit0 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit0 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_REG register
|
||||
* system timer unit1 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit1 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_INT_ENA_REG register
|
||||
* systimer interrupt enable register
|
||||
*/
|
||||
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
|
||||
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_ENA_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_ENA_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_ENA_S 2
|
||||
|
||||
/** SYSTIMER_INT_RAW_REG register
|
||||
* systimer interrupt raw register
|
||||
*/
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
|
||||
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_RAW_S 0
|
||||
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_RAW_S 1
|
||||
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_RAW_S 2
|
||||
|
||||
/** SYSTIMER_INT_CLR_REG register
|
||||
* systimer interrupt clear register
|
||||
*/
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
|
||||
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_CLR_S 0
|
||||
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_CLR_S 1
|
||||
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_CLR_S 2
|
||||
|
||||
/** SYSTIMER_INT_ST_REG register
|
||||
* systimer interrupt status register
|
||||
*/
|
||||
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
|
||||
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* interupt0 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
|
||||
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_ST_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* interupt1 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
|
||||
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_ST_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* interupt2 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
|
||||
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_ST_S 2
|
||||
|
||||
/** SYSTIMER_REAL_TARGET0_LO_REG register
|
||||
* system timer comp0 actual target value low register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
|
||||
/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
|
||||
#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET0_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET0_HI_REG register
|
||||
* system timer comp0 actual target value high register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
|
||||
/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
|
||||
#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET0_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET1_LO_REG register
|
||||
* system timer comp1 actual target value low register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
|
||||
/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
|
||||
#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET1_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET1_HI_REG register
|
||||
* system timer comp1 actual target value high register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
|
||||
/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
|
||||
#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET1_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET2_LO_REG register
|
||||
* system timer comp2 actual target value low register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
|
||||
/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
|
||||
#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET2_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET2_HI_REG register
|
||||
* system timer comp2 actual target value high register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
|
||||
/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
|
||||
#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET2_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_DATE_REG register
|
||||
* system timer version control register
|
||||
*/
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
|
||||
* systimer register version
|
||||
*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFFU
|
||||
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
683
components/soc/esp32c5/include/soc/systimer_struct.h
Normal file
683
components/soc/esp32c5/include/soc/systimer_struct.h
Normal file
@@ -0,0 +1,683 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
|
||||
/** Type of conf register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:1;
|
||||
/** etm_en : R/W; bitpos: [1]; default: 0;
|
||||
* enable systimer's etm task and event
|
||||
*/
|
||||
uint32_t etm_en:1;
|
||||
uint32_t reserved_2:20;
|
||||
/** target2_work_en : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
uint32_t target2_work_en:1;
|
||||
/** target1_work_en : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
uint32_t target1_work_en:1;
|
||||
/** target0_work_en : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
uint32_t target0_work_en:1;
|
||||
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
uint32_t timer_unit1_core1_stall_en:1;
|
||||
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
uint32_t timer_unit1_core0_stall_en:1;
|
||||
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
uint32_t timer_unit0_core1_stall_en:1;
|
||||
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
uint32_t timer_unit0_core0_stall_en:1;
|
||||
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
uint32_t timer_unit1_work_en:1;
|
||||
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
uint32_t timer_unit0_work_en:1;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_conf_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of unit0_op register
|
||||
* system timer unit0 value update register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:29;
|
||||
/** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
uint32_t timer_unit0_value_valid:1;
|
||||
/** timer_unit0_update : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
uint32_t timer_unit0_update:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_op_reg_t;
|
||||
|
||||
/** Type of unit0_load_hi register
|
||||
* system timer unit0 value high load register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit0 load high 20 bits
|
||||
*/
|
||||
uint32_t timer_unit0_load_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_hi_reg_t;
|
||||
|
||||
/** Type of unit0_load_lo register
|
||||
* system timer unit0 value low load register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit0 load low 32 bits
|
||||
*/
|
||||
uint32_t timer_unit0_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_lo_reg_t;
|
||||
|
||||
/** Type of unit0_value_hi register
|
||||
* system timer unit0 value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
uint32_t timer_unit0_value_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_value_hi_reg_t;
|
||||
|
||||
/** Type of unit0_value_lo register
|
||||
* system timer unit0 value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
uint32_t timer_unit0_value_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_value_lo_reg_t;
|
||||
|
||||
/** Type of unit0_load register
|
||||
* system timer unit0 conf sync register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_load : WT; bitpos: [0]; default: 0;
|
||||
* timer unit0 sync enable signal
|
||||
*/
|
||||
uint32_t timer_unit0_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of unit1_op register
|
||||
* system timer unit1 value update register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:29;
|
||||
/** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
uint32_t timer_unit1_value_valid:1;
|
||||
/** timer_unit1_update : WT; bitpos: [30]; default: 0;
|
||||
* update timer unit1
|
||||
*/
|
||||
uint32_t timer_unit1_update:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_op_reg_t;
|
||||
|
||||
/** Type of unit1_load_hi register
|
||||
* system timer unit1 value high load register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit1 load high 20 bits
|
||||
*/
|
||||
uint32_t timer_unit1_load_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_load_hi_reg_t;
|
||||
|
||||
/** Type of unit1_load_lo register
|
||||
* system timer unit1 value low load register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit1 load low 32 bits
|
||||
*/
|
||||
uint32_t timer_unit1_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_load_lo_reg_t;
|
||||
|
||||
/** Type of unit1_value_hi register
|
||||
* system timer unit1 value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
uint32_t timer_unit1_value_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_value_hi_reg_t;
|
||||
|
||||
/** Type of unit1_value_lo register
|
||||
* system timer unit1 value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
uint32_t timer_unit1_value_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_value_lo_reg_t;
|
||||
|
||||
/** Type of unit1_load register
|
||||
* system timer unit1 conf sync register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_load : WT; bitpos: [0]; default: 0;
|
||||
* timer unit1 sync enable signal
|
||||
*/
|
||||
uint32_t timer_unit1_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of target0_hi register
|
||||
* system timer comp0 value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget0 high 20 bits
|
||||
*/
|
||||
uint32_t timer_target0_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_hi_reg_t;
|
||||
|
||||
/** Type of target0_lo register
|
||||
* system timer comp0 value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget0 low 32 bits
|
||||
*/
|
||||
uint32_t timer_target0_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_lo_reg_t;
|
||||
|
||||
/** Type of target0_conf register
|
||||
* system timer comp0 target mode register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* target0 period
|
||||
*/
|
||||
uint32_t target0_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target0_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Set target0 to period mode
|
||||
*/
|
||||
uint32_t target0_period_mode:1;
|
||||
/** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
uint32_t target0_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_conf_reg_t;
|
||||
|
||||
/** Type of comp0_load register
|
||||
* system timer comp0 conf sync register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp0_load : WT; bitpos: [0]; default: 0;
|
||||
* timer comp0 sync enable signal
|
||||
*/
|
||||
uint32_t timer_comp0_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp0_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of target1_hi register
|
||||
* system timer comp1 value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target1_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget1 high 20 bits
|
||||
*/
|
||||
uint32_t timer_target1_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target1_hi_reg_t;
|
||||
|
||||
/** Type of target1_lo register
|
||||
* system timer comp1 value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target1_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget1 low 32 bits
|
||||
*/
|
||||
uint32_t timer_target1_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target1_lo_reg_t;
|
||||
|
||||
/** Type of target1_conf register
|
||||
* system timer comp1 target mode register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target1_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* target1 period
|
||||
*/
|
||||
uint32_t target1_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target1_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Set target1 to period mode
|
||||
*/
|
||||
uint32_t target1_period_mode:1;
|
||||
/** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
uint32_t target1_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target1_conf_reg_t;
|
||||
|
||||
/** Type of comp1_load register
|
||||
* system timer comp1 conf sync register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp1_load : WT; bitpos: [0]; default: 0;
|
||||
* timer comp1 sync enable signal
|
||||
*/
|
||||
uint32_t timer_comp1_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp1_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of target2_hi register
|
||||
* system timer comp2 value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target2_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget2 high 20 bits
|
||||
*/
|
||||
uint32_t timer_target2_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target2_hi_reg_t;
|
||||
|
||||
/** Type of target2_lo register
|
||||
* system timer comp2 value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target2_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget2 low 32 bits
|
||||
*/
|
||||
uint32_t timer_target2_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target2_lo_reg_t;
|
||||
|
||||
/** Type of target2_conf register
|
||||
* system timer comp2 target mode register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target2_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* target2 period
|
||||
*/
|
||||
uint32_t target2_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target2_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Set target2 to period mode
|
||||
*/
|
||||
uint32_t target2_period_mode:1;
|
||||
/** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
uint32_t target2_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target2_conf_reg_t;
|
||||
|
||||
/** Type of comp2_load register
|
||||
* system timer comp2 conf sync register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp2_load : WT; bitpos: [0]; default: 0;
|
||||
* timer comp2 sync enable signal
|
||||
*/
|
||||
uint32_t timer_comp2_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp2_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER INTERRUPT REGISTER */
|
||||
/** Type of int_ena register
|
||||
* systimer interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
uint32_t target0_int_ena:1;
|
||||
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
uint32_t target1_int_ena:1;
|
||||
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
uint32_t target2_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* systimer interrupt raw register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
uint32_t target0_int_raw:1;
|
||||
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
uint32_t target1_int_raw:1;
|
||||
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
uint32_t target2_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* systimer interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
uint32_t target0_int_clr:1;
|
||||
/** target1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
uint32_t target1_int_clr:1;
|
||||
/** target2_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
uint32_t target2_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_clr_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* systimer interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* interupt0 status
|
||||
*/
|
||||
uint32_t target0_int_st:1;
|
||||
/** target1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* interupt1 status
|
||||
*/
|
||||
uint32_t target1_int_st:1;
|
||||
/** target2_int_st : RO; bitpos: [2]; default: 0;
|
||||
* interupt2 status
|
||||
*/
|
||||
uint32_t target2_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_st_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */
|
||||
/** Type of real_target0_lo register
|
||||
* system timer comp0 actual target value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
uint32_t target0_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target0_lo_reg_t;
|
||||
|
||||
/** Type of real_target0_hi register
|
||||
* system timer comp0 actual target value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
uint32_t target0_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target0_hi_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */
|
||||
/** Type of real_target1_lo register
|
||||
* system timer comp1 actual target value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target1_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
uint32_t target1_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target1_lo_reg_t;
|
||||
|
||||
/** Type of real_target1_hi register
|
||||
* system timer comp1 actual target value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target1_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
uint32_t target1_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target1_hi_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */
|
||||
/** Type of real_target2_lo register
|
||||
* system timer comp2 actual target value low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target2_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
uint32_t target2_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target2_lo_reg_t;
|
||||
|
||||
/** Type of real_target2_hi register
|
||||
* system timer comp2 actual target value high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target2_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
uint32_t target2_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target2_hi_reg_t;
|
||||
|
||||
|
||||
/** Group: VERSION REGISTER */
|
||||
/** Type of date register
|
||||
* system timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 35655795;
|
||||
* systimer register version
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile systimer_conf_reg_t conf;
|
||||
volatile systimer_unit0_op_reg_t unit0_op;
|
||||
volatile systimer_unit1_op_reg_t unit1_op;
|
||||
volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
|
||||
volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
|
||||
volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
|
||||
volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
|
||||
volatile systimer_target0_hi_reg_t target0_hi;
|
||||
volatile systimer_target0_lo_reg_t target0_lo;
|
||||
volatile systimer_target1_hi_reg_t target1_hi;
|
||||
volatile systimer_target1_lo_reg_t target1_lo;
|
||||
volatile systimer_target2_hi_reg_t target2_hi;
|
||||
volatile systimer_target2_lo_reg_t target2_lo;
|
||||
volatile systimer_target0_conf_reg_t target0_conf;
|
||||
volatile systimer_target1_conf_reg_t target1_conf;
|
||||
volatile systimer_target2_conf_reg_t target2_conf;
|
||||
volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
|
||||
volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
|
||||
volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
|
||||
volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
|
||||
volatile systimer_comp0_load_reg_t comp0_load;
|
||||
volatile systimer_comp1_load_reg_t comp1_load;
|
||||
volatile systimer_comp2_load_reg_t comp2_load;
|
||||
volatile systimer_unit0_load_reg_t unit0_load;
|
||||
volatile systimer_unit1_load_reg_t unit1_load;
|
||||
volatile systimer_int_ena_reg_t int_ena;
|
||||
volatile systimer_int_raw_reg_t int_raw;
|
||||
volatile systimer_int_clr_reg_t int_clr;
|
||||
volatile systimer_int_st_reg_t int_st;
|
||||
volatile systimer_real_target0_lo_reg_t real_target0_lo;
|
||||
volatile systimer_real_target0_hi_reg_t real_target0_hi;
|
||||
volatile systimer_real_target1_lo_reg_t real_target1_lo;
|
||||
volatile systimer_real_target1_hi_reg_t real_target1_hi;
|
||||
volatile systimer_real_target2_lo_reg_t real_target2_lo;
|
||||
volatile systimer_real_target2_hi_reg_t real_target2_hi;
|
||||
uint32_t reserved_08c[28];
|
||||
volatile systimer_date_reg_t date;
|
||||
} systimer_dev_t;
|
||||
|
||||
extern systimer_dev_t SYSTIMER;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
538
components/soc/esp32c5/include/soc/timer_group_reg.h
Normal file
538
components/soc/esp32c5/include/soc/timer_group_reg.h
Normal file
@@ -0,0 +1,538 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
*/
|
||||
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
|
||||
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_EN (BIT(10))
|
||||
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
|
||||
#define TIMG_T0_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T0_ALARM_EN_S 10
|
||||
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer 0 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_T0_DIVCNT_RST (BIT(12))
|
||||
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
|
||||
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_T0_DIVCNT_RST_S 12
|
||||
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 0 clock (T0_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T0_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
|
||||
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_S 13
|
||||
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 0 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T0_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
|
||||
#define TIMG_T0_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T0_AUTORELOAD_S 29
|
||||
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 0 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 0 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T0_INCREASE (BIT(30))
|
||||
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
|
||||
#define TIMG_T0_INCREASE_V 0x00000001U
|
||||
#define TIMG_T0_INCREASE_S 30
|
||||
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer 0 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T0_EN (BIT(31))
|
||||
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
|
||||
#define TIMG_T0_EN_V 0x00000001U
|
||||
#define TIMG_T0_EN_S 31
|
||||
|
||||
/** TIMG_T0LO_REG register
|
||||
* Timer 0 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
|
||||
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
|
||||
#define TIMG_T0_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_S 0
|
||||
|
||||
/** TIMG_T0HI_REG register
|
||||
* Timer 0 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
|
||||
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_HI 0x003FFFFFU
|
||||
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
|
||||
#define TIMG_T0_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_HI_S 0
|
||||
|
||||
/** TIMG_T0UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
|
||||
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T0_UPDATE (BIT(31))
|
||||
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
|
||||
#define TIMG_T0_UPDATE_V 0x00000001U
|
||||
#define TIMG_T0_UPDATE_S 31
|
||||
|
||||
/** TIMG_T0ALARMLO_REG register
|
||||
* Timer 0 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
|
||||
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
|
||||
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T0ALARMHI_REG register
|
||||
* Timer 0 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
|
||||
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
|
||||
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T0LOADLO_REG register
|
||||
* Timer 0 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
|
||||
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 0 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
|
||||
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T0LOADHI_REG register
|
||||
* Timer 0 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
|
||||
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 0 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
|
||||
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T0LOAD_REG register
|
||||
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
|
||||
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 0 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T0_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
|
||||
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG0_REG register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
|
||||
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_S 12
|
||||
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_S 13
|
||||
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
|
||||
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
|
||||
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
|
||||
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_S 22
|
||||
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG3 0x00000003U
|
||||
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
|
||||
#define TIMG_WDT_STG3_V 0x00000003U
|
||||
#define TIMG_WDT_STG3_S 23
|
||||
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG2 0x00000003U
|
||||
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
|
||||
#define TIMG_WDT_STG2_V 0x00000003U
|
||||
#define TIMG_WDT_STG2_S 25
|
||||
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG1 0x00000003U
|
||||
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
|
||||
#define TIMG_WDT_STG1_V 0x00000003U
|
||||
#define TIMG_WDT_STG1_S 27
|
||||
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG0 0x00000003U
|
||||
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
|
||||
#define TIMG_WDT_STG0_V 0x00000003U
|
||||
#define TIMG_WDT_STG0_S 29
|
||||
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_EN (BIT(31))
|
||||
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
|
||||
#define TIMG_WDT_EN_V 0x00000001U
|
||||
#define TIMG_WDT_EN_S 31
|
||||
|
||||
/** TIMG_WDTCONFIG1_REG register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
|
||||
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_WDT_DIVCNT_RST (BIT(0))
|
||||
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
|
||||
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_WDT_DIVCNT_RST_S 0
|
||||
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
|
||||
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_S 16
|
||||
|
||||
/** TIMG_WDTCONFIG2_REG register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
|
||||
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
|
||||
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG3_REG register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
|
||||
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
|
||||
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG4_REG register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
|
||||
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
|
||||
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG5_REG register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
|
||||
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
|
||||
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTFEED_REG register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
|
||||
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
#define TIMG_WDT_FEED 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
|
||||
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_S 0
|
||||
|
||||
/** TIMG_WDTWPROTECT_REG register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
|
||||
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_WKEY 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
|
||||
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_S 0
|
||||
|
||||
/** TIMG_RTCCALICFG_REG register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
|
||||
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
|
||||
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
|
||||
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_CYCLING_S 12
|
||||
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
|
||||
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_S 13
|
||||
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
|
||||
* indicate one-shot frequency calculation is done.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_RDY (BIT(15))
|
||||
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
|
||||
#define TIMG_RTC_CALI_RDY_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_RDY_S 15
|
||||
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
|
||||
* Configure the time to calculate RTC slow clock's frequency.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_MAX 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
|
||||
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_S 16
|
||||
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start one-shot frequency calculation.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START (BIT(31))
|
||||
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
|
||||
#define TIMG_RTC_CALI_START_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_S 31
|
||||
|
||||
/** TIMG_RTCCALICFG1_REG register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
|
||||
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
|
||||
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
|
||||
* When one-shot or periodic frequency calculation is done, read this value to
|
||||
* calculate RTC slow clock's frequency.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
|
||||
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_S 7
|
||||
|
||||
/** TIMG_INT_ENA_TIMERS_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
|
||||
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ENA (BIT(0))
|
||||
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
|
||||
#define TIMG_T0_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T0_INT_ENA_S 0
|
||||
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ENA (BIT(2))
|
||||
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
|
||||
#define TIMG_WDT_INT_ENA_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ENA_S 2
|
||||
|
||||
/** TIMG_INT_RAW_TIMERS_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
|
||||
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_RAW (BIT(0))
|
||||
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
|
||||
#define TIMG_T0_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T0_INT_RAW_S 0
|
||||
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_RAW (BIT(2))
|
||||
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
|
||||
#define TIMG_WDT_INT_RAW_V 0x00000001U
|
||||
#define TIMG_WDT_INT_RAW_S 2
|
||||
|
||||
/** TIMG_INT_ST_TIMERS_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
|
||||
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ST (BIT(0))
|
||||
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
|
||||
#define TIMG_T0_INT_ST_V 0x00000001U
|
||||
#define TIMG_T0_INT_ST_S 0
|
||||
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ST (BIT(2))
|
||||
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
|
||||
#define TIMG_WDT_INT_ST_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ST_S 2
|
||||
|
||||
/** TIMG_INT_CLR_TIMERS_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
|
||||
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_CLR (BIT(0))
|
||||
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
|
||||
#define TIMG_T0_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T0_INT_CLR_S 0
|
||||
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_CLR (BIT(2))
|
||||
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
|
||||
#define TIMG_WDT_INT_CLR_V 0x00000001U
|
||||
#define TIMG_WDT_INT_CLR_S 2
|
||||
|
||||
/** TIMG_RTCCALICFG2_REG register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
|
||||
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
|
||||
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_TIMEOUT_S 0
|
||||
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
|
||||
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
|
||||
|
||||
/** TIMG_NTIMERS_DATE_REG register
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
|
||||
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
|
||||
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_S 0
|
||||
|
||||
/** TIMG_REGCLK_REG register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
|
||||
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
#define TIMG_ETM_EN (BIT(28))
|
||||
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
|
||||
#define TIMG_ETM_EN_V 0x00000001U
|
||||
#define TIMG_ETM_EN_S 28
|
||||
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
#define TIMG_CLK_EN (BIT(31))
|
||||
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
|
||||
#define TIMG_CLK_EN_V 0x00000001U
|
||||
#define TIMG_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
552
components/soc/esp32c5/include/soc/timer_group_struct.h
Normal file
552
components/soc/esp32c5/include/soc/timer_group_struct.h
Normal file
@@ -0,0 +1,552 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: T0 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:10;
|
||||
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tx_alarm_en:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer x 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tx_divcnt_rst:1;
|
||||
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer x clock (Tx_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tx_divider:16;
|
||||
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer x auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tx_autoreload:1;
|
||||
/** tx_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer x time-base counter will increment every clock tick. When
|
||||
* cleared, the timer x time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tx_increase:1;
|
||||
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer x time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tx_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txconfig_reg_t;
|
||||
|
||||
/** Type of txlo register
|
||||
* Timer x current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txlo_reg_t;
|
||||
|
||||
/** Type of txhi register
|
||||
* Timer x current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txhi_reg_t;
|
||||
|
||||
/** Type of txupdate register
|
||||
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tx_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txupdate_reg_t;
|
||||
|
||||
/** Type of txalarmlo register
|
||||
* Timer x alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmlo_reg_t;
|
||||
|
||||
/** Type of txalarmhi register
|
||||
* Timer x alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmhi_reg_t;
|
||||
|
||||
/** Type of txloadlo register
|
||||
* Timer x reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer x time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tx_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadlo_reg_t;
|
||||
|
||||
/** Type of txloadhi register
|
||||
* Timer x reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer x time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tx_load_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadhi_reg_t;
|
||||
|
||||
/** Type of txload register
|
||||
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer x time-base counter reload.
|
||||
*/
|
||||
uint32_t tx_load:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txload_reg_t;
|
||||
|
||||
|
||||
/** Group: WDT Control and configuration registers */
|
||||
/** Type of wdtconfig0 register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en:1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en:1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en:1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length:3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length:3;
|
||||
uint32_t reserved_21:1;
|
||||
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
uint32_t wdt_conf_update_en:1;
|
||||
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg3:2;
|
||||
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg2:2;
|
||||
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg1:2;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg0:2;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig0_reg_t;
|
||||
|
||||
/** Type of wdtconfig1 register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t wdt_divcnt_rst:1;
|
||||
uint32_t reserved_1:15;
|
||||
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
uint32_t wdt_clk_prescale:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig1_reg_t;
|
||||
|
||||
/** Type of wdtconfig2 register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig2_reg_t;
|
||||
|
||||
/** Type of wdtconfig3 register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig3_reg_t;
|
||||
|
||||
/** Type of wdtconfig4 register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig4_reg_t;
|
||||
|
||||
/** Type of wdtconfig5 register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig5_reg_t;
|
||||
|
||||
/** Type of wdtfeed register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
uint32_t wdt_feed:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtfeed_reg_t;
|
||||
|
||||
/** Type of wdtwprotect register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtwprotect_reg_t;
|
||||
|
||||
|
||||
/** Group: RTC CALI Control and configuration registers */
|
||||
/** Type of rtccalicfg register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
uint32_t rtc_cali_start_cycling:1;
|
||||
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
uint32_t rtc_cali_clk_sel:2;
|
||||
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
|
||||
* indicate one-shot frequency calculation is done.
|
||||
*/
|
||||
uint32_t rtc_cali_rdy:1;
|
||||
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
|
||||
* Configure the time to calculate RTC slow clock's frequency.
|
||||
*/
|
||||
uint32_t rtc_cali_max:15;
|
||||
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start one-shot frequency calculation.
|
||||
*/
|
||||
uint32_t rtc_cali_start:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg_reg_t;
|
||||
|
||||
/** Type of rtccalicfg1 register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
uint32_t rtc_cali_cycling_data_vld:1;
|
||||
uint32_t reserved_1:6;
|
||||
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
|
||||
* When one-shot or periodic frequency calculation is done, read this value to
|
||||
* calculate RTC slow clock's frequency.
|
||||
*/
|
||||
uint32_t rtc_cali_value:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg1_reg_t;
|
||||
|
||||
/** Type of rtccalicfg2 register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
uint32_t rtc_cali_timeout:1;
|
||||
uint32_t reserved_1:2;
|
||||
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_rst_cnt:4;
|
||||
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_thres:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg2_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_ena_timers register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_ena:1;
|
||||
uint32_t reserved_1:1;
|
||||
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_ena_timers_reg_t;
|
||||
|
||||
/** Type of int_raw_timers register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_raw:1;
|
||||
uint32_t reserved_1:1;
|
||||
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_raw_timers_reg_t;
|
||||
|
||||
/** Type of int_st_timers register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_st:1;
|
||||
uint32_t reserved_1:1;
|
||||
/** wdt_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_st_timers_reg_t;
|
||||
|
||||
/** Type of int_clr_timers register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_clr:1;
|
||||
uint32_t reserved_1:1;
|
||||
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_clr_timers_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of ntimers_date register
|
||||
* Timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
uint32_t ntimgs_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_ntimers_date_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock configuration registers */
|
||||
/** Type of regclk register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:28;
|
||||
/** etm_en : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
uint32_t etm_en:1;
|
||||
uint32_t reserved_29:2;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_regclk_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile timg_txconfig_reg_t t0config;
|
||||
volatile timg_txlo_reg_t t0lo;
|
||||
volatile timg_txhi_reg_t t0hi;
|
||||
volatile timg_txupdate_reg_t t0update;
|
||||
volatile timg_txalarmlo_reg_t t0alarmlo;
|
||||
volatile timg_txalarmhi_reg_t t0alarmhi;
|
||||
volatile timg_txloadlo_reg_t t0loadlo;
|
||||
volatile timg_txloadhi_reg_t t0loadhi;
|
||||
volatile timg_txload_reg_t t0load;
|
||||
uint32_t reserved_024[9];
|
||||
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
||||
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
||||
volatile timg_wdtconfig2_reg_t wdtconfig2;
|
||||
volatile timg_wdtconfig3_reg_t wdtconfig3;
|
||||
volatile timg_wdtconfig4_reg_t wdtconfig4;
|
||||
volatile timg_wdtconfig5_reg_t wdtconfig5;
|
||||
volatile timg_wdtfeed_reg_t wdtfeed;
|
||||
volatile timg_wdtwprotect_reg_t wdtwprotect;
|
||||
volatile timg_rtccalicfg_reg_t rtccalicfg;
|
||||
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
|
||||
volatile timg_int_ena_timers_reg_t int_ena_timers;
|
||||
volatile timg_int_raw_timers_reg_t int_raw_timers;
|
||||
volatile timg_int_st_timers_reg_t int_st_timers;
|
||||
volatile timg_int_clr_timers_reg_t int_clr_timers;
|
||||
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
|
||||
uint32_t reserved_084[29];
|
||||
volatile timg_ntimers_date_reg_t ntimers_date;
|
||||
volatile timg_regclk_reg_t regclk;
|
||||
} timg_dev_t;
|
||||
|
||||
extern timg_dev_t TIMERG0;
|
||||
extern timg_dev_t TIMERG1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
463
components/soc/esp32c5/include/soc/trace_reg.h
Normal file
463
components/soc/esp32c5/include/soc/trace_reg.h
Normal file
@@ -0,0 +1,463 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** TRACE_MEM_START_ADDR_REG register
|
||||
* mem start addr
|
||||
*/
|
||||
#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
|
||||
/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
|
||||
* The start address of trace memory
|
||||
*/
|
||||
#define TRACE_MEM_START_ADDR 0xFFFFFFFFU
|
||||
#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
|
||||
#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU
|
||||
#define TRACE_MEM_START_ADDR_S 0
|
||||
|
||||
/** TRACE_MEM_END_ADDR_REG register
|
||||
* mem end addr
|
||||
*/
|
||||
#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
|
||||
/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* The end address of trace memory
|
||||
*/
|
||||
#define TRACE_MEM_END_ADDR 0xFFFFFFFFU
|
||||
#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
|
||||
#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU
|
||||
#define TRACE_MEM_END_ADDR_S 0
|
||||
|
||||
/** TRACE_MEM_CURRENT_ADDR_REG register
|
||||
* mem current addr
|
||||
*/
|
||||
#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
|
||||
/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
|
||||
* current_mem_addr,indicate that next writing addr
|
||||
*/
|
||||
#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU
|
||||
#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
|
||||
#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
|
||||
#define TRACE_MEM_CURRENT_ADDR_S 0
|
||||
|
||||
/** TRACE_MEM_ADDR_UPDATE_REG register
|
||||
* mem addr update
|
||||
*/
|
||||
#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
|
||||
/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
|
||||
* when set, the will
|
||||
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
|
||||
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
|
||||
*/
|
||||
#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0))
|
||||
#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
|
||||
#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U
|
||||
#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0
|
||||
|
||||
/** TRACE_FIFO_STATUS_REG register
|
||||
* fifo status register
|
||||
*/
|
||||
#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
|
||||
/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
|
||||
* Represent whether the fifo is empty. \\1: empty \\0: not empty
|
||||
*/
|
||||
#define TRACE_FIFO_EMPTY (BIT(0))
|
||||
#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
|
||||
#define TRACE_FIFO_EMPTY_V 0x00000001U
|
||||
#define TRACE_FIFO_EMPTY_S 0
|
||||
/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
|
||||
* Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due
|
||||
* to hart halted or havereset \\3: lost state
|
||||
*/
|
||||
#define TRACE_WORK_STATUS 0x00000003U
|
||||
#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
|
||||
#define TRACE_WORK_STATUS_V 0x00000003U
|
||||
#define TRACE_WORK_STATUS_S 1
|
||||
|
||||
/** TRACE_INTR_ENA_REG register
|
||||
* interrupt enable register
|
||||
*/
|
||||
#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
|
||||
/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Set 1 enable fifo_overflow interrupt
|
||||
*/
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0))
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0
|
||||
/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Set 1 enable mem_full interrupt
|
||||
*/
|
||||
#define TRACE_MEM_FULL_INTR_ENA (BIT(1))
|
||||
#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
|
||||
#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U
|
||||
#define TRACE_MEM_FULL_INTR_ENA_S 1
|
||||
|
||||
/** TRACE_INTR_RAW_REG register
|
||||
* interrupt status register
|
||||
*/
|
||||
#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
|
||||
/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
|
||||
* fifo_overflow interrupt status
|
||||
*/
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0))
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0
|
||||
/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
|
||||
* mem_full interrupt status
|
||||
*/
|
||||
#define TRACE_MEM_FULL_INTR_RAW (BIT(1))
|
||||
#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
|
||||
#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U
|
||||
#define TRACE_MEM_FULL_INTR_RAW_S 1
|
||||
|
||||
/** TRACE_INTR_CLR_REG register
|
||||
* interrupt clear register
|
||||
*/
|
||||
#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
|
||||
/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set 1 clear fifo overflow interrupt
|
||||
*/
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0))
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U
|
||||
#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0
|
||||
/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set 1 clear mem full interrupt
|
||||
*/
|
||||
#define TRACE_MEM_FULL_INTR_CLR (BIT(1))
|
||||
#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
|
||||
#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U
|
||||
#define TRACE_MEM_FULL_INTR_CLR_S 1
|
||||
|
||||
/** TRACE_TRIGGER_REG register
|
||||
* trigger register
|
||||
*/
|
||||
#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
|
||||
/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not start trace.\\1: start trace \\0: invalid\\
|
||||
*/
|
||||
#define TRACE_TRIGGER_ON (BIT(0))
|
||||
#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
|
||||
#define TRACE_TRIGGER_ON_V 0x00000001U
|
||||
#define TRACE_TRIGGER_ON_S 0
|
||||
/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
|
||||
* Configure whether or not stop trace.\\1: stop trace \\0: invalid\\
|
||||
*/
|
||||
#define TRACE_TRIGGER_OFF (BIT(1))
|
||||
#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
|
||||
#define TRACE_TRIGGER_OFF_V 0x00000001U
|
||||
#define TRACE_TRIGGER_OFF_S 1
|
||||
/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
|
||||
* Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when
|
||||
* mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\
|
||||
*/
|
||||
#define TRACE_MEM_LOOP (BIT(2))
|
||||
#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
|
||||
#define TRACE_MEM_LOOP_V 0x00000001U
|
||||
#define TRACE_MEM_LOOP_S 2
|
||||
/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
|
||||
* Configure whether or not enable auto-restart.\\1: enable\\0: disable\\
|
||||
*/
|
||||
#define TRACE_RESTART_ENA (BIT(3))
|
||||
#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
|
||||
#define TRACE_RESTART_ENA_V 0x00000001U
|
||||
#define TRACE_RESTART_ENA_S 3
|
||||
|
||||
/** TRACE_CONFIG_REG register
|
||||
* trace configuration register
|
||||
*/
|
||||
#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24)
|
||||
/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\
|
||||
*/
|
||||
#define TRACE_DM_TRIGGER_ENA (BIT(0))
|
||||
#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
|
||||
#define TRACE_DM_TRIGGER_ENA_V 0x00000001U
|
||||
#define TRACE_DM_TRIGGER_ENA_S 0
|
||||
/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Configure whether or not enable trace cpu haverest, when enabeld, if cpu have
|
||||
* reset, the encoder will output a packet to report the address of the last
|
||||
* instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0:
|
||||
* disabled\\
|
||||
*/
|
||||
#define TRACE_RESET_ENA (BIT(1))
|
||||
#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
|
||||
#define TRACE_RESET_ENA_V 0x00000001U
|
||||
#define TRACE_RESET_ENA_S 1
|
||||
/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* Configure whether or not enable trace cpu is halted, when enabeld, if the cpu
|
||||
* halted, the encoder will output a packet to report the address of the last
|
||||
* instruction, and upon halted deassertion, the encoder start again.When disabled,
|
||||
* encoder will not report the last address before halted and first address after
|
||||
* halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\
|
||||
*/
|
||||
#define TRACE_HALT_ENA (BIT(2))
|
||||
#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
|
||||
#define TRACE_HALT_ENA_V 0x00000001U
|
||||
#define TRACE_HALT_ENA_S 2
|
||||
/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
|
||||
* the cpu will be stalled until the packets is able to write to fifo.\\1:
|
||||
* enabled.\\0: disabled\\
|
||||
*/
|
||||
#define TRACE_STALL_ENA (BIT(3))
|
||||
#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
|
||||
#define TRACE_STALL_ENA_V 0x00000001U
|
||||
#define TRACE_STALL_ENA_S 3
|
||||
/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
|
||||
* Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta
|
||||
* address mode\\
|
||||
*/
|
||||
#define TRACE_FULL_ADDRESS (BIT(4))
|
||||
#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
|
||||
#define TRACE_FULL_ADDRESS_V 0x00000001U
|
||||
#define TRACE_FULL_ADDRESS_S 4
|
||||
/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
|
||||
* Configure whether or not enabel implicit exception mode. When enabled,, do not sent
|
||||
* exception address, only exception cause in exception packets.\\1: enabled\\0:
|
||||
* disabled\\
|
||||
*/
|
||||
#define TRACE_IMPLICIT_EXCEPT (BIT(5))
|
||||
#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
|
||||
#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U
|
||||
#define TRACE_IMPLICIT_EXCEPT_S 5
|
||||
|
||||
/** TRACE_FILTER_CONTROL_REG register
|
||||
* filter control register
|
||||
*/
|
||||
#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28)
|
||||
/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match
|
||||
*/
|
||||
#define TRACE_FILTER_EN (BIT(0))
|
||||
#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
|
||||
#define TRACE_FILTER_EN_V 0x00000001U
|
||||
#define TRACE_FILTER_EN_S 0
|
||||
/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
|
||||
* when set, the comparator must be high in order for the filter to match
|
||||
*/
|
||||
#define TRACE_MATCH_COMP (BIT(1))
|
||||
#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
|
||||
#define TRACE_MATCH_COMP_V 0x00000001U
|
||||
#define TRACE_MATCH_COMP_S 1
|
||||
/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
|
||||
* when set, match privilege levels specified by
|
||||
* \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
|
||||
*/
|
||||
#define TRACE_MATCH_PRIVILEGE (BIT(2))
|
||||
#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
|
||||
#define TRACE_MATCH_PRIVILEGE_V 0x00000001U
|
||||
#define TRACE_MATCH_PRIVILEGE_S 2
|
||||
/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
|
||||
* when set, start matching from exception cause codes specified by
|
||||
* \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
|
||||
* matching upon return from the 1st matching exception.
|
||||
*/
|
||||
#define TRACE_MATCH_ECAUSE (BIT(3))
|
||||
#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
|
||||
#define TRACE_MATCH_ECAUSE_V 0x00000001U
|
||||
#define TRACE_MATCH_ECAUSE_S 3
|
||||
/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
|
||||
* when set, start matching from a trap with the interrupt level codes specified by
|
||||
* \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
|
||||
* stop matching upon return from the 1st matching trap.
|
||||
*/
|
||||
#define TRACE_MATCH_INTERRUPT (BIT(4))
|
||||
#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
|
||||
#define TRACE_MATCH_INTERRUPT_V 0x00000001U
|
||||
#define TRACE_MATCH_INTERRUPT_S 4
|
||||
|
||||
/** TRACE_FILTER_MATCH_CONTROL_REG register
|
||||
* filter match control register
|
||||
*/
|
||||
#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c)
|
||||
/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
|
||||
* Select match which privilege level when
|
||||
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1:
|
||||
* machine mode. \\0: user mode
|
||||
*/
|
||||
#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0))
|
||||
#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
|
||||
#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U
|
||||
#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0
|
||||
/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
|
||||
* Select which match which itype when
|
||||
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match
|
||||
* itype of 2. \\0: match itype or 1.
|
||||
*/
|
||||
#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1))
|
||||
#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
|
||||
#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U
|
||||
#define TRACE_MATCH_VALUE_INTERRUPT_S 1
|
||||
/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
|
||||
* specified which ecause matched.
|
||||
*/
|
||||
#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU
|
||||
#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
|
||||
#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU
|
||||
#define TRACE_MATCH_CHOICE_ECAUSE_S 2
|
||||
|
||||
/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
|
||||
* filter comparator match control register
|
||||
*/
|
||||
#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30)
|
||||
/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
|
||||
* Determines which input to compare against the primary comparator, \\0: iaddr, \\1:
|
||||
* tval.
|
||||
*/
|
||||
#define TRACE_P_INPUT (BIT(0))
|
||||
#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
|
||||
#define TRACE_P_INPUT_V 0x00000001U
|
||||
#define TRACE_P_INPUT_S 0
|
||||
/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
|
||||
* Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than,
|
||||
* \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other:
|
||||
* always match
|
||||
*/
|
||||
#define TRACE_P_FUNCTION 0x00000007U
|
||||
#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
|
||||
#define TRACE_P_FUNCTION_V 0x00000007U
|
||||
#define TRACE_P_FUNCTION_S 2
|
||||
/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
|
||||
* Generate a trace packet explicitly reporting the address that cause the primary
|
||||
* match
|
||||
*/
|
||||
#define TRACE_P_NOTIFY (BIT(5))
|
||||
#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
|
||||
#define TRACE_P_NOTIFY_V 0x00000001U
|
||||
#define TRACE_P_NOTIFY_S 5
|
||||
/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
|
||||
* Determines which input to compare against the secondary comparator, \\0: iaddr,
|
||||
* \\1: tval.
|
||||
*/
|
||||
#define TRACE_S_INPUT (BIT(8))
|
||||
#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
|
||||
#define TRACE_S_INPUT_V 0x00000001U
|
||||
#define TRACE_S_INPUT_S 8
|
||||
/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
|
||||
* Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less
|
||||
* than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal,
|
||||
* \\other: always match
|
||||
*/
|
||||
#define TRACE_S_FUNCTION 0x00000007U
|
||||
#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
|
||||
#define TRACE_S_FUNCTION_V 0x00000007U
|
||||
#define TRACE_S_FUNCTION_S 10
|
||||
/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
|
||||
* Generate a trace packet explicitly reporting the address that cause the secondary
|
||||
* match
|
||||
*/
|
||||
#define TRACE_S_NOTIFY (BIT(13))
|
||||
#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
|
||||
#define TRACE_S_NOTIFY_V 0x00000001U
|
||||
#define TRACE_S_NOTIFY_S 13
|
||||
/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
|
||||
* 0: only primary matches, \\1: primary and secondary comparator both
|
||||
* matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3:
|
||||
* set when primary matches and continue to match until after secondary comparator
|
||||
* matches
|
||||
*/
|
||||
#define TRACE_MATCH_MODE 0x00000003U
|
||||
#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
|
||||
#define TRACE_MATCH_MODE_V 0x00000003U
|
||||
#define TRACE_MATCH_MODE_S 16
|
||||
|
||||
/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
|
||||
* primary comparator match value
|
||||
*/
|
||||
#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34)
|
||||
/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
|
||||
* primary comparator match value
|
||||
*/
|
||||
#define TRACE_P_MATCH 0xFFFFFFFFU
|
||||
#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
|
||||
#define TRACE_P_MATCH_V 0xFFFFFFFFU
|
||||
#define TRACE_P_MATCH_S 0
|
||||
|
||||
/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
|
||||
* secondary comparator match value
|
||||
*/
|
||||
#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38)
|
||||
/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
|
||||
* secondary comparator match value
|
||||
*/
|
||||
#define TRACE_S_MATCH 0xFFFFFFFFU
|
||||
#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
|
||||
#define TRACE_S_MATCH_V 0xFFFFFFFFU
|
||||
#define TRACE_S_MATCH_S 0
|
||||
|
||||
/** TRACE_RESYNC_PROLONGED_REG register
|
||||
* resync configuration register
|
||||
*/
|
||||
#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c)
|
||||
/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
|
||||
* count number, when count to this value, send a sync package
|
||||
*/
|
||||
#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU
|
||||
#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
|
||||
#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU
|
||||
#define TRACE_RESYNC_PROLONGED_S 0
|
||||
/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
|
||||
* resyc mode sel: \\0: off, \\2: cycle count \\3: package num count
|
||||
*/
|
||||
#define TRACE_RESYNC_MODE 0x00000003U
|
||||
#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
|
||||
#define TRACE_RESYNC_MODE_V 0x00000003U
|
||||
#define TRACE_RESYNC_MODE_S 24
|
||||
|
||||
/** TRACE_AHB_CONFIG_REG register
|
||||
* AHB config register
|
||||
*/
|
||||
#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
|
||||
/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
|
||||
* set hburst
|
||||
*/
|
||||
#define TRACE_HBURST 0x00000007U
|
||||
#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S)
|
||||
#define TRACE_HBURST_V 0x00000007U
|
||||
#define TRACE_HBURST_S 0
|
||||
/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
|
||||
* set max continuous access for incr mode
|
||||
*/
|
||||
#define TRACE_MAX_INCR 0x00000007U
|
||||
#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
|
||||
#define TRACE_MAX_INCR_V 0x00000007U
|
||||
#define TRACE_MAX_INCR_S 3
|
||||
|
||||
/** TRACE_CLOCK_GATE_REG register
|
||||
* Clock gate control register
|
||||
*/
|
||||
#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44)
|
||||
/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* The bit is used to enable clock gate when access all registers in this module.
|
||||
*/
|
||||
#define TRACE_CLK_EN (BIT(0))
|
||||
#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
|
||||
#define TRACE_CLK_EN_V 0x00000001U
|
||||
#define TRACE_CLK_EN_S 0
|
||||
|
||||
/** TRACE_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
|
||||
/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
|
||||
* version control register. Note that this default value stored is the latest date
|
||||
* when the hardware logic was updated.
|
||||
*/
|
||||
#define TRACE_DATE 0x0FFFFFFFU
|
||||
#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S)
|
||||
#define TRACE_DATE_V 0x0FFFFFFFU
|
||||
#define TRACE_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
461
components/soc/esp32c5/include/soc/trace_struct.h
Normal file
461
components/soc/esp32c5/include/soc/trace_struct.h
Normal file
@@ -0,0 +1,461 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Trace memory configuration registers */
|
||||
/** Type of mem_start_addr register
|
||||
* mem start addr
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
|
||||
* The start address of trace memory
|
||||
*/
|
||||
uint32_t mem_start_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_mem_start_addr_reg_t;
|
||||
|
||||
/** Type of mem_end_addr register
|
||||
* mem end addr
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* The end address of trace memory
|
||||
*/
|
||||
uint32_t mem_end_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_mem_end_addr_reg_t;
|
||||
|
||||
/** Type of mem_current_addr register
|
||||
* mem current addr
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mem_current_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* current_mem_addr,indicate that next writing addr
|
||||
*/
|
||||
uint32_t mem_current_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_mem_current_addr_reg_t;
|
||||
|
||||
/** Type of mem_addr_update register
|
||||
* mem addr update
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mem_current_addr_update : WT; bitpos: [0]; default: 0;
|
||||
* when set, the will
|
||||
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
|
||||
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
|
||||
*/
|
||||
uint32_t mem_current_addr_update:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_mem_addr_update_reg_t;
|
||||
|
||||
|
||||
/** Group: Trace fifo status register */
|
||||
/** Type of fifo_status register
|
||||
* fifo status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** fifo_empty : RO; bitpos: [0]; default: 1;
|
||||
* Represent whether the fifo is empty. \\1: empty \\0: not empty
|
||||
*/
|
||||
uint32_t fifo_empty:1;
|
||||
/** work_status : RO; bitpos: [2:1]; default: 0;
|
||||
* Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due
|
||||
* to hart halted or havereset \\3: lost state
|
||||
*/
|
||||
uint32_t work_status:2;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_fifo_status_reg_t;
|
||||
|
||||
|
||||
/** Group: Trace interrupt configuration registers */
|
||||
/** Type of intr_ena register
|
||||
* interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Set 1 enable fifo_overflow interrupt
|
||||
*/
|
||||
uint32_t fifo_overflow_intr_ena:1;
|
||||
/** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Set 1 enable mem_full interrupt
|
||||
*/
|
||||
uint32_t mem_full_intr_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_intr_ena_reg_t;
|
||||
|
||||
/** Type of intr_raw register
|
||||
* interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
|
||||
* fifo_overflow interrupt status
|
||||
*/
|
||||
uint32_t fifo_overflow_intr_raw:1;
|
||||
/** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
|
||||
* mem_full interrupt status
|
||||
*/
|
||||
uint32_t mem_full_intr_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_intr_raw_reg_t;
|
||||
|
||||
/** Type of intr_clr register
|
||||
* interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set 1 clear fifo overflow interrupt
|
||||
*/
|
||||
uint32_t fifo_overflow_intr_clr:1;
|
||||
/** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set 1 clear mem full interrupt
|
||||
*/
|
||||
uint32_t mem_full_intr_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_intr_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Trace configuration register */
|
||||
/** Type of trigger register
|
||||
* trigger register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** trigger_on : WT; bitpos: [0]; default: 0;
|
||||
* Configure whether or not start trace.\\1: start trace \\0: invalid\\
|
||||
*/
|
||||
uint32_t trigger_on:1;
|
||||
/** trigger_off : WT; bitpos: [1]; default: 0;
|
||||
* Configure whether or not stop trace.\\1: stop trace \\0: invalid\\
|
||||
*/
|
||||
uint32_t trigger_off:1;
|
||||
/** mem_loop : R/W; bitpos: [2]; default: 1;
|
||||
* Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when
|
||||
* mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\
|
||||
*/
|
||||
uint32_t mem_loop:1;
|
||||
/** restart_ena : R/W; bitpos: [3]; default: 1;
|
||||
* Configure whether or not enable auto-restart.\\1: enable\\0: disable\\
|
||||
*/
|
||||
uint32_t restart_ena:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_trigger_reg_t;
|
||||
|
||||
/** Type of config register
|
||||
* trace configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\
|
||||
*/
|
||||
uint32_t dm_trigger_ena:1;
|
||||
/** reset_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Configure whether or not enable trace cpu haverest, when enabeld, if cpu have
|
||||
* reset, the encoder will output a packet to report the address of the last
|
||||
* instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0:
|
||||
* disabled\\
|
||||
*/
|
||||
uint32_t reset_ena:1;
|
||||
/** halt_ena : R/W; bitpos: [2]; default: 0;
|
||||
* Configure whether or not enable trace cpu is halted, when enabeld, if the cpu
|
||||
* halted, the encoder will output a packet to report the address of the last
|
||||
* instruction, and upon halted deassertion, the encoder start again.When disabled,
|
||||
* encoder will not report the last address before halted and first address after
|
||||
* halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\
|
||||
*/
|
||||
uint32_t halt_ena:1;
|
||||
/** stall_ena : R/W; bitpos: [3]; default: 0;
|
||||
* Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
|
||||
* the cpu will be stalled until the packets is able to write to fifo.\\1:
|
||||
* enabled.\\0: disabled\\
|
||||
*/
|
||||
uint32_t stall_ena:1;
|
||||
/** full_address : R/W; bitpos: [4]; default: 0;
|
||||
* Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta
|
||||
* address mode\\
|
||||
*/
|
||||
uint32_t full_address:1;
|
||||
/** implicit_except : R/W; bitpos: [5]; default: 0;
|
||||
* Configure whether or not enabel implicit exception mode. When enabled,, do not sent
|
||||
* exception address, only exception cause in exception packets.\\1: enabled\\0:
|
||||
* disabled\\
|
||||
*/
|
||||
uint32_t implicit_except:1;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_config_reg_t;
|
||||
|
||||
/** Type of filter_control register
|
||||
* filter control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** filter_en : R/W; bitpos: [0]; default: 0;
|
||||
* Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match
|
||||
*/
|
||||
uint32_t filter_en:1;
|
||||
/** match_comp : R/W; bitpos: [1]; default: 0;
|
||||
* when set, the comparator must be high in order for the filter to match
|
||||
*/
|
||||
uint32_t match_comp:1;
|
||||
/** match_privilege : R/W; bitpos: [2]; default: 0;
|
||||
* when set, match privilege levels specified by
|
||||
* \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
|
||||
*/
|
||||
uint32_t match_privilege:1;
|
||||
/** match_ecause : R/W; bitpos: [3]; default: 0;
|
||||
* when set, start matching from exception cause codes specified by
|
||||
* \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
|
||||
* matching upon return from the 1st matching exception.
|
||||
*/
|
||||
uint32_t match_ecause:1;
|
||||
/** match_interrupt : R/W; bitpos: [4]; default: 0;
|
||||
* when set, start matching from a trap with the interrupt level codes specified by
|
||||
* \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
|
||||
* stop matching upon return from the 1st matching trap.
|
||||
*/
|
||||
uint32_t match_interrupt:1;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_filter_control_reg_t;
|
||||
|
||||
/** Type of filter_match_control register
|
||||
* filter match control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** match_choice_privilege : R/W; bitpos: [0]; default: 0;
|
||||
* Select match which privilege level when
|
||||
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1:
|
||||
* machine mode. \\0: user mode
|
||||
*/
|
||||
uint32_t match_choice_privilege:1;
|
||||
/** match_value_interrupt : R/W; bitpos: [1]; default: 0;
|
||||
* Select which match which itype when
|
||||
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match
|
||||
* itype of 2. \\0: match itype or 1.
|
||||
*/
|
||||
uint32_t match_value_interrupt:1;
|
||||
/** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
|
||||
* specified which ecause matched.
|
||||
*/
|
||||
uint32_t match_choice_ecause:6;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_filter_match_control_reg_t;
|
||||
|
||||
/** Type of filter_comparator_control register
|
||||
* filter comparator match control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** p_input : R/W; bitpos: [0]; default: 0;
|
||||
* Determines which input to compare against the primary comparator, \\0: iaddr, \\1:
|
||||
* tval.
|
||||
*/
|
||||
uint32_t p_input:1;
|
||||
uint32_t reserved_1:1;
|
||||
/** p_function : R/W; bitpos: [4:2]; default: 0;
|
||||
* Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than,
|
||||
* \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other:
|
||||
* always match
|
||||
*/
|
||||
uint32_t p_function:3;
|
||||
/** p_notify : R/W; bitpos: [5]; default: 0;
|
||||
* Generate a trace packet explicitly reporting the address that cause the primary
|
||||
* match
|
||||
*/
|
||||
uint32_t p_notify:1;
|
||||
uint32_t reserved_6:2;
|
||||
/** s_input : R/W; bitpos: [8]; default: 0;
|
||||
* Determines which input to compare against the secondary comparator, \\0: iaddr,
|
||||
* \\1: tval.
|
||||
*/
|
||||
uint32_t s_input:1;
|
||||
uint32_t reserved_9:1;
|
||||
/** s_function : R/W; bitpos: [12:10]; default: 0;
|
||||
* Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less
|
||||
* than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal,
|
||||
* \\other: always match
|
||||
*/
|
||||
uint32_t s_function:3;
|
||||
/** s_notify : R/W; bitpos: [13]; default: 0;
|
||||
* Generate a trace packet explicitly reporting the address that cause the secondary
|
||||
* match
|
||||
*/
|
||||
uint32_t s_notify:1;
|
||||
uint32_t reserved_14:2;
|
||||
/** match_mode : R/W; bitpos: [17:16]; default: 0;
|
||||
* 0: only primary matches, \\1: primary and secondary comparator both
|
||||
* matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3:
|
||||
* set when primary matches and continue to match until after secondary comparator
|
||||
* matches
|
||||
*/
|
||||
uint32_t match_mode:2;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_filter_comparator_control_reg_t;
|
||||
|
||||
/** Type of filter_p_comparator_match register
|
||||
* primary comparator match value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** p_match : R/W; bitpos: [31:0]; default: 0;
|
||||
* primary comparator match value
|
||||
*/
|
||||
uint32_t p_match:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_filter_p_comparator_match_reg_t;
|
||||
|
||||
/** Type of filter_s_comparator_match register
|
||||
* secondary comparator match value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** s_match : R/W; bitpos: [31:0]; default: 0;
|
||||
* secondary comparator match value
|
||||
*/
|
||||
uint32_t s_match:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_filter_s_comparator_match_reg_t;
|
||||
|
||||
/** Type of resync_prolonged register
|
||||
* resync configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
|
||||
* count number, when count to this value, send a sync package
|
||||
*/
|
||||
uint32_t resync_prolonged:24;
|
||||
/** resync_mode : R/W; bitpos: [25:24]; default: 0;
|
||||
* resyc mode sel: \\0: off, \\2: cycle count \\3: package num count
|
||||
*/
|
||||
uint32_t resync_mode:2;
|
||||
uint32_t reserved_26:6;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_resync_prolonged_reg_t;
|
||||
|
||||
/** Type of ahb_config register
|
||||
* AHB config register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hburst : R/W; bitpos: [2:0]; default: 0;
|
||||
* set hburst
|
||||
*/
|
||||
uint32_t hburst:3;
|
||||
/** max_incr : R/W; bitpos: [5:3]; default: 0;
|
||||
* set max continuous access for incr mode
|
||||
*/
|
||||
uint32_t max_incr:3;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_ahb_config_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock Gate Control and configuration register */
|
||||
/** Type of clock_gate register
|
||||
* Clock gate control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* The bit is used to enable clock gate when access all registers in this module.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 35721984;
|
||||
* version control register. Note that this default value stored is the latest date
|
||||
* when the hardware logic was updated.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} trace_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile trace_mem_start_addr_reg_t mem_start_addr;
|
||||
volatile trace_mem_end_addr_reg_t mem_end_addr;
|
||||
volatile trace_mem_current_addr_reg_t mem_current_addr;
|
||||
volatile trace_mem_addr_update_reg_t mem_addr_update;
|
||||
volatile trace_fifo_status_reg_t fifo_status;
|
||||
volatile trace_intr_ena_reg_t intr_ena;
|
||||
volatile trace_intr_raw_reg_t intr_raw;
|
||||
volatile trace_intr_clr_reg_t intr_clr;
|
||||
volatile trace_trigger_reg_t trigger;
|
||||
volatile trace_config_reg_t config;
|
||||
volatile trace_filter_control_reg_t filter_control;
|
||||
volatile trace_filter_match_control_reg_t filter_match_control;
|
||||
volatile trace_filter_comparator_control_reg_t filter_comparator_control;
|
||||
volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
|
||||
volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
|
||||
volatile trace_resync_prolonged_reg_t resync_prolonged;
|
||||
volatile trace_ahb_config_reg_t ahb_config;
|
||||
volatile trace_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_048[237];
|
||||
volatile trace_date_reg_t date;
|
||||
} trace_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1579
components/soc/esp32c5/include/soc/uart_reg.h
Normal file
1579
components/soc/esp32c5/include/soc/uart_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1271
components/soc/esp32c5/include/soc/uart_struct.h
Normal file
1271
components/soc/esp32c5/include/soc/uart_struct.h
Normal file
File diff suppressed because it is too large
Load Diff
966
components/soc/esp32c5/include/soc/uhci_reg.h
Normal file
966
components/soc/esp32c5/include/soc/uhci_reg.h
Normal file
@@ -0,0 +1,966 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** UHCI_CONF0_REG register
|
||||
* UHCI Configuration Register0
|
||||
*/
|
||||
#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
|
||||
/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 then write 0 to this bit to reset decode state machine.
|
||||
*/
|
||||
#define UHCI_TX_RST (BIT(0))
|
||||
#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S)
|
||||
#define UHCI_TX_RST_V 0x00000001U
|
||||
#define UHCI_TX_RST_S 0
|
||||
/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 then write 0 to this bit to reset encode state machine.
|
||||
*/
|
||||
#define UHCI_RX_RST (BIT(1))
|
||||
#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S)
|
||||
#define UHCI_RX_RST_V 0x00000001U
|
||||
#define UHCI_RX_RST_S 1
|
||||
/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7;
|
||||
* Select which uart to connect with GDMA.
|
||||
*/
|
||||
#define UHCI_UART_SEL 0x00000007U
|
||||
#define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S)
|
||||
#define UHCI_UART_SEL_V 0x00000007U
|
||||
#define UHCI_UART_SEL_S 2
|
||||
/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
|
||||
* Set this bit to separate the data frame using a special char.
|
||||
*/
|
||||
#define UHCI_SEPER_EN (BIT(5))
|
||||
#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
|
||||
#define UHCI_SEPER_EN_V 0x00000001U
|
||||
#define UHCI_SEPER_EN_S 5
|
||||
/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
|
||||
* Set this bit to encode the data packet with a formatting header.
|
||||
*/
|
||||
#define UHCI_HEAD_EN (BIT(6))
|
||||
#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
|
||||
#define UHCI_HEAD_EN_V 0x00000001U
|
||||
#define UHCI_HEAD_EN_S 6
|
||||
/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
|
||||
* Set this bit to enable UHCI to receive the 16 bit CRC.
|
||||
*/
|
||||
#define UHCI_CRC_REC_EN (BIT(7))
|
||||
#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
|
||||
#define UHCI_CRC_REC_EN_V 0x00000001U
|
||||
#define UHCI_CRC_REC_EN_S 7
|
||||
/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
|
||||
* If this bit is set to 1 UHCI will end the payload receiving process when UART has
|
||||
* been in idle state.
|
||||
*/
|
||||
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
|
||||
#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
|
||||
#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U
|
||||
#define UHCI_UART_IDLE_EOF_EN_S 8
|
||||
/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
|
||||
* If this bit is set to 1 UHCI decoder receiving payload data is end when the
|
||||
* receiving byte count has reached the specified value. The value is payload length
|
||||
* indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
|
||||
* configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
|
||||
* receiving payload data is end when 0xc0 is received.
|
||||
*/
|
||||
#define UHCI_LEN_EOF_EN (BIT(9))
|
||||
#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
|
||||
#define UHCI_LEN_EOF_EN_V 0x00000001U
|
||||
#define UHCI_LEN_EOF_EN_S 9
|
||||
/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
|
||||
* Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
|
||||
* end of the payload.
|
||||
*/
|
||||
#define UHCI_ENCODE_CRC_EN (BIT(10))
|
||||
#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
|
||||
#define UHCI_ENCODE_CRC_EN_V 0x00000001U
|
||||
#define UHCI_ENCODE_CRC_EN_S 10
|
||||
/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
|
||||
* 1'b1: Force clock on for register. 1'b0: Support clock only when application writes
|
||||
* registers.
|
||||
*/
|
||||
#define UHCI_CLK_EN (BIT(11))
|
||||
#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
|
||||
#define UHCI_CLK_EN_V 0x00000001U
|
||||
#define UHCI_CLK_EN_S 11
|
||||
/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
|
||||
* If this bit is set to 1 UHCI will end payload receive process when NULL frame is
|
||||
* received by UART.
|
||||
*/
|
||||
#define UHCI_UART_RX_BRK_EOF_EN (BIT(12))
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_S 12
|
||||
|
||||
/** UHCI_INT_RAW_REG register
|
||||
* UHCI Interrupt Raw Register
|
||||
*/
|
||||
#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
|
||||
/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
|
||||
* delimiter is sent successfully.
|
||||
*/
|
||||
#define UHCI_RX_START_INT_RAW (BIT(0))
|
||||
#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S)
|
||||
#define UHCI_RX_START_INT_RAW_V 0x00000001U
|
||||
#define UHCI_RX_START_INT_RAW_S 0
|
||||
/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
|
||||
* DMA detects delimiter.
|
||||
*/
|
||||
#define UHCI_TX_START_INT_RAW (BIT(1))
|
||||
#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S)
|
||||
#define UHCI_TX_START_INT_RAW_V 0x00000001U
|
||||
#define UHCI_TX_START_INT_RAW_S 1
|
||||
/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
|
||||
* the required time of DMA receiving data exceeds the configuration value.
|
||||
*/
|
||||
#define UHCI_RX_HUNG_INT_RAW (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S)
|
||||
#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U
|
||||
#define UHCI_RX_HUNG_INT_RAW_S 2
|
||||
/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
|
||||
* the required time of DMA reading RAM data exceeds the configuration value.
|
||||
*/
|
||||
#define UHCI_TX_HUNG_INT_RAW (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S)
|
||||
#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U
|
||||
#define UHCI_TX_HUNG_INT_RAW_S 3
|
||||
/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
|
||||
* when UHCI sends short packet successfully with single_send mode.
|
||||
*/
|
||||
#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4))
|
||||
#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S)
|
||||
#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U
|
||||
#define UHCI_SEND_S_REG_Q_INT_RAW_S 4
|
||||
/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
|
||||
* when UHCI sends short packet successfully with always_send mode.
|
||||
*/
|
||||
#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5))
|
||||
#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S)
|
||||
#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U
|
||||
#define UHCI_SEND_A_REG_Q_INT_RAW_S 5
|
||||
/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
|
||||
* there are errors in EOF.
|
||||
*/
|
||||
#define UHCI_OUT_EOF_INT_RAW (BIT(6))
|
||||
#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S)
|
||||
#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U
|
||||
#define UHCI_OUT_EOF_INT_RAW_S 6
|
||||
/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
|
||||
* UHCI_APP_CTRL0_IN_SET is set to 1.
|
||||
*/
|
||||
#define UHCI_APP_CTRL0_INT_RAW (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S)
|
||||
#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U
|
||||
#define UHCI_APP_CTRL0_INT_RAW_S 7
|
||||
/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
|
||||
* UHCI_APP_CTRL1_IN_SET is set to 1.
|
||||
*/
|
||||
#define UHCI_APP_CTRL1_INT_RAW (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S)
|
||||
#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U
|
||||
#define UHCI_APP_CTRL1_INT_RAW_S 8
|
||||
|
||||
/** UHCI_INT_ST_REG register
|
||||
* UHCI Interrupt Status Register
|
||||
*/
|
||||
#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
|
||||
/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_RX_START_INT.
|
||||
*/
|
||||
#define UHCI_RX_START_INT_ST (BIT(0))
|
||||
#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S)
|
||||
#define UHCI_RX_START_INT_ST_V 0x00000001U
|
||||
#define UHCI_RX_START_INT_ST_S 0
|
||||
/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_TX_START_INT.
|
||||
*/
|
||||
#define UHCI_TX_START_INT_ST (BIT(1))
|
||||
#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S)
|
||||
#define UHCI_TX_START_INT_ST_V 0x00000001U
|
||||
#define UHCI_TX_START_INT_ST_S 1
|
||||
/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_RX_HUNG_INT.
|
||||
*/
|
||||
#define UHCI_RX_HUNG_INT_ST (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S)
|
||||
#define UHCI_RX_HUNG_INT_ST_V 0x00000001U
|
||||
#define UHCI_RX_HUNG_INT_ST_S 2
|
||||
/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_TX_HUNG_INT.
|
||||
*/
|
||||
#define UHCI_TX_HUNG_INT_ST (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S)
|
||||
#define UHCI_TX_HUNG_INT_ST_V 0x00000001U
|
||||
#define UHCI_TX_HUNG_INT_ST_S 3
|
||||
/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
|
||||
*/
|
||||
#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4))
|
||||
#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S)
|
||||
#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U
|
||||
#define UHCI_SEND_S_REG_Q_INT_ST_S 4
|
||||
/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
|
||||
*/
|
||||
#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5))
|
||||
#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S)
|
||||
#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U
|
||||
#define UHCI_SEND_A_REG_Q_INT_ST_S 5
|
||||
/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_OUT_EOF_INT.
|
||||
*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S)
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6
|
||||
/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_APP_CTRL0_INT.
|
||||
*/
|
||||
#define UHCI_APP_CTRL0_INT_ST (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S)
|
||||
#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U
|
||||
#define UHCI_APP_CTRL0_INT_ST_S 7
|
||||
/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_APP_CTRL1_INT.
|
||||
*/
|
||||
#define UHCI_APP_CTRL1_INT_ST (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S)
|
||||
#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U
|
||||
#define UHCI_APP_CTRL1_INT_ST_S 8
|
||||
|
||||
/** UHCI_INT_ENA_REG register
|
||||
* UHCI Interrupt Enable Register
|
||||
*/
|
||||
#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
|
||||
/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_RX_START_INT.
|
||||
*/
|
||||
#define UHCI_RX_START_INT_ENA (BIT(0))
|
||||
#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S)
|
||||
#define UHCI_RX_START_INT_ENA_V 0x00000001U
|
||||
#define UHCI_RX_START_INT_ENA_S 0
|
||||
/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_TX_START_INT.
|
||||
*/
|
||||
#define UHCI_TX_START_INT_ENA (BIT(1))
|
||||
#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S)
|
||||
#define UHCI_TX_START_INT_ENA_V 0x00000001U
|
||||
#define UHCI_TX_START_INT_ENA_S 1
|
||||
/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
|
||||
*/
|
||||
#define UHCI_RX_HUNG_INT_ENA (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S)
|
||||
#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U
|
||||
#define UHCI_RX_HUNG_INT_ENA_S 2
|
||||
/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
|
||||
*/
|
||||
#define UHCI_TX_HUNG_INT_ENA (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S)
|
||||
#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U
|
||||
#define UHCI_TX_HUNG_INT_ENA_S 3
|
||||
/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
|
||||
*/
|
||||
#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4))
|
||||
#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S)
|
||||
#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U
|
||||
#define UHCI_SEND_S_REG_Q_INT_ENA_S 4
|
||||
/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
|
||||
*/
|
||||
#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5))
|
||||
#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S)
|
||||
#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U
|
||||
#define UHCI_SEND_A_REG_Q_INT_ENA_S 5
|
||||
/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
|
||||
*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S)
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6
|
||||
/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
|
||||
*/
|
||||
#define UHCI_APP_CTRL0_INT_ENA (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S)
|
||||
#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U
|
||||
#define UHCI_APP_CTRL0_INT_ENA_S 7
|
||||
/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
|
||||
*/
|
||||
#define UHCI_APP_CTRL1_INT_ENA (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S)
|
||||
#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U
|
||||
#define UHCI_APP_CTRL1_INT_ENA_S 8
|
||||
|
||||
/** UHCI_INT_CLR_REG register
|
||||
* UHCI Interrupt Clear Register
|
||||
*/
|
||||
#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
|
||||
/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
|
||||
*/
|
||||
#define UHCI_RX_START_INT_CLR (BIT(0))
|
||||
#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S)
|
||||
#define UHCI_RX_START_INT_CLR_V 0x00000001U
|
||||
#define UHCI_RX_START_INT_CLR_S 0
|
||||
/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
|
||||
*/
|
||||
#define UHCI_TX_START_INT_CLR (BIT(1))
|
||||
#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S)
|
||||
#define UHCI_TX_START_INT_CLR_V 0x00000001U
|
||||
#define UHCI_TX_START_INT_CLR_S 1
|
||||
/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
|
||||
*/
|
||||
#define UHCI_RX_HUNG_INT_CLR (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S)
|
||||
#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U
|
||||
#define UHCI_RX_HUNG_INT_CLR_S 2
|
||||
/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
|
||||
*/
|
||||
#define UHCI_TX_HUNG_INT_CLR (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S)
|
||||
#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U
|
||||
#define UHCI_TX_HUNG_INT_CLR_S 3
|
||||
/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
|
||||
*/
|
||||
#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4))
|
||||
#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S)
|
||||
#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U
|
||||
#define UHCI_SEND_S_REG_Q_INT_CLR_S 4
|
||||
/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
|
||||
*/
|
||||
#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5))
|
||||
#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S)
|
||||
#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U
|
||||
#define UHCI_SEND_A_REG_Q_INT_CLR_S 5
|
||||
/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
|
||||
*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S)
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6
|
||||
/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
|
||||
*/
|
||||
#define UHCI_APP_CTRL0_INT_CLR (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S)
|
||||
#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U
|
||||
#define UHCI_APP_CTRL0_INT_CLR_S 7
|
||||
/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
|
||||
*/
|
||||
#define UHCI_APP_CTRL1_INT_CLR (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S)
|
||||
#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U
|
||||
#define UHCI_APP_CTRL1_INT_CLR_S 8
|
||||
|
||||
/** UHCI_CONF1_REG register
|
||||
* UHCI Configuration Register1
|
||||
*/
|
||||
#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
|
||||
/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Set this bit to enable head checksum check when receiving.
|
||||
*/
|
||||
#define UHCI_CHECK_SUM_EN (BIT(0))
|
||||
#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
|
||||
#define UHCI_CHECK_SUM_EN_V 0x00000001U
|
||||
#define UHCI_CHECK_SUM_EN_S 0
|
||||
/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
|
||||
* Set this bit to enable sequence number check when receiving.
|
||||
*/
|
||||
#define UHCI_CHECK_SEQ_EN (BIT(1))
|
||||
#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
|
||||
#define UHCI_CHECK_SEQ_EN_V 0x00000001U
|
||||
#define UHCI_CHECK_SEQ_EN_S 1
|
||||
/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to support CRC calculation, and data integrity check bit should 1.
|
||||
*/
|
||||
#define UHCI_CRC_DISABLE (BIT(2))
|
||||
#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
|
||||
#define UHCI_CRC_DISABLE_V 0x00000001U
|
||||
#define UHCI_CRC_DISABLE_S 2
|
||||
/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to save data packet head when UHCI receive data.
|
||||
*/
|
||||
#define UHCI_SAVE_HEAD (BIT(3))
|
||||
#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
|
||||
#define UHCI_SAVE_HEAD_V 0x00000001U
|
||||
#define UHCI_SAVE_HEAD_S 3
|
||||
/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
|
||||
* Set this bit to encode data packet with checksum.
|
||||
*/
|
||||
#define UHCI_TX_CHECK_SUM_RE (BIT(4))
|
||||
#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
|
||||
#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U
|
||||
#define UHCI_TX_CHECK_SUM_RE_S 4
|
||||
/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
|
||||
* Set this bit to encode data packet with ACK when reliable data packet is ready.
|
||||
*/
|
||||
#define UHCI_TX_ACK_NUM_RE (BIT(5))
|
||||
#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
|
||||
#define UHCI_TX_ACK_NUM_RE_V 0x00000001U
|
||||
#define UHCI_TX_ACK_NUM_RE_S 5
|
||||
/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
|
||||
*/
|
||||
#define UHCI_WAIT_SW_START (BIT(7))
|
||||
#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
|
||||
#define UHCI_WAIT_SW_START_V 0x00000001U
|
||||
#define UHCI_WAIT_SW_START_S 7
|
||||
/** UHCI_SW_START : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
|
||||
*/
|
||||
#define UHCI_SW_START (BIT(8))
|
||||
#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S)
|
||||
#define UHCI_SW_START_V 0x00000001U
|
||||
#define UHCI_SW_START_S 8
|
||||
|
||||
/** UHCI_STATE0_REG register
|
||||
* UHCI Receive Status Register
|
||||
*/
|
||||
#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
|
||||
/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
|
||||
* Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
|
||||
* checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
|
||||
* bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
|
||||
* not found, but received packet is completed. 3'b110: CRC check error.
|
||||
*/
|
||||
#define UHCI_RX_ERR_CAUSE 0x00000007U
|
||||
#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
|
||||
#define UHCI_RX_ERR_CAUSE_V 0x00000007U
|
||||
#define UHCI_RX_ERR_CAUSE_S 0
|
||||
/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0;
|
||||
* Indicates UHCI decoder status.
|
||||
*/
|
||||
#define UHCI_DECODE_STATE 0x00000007U
|
||||
#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S)
|
||||
#define UHCI_DECODE_STATE_V 0x00000007U
|
||||
#define UHCI_DECODE_STATE_S 3
|
||||
|
||||
/** UHCI_STATE1_REG register
|
||||
* UHCI Transmit Status Register
|
||||
*/
|
||||
#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
|
||||
/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
|
||||
* Indicates UHCI encoder status.
|
||||
*/
|
||||
#define UHCI_ENCODE_STATE 0x00000007U
|
||||
#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S)
|
||||
#define UHCI_ENCODE_STATE_V 0x00000007U
|
||||
#define UHCI_ENCODE_STATE_S 0
|
||||
|
||||
/** UHCI_ESCAPE_CONF_REG register
|
||||
* UHCI Escapes Configuration Register0
|
||||
*/
|
||||
#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
|
||||
/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Set this bit to enable resolve char 0xC0 when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_TX_C0_ESC_EN (BIT(0))
|
||||
#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
|
||||
#define UHCI_TX_C0_ESC_EN_V 0x00000001U
|
||||
#define UHCI_TX_C0_ESC_EN_S 0
|
||||
/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
|
||||
* Set this bit to enable resolve char 0xDB when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_TX_DB_ESC_EN (BIT(1))
|
||||
#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
|
||||
#define UHCI_TX_DB_ESC_EN_V 0x00000001U
|
||||
#define UHCI_TX_DB_ESC_EN_S 1
|
||||
/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_TX_11_ESC_EN (BIT(2))
|
||||
#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
|
||||
#define UHCI_TX_11_ESC_EN_V 0x00000001U
|
||||
#define UHCI_TX_11_ESC_EN_S 2
|
||||
/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_TX_13_ESC_EN (BIT(3))
|
||||
#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
|
||||
#define UHCI_TX_13_ESC_EN_V 0x00000001U
|
||||
#define UHCI_TX_13_ESC_EN_S 3
|
||||
/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
|
||||
* Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_RX_C0_ESC_EN (BIT(4))
|
||||
#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
|
||||
#define UHCI_RX_C0_ESC_EN_V 0x00000001U
|
||||
#define UHCI_RX_C0_ESC_EN_S 4
|
||||
/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
|
||||
* Set this bit to enable replacing 0xDB with special char when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_RX_DB_ESC_EN (BIT(5))
|
||||
#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
|
||||
#define UHCI_RX_DB_ESC_EN_V 0x00000001U
|
||||
#define UHCI_RX_DB_ESC_EN_S 5
|
||||
/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
|
||||
* Set this bit to enable replacing 0x11 with special char when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_RX_11_ESC_EN (BIT(6))
|
||||
#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
|
||||
#define UHCI_RX_11_ESC_EN_V 0x00000001U
|
||||
#define UHCI_RX_11_ESC_EN_S 6
|
||||
/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable replacing 0x13 with special char when DMA receiving data.
|
||||
*/
|
||||
#define UHCI_RX_13_ESC_EN (BIT(7))
|
||||
#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
|
||||
#define UHCI_RX_13_ESC_EN_V 0x00000001U
|
||||
#define UHCI_RX_13_ESC_EN_S 7
|
||||
|
||||
/** UHCI_HUNG_CONF_REG register
|
||||
* UHCI Hung Configuration Register0
|
||||
*/
|
||||
#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
|
||||
/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
|
||||
* Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
|
||||
* data.
|
||||
*/
|
||||
#define UHCI_TXFIFO_TIMEOUT 0x000000FFU
|
||||
#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
|
||||
#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU
|
||||
#define UHCI_TXFIFO_TIMEOUT_S 0
|
||||
/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
|
||||
* Configures the maximum counter value.
|
||||
*/
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S)
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
|
||||
/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
|
||||
* Set this bit to enable TX FIFO timeout when receiving.
|
||||
*/
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
|
||||
/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
|
||||
* Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
|
||||
* RAM data.
|
||||
*/
|
||||
#define UHCI_RXFIFO_TIMEOUT 0x000000FFU
|
||||
#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
|
||||
#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU
|
||||
#define UHCI_RXFIFO_TIMEOUT_S 12
|
||||
/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0;
|
||||
* Configures the maximum counter value.
|
||||
*/
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S)
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
|
||||
/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
|
||||
* Set this bit to enable TX FIFO timeout when DMA sending data.
|
||||
*/
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_S 23
|
||||
|
||||
/** UHCI_ACK_NUM_REG register
|
||||
* UHCI Ack Value Configuration Register0
|
||||
*/
|
||||
#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
|
||||
/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
|
||||
* Indicates the ACK number during software flow control.
|
||||
*/
|
||||
#define UHCI_ACK_NUM 0x00000007U
|
||||
#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S)
|
||||
#define UHCI_ACK_NUM_V 0x00000007U
|
||||
#define UHCI_ACK_NUM_S 0
|
||||
/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to load the ACK value of UHCI_ACK_NUM.
|
||||
*/
|
||||
#define UHCI_ACK_NUM_LOAD (BIT(3))
|
||||
#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
|
||||
#define UHCI_ACK_NUM_LOAD_V 0x00000001U
|
||||
#define UHCI_ACK_NUM_LOAD_S 3
|
||||
|
||||
/** UHCI_RX_HEAD_REG register
|
||||
* UHCI Head Register
|
||||
*/
|
||||
#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
|
||||
/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the head of received packet.
|
||||
*/
|
||||
#define UHCI_RX_HEAD 0xFFFFFFFFU
|
||||
#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S)
|
||||
#define UHCI_RX_HEAD_V 0xFFFFFFFFU
|
||||
#define UHCI_RX_HEAD_S 0
|
||||
|
||||
/** UHCI_QUICK_SENT_REG register
|
||||
* UCHI Quick send Register
|
||||
*/
|
||||
#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
|
||||
/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures single_send mode.
|
||||
*/
|
||||
#define UHCI_SINGLE_SEND_NUM 0x00000007U
|
||||
#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
|
||||
#define UHCI_SINGLE_SEND_NUM_V 0x00000007U
|
||||
#define UHCI_SINGLE_SEND_NUM_S 0
|
||||
/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to enable sending short packet with single_send mode.
|
||||
*/
|
||||
#define UHCI_SINGLE_SEND_EN (BIT(3))
|
||||
#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S)
|
||||
#define UHCI_SINGLE_SEND_EN_V 0x00000001U
|
||||
#define UHCI_SINGLE_SEND_EN_S 3
|
||||
/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
|
||||
* Configures always_send mode.
|
||||
*/
|
||||
#define UHCI_ALWAYS_SEND_NUM 0x00000007U
|
||||
#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
|
||||
#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U
|
||||
#define UHCI_ALWAYS_SEND_NUM_S 4
|
||||
/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable sending short packet with always_send mode.
|
||||
*/
|
||||
#define UHCI_ALWAYS_SEND_EN (BIT(7))
|
||||
#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
|
||||
#define UHCI_ALWAYS_SEND_EN_V 0x00000001U
|
||||
#define UHCI_ALWAYS_SEND_EN_S 7
|
||||
|
||||
/** UHCI_REG_Q0_WORD0_REG register
|
||||
* UHCI Q0_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
|
||||
/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S)
|
||||
#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q0_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q0_WORD1_REG register
|
||||
* UHCI Q0_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
|
||||
/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S)
|
||||
#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q0_WORD1_S 0
|
||||
|
||||
/** UHCI_REG_Q1_WORD0_REG register
|
||||
* UHCI Q1_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
|
||||
/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S)
|
||||
#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q1_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q1_WORD1_REG register
|
||||
* UHCI Q1_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
|
||||
/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S)
|
||||
#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q1_WORD1_S 0
|
||||
|
||||
/** UHCI_REG_Q2_WORD0_REG register
|
||||
* UHCI Q2_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
|
||||
/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S)
|
||||
#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q2_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q2_WORD1_REG register
|
||||
* UHCI Q2_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
|
||||
/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S)
|
||||
#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q2_WORD1_S 0
|
||||
|
||||
/** UHCI_REG_Q3_WORD0_REG register
|
||||
* UHCI Q3_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
|
||||
/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S)
|
||||
#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q3_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q3_WORD1_REG register
|
||||
* UHCI Q3_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
|
||||
/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S)
|
||||
#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q3_WORD1_S 0
|
||||
|
||||
/** UHCI_REG_Q4_WORD0_REG register
|
||||
* UHCI Q4_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
|
||||
/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S)
|
||||
#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q4_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q4_WORD1_REG register
|
||||
* UHCI Q4_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
|
||||
/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S)
|
||||
#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q4_WORD1_S 0
|
||||
|
||||
/** UHCI_REG_Q5_WORD0_REG register
|
||||
* UHCI Q5_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
|
||||
/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S)
|
||||
#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q5_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q5_WORD1_REG register
|
||||
* UHCI Q5_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
|
||||
/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S)
|
||||
#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q5_WORD1_S 0
|
||||
|
||||
/** UHCI_REG_Q6_WORD0_REG register
|
||||
* UHCI Q6_WORD0 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
|
||||
/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S)
|
||||
#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q6_WORD0_S 0
|
||||
|
||||
/** UHCI_REG_Q6_WORD1_REG register
|
||||
* UHCI Q6_WORD1 Quick Send Register
|
||||
*/
|
||||
#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
|
||||
/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S)
|
||||
#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU
|
||||
#define UHCI_SEND_Q6_WORD1_S 0
|
||||
|
||||
/** UHCI_ESC_CONF0_REG register
|
||||
* UHCI Escapes Sequence Configuration Register0
|
||||
*/
|
||||
#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
|
||||
/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
|
||||
* Configures the delimiter for encoding, default value is 0xC0.
|
||||
*/
|
||||
#define UHCI_SEPER_CHAR 0x000000FFU
|
||||
#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S)
|
||||
#define UHCI_SEPER_CHAR_V 0x000000FFU
|
||||
#define UHCI_SEPER_CHAR_S 0
|
||||
/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
#define UHCI_SEPER_ESC_CHAR0 0x000000FFU
|
||||
#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S)
|
||||
#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU
|
||||
#define UHCI_SEPER_ESC_CHAR0_S 8
|
||||
/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDC.
|
||||
*/
|
||||
#define UHCI_SEPER_ESC_CHAR1 0x000000FFU
|
||||
#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S)
|
||||
#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU
|
||||
#define UHCI_SEPER_ESC_CHAR1_S 16
|
||||
|
||||
/** UHCI_ESC_CONF1_REG register
|
||||
* UHCI Escapes Sequence Configuration Register1
|
||||
*/
|
||||
#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
|
||||
/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
|
||||
* Configures the char needing encoding, which is 0xDB as flow control char by default.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ0 0x000000FFU
|
||||
#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S)
|
||||
#define UHCI_ESC_SEQ0_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ0_S 0
|
||||
/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU
|
||||
#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S)
|
||||
#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ0_CHAR0_S 8
|
||||
/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDD.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU
|
||||
#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S)
|
||||
#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ0_CHAR1_S 16
|
||||
|
||||
/** UHCI_ESC_CONF2_REG register
|
||||
* UHCI Escapes Sequence Configuration Register2
|
||||
*/
|
||||
#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
|
||||
/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
|
||||
* Configures the char needing encoding, which is 0x11 as flow control char by default.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ1 0x000000FFU
|
||||
#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S)
|
||||
#define UHCI_ESC_SEQ1_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ1_S 0
|
||||
/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU
|
||||
#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S)
|
||||
#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ1_CHAR0_S 8
|
||||
/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDE.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU
|
||||
#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S)
|
||||
#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ1_CHAR1_S 16
|
||||
|
||||
/** UHCI_ESC_CONF3_REG register
|
||||
* UHCI Escapes Sequence Configuration Register3
|
||||
*/
|
||||
#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
|
||||
/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
|
||||
* Configures the char needing encoding, which is 0x13 as flow control char by default.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ2 0x000000FFU
|
||||
#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S)
|
||||
#define UHCI_ESC_SEQ2_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ2_S 0
|
||||
/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU
|
||||
#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S)
|
||||
#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ2_CHAR0_S 8
|
||||
/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDF.
|
||||
*/
|
||||
#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU
|
||||
#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S)
|
||||
#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU
|
||||
#define UHCI_ESC_SEQ2_CHAR1_S 16
|
||||
|
||||
/** UHCI_PKT_THRES_REG register
|
||||
* UCHI Packet Length Configuration Register
|
||||
*/
|
||||
#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
|
||||
/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
|
||||
* Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
|
||||
*/
|
||||
#define UHCI_PKT_THRS 0x00001FFFU
|
||||
#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
|
||||
#define UHCI_PKT_THRS_V 0x00001FFFU
|
||||
#define UHCI_PKT_THRS_S 0
|
||||
|
||||
/** UHCI_DATE_REG register
|
||||
* UHCI Version Register
|
||||
*/
|
||||
#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
|
||||
/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
|
||||
* Configures version.
|
||||
*/
|
||||
#define UHCI_DATE 0xFFFFFFFFU
|
||||
#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S)
|
||||
#define UHCI_DATE_V 0xFFFFFFFFU
|
||||
#define UHCI_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
844
components/soc/esp32c5/include/soc/uhci_struct.h
Normal file
844
components/soc/esp32c5/include/soc/uhci_struct.h
Normal file
@@ -0,0 +1,844 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration Register */
|
||||
/** Type of conf0 register
|
||||
* UHCI Configuration Register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_rst : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 then write 0 to this bit to reset decode state machine.
|
||||
*/
|
||||
uint32_t tx_rst:1;
|
||||
/** rx_rst : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 then write 0 to this bit to reset encode state machine.
|
||||
*/
|
||||
uint32_t rx_rst:1;
|
||||
/** uart_sel : R/W; bitpos: [4:2]; default: 7;
|
||||
* Select which uart to connect with GDMA.
|
||||
*/
|
||||
uint32_t uart_sel:3;
|
||||
/** seper_en : R/W; bitpos: [5]; default: 1;
|
||||
* Set this bit to separate the data frame using a special char.
|
||||
*/
|
||||
uint32_t seper_en:1;
|
||||
/** head_en : R/W; bitpos: [6]; default: 1;
|
||||
* Set this bit to encode the data packet with a formatting header.
|
||||
*/
|
||||
uint32_t head_en:1;
|
||||
/** crc_rec_en : R/W; bitpos: [7]; default: 1;
|
||||
* Set this bit to enable UHCI to receive the 16 bit CRC.
|
||||
*/
|
||||
uint32_t crc_rec_en:1;
|
||||
/** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
|
||||
* If this bit is set to 1 UHCI will end the payload receiving process when UART has
|
||||
* been in idle state.
|
||||
*/
|
||||
uint32_t uart_idle_eof_en:1;
|
||||
/** len_eof_en : R/W; bitpos: [9]; default: 1;
|
||||
* If this bit is set to 1 UHCI decoder receiving payload data is end when the
|
||||
* receiving byte count has reached the specified value. The value is payload length
|
||||
* indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
|
||||
* configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
|
||||
* receiving payload data is end when 0xc0 is received.
|
||||
*/
|
||||
uint32_t len_eof_en:1;
|
||||
/** encode_crc_en : R/W; bitpos: [10]; default: 1;
|
||||
* Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
|
||||
* end of the payload.
|
||||
*/
|
||||
uint32_t encode_crc_en:1;
|
||||
/** clk_en : R/W; bitpos: [11]; default: 0;
|
||||
* 1'b1: Force clock on for register. 1'b0: Support clock only when application writes
|
||||
* registers.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
/** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
|
||||
* If this bit is set to 1 UHCI will end payload receive process when NULL frame is
|
||||
* received by UART.
|
||||
*/
|
||||
uint32_t uart_rx_brk_eof_en:1;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_conf0_reg_t;
|
||||
|
||||
/** Type of conf1 register
|
||||
* UHCI Configuration Register1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** check_sum_en : R/W; bitpos: [0]; default: 1;
|
||||
* Set this bit to enable head checksum check when receiving.
|
||||
*/
|
||||
uint32_t check_sum_en:1;
|
||||
/** check_seq_en : R/W; bitpos: [1]; default: 1;
|
||||
* Set this bit to enable sequence number check when receiving.
|
||||
*/
|
||||
uint32_t check_seq_en:1;
|
||||
/** crc_disable : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to support CRC calculation, and data integrity check bit should 1.
|
||||
*/
|
||||
uint32_t crc_disable:1;
|
||||
/** save_head : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to save data packet head when UHCI receive data.
|
||||
*/
|
||||
uint32_t save_head:1;
|
||||
/** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
|
||||
* Set this bit to encode data packet with checksum.
|
||||
*/
|
||||
uint32_t tx_check_sum_re:1;
|
||||
/** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
|
||||
* Set this bit to encode data packet with ACK when reliable data packet is ready.
|
||||
*/
|
||||
uint32_t tx_ack_num_re:1;
|
||||
uint32_t reserved_6:1;
|
||||
/** wait_sw_start : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
|
||||
*/
|
||||
uint32_t wait_sw_start:1;
|
||||
/** sw_start : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
|
||||
*/
|
||||
uint32_t sw_start:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_conf1_reg_t;
|
||||
|
||||
/** Type of escape_conf register
|
||||
* UHCI Escapes Configuration Register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
|
||||
* Set this bit to enable resolve char 0xC0 when DMA receiving data.
|
||||
*/
|
||||
uint32_t tx_c0_esc_en:1;
|
||||
/** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
|
||||
* Set this bit to enable resolve char 0xDB when DMA receiving data.
|
||||
*/
|
||||
uint32_t tx_db_esc_en:1;
|
||||
/** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
|
||||
*/
|
||||
uint32_t tx_11_esc_en:1;
|
||||
/** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
|
||||
*/
|
||||
uint32_t tx_13_esc_en:1;
|
||||
/** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
|
||||
* Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
|
||||
*/
|
||||
uint32_t rx_c0_esc_en:1;
|
||||
/** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
|
||||
* Set this bit to enable replacing 0xDB with special char when DMA receiving data.
|
||||
*/
|
||||
uint32_t rx_db_esc_en:1;
|
||||
/** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
|
||||
* Set this bit to enable replacing 0x11 with special char when DMA receiving data.
|
||||
*/
|
||||
uint32_t rx_11_esc_en:1;
|
||||
/** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable replacing 0x13 with special char when DMA receiving data.
|
||||
*/
|
||||
uint32_t rx_13_esc_en:1;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_escape_conf_reg_t;
|
||||
|
||||
/** Type of hung_conf register
|
||||
* UHCI Hung Configuration Register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
|
||||
* Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
|
||||
* data.
|
||||
*/
|
||||
uint32_t txfifo_timeout:8;
|
||||
/** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
|
||||
* Configures the maximum counter value.
|
||||
*/
|
||||
uint32_t txfifo_timeout_shift:3;
|
||||
/** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
|
||||
* Set this bit to enable TX FIFO timeout when receiving.
|
||||
*/
|
||||
uint32_t txfifo_timeout_ena:1;
|
||||
/** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
|
||||
* Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
|
||||
* RAM data.
|
||||
*/
|
||||
uint32_t rxfifo_timeout:8;
|
||||
/** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
|
||||
* Configures the maximum counter value.
|
||||
*/
|
||||
uint32_t rxfifo_timeout_shift:3;
|
||||
/** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
|
||||
* Set this bit to enable TX FIFO timeout when DMA sending data.
|
||||
*/
|
||||
uint32_t rxfifo_timeout_ena:1;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_hung_conf_reg_t;
|
||||
|
||||
/** Type of ack_num register
|
||||
* UHCI Ack Value Configuration Register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ack_num : R/W; bitpos: [2:0]; default: 0;
|
||||
* Indicates the ACK number during software flow control.
|
||||
*/
|
||||
uint32_t ack_num:3;
|
||||
/** ack_num_load : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to load the ACK value of UHCI_ACK_NUM.
|
||||
*/
|
||||
uint32_t ack_num_load:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_ack_num_reg_t;
|
||||
|
||||
/** Type of quick_sent register
|
||||
* UCHI Quick send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** single_send_num : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures single_send mode.
|
||||
*/
|
||||
uint32_t single_send_num:3;
|
||||
/** single_send_en : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to enable sending short packet with single_send mode.
|
||||
*/
|
||||
uint32_t single_send_en:1;
|
||||
/** always_send_num : R/W; bitpos: [6:4]; default: 0;
|
||||
* Configures always_send mode.
|
||||
*/
|
||||
uint32_t always_send_num:3;
|
||||
/** always_send_en : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable sending short packet with always_send mode.
|
||||
*/
|
||||
uint32_t always_send_en:1;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_quick_sent_reg_t;
|
||||
|
||||
/** Type of reg_q0_word0 register
|
||||
* UHCI Q0_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q0_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q0_word0_reg_t;
|
||||
|
||||
/** Type of reg_q0_word1 register
|
||||
* UHCI Q0_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q0_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q0_word1_reg_t;
|
||||
|
||||
/** Type of reg_q1_word0 register
|
||||
* UHCI Q1_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q1_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q1_word0_reg_t;
|
||||
|
||||
/** Type of reg_q1_word1 register
|
||||
* UHCI Q1_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q1_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q1_word1_reg_t;
|
||||
|
||||
/** Type of reg_q2_word0 register
|
||||
* UHCI Q2_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q2_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q2_word0_reg_t;
|
||||
|
||||
/** Type of reg_q2_word1 register
|
||||
* UHCI Q2_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q2_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q2_word1_reg_t;
|
||||
|
||||
/** Type of reg_q3_word0 register
|
||||
* UHCI Q3_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q3_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q3_word0_reg_t;
|
||||
|
||||
/** Type of reg_q3_word1 register
|
||||
* UHCI Q3_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q3_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q3_word1_reg_t;
|
||||
|
||||
/** Type of reg_q4_word0 register
|
||||
* UHCI Q4_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q4_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q4_word0_reg_t;
|
||||
|
||||
/** Type of reg_q4_word1 register
|
||||
* UHCI Q4_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q4_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q4_word1_reg_t;
|
||||
|
||||
/** Type of reg_q5_word0 register
|
||||
* UHCI Q5_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q5_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q5_word0_reg_t;
|
||||
|
||||
/** Type of reg_q5_word1 register
|
||||
* UHCI Q5_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q5_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q5_word1_reg_t;
|
||||
|
||||
/** Type of reg_q6_word0 register
|
||||
* UHCI Q6_WORD0 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q6_word0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q6_word0_reg_t;
|
||||
|
||||
/** Type of reg_q6_word1 register
|
||||
* UHCI Q6_WORD1 Quick Send Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
|
||||
* UHCI_SINGLE_SEND_NUM.
|
||||
*/
|
||||
uint32_t send_q6_word1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_reg_q6_word1_reg_t;
|
||||
|
||||
/** Type of esc_conf0 register
|
||||
* UHCI Escapes Sequence Configuration Register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** seper_char : R/W; bitpos: [7:0]; default: 192;
|
||||
* Configures the delimiter for encoding, default value is 0xC0.
|
||||
*/
|
||||
uint32_t seper_char:8;
|
||||
/** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
uint32_t seper_esc_char0:8;
|
||||
/** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDC.
|
||||
*/
|
||||
uint32_t seper_esc_char1:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_esc_conf0_reg_t;
|
||||
|
||||
/** Type of esc_conf1 register
|
||||
* UHCI Escapes Sequence Configuration Register1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
|
||||
* Configures the char needing encoding, which is 0xDB as flow control char by default.
|
||||
*/
|
||||
uint32_t esc_seq0:8;
|
||||
/** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
uint32_t esc_seq0_char0:8;
|
||||
/** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDD.
|
||||
*/
|
||||
uint32_t esc_seq0_char1:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_esc_conf1_reg_t;
|
||||
|
||||
/** Type of esc_conf2 register
|
||||
* UHCI Escapes Sequence Configuration Register2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
|
||||
* Configures the char needing encoding, which is 0x11 as flow control char by default.
|
||||
*/
|
||||
uint32_t esc_seq1:8;
|
||||
/** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
uint32_t esc_seq1_char0:8;
|
||||
/** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDE.
|
||||
*/
|
||||
uint32_t esc_seq1_char1:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_esc_conf2_reg_t;
|
||||
|
||||
/** Type of esc_conf3 register
|
||||
* UHCI Escapes Sequence Configuration Register3
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
|
||||
* Configures the char needing encoding, which is 0x13 as flow control char by default.
|
||||
*/
|
||||
uint32_t esc_seq2:8;
|
||||
/** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
|
||||
* Configures the first char of SLIP escape character, default value is 0xDB.
|
||||
*/
|
||||
uint32_t esc_seq2_char0:8;
|
||||
/** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
|
||||
* Configures the second char of SLIP escape character, default value is 0xDF.
|
||||
*/
|
||||
uint32_t esc_seq2_char1:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_esc_conf3_reg_t;
|
||||
|
||||
/** Type of pkt_thres register
|
||||
* UCHI Packet Length Configuration Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
|
||||
* Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
|
||||
*/
|
||||
uint32_t pkt_thrs:13;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_pkt_thres_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Register */
|
||||
/** Type of int_raw register
|
||||
* UHCI Interrupt Raw Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
|
||||
* delimiter is sent successfully.
|
||||
*/
|
||||
uint32_t rx_start_int_raw:1;
|
||||
/** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
|
||||
* DMA detects delimiter.
|
||||
*/
|
||||
uint32_t tx_start_int_raw:1;
|
||||
/** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
|
||||
* the required time of DMA receiving data exceeds the configuration value.
|
||||
*/
|
||||
uint32_t rx_hung_int_raw:1;
|
||||
/** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
|
||||
* the required time of DMA reading RAM data exceeds the configuration value.
|
||||
*/
|
||||
uint32_t tx_hung_int_raw:1;
|
||||
/** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
|
||||
* when UHCI sends short packet successfully with single_send mode.
|
||||
*/
|
||||
uint32_t send_s_reg_q_int_raw:1;
|
||||
/** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
|
||||
* when UHCI sends short packet successfully with always_send mode.
|
||||
*/
|
||||
uint32_t send_a_reg_q_int_raw:1;
|
||||
/** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
|
||||
* there are errors in EOF.
|
||||
*/
|
||||
uint32_t out_eof_int_raw:1;
|
||||
/** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
|
||||
* UHCI_APP_CTRL0_IN_SET is set to 1.
|
||||
*/
|
||||
uint32_t app_ctrl0_int_raw:1;
|
||||
/** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
|
||||
* Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
|
||||
* UHCI_APP_CTRL1_IN_SET is set to 1.
|
||||
*/
|
||||
uint32_t app_ctrl1_int_raw:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* UHCI Interrupt Status Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_start_int_st : RO; bitpos: [0]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_RX_START_INT.
|
||||
*/
|
||||
uint32_t rx_start_int_st:1;
|
||||
/** tx_start_int_st : RO; bitpos: [1]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_TX_START_INT.
|
||||
*/
|
||||
uint32_t tx_start_int_st:1;
|
||||
/** rx_hung_int_st : RO; bitpos: [2]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_RX_HUNG_INT.
|
||||
*/
|
||||
uint32_t rx_hung_int_st:1;
|
||||
/** tx_hung_int_st : RO; bitpos: [3]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_TX_HUNG_INT.
|
||||
*/
|
||||
uint32_t tx_hung_int_st:1;
|
||||
/** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
|
||||
*/
|
||||
uint32_t send_s_reg_q_int_st:1;
|
||||
/** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
|
||||
*/
|
||||
uint32_t send_a_reg_q_int_st:1;
|
||||
/** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_OUT_EOF_INT.
|
||||
*/
|
||||
uint32_t outlink_eof_err_int_st:1;
|
||||
/** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_APP_CTRL0_INT.
|
||||
*/
|
||||
uint32_t app_ctrl0_int_st:1;
|
||||
/** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
|
||||
* Indicates the interrupt status of UHCI_APP_CTRL1_INT.
|
||||
*/
|
||||
uint32_t app_ctrl1_int_st:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* UHCI Interrupt Enable Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_RX_START_INT.
|
||||
*/
|
||||
uint32_t rx_start_int_ena:1;
|
||||
/** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_TX_START_INT.
|
||||
*/
|
||||
uint32_t tx_start_int_ena:1;
|
||||
/** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
|
||||
*/
|
||||
uint32_t rx_hung_int_ena:1;
|
||||
/** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
|
||||
*/
|
||||
uint32_t tx_hung_int_ena:1;
|
||||
/** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
|
||||
*/
|
||||
uint32_t send_s_reg_q_int_ena:1;
|
||||
/** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
|
||||
*/
|
||||
uint32_t send_a_reg_q_int_ena:1;
|
||||
/** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
|
||||
*/
|
||||
uint32_t outlink_eof_err_int_ena:1;
|
||||
/** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
|
||||
*/
|
||||
uint32_t app_ctrl0_int_ena:1;
|
||||
/** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
|
||||
* Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
|
||||
*/
|
||||
uint32_t app_ctrl1_int_ena:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* UHCI Interrupt Clear Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_start_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
|
||||
*/
|
||||
uint32_t rx_start_int_clr:1;
|
||||
/** tx_start_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
|
||||
*/
|
||||
uint32_t tx_start_int_clr:1;
|
||||
/** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
|
||||
*/
|
||||
uint32_t rx_hung_int_clr:1;
|
||||
/** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
|
||||
*/
|
||||
uint32_t tx_hung_int_clr:1;
|
||||
/** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
|
||||
*/
|
||||
uint32_t send_s_reg_q_int_clr:1;
|
||||
/** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
|
||||
*/
|
||||
uint32_t send_a_reg_q_int_clr:1;
|
||||
/** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
|
||||
*/
|
||||
uint32_t outlink_eof_err_int_clr:1;
|
||||
/** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
|
||||
*/
|
||||
uint32_t app_ctrl0_int_clr:1;
|
||||
/** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
|
||||
*/
|
||||
uint32_t app_ctrl1_int_clr:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: UHCI Status Register */
|
||||
/** Type of state0 register
|
||||
* UHCI Receive Status Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_err_cause : RO; bitpos: [2:0]; default: 0;
|
||||
* Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
|
||||
* checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
|
||||
* bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
|
||||
* not found, but received packet is completed. 3'b110: CRC check error.
|
||||
*/
|
||||
uint32_t rx_err_cause:3;
|
||||
/** decode_state : RO; bitpos: [5:3]; default: 0;
|
||||
* Indicates UHCI decoder status.
|
||||
*/
|
||||
uint32_t decode_state:3;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_state0_reg_t;
|
||||
|
||||
/** Type of state1 register
|
||||
* UHCI Transmit Status Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** encode_state : RO; bitpos: [2:0]; default: 0;
|
||||
* Indicates UHCI encoder status.
|
||||
*/
|
||||
uint32_t encode_state:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_state1_reg_t;
|
||||
|
||||
/** Type of rx_head register
|
||||
* UHCI Head Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_head : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the head of received packet.
|
||||
*/
|
||||
uint32_t rx_head:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_rx_head_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* UHCI Version Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 35655936;
|
||||
* Configures version.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} uhci_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile uhci_conf0_reg_t conf0;
|
||||
volatile uhci_int_raw_reg_t int_raw;
|
||||
volatile uhci_int_st_reg_t int_st;
|
||||
volatile uhci_int_ena_reg_t int_ena;
|
||||
volatile uhci_int_clr_reg_t int_clr;
|
||||
volatile uhci_conf1_reg_t conf1;
|
||||
volatile uhci_state0_reg_t state0;
|
||||
volatile uhci_state1_reg_t state1;
|
||||
volatile uhci_escape_conf_reg_t escape_conf;
|
||||
volatile uhci_hung_conf_reg_t hung_conf;
|
||||
volatile uhci_ack_num_reg_t ack_num;
|
||||
volatile uhci_rx_head_reg_t rx_head;
|
||||
volatile uhci_quick_sent_reg_t quick_sent;
|
||||
volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
|
||||
volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
|
||||
volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
|
||||
volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
|
||||
volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
|
||||
volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
|
||||
volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
|
||||
volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
|
||||
volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
|
||||
volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
|
||||
volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
|
||||
volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
|
||||
volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
|
||||
volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
|
||||
volatile uhci_esc_conf0_reg_t esc_conf0;
|
||||
volatile uhci_esc_conf1_reg_t esc_conf1;
|
||||
volatile uhci_esc_conf2_reg_t esc_conf2;
|
||||
volatile uhci_esc_conf3_reg_t esc_conf3;
|
||||
volatile uhci_pkt_thres_reg_t pkt_thres;
|
||||
volatile uhci_date_reg_t date;
|
||||
} uhci_dev_t;
|
||||
|
||||
extern uhci_dev_t UHCI0;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
78
components/soc/esp32c5/ld/esp32c5.peripherals.ld
Normal file
78
components/soc/esp32c5/ld/esp32c5.peripherals.ld
Normal file
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
PROVIDE ( UART0 = 0x60000000 );
|
||||
PROVIDE ( UART1 = 0x60001000 );
|
||||
PROVIDE ( SPIMEM0 = 0x60002000 );
|
||||
PROVIDE ( SPIMEM1 = 0x60003000 );
|
||||
PROVIDE ( I2C0 = 0x60004000 );
|
||||
PROVIDE ( UHCI0 = 0x60005000 );
|
||||
PROVIDE ( RMT = 0x60006000 );
|
||||
PROVIDE ( RMTMEM = 0x60006400 );
|
||||
PROVIDE ( LEDC = 0x60007000 );
|
||||
PROVIDE ( TIMERG0 = 0x60008000 );
|
||||
PROVIDE ( TIMERG1 = 0x60009000 );
|
||||
PROVIDE ( SYSTIMER = 0x6000A000 );
|
||||
PROVIDE ( TWAI0 = 0x6000B000 );
|
||||
PROVIDE ( I2S0 = 0x6000C000 );
|
||||
PROVIDE ( TWAI1 = 0x6000D000 );
|
||||
PROVIDE ( APB_SARADC = 0x6000E000 );
|
||||
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
|
||||
|
||||
PROVIDE ( INTMTX = 0x60010000 );
|
||||
PROVIDE ( ATOMIC_LOCKER = 0x60011000 );
|
||||
PROVIDE ( PCNT = 0x60012000 );
|
||||
PROVIDE ( SOC_ETM = 0x60013000 );
|
||||
PROVIDE ( MCPWM0 = 0x60014000 );
|
||||
PROVIDE ( PARL_IO = 0x60015000 );
|
||||
PROVIDE ( HINF = 0x60016000 );
|
||||
PROVIDE ( SLC = 0x60017000 );
|
||||
PROVIDE ( HOST = 0x60018000 );
|
||||
PROVIDE ( PVT_MONITOR = 0x60019000 );
|
||||
|
||||
PROVIDE ( GDMA = 0x60080000 );
|
||||
PROVIDE ( GPSPI2 = 0x60081000 );
|
||||
|
||||
PROVIDE ( AES = 0x60088000 );
|
||||
PROVIDE ( SHA = 0x60089000 );
|
||||
PROVIDE ( RSA = 0x6008A000 );
|
||||
PROVIDE ( ECC = 0x6008B000 );
|
||||
PROVIDE ( DS = 0x6008C000 );
|
||||
PROVIDE ( HMAC = 0x6008D000 );
|
||||
|
||||
PROVIDE ( IO_MUX = 0x60090000 );
|
||||
PROVIDE ( GPIO = 0x60091000 );
|
||||
PROVIDE ( GPIO_EXT = 0x60091f00 );
|
||||
PROVIDE ( SDM = 0x60091f00 );
|
||||
PROVIDE ( GLITCH_FILTER = 0x60091f30 );
|
||||
PROVIDE ( GPIO_ETM = 0x60091f60 );
|
||||
|
||||
PROVIDE ( MEM_MONITOR = 0x60092000 );
|
||||
PROVIDE ( PAU = 0x60093000 );
|
||||
PROVIDE ( HP_SYSTEM = 0x60095000 );
|
||||
PROVIDE ( PCR = 0x60096000 );
|
||||
PROVIDE ( TEE = 0x60098000 );
|
||||
PROVIDE ( HP_APM = 0x60099000 );
|
||||
|
||||
PROVIDE ( IEEE802154 = 0x600A3000 );
|
||||
PROVIDE ( MODEM_SYSCON = 0x600A9800 );
|
||||
PROVIDE ( MODEM_LPCON = 0x600AF000 );
|
||||
|
||||
PROVIDE ( PMU = 0x600B0000 );
|
||||
PROVIDE ( LP_CLKRST = 0x600B0400 );
|
||||
PROVIDE ( EFUSE = 0x600B0800 );
|
||||
PROVIDE ( LP_TIMER = 0x600B0C00 );
|
||||
PROVIDE ( LP_AON = 0x600B1000 );
|
||||
PROVIDE ( LP_UART = 0x600B1400 );
|
||||
PROVIDE ( LP_I2C = 0x600B1800 );
|
||||
PROVIDE ( LP_WDT = 0x600B1C00 );
|
||||
PROVIDE ( LP_IO = 0x600B2000 );
|
||||
PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 );
|
||||
PROVIDE ( LPPERI = 0x600B2800 );
|
||||
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
|
||||
PROVIDE ( LP_APM = 0x600B3800 );
|
||||
PROVIDE ( OTP_DEBUG = 0x600B3C00 );
|
||||
Reference in New Issue
Block a user