feat(soc): p4 hw ver2 registers

components/soc/esp32p4/register/hw_ver2/soc/interrupts.h

@@ -0,0 +1,157 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//Interrupt hardware source table
+//This table is decided by hardware, don't touch this.
+typedef enum {
+    ETS_LP_RTC_INT_SOURCE,
+    ETS_LP_WDT_INT_SOURCE,
+    ETS_LP_TIMER_REG_0_INT_SOURCE,
+    ETS_LP_TIMER_REG_1_INT_SOURCE,
+    ETS_MB_HP_INT_SOURCE,
+    ETS_MB_LP_INT_SOURCE,
+    ETS_PMU_REG_0_INT_SOURCE,
+    ETS_PMU_REG_1_INT_SOURCE,
+    ETS_LP_ANAPERI_INT_SOURCE,
+    ETS_LP_ADC_INT_SOURCE,
+    ETS_LP_GPIO_INT_SOURCE,
+    ETS_LP_I2C_INT_SOURCE,
+    ETS_LP_I2S_INT_SOURCE,
+    ETS_LP_SPI_INT_SOURCE,
+    ETS_LP_TOUCH_INT_SOURCE,
+    ETS_LP_TSENS_INT_SOURCE,
+    ETS_LP_UART_INT_SOURCE,
+    ETS_LP_EFUSE_INT_SOURCE,
+    ETS_LP_SW_INT_SOURCE,
+    ETS_LP_SYSREG_INT_SOURCE,
+    ETS_LP_HUK_INT_SOURCE,
+    ETS_SYS_ICM_INT_SOURCE,
+    ETS_USB_DEVICE_INT_SOURCE,
+    ETS_SDIO_HOST_INT_SOURCE,
+    ETS_GDMA_INT_SOURCE,
+    ETS_SPI2_INT_SOURCE,
+    ETS_SPI3_INT_SOURCE,
+    ETS_I2S0_INT_SOURCE,
+    ETS_I2S1_INT_SOURCE,
+    ETS_I2S2_INT_SOURCE,
+    ETS_UHCI0_INT_SOURCE,
+    ETS_UART0_INT_SOURCE,
+    ETS_UART1_INT_SOURCE,
+    ETS_UART2_INT_SOURCE,
+    ETS_UART3_INT_SOURCE,
+    ETS_UART4_INT_SOURCE,
+    ETS_LCD_CAM_INT_SOURCE,
+    ETS_ADC_INT_SOURCE,
+    ETS_PWM0_INT_SOURCE,
+    ETS_PWM1_INT_SOURCE,
+    ETS_TWAI0_INT_SOURCE,
+    ETS_TWAI1_INT_SOURCE,
+    ETS_TWAI2_INT_SOURCE,
+    ETS_RMT_INT_SOURCE,
+    ETS_I2C0_INT_SOURCE,
+    ETS_I2C1_INT_SOURCE,
+    ETS_TIMERGRP0_T0_INT_SOURCE,
+    ETS_TIMERGRP0_T1_INT_SOURCE,
+    ETS_TIMERGRP0_WDT_INT_SOURCE,
+    ETS_TIMERGRP1_T0_INT_SOURCE,
+    ETS_TIMERGRP1_T1_INT_SOURCE,
+    ETS_TIMERGRP1_WDT_INT_SOURCE,
+    ETS_LEDC_INT_SOURCE,
+    ETS_SYSTIMER_TARGET0_INT_SOURCE,
+    ETS_SYSTIMER_TARGET1_INT_SOURCE,
+    ETS_SYSTIMER_TARGET2_INT_SOURCE,
+    ETS_AHB_PDMA_IN_CH0_INT_SOURCE,
+    ETS_AHB_PDMA_IN_CH1_INT_SOURCE,
+    ETS_AHB_PDMA_IN_CH2_INT_SOURCE,
+    ETS_AHB_PDMA_OUT_CH0_INT_SOURCE,
+    ETS_AHB_PDMA_OUT_CH1_INT_SOURCE,
+    ETS_AHB_PDMA_OUT_CH2_INT_SOURCE,
+    ETS_AXI_PDMA_IN_CH0_INT_SOURCE,
+    ETS_AXI_PDMA_IN_CH1_INT_SOURCE,
+    ETS_AXI_PDMA_IN_CH2_INT_SOURCE,
+    ETS_AXI_PDMA_OUT_CH0_INT_SOURCE,
+    ETS_AXI_PDMA_OUT_CH1_INT_SOURCE,
+    ETS_AXI_PDMA_OUT_CH2_INT_SOURCE,
+    ETS_RSA_INT_SOURCE,
+    ETS_AES_INT_SOURCE,
+    ETS_SHA_INT_SOURCE,
+    ETS_ECC_INT_SOURCE,
+    ETS_ECDSA_INT_SOURCE,
+    ETS_KM_INT_SOURCE,
+    ETS_GPIO_INT0_SOURCE,
+    ETS_GPIO_INT1_SOURCE,
+    ETS_GPIO_INT2_SOURCE,
+    ETS_GPIO_INT3_SOURCE,
+    ETS_GPIO_PAD_COMP_INT_SOURCE,
+    ETS_CPU_INT_FROM_CPU_0_SOURCE,
+    ETS_CPU_INT_FROM_CPU_1_SOURCE,
+    ETS_CPU_INT_FROM_CPU_2_SOURCE,
+    ETS_CPU_INT_FROM_CPU_3_SOURCE,
+    ETS_CACHE_INT_SOURCE,
+    ETS_FLASH_MSPI_INT_SOURCE,
+    ETS_CSI_BRIDGE_INT_SOURCE,
+    ETS_DSI_BRIDGE_INT_SOURCE,
+    ETS_CSI_INT_SOURCE,
+    ETS_DSI_INT_SOURCE,
+    ETS_GMII_PHY_INT_SOURCE,
+    ETS_LPI_INT_SOURCE,
+    ETS_PMT_INT_SOURCE,
+    ETS_SBD_INT_SOURCE,
+    ETS_USB_OTG_INT_SOURCE,
+    ETS_USB_OTG_ENDP_MULTI_PROC_INT_SOURCE,
+    ETS_JPEG_INT_SOURCE,
+    ETS_PPA_INT_SOURCE,
+    ETS_CORE0_TRACE_INT_SOURCE,
+    ETS_CORE1_TRACE_INT_SOURCE,
+    ETS_HP_CORE_CTRL_INT_SOURCE,
+    ETS_ISP_INT_SOURCE,
+    ETS_I3C_MST_INT_SOURCE,
+    ETS_I3C_SLV_INT_SOURCE,
+    ETS_USB_OTG11_INT_SOURCE,
+    ETS_DMA2D_IN_CH0_INT_SOURCE,
+    ETS_DMA2D_IN_CH1_INT_SOURCE,
+    ETS_DMA2D_OUT_CH0_INT_SOURCE,
+    ETS_DMA2D_OUT_CH1_INT_SOURCE,
+    ETS_DMA2D_OUT_CH2_INT_SOURCE,
+    ETS_PSRAM_MSPI_INT_SOURCE,
+    ETS_HP_SYSREG_INT_SOURCE,
+    ETS_PCNT_INT_SOURCE,
+    ETS_HP_PAU_INT_SOURCE,
+    ETS_HP_PARLIO_RX_INT_SOURCE,
+    ETS_HP_PARLIO_TX_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH0_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH1_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH2_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH3_INT_SOURCE,
+    ETS_H264_DMA2D_OUT_CH4_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH0_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH1_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH2_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH3_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH4_INT_SOURCE,
+    ETS_H264_DMA2D_IN_CH5_INT_SOURCE,
+    ETS_H264_REG_INT_SOURCE,
+    ETS_ASSIST_DEBUG_INT_SOURCE,
+    ETS_DMA2D_IN_CH2_INT_SOURCE,
+    ETS_DMA2D_OUT_CH3_INT_SOURCE,
+    ETS_AXI_PERF_MON_INT_SOURCE,
+    ETS_MAX_INTR_SOURCE,
+} periph_interrupt_t;
+
+extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/io_mux_reg.h

@@ -0,0 +1,524 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+
+//TODO: IDF-13419
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_GPIO0
+#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_GPIO1
+#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_GPIO2
+#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_GPIO3
+#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_GPIO4
+#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_GPIO5
+#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_GPIO6
+#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
+#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
+#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
+#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_GPIO10
+#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_GPIO11
+#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_GPIO12
+#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
+#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_GPIO14
+#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_GPIO15
+#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_GPIO16
+#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_GPIO17
+#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_GPIO18
+#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_GPIO19
+#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_GPIO20
+#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_GPIO21
+#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_GPIO22
+#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_GPIO23
+#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_GPIO24
+#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_PAD_GPIO25
+#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_PAD_GPIO26
+#define IO_MUX_GPIO27_REG                   PERIPHS_IO_MUX_U_PAD_GPIO27
+#define IO_MUX_GPIO28_REG                   PERIPHS_IO_MUX_U_PAD_GPIO28
+#define IO_MUX_GPIO29_REG                   PERIPHS_IO_MUX_U_PAD_GPIO29
+#define IO_MUX_GPIO30_REG                   PERIPHS_IO_MUX_U_PAD_GPIO30
+#define IO_MUX_GPIO31_REG                   PERIPHS_IO_MUX_U_PAD_GPIO31
+#define IO_MUX_GPIO32_REG                   PERIPHS_IO_MUX_U_PAD_GPIO32
+#define IO_MUX_GPIO33_REG                   PERIPHS_IO_MUX_U_PAD_GPIO33
+#define IO_MUX_GPIO34_REG                   PERIPHS_IO_MUX_U_PAD_GPIO34
+#define IO_MUX_GPIO35_REG                   PERIPHS_IO_MUX_U_PAD_GPIO35
+#define IO_MUX_GPIO36_REG                   PERIPHS_IO_MUX_U_PAD_GPIO36
+#define IO_MUX_GPIO37_REG                   PERIPHS_IO_MUX_U_PAD_GPIO37
+#define IO_MUX_GPIO38_REG                   PERIPHS_IO_MUX_U_PAD_GPIO38
+#define IO_MUX_GPIO39_REG                   PERIPHS_IO_MUX_U_PAD_GPIO39
+#define IO_MUX_GPIO40_REG                   PERIPHS_IO_MUX_U_PAD_GPIO40
+#define IO_MUX_GPIO41_REG                   PERIPHS_IO_MUX_U_PAD_GPIO41
+#define IO_MUX_GPIO42_REG                   PERIPHS_IO_MUX_U_PAD_GPIO42
+#define IO_MUX_GPIO43_REG                   PERIPHS_IO_MUX_U_PAD_GPIO43
+#define IO_MUX_GPIO44_REG                   PERIPHS_IO_MUX_U_PAD_GPIO44
+#define IO_MUX_GPIO45_REG                   PERIPHS_IO_MUX_U_PAD_GPIO45
+#define IO_MUX_GPIO46_REG                   PERIPHS_IO_MUX_U_PAD_GPIO46
+#define IO_MUX_GPIO47_REG                   PERIPHS_IO_MUX_U_PAD_GPIO47
+#define IO_MUX_GPIO48_REG                   PERIPHS_IO_MUX_U_PAD_GPIO48
+#define IO_MUX_GPIO49_REG                   PERIPHS_IO_MUX_U_PAD_GPIO49
+#define IO_MUX_GPIO50_REG                   PERIPHS_IO_MUX_U_PAD_GPIO50
+#define IO_MUX_GPIO51_REG                   PERIPHS_IO_MUX_U_PAD_GPIO51
+#define IO_MUX_GPIO52_REG                   PERIPHS_IO_MUX_U_PAD_GPIO52
+#define IO_MUX_GPIO53_REG                   PERIPHS_IO_MUX_U_PAD_GPIO53
+#define IO_MUX_GPIO54_REG                   PERIPHS_IO_MUX_U_PAD_GPIO54
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+// TODO: IDF-7499, IDF-7495
+// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore.
+// Please check iomux_mspi_pin_struct/reg.h
+#include "soc/gpio_num.h"
+#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX
+#define SPI_HD_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_WP_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX
+#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX
+#define SPI_Q_GPIO_NUM   GPIO_NUM_MAX
+#define SPI_D_GPIO_NUM   GPIO_NUM_MAX
+#define SPI_D4_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D5_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D6_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D7_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX
+
+#define SD_CLK_GPIO_NUM           43
+#define SD_CMD_GPIO_NUM           44
+#define SD_DATA0_GPIO_NUM         39
+#define SD_DATA1_GPIO_NUM         40
+#define SD_DATA2_GPIO_NUM         41
+#define SD_DATA3_GPIO_NUM         42
+#define SD_DATA4_GPIO_NUM         45
+#define SD_DATA5_GPIO_NUM         46
+#define SD_DATA6_GPIO_NUM         47
+#define SD_DATA7_GPIO_NUM         48
+
+#define USB_INT_PHY0_DM_GPIO_NUM  24
+#define USB_INT_PHY0_DP_GPIO_NUM  25
+#define USB_INT_PHY1_DM_GPIO_NUM  26
+#define USB_INT_PHY1_DP_GPIO_NUM  27
+
+// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG
+#define USB_USJ_INT_PHY_DM_GPIO_NUM     USB_INT_PHY0_DM_GPIO_NUM
+#define USB_USJ_INT_PHY_DP_GPIO_NUM     USB_INT_PHY0_DP_GPIO_NUM
+#define USB_OTG_INT_PHY_DM_GPIO_NUM     USB_INT_PHY1_DM_GPIO_NUM
+#define USB_OTG_INT_PHY_DP_GPIO_NUM     USB_INT_PHY1_DP_GPIO_NUM
+
+#define MAX_RTC_GPIO_NUM             15
+#define MAX_PAD_GPIO_NUM             54
+#define MAX_GPIO_NUM                 56
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_U_PAD_GPIO0                 (REG_IO_MUX_BASE + 0x4)
+#define FUNC_GPIO0_GPIO0                                                 1
+#define FUNC_GPIO0_GPIO0_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO1                 (REG_IO_MUX_BASE + 0x8)
+#define FUNC_GPIO1_GPIO1                                                 1
+#define FUNC_GPIO1_GPIO1_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO2                 (REG_IO_MUX_BASE + 0xC)
+#define FUNC_GPIO2_GPIO2                                                 1
+#define FUNC_GPIO2_MTCK                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO3                (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3                                                 1
+#define FUNC_GPIO3_MTDI                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO4                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_GPIO4_GPIO4                                                 1
+#define FUNC_GPIO4_MTMS                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO5                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_GPIO5_GPIO5                                                 1
+#define FUNC_GPIO5_MTDO                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO6                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_GPIO6_SPI2_HOLD_PAD                                         3
+#define FUNC_GPIO6_GPIO6                                                 1
+#define FUNC_GPIO6_GPIO6_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO7_SPI2_CS_PAD                                           3
+#define FUNC_GPIO7_GPIO7                                                 1
+#define FUNC_GPIO7_GPIO7_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_SPI2_D_PAD                                            3
+#define FUNC_GPIO8_UART0_RTS_PAD                                         2
+#define FUNC_GPIO8_GPIO8                                                 1
+#define FUNC_GPIO8_GPIO8_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_SPI2_CK_PAD                                           3
+#define FUNC_GPIO9_UART0_CTS_PAD                                         2
+#define FUNC_GPIO9_GPIO9                                                 1
+#define FUNC_GPIO9_GPIO9_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO10               (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_SPI2_Q_PAD                                           3
+#define FUNC_GPIO10_UART1_TXD_PAD                                        2
+#define FUNC_GPIO10_GPIO10                                               1
+#define FUNC_GPIO10_GPIO10_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO11               (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO11_SPI2_WP_PAD                                          3
+#define FUNC_GPIO11_UART1_RXD_PAD                                        2
+#define FUNC_GPIO11_GPIO11                                               1
+#define FUNC_GPIO11_GPIO11_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO12               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO12_UART1_RTS_PAD                                        2
+#define FUNC_GPIO12_GPIO12                                               1
+#define FUNC_GPIO12_GPIO12_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_GPIO13_UART1_CTS_PAD                                        2
+#define FUNC_GPIO13_GPIO13                                               1
+#define FUNC_GPIO13_GPIO13_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO14               (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_GPIO14_GPIO14                                               1
+#define FUNC_GPIO14_GPIO14_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO15               (REG_IO_MUX_BASE + 0x40)
+#define FUNC_GPIO15_GPIO15                                               1
+#define FUNC_GPIO15_GPIO15_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO16               (REG_IO_MUX_BASE + 0x44)
+#define FUNC_GPIO16_GPIO16                                               1
+#define FUNC_GPIO16_GPIO16_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO17               (REG_IO_MUX_BASE + 0x48)
+#define FUNC_GPIO17_GPIO17                                               1
+#define FUNC_GPIO17_GPIO17_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO18               (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_GPIO18_GPIO18                                               1
+#define FUNC_GPIO18_GPIO18_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO19               (REG_IO_MUX_BASE + 0x50)
+#define FUNC_GPIO19_GPIO19                                               1
+#define FUNC_GPIO19_GPIO19_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO20               (REG_IO_MUX_BASE + 0x54)
+#define FUNC_GPIO20_GPIO20                                               1
+#define FUNC_GPIO20_GPIO20_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO21               (REG_IO_MUX_BASE + 0x58)
+#define FUNC_GPIO21_GPIO21                                               1
+#define FUNC_GPIO21_GPIO21_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO22               (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_GPIO22_DBG_PSRAM_CK_PAD                                     4
+#define FUNC_GPIO22_GPIO22                                               1
+#define FUNC_GPIO22_GPIO22_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO23               (REG_IO_MUX_BASE + 0x60)
+#define FUNC_GPIO23_DBG_PSRAM_CS_PAD                                     4
+#define FUNC_GPIO23_REF_50M_CLK_PAD                                      3
+#define FUNC_GPIO23_GPIO23                                               1
+#define FUNC_GPIO23_GPIO23_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO24               (REG_IO_MUX_BASE + 0x64)
+#define FUNC_GPIO24_GPIO24                                               1
+#define FUNC_GPIO24_GPIO24_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO25               (REG_IO_MUX_BASE + 0x68)
+#define FUNC_GPIO25_GPIO25                                               1
+#define FUNC_GPIO25_GPIO25_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO26               (REG_IO_MUX_BASE + 0x6C)
+#define FUNC_GPIO26_GPIO26                                               1
+#define FUNC_GPIO26_GPIO26_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO27               (REG_IO_MUX_BASE + 0x70)
+#define FUNC_GPIO27_GPIO27                                               1
+#define FUNC_GPIO27_GPIO27_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO28               (REG_IO_MUX_BASE + 0x74)
+#define FUNC_GPIO28_DBG_PSRAM_D_PAD                                      4
+#define FUNC_GPIO28_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO28_SPI2_CS_PAD                                          2
+#define FUNC_GPIO28_GPIO28                                               1
+#define FUNC_GPIO28_GPIO28_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO29               (REG_IO_MUX_BASE + 0x78)
+#define FUNC_GPIO29_DBG_PSRAM_Q_PAD                                      4
+#define FUNC_GPIO29_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO29_SPI2_D_PAD                                           2
+#define FUNC_GPIO29_GPIO29                                               1
+#define FUNC_GPIO29_GPIO29_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO30               (REG_IO_MUX_BASE + 0x7C)
+#define FUNC_GPIO30_DBG_PSRAM_WP_PAD                                     4
+#define FUNC_GPIO30_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO30_SPI2_CK_PAD                                          2
+#define FUNC_GPIO30_GPIO30                                               1
+#define FUNC_GPIO30_GPIO30_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO31               (REG_IO_MUX_BASE + 0x80)
+#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD                                   4
+#define FUNC_GPIO31_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO31_SPI2_Q_PAD                                           2
+#define FUNC_GPIO31_GPIO31                                               1
+#define FUNC_GPIO31_GPIO31_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO32               (REG_IO_MUX_BASE + 0x84)
+#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                    4
+#define FUNC_GPIO32_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO32_SPI2_HOLD_PAD                                        2
+#define FUNC_GPIO32_GPIO32                                               1
+#define FUNC_GPIO32_GPIO32_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO33               (REG_IO_MUX_BASE + 0x88)
+#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                    4
+#define FUNC_GPIO33_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO33_SPI2_WP_PAD                                          2
+#define FUNC_GPIO33_GPIO33                                               1
+#define FUNC_GPIO33_GPIO33_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO34               (REG_IO_MUX_BASE + 0x8C)
+#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                    4
+#define FUNC_GPIO34_EMAC_PHY_TXD0_PAD                                    3
+#define FUNC_GPIO34_SPI2_IO4_PAD                                         2
+#define FUNC_GPIO34_GPIO34                                               1
+#define FUNC_GPIO34_GPIO34_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO35               (REG_IO_MUX_BASE + 0x90)
+#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                    4
+#define FUNC_GPIO35_EMAC_PHY_TXD1_PAD                                    3
+#define FUNC_GPIO35_SPI2_IO5_PAD                                         2
+#define FUNC_GPIO35_GPIO35                                               1
+#define FUNC_GPIO35_GPIO35_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO36               (REG_IO_MUX_BASE + 0x94)
+#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                  4
+#define FUNC_GPIO36_EMAC_PHY_TXER_PAD                                    3
+#define FUNC_GPIO36_SPI2_IO6_PAD                                         2
+#define FUNC_GPIO36_GPIO36                                               1
+#define FUNC_GPIO36_GPIO36_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO37               (REG_IO_MUX_BASE + 0x98)
+#define FUNC_GPIO37_SPI2_IO7_PAD                                         2
+#define FUNC_GPIO37_GPIO37                                               1
+#define FUNC_GPIO37_UART0_TXD_PAD                                        0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO38               (REG_IO_MUX_BASE + 0x9C)
+#define FUNC_GPIO38_SPI2_DQS_PAD                                         2
+#define FUNC_GPIO38_GPIO38                                               1
+#define FUNC_GPIO38_UART0_RXD_PAD                                        0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO39               (REG_IO_MUX_BASE + 0xA0)
+#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD                                    4
+#define FUNC_GPIO39_REF_50M_CLK_PAD                                      3
+#define FUNC_GPIO39_BIST_PAD                                             2
+#define FUNC_GPIO39_GPIO39                                               1
+#define FUNC_GPIO39_SD1_CDATA0_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO40               (REG_IO_MUX_BASE + 0xA4)
+#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD                                    4
+#define FUNC_GPIO40_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO40_BIST_PAD                                             2
+#define FUNC_GPIO40_GPIO40                                               1
+#define FUNC_GPIO40_SD1_CDATA1_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO41               (REG_IO_MUX_BASE + 0xA8)
+#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD                                   4
+#define FUNC_GPIO41_EMAC_PHY_TXD0_PAD                                    3
+#define FUNC_GPIO41_BIST_PAD                                             2
+#define FUNC_GPIO41_GPIO41                                               1
+#define FUNC_GPIO41_SD1_CDATA2_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO42               (REG_IO_MUX_BASE + 0xAC)
+#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD                                   4
+#define FUNC_GPIO42_EMAC_PHY_TXD1_PAD                                    3
+#define FUNC_GPIO42_BIST_PAD                                             2
+#define FUNC_GPIO42_GPIO42                                               1
+#define FUNC_GPIO42_SD1_CDATA3_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO43               (REG_IO_MUX_BASE + 0xB0)
+#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD                                   4
+#define FUNC_GPIO43_EMAC_PHY_TXER_PAD                                    3
+#define FUNC_GPIO43_BIST_PAD                                             2
+#define FUNC_GPIO43_GPIO43                                               1
+#define FUNC_GPIO43_SD1_CCLK_PAD                                         0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO44               (REG_IO_MUX_BASE + 0xB4)
+#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD                                   4
+#define FUNC_GPIO44_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO44_BIST_PAD                                             2
+#define FUNC_GPIO44_GPIO44                                               1
+#define FUNC_GPIO44_SD1_CCMD_PAD                                         0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO45               (REG_IO_MUX_BASE + 0xB8)
+#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD                                   4
+#define FUNC_GPIO45_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO45_BIST_PAD                                             2
+#define FUNC_GPIO45_GPIO45                                               1
+#define FUNC_GPIO45_SD1_CDATA4_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO46               (REG_IO_MUX_BASE + 0xBC)
+#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD                                   4
+#define FUNC_GPIO46_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO46_BIST_PAD                                             2
+#define FUNC_GPIO46_GPIO46                                               1
+#define FUNC_GPIO46_SD1_CDATA5_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO47               (REG_IO_MUX_BASE + 0xC0)
+#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD                                  4
+#define FUNC_GPIO47_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO47_BIST_PAD                                             2
+#define FUNC_GPIO47_GPIO47                                               1
+#define FUNC_GPIO47_SD1_CDATA6_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO48               (REG_IO_MUX_BASE + 0xC4)
+#define FUNC_GPIO48_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO48_BIST_PAD                                             2
+#define FUNC_GPIO48_GPIO48                                               1
+#define FUNC_GPIO48_SD1_CDATA7_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO49               (REG_IO_MUX_BASE + 0xC8)
+#define FUNC_GPIO49_DBG_FLASH_CS_PAD                                      4
+#define FUNC_GPIO49_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO49_GPIO49                                               1
+#define FUNC_GPIO49_GPIO49_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO50               (REG_IO_MUX_BASE + 0xCC)
+#define FUNC_GPIO50_DBG_FLASH_Q_PAD                                       4
+#define FUNC_GPIO50_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO50_GPIO50                                               1
+#define FUNC_GPIO50_GPIO50_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO51               (REG_IO_MUX_BASE + 0xD0)
+#define FUNC_GPIO51_DBG_FLASH_WP_PAD                                     4
+#define FUNC_GPIO51_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO51_GPIO51                                               1
+#define FUNC_GPIO51_GPIO51_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO52               (REG_IO_MUX_BASE + 0xD4)
+#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD                                   4
+#define FUNC_GPIO52_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO52_GPIO52                                               1
+#define FUNC_GPIO52_GPIO52_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO53               (REG_IO_MUX_BASE + 0xD8)
+#define FUNC_GPIO53_DBG_FLASH_CK_PAD                                      4
+#define FUNC_GPIO53_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO53_GPIO53                                               1
+#define FUNC_GPIO53_GPIO53_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO54               (REG_IO_MUX_BASE + 0xDC)
+#define FUNC_GPIO54_DBG_FLASH_D_PAD                                       4
+#define FUNC_GPIO54_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO54_GPIO54                                               1
+#define FUNC_GPIO54_GPIO54_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO55               (REG_IO_MUX_BASE + 0xE0)
+#define FUNC_GPIO55_GPIO55                                               1
+#define FUNC_GPIO55_GPIO55_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO56               (REG_IO_MUX_BASE + 0xE4)
+#define FUNC_GPIO56_GPIO56                                               1
+#define FUNC_GPIO56_GPIO56_0                                             0
+
+#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0x104)
+/* IO_MUX_DATE : R/W ;bitpos:[27:0] ;default: 27'h0201222 ; */
+/*description: csv date.*/
+#define IO_MUX_DATE    0x0FFFFFFF
+#define IO_MUX_DATE_M  ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S))
+#define IO_MUX_DATE_V  0xFFFFFFF
+#define IO_MUX_DATE_S  0

components/soc/esp32p4/register/hw_ver2/soc/io_mux_struct.h

@@ -0,0 +1,102 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13419
+/** Type of GPIO register
+ *  IO MUX gpio configuration register
+ */
+typedef union {
+    struct {
+        /** mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  output enable on sleep mode
+         */
+        uint32_t mcu_oe:1;
+        /** slp_sel : R/W; bitpos: [1]; default: 0;
+         *  io sleep mode enable. set 1 to enable sleep mode.
+         */
+        uint32_t slp_sel:1;
+        /** mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  pull-down enable on sleep mode
+         */
+        uint32_t mcu_wpd:1;
+        /** mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  pull-up enable on sleep mode
+         */
+        uint32_t mcu_wpu:1;
+        /** mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  input enable on sleep mode
+         */
+        uint32_t mcu_ie:1;
+        /** mcu_drv : R/W; bitpos: [5:6]; default: 0;
+         *  select drive strength on sleep mode
+         */
+        uint32_t mcu_drv:2;
+        /** fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  pull-down enable
+         */
+        uint32_t fun_wpd:1;
+        /** fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  pull-up enable
+         */
+        uint32_t fun_wpu:1;
+        /** fun_ie : R/W; bitpos: [9]; default: 0;
+         *  input enable
+         */
+        uint32_t fun_ie:1;
+        /** fun_drv : R/W; bitpos: [10:11]; default: 2;
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         */
+        uint32_t fun_drv:2;
+        /** mcu_sel : R/W; bitpos: [12:14]; default: 0;
+         *  0:select function0, 1:select function1 ...
+         */
+        uint32_t mcu_sel:3;
+        /** filter_en : R/W; bitpos: [15]; default: 0;
+         *  input filter enable
+         */
+        uint32_t filter_en:1;
+        uint32_t reserved16 :16;
+    };
+    uint32_t val;
+} io_mux_gpio_reg_t;
+
+/** Type of date register
+ *  IO_MUX version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2101794;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} io_mux_date_reg_t;
+
+
+typedef struct io_mux_dev_t {
+    uint32_t reserved_0;
+    volatile io_mux_gpio_reg_t gpio[57];
+    uint32_t reserved_e8[7];
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
+
+extern io_mux_dev_t IO_MUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_struct.h

@@ -0,0 +1,333 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en0 register
+ *  apb registers auto clock gating reg
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  1: auto clock gating on
+         *  0: auto clock gating off
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} iomux_mspi_pin_clk_en0_reg_t;
+
+
+/** Group: flash_cs_pin */
+/** Type of flash_cs_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_cs_hys : R/W; bitpos: [0]; default: 0;
+         *  flash cs hys
+         */
+        uint32_t reg_flash_cs_hys:1;
+        /** reg_flash_cs_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_cs_ie:1;
+        /** reg_flash_cs_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash cs wpu
+         */
+        uint32_t reg_flash_cs_wpu:1;
+        /** reg_flash_cs_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash cs wpd
+         */
+        uint32_t reg_flash_cs_wpd:1;
+        /** reg_flash_cs_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash cs drv
+         */
+        uint32_t reg_flash_cs_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_cs_pin0_reg_t;
+
+
+/** Group: flash_q_pin */
+/** Type of flash_q_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_q_hys : R/W; bitpos: [0]; default: 0;
+         *  flash q hys
+         */
+        uint32_t reg_flash_q_hys:1;
+        /** reg_flash_q_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_q_ie:1;
+        /** reg_flash_q_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash q wpu
+         */
+        uint32_t reg_flash_q_wpu:1;
+        /** reg_flash_q_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash q wpd
+         */
+        uint32_t reg_flash_q_wpd:1;
+        /** reg_flash_q_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash q drv
+         */
+        uint32_t reg_flash_q_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_q_pin0_reg_t;
+
+
+/** Group: flash_wp_pin */
+/** Type of flash_wp_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_wp_hys : R/W; bitpos: [0]; default: 0;
+         *  flash wp hys
+         */
+        uint32_t reg_flash_wp_hys:1;
+        /** reg_flash_wp_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_wp_ie:1;
+        /** reg_flash_wp_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash wp wpu
+         */
+        uint32_t reg_flash_wp_wpu:1;
+        /** reg_flash_wp_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash wp wpd
+         */
+        uint32_t reg_flash_wp_wpd:1;
+        /** reg_flash_wp_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash wp drv
+         */
+        uint32_t reg_flash_wp_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_wp_pin0_reg_t;
+
+
+/** Group: flash_hold_pin */
+/** Type of flash_hold_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_hold_hys : R/W; bitpos: [0]; default: 0;
+         *  flash hold hys
+         */
+        uint32_t reg_flash_hold_hys:1;
+        /** reg_flash_hold_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_hold_ie:1;
+        /** reg_flash_hold_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash hold wpu
+         */
+        uint32_t reg_flash_hold_wpu:1;
+        /** reg_flash_hold_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash hold wpd
+         */
+        uint32_t reg_flash_hold_wpd:1;
+        /** reg_flash_hold_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash hold drv
+         */
+        uint32_t reg_flash_hold_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_hold_pin0_reg_t;
+
+
+/** Group: flash_ck_pin */
+/** Type of flash_ck_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_ck_hys : R/W; bitpos: [0]; default: 0;
+         *  flash ck hys
+         */
+        uint32_t reg_flash_ck_hys:1;
+        /** reg_flash_ck_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_ck_ie:1;
+        /** reg_flash_ck_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash ck wpu
+         */
+        uint32_t reg_flash_ck_wpu:1;
+        /** reg_flash_ck_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash ck wpd
+         */
+        uint32_t reg_flash_ck_wpd:1;
+        /** reg_flash_ck_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash ck drv
+         */
+        uint32_t reg_flash_ck_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_ck_pin0_reg_t;
+
+
+/** Group: flash_d_pin */
+/** Type of flash_d_pin0 register
+ *  IOMUX_MSPI_PIN_FLASH_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_flash_d_hys : R/W; bitpos: [0]; default: 0;
+         *  flash d hys
+         */
+        uint32_t reg_flash_d_hys:1;
+        /** reg_flash_d_ie : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_d_ie:1;
+        /** reg_flash_d_wpu : R/W; bitpos: [2]; default: 0;
+         *  flash d wpu
+         */
+        uint32_t reg_flash_d_wpu:1;
+        /** reg_flash_d_wpd : R/W; bitpos: [3]; default: 0;
+         *  flash d wpd
+         */
+        uint32_t reg_flash_d_wpd:1;
+        /** reg_flash_d_drv : R/W; bitpos: [5:4]; default: 0;
+         *  flash d drv
+         */
+        uint32_t reg_flash_d_drv:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} iomux_mspi_pin_flash_d_pin0_reg_t;
+
+
+/** psram_pin */
+typedef union {
+    struct {
+        /** reg_psram_pin_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram pin dli
+         */
+        uint32_t reg_psram_pin_dli:4;
+        /** reg_psram_pin_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram pin dlc
+         */
+        uint32_t reg_psram_pin_dlc:4;
+        /** reg_psram_pin_hys : R/W; bitpos: [8]; default: 0;
+         *  psram pin hys
+         */
+        uint32_t reg_psram_pin_hys:1;
+        /** reg_psram_pin_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_pin_ie:1;
+        /** reg_psram_pin_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram pin wpu
+         */
+        uint32_t reg_psram_pin_wpu:1;
+        /** reg_psram_pin_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram pin wpd
+         */
+        uint32_t reg_psram_pin_wpd:1;
+        /** reg_psram_d_drv : R/W; bitpos: [13:12]; default: 0;
+         *  psram pin drv
+         */
+        uint32_t reg_psram_d_drv:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_pin_reg_t;
+
+/** psram_dqs_pin */
+typedef union {
+    struct {
+        /** reg_psram_dqs_xpd : R/W; bitpos: [0]; default: 0;
+         *  psram xpd dqs
+         */
+        uint32_t reg_psram_dqs_xpd:1;
+        /** reg_psram_dqs_phase : R/W; bitpos: [2:1]; default: 0;
+         *  psram dqs phase
+         */
+        uint32_t reg_psram_dqs_phase:2;
+        /** reg_psram_dqs_dli : R/W; bitpos: [6:3]; default: 0;
+         *  psram dqs dli
+         */
+        uint32_t reg_psram_dqs_dli:4;
+        /** reg_psram_dqs_delay_90 : R/W; bitpos: [10:7]; default: 0;
+         *  psram dqs delay 90
+         */
+        uint32_t reg_psram_dqs_delay_90:4;
+        /** reg_psram_dqs_hys : R/W; bitpos: [11]; default: 0;
+         *  psram dqs hys
+         */
+        uint32_t reg_psram_dqs_hys:1;
+        /** reg_psram_dqs_ie : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dqs_ie:1;
+        /** reg_psram_dqs_wpu : R/W; bitpos: [13]; default: 0;
+         *  psram dqs wpu
+         */
+        uint32_t reg_psram_dqs_wpu:1;
+        /** reg_psram_dqs_wpd : R/W; bitpos: [14]; default: 0;
+         *  psram dqs wpd
+         */
+        uint32_t reg_psram_dqs_wpd:1;
+        /** reg_psram_dqs_drv : R/W; bitpos: [16:15]; default: 0;
+         *  psram dqs drv
+         */
+        uint32_t reg_psram_dqs_drv:2;
+        /** reg_psram_dqs_delay_270 : R/W; bitpos: [20:17]; default: 0;
+         *  psram dqs delay 270
+         */
+        uint32_t reg_psram_dqs_delay_270:4;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dqs_pin_reg_t;
+
+/** psram_pin group */
+typedef struct {
+    volatile iomux_mspi_pin_psram_pin_reg_t pin_group0[8];   //for d, q, wp, hold, dq4, dq5, dq6, dq7
+    volatile iomux_mspi_pin_psram_dqs_pin_reg_t dqs0;
+    volatile iomux_mspi_pin_psram_pin_reg_t pin_group1[10];  //for ck, cs, dq8, dq9, dq10, dq11, dq12, dq13, dq14, dq15
+    volatile iomux_mspi_pin_psram_dqs_pin_reg_t dqs1;
+} iomux_mspi_pin_psram_pin_grp_reg_t;
+
+typedef struct {
+    volatile iomux_mspi_pin_clk_en0_reg_t clk_en0;
+    volatile iomux_mspi_pin_flash_cs_pin0_reg_t flash_cs_pin0;
+    volatile iomux_mspi_pin_flash_q_pin0_reg_t flash_q_pin0;
+    volatile iomux_mspi_pin_flash_wp_pin0_reg_t flash_wp_pin0;
+    volatile iomux_mspi_pin_flash_hold_pin0_reg_t flash_hold_pin0;
+    volatile iomux_mspi_pin_flash_ck_pin0_reg_t flash_ck_pin0;
+    volatile iomux_mspi_pin_flash_d_pin0_reg_t flash_d_pin0;
+    volatile iomux_mspi_pin_psram_pin_grp_reg_t psram_pin_group;
+} iomux_mspi_pin_dev_t;
+
+extern iomux_mspi_pin_dev_t MSPI_IOMUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(iomux_mspi_pin_dev_t) == 0x6c, "Invalid size of iomux_mspi_pin_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/keymng_eco5_reg.h

@@ -0,0 +1,395 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** KEYMNG_CLK_REG register
+ *  Key Manager clock gate control register
+ */
+#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
+/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define KEYMNG_REG_CG_FORCE_ON    (BIT(0))
+#define KEYMNG_REG_CG_FORCE_ON_M  (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
+#define KEYMNG_REG_CG_FORCE_ON_V  0x00000001U
+#define KEYMNG_REG_CG_FORCE_ON_S  0
+/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define KEYMNG_MEM_CG_FORCE_ON    (BIT(1))
+#define KEYMNG_MEM_CG_FORCE_ON_M  (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
+#define KEYMNG_MEM_CG_FORCE_ON_V  0x00000001U
+#define KEYMNG_MEM_CG_FORCE_ON_S  1
+
+/** KEYMNG_INT_RAW_REG register
+ *  Key Manager interrupt raw register, valid in level.
+ */
+#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
+/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_RAW    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_RAW_M  (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
+#define KEYMNG_PREP_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_RAW_S  0
+/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_RAW    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_RAW_M  (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
+#define KEYMNG_PROC_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_RAW_S  1
+/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_RAW    (BIT(2))
+#define KEYMNG_POST_DONE_INT_RAW_M  (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
+#define KEYMNG_POST_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_RAW_S  2
+
+/** KEYMNG_INT_ST_REG register
+ *  Key Manager interrupt status register.
+ */
+#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
+/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ST    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ST_M  (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
+#define KEYMNG_PREP_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ST_S  0
+/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ST    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ST_M  (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
+#define KEYMNG_PROC_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ST_S  1
+/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ST    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ST_M  (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
+#define KEYMNG_POST_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ST_S  2
+
+/** KEYMNG_INT_ENA_REG register
+ *  Key Manager interrupt enable register.
+ */
+#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
+/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ENA    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ENA_M  (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
+#define KEYMNG_PREP_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ENA_S  0
+/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ENA    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ENA_M  (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
+#define KEYMNG_PROC_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ENA_S  1
+/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ENA    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ENA_M  (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
+#define KEYMNG_POST_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ENA_S  2
+
+/** KEYMNG_INT_CLR_REG register
+ *  Key Manager interrupt clear register.
+ */
+#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
+/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_CLR    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_CLR_M  (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
+#define KEYMNG_PREP_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_CLR_S  0
+/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_CLR    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_CLR_M  (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
+#define KEYMNG_PROC_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_CLR_S  1
+/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_CLR    (BIT(2))
+#define KEYMNG_POST_DONE_INT_CLR_M  (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
+#define KEYMNG_POST_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_CLR_S  2
+
+/** KEYMNG_STATIC_REG register
+ *  Key Manager static configuration register
+ */
+#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
+/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
+ *  Set each bit to choose efuse key instead of key manager deployed key. Each bit
+ *  stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
+ *  bit 1 for flash_key; bit 0 for ecdsa_key
+ */
+#define KEYMNG_USE_EFUSE_KEY    0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_M  (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
+#define KEYMNG_USE_EFUSE_KEY_V  0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_S  0
+/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
+ *  The core clock cycle number to sample one rng input data. Please set it bigger than
+ *  the clock cycle ratio: T_rng/T_km
+ */
+#define KEYMNG_RND_SWITCH_CYCLE    0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_M  (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
+#define KEYMNG_RND_SWITCH_CYCLE_V  0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_S  5
+/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to use software written init key instead of efuse_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY    (BIT(10))
+#define KEYMNG_USE_SW_INIT_KEY_M  (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
+#define KEYMNG_USE_SW_INIT_KEY_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_S  10
+/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
+ *  xts-aes-256. 0: use xts-aes-128.
+ */
+#define KEYMNG_FLASH_KEY_LEN    (BIT(11))
+#define KEYMNG_FLASH_KEY_LEN_M  (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
+#define KEYMNG_FLASH_KEY_LEN_V  0x00000001U
+#define KEYMNG_FLASH_KEY_LEN_S  11
+/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
+ *  xts-aes-256. 0: use xts-aes-128.
+ */
+#define KEYMNG_PSRAM_KEY_LEN    (BIT(12))
+#define KEYMNG_PSRAM_KEY_LEN_M  (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
+#define KEYMNG_PSRAM_KEY_LEN_V  0x00000001U
+#define KEYMNG_PSRAM_KEY_LEN_S  12
+
+/** KEYMNG_LOCK_REG register
+ *  Key Manager static configuration locker register
+ */
+#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
+/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
+ *  Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
+ *  reg_use_efuse_key.
+ */
+#define KEYMNG_USE_EFUSE_KEY_LOCK    0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_LOCK_M  (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
+#define KEYMNG_USE_EFUSE_KEY_LOCK_V  0x0000001FU
+#define KEYMNG_USE_EFUSE_KEY_LOCK_S  0
+/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
+ *  Write 1 to lock reg_rnd_switch_cycle.
+ */
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK    (BIT(5))
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M  (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V  0x00000001U
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S  5
+/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
+ *  Write 1 to lock reg_use_sw_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY_LOCK    (BIT(6))
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_M  (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_S  6
+/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
+ *  Write 1 to lock reg_flash_key_len.
+ */
+#define KEYMNG_FLASH_KEY_LEN_LOCK    (BIT(7))
+#define KEYMNG_FLASH_KEY_LEN_LOCK_M  (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
+#define KEYMNG_FLASH_KEY_LEN_LOCK_V  0x00000001U
+#define KEYMNG_FLASH_KEY_LEN_LOCK_S  7
+/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
+ *  Write 1 to lock reg_psram_key_len.
+ */
+#define KEYMNG_PSRAM_KEY_LEN_LOCK    (BIT(8))
+#define KEYMNG_PSRAM_KEY_LEN_LOCK_M  (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
+#define KEYMNG_PSRAM_KEY_LEN_LOCK_V  0x00000001U
+#define KEYMNG_PSRAM_KEY_LEN_LOCK_S  8
+
+/** KEYMNG_CONF_REG register
+ *  Key Manager configuration register
+ */
+#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
+/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
+ *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
+ */
+#define KEYMNG_KGEN_MODE    0x00000007U
+#define KEYMNG_KGEN_MODE_M  (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
+#define KEYMNG_KGEN_MODE_V  0x00000007U
+#define KEYMNG_KGEN_MODE_S  0
+/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
+ *  Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
+ *  flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
+ *  psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
+ *  ecdsa_key_384_h. Others: reserved.
+ */
+#define KEYMNG_KEY_PURPOSE    0x0000000FU
+#define KEYMNG_KEY_PURPOSE_M  (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
+#define KEYMNG_KEY_PURPOSE_V  0x0000000FU
+#define KEYMNG_KEY_PURPOSE_S  3
+
+/** KEYMNG_START_REG register
+ *  Key Manager control register
+ */
+#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
+/** KEYMNG_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
+ */
+#define KEYMNG_START    (BIT(0))
+#define KEYMNG_START_M  (KEYMNG_START_V << KEYMNG_START_S)
+#define KEYMNG_START_V  0x00000001U
+#define KEYMNG_START_S  0
+/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start Key Manager at IDLE state.
+ */
+#define KEYMNG_CONTINUE    (BIT(1))
+#define KEYMNG_CONTINUE_M  (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
+#define KEYMNG_CONTINUE_V  0x00000001U
+#define KEYMNG_CONTINUE_S  1
+
+/** KEYMNG_STATE_REG register
+ *  Key Manager state register
+ */
+#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
+/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define KEYMNG_STATE    0x00000003U
+#define KEYMNG_STATE_M  (KEYMNG_STATE_V << KEYMNG_STATE_S)
+#define KEYMNG_STATE_V  0x00000003U
+#define KEYMNG_STATE_S  0
+
+/** KEYMNG_RESULT_REG register
+ *  Key Manager operation result register
+ */
+#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
+/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
+ *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
+ */
+#define KEYMNG_PROC_RESULT    (BIT(0))
+#define KEYMNG_PROC_RESULT_M  (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
+#define KEYMNG_PROC_RESULT_V  0x00000001U
+#define KEYMNG_PROC_RESULT_S  0
+
+/** KEYMNG_KEY_VLD_REG register
+ *  Key Manager key status register
+ */
+#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
+/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
+ *  The status bit for key_ecdsa_192.   1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_192_VLD    (BIT(0))
+#define KEYMNG_KEY_ECDSA_192_VLD_M  (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
+#define KEYMNG_KEY_ECDSA_192_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_192_VLD_S  0
+/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
+ *  The status bit for key_ecdsa_256.   1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_256_VLD    (BIT(1))
+#define KEYMNG_KEY_ECDSA_256_VLD_M  (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
+#define KEYMNG_KEY_ECDSA_256_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_256_VLD_S  1
+/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
+ *  The status bit for key_flash.     1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_FLASH_VLD    (BIT(2))
+#define KEYMNG_KEY_FLASH_VLD_M  (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
+#define KEYMNG_KEY_FLASH_VLD_V  0x00000001U
+#define KEYMNG_KEY_FLASH_VLD_S  2
+/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
+ *  The status bit for key_hmac.    1: The key has been deployed correctly. 0: The key
+ *  has not been deployed yet.
+ */
+#define KEYMNG_KEY_HMAC_VLD    (BIT(3))
+#define KEYMNG_KEY_HMAC_VLD_M  (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
+#define KEYMNG_KEY_HMAC_VLD_V  0x00000001U
+#define KEYMNG_KEY_HMAC_VLD_S  3
+/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
+ *  The status bit for key_ds.         1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_DS_VLD    (BIT(4))
+#define KEYMNG_KEY_DS_VLD_M  (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
+#define KEYMNG_KEY_DS_VLD_V  0x00000001U
+#define KEYMNG_KEY_DS_VLD_S  4
+/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
+ *  The status bit for key_psram.   1: The key has been deployed correctly. 0: The key
+ *  has not been deployed yet.
+ */
+#define KEYMNG_KEY_PSRAM_VLD    (BIT(5))
+#define KEYMNG_KEY_PSRAM_VLD_M  (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
+#define KEYMNG_KEY_PSRAM_VLD_V  0x00000001U
+#define KEYMNG_KEY_PSRAM_VLD_S  5
+/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
+ *  The status bit for key_ecdsa_384.   1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_384_VLD    (BIT(6))
+#define KEYMNG_KEY_ECDSA_384_VLD_M  (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
+#define KEYMNG_KEY_ECDSA_384_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_384_VLD_S  6
+
+/** KEYMNG_HUK_VLD_REG register
+ *  Key Manager HUK status register
+ */
+#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
+/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
+ *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
+ */
+#define KEYMNG_HUK_VALID    (BIT(0))
+#define KEYMNG_HUK_VALID_M  (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
+#define KEYMNG_HUK_VALID_V  0x00000001U
+#define KEYMNG_HUK_VALID_S  0
+
+/** KEYMNG_DATE_REG register
+ *  Version control register
+ */
+#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
+/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
+ *  Key Manager version control register.
+ */
+#define KEYMNG_DATE    0x0FFFFFFFU
+#define KEYMNG_DATE_M  (KEYMNG_DATE_V << KEYMNG_DATE_S)
+#define KEYMNG_DATE_V  0x0FFFFFFFU
+#define KEYMNG_DATE_S  0
+
+/** KEYMNG_ASSIST_INFO_MEM register
+ *  The memory that stores assist key info.
+ */
+#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
+#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_PUBLIC_INFO_MEM register
+ *  The memory that stores public key info.
+ */
+#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
+#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_SW_INIT_KEY_MEM register
+ *  The memory that stores software written init key.
+ */
+#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
+#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/keymng_reg.h

@@ -0,0 +1,366 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** KEYMNG_CLK_REG register
+ *  Key Manager clock gate control register
+ */
+#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
+/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define KEYMNG_CLK_EN    (BIT(0))
+#define KEYMNG_CLK_EN_M  (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
+#define KEYMNG_CLK_EN_V  0x00000001U
+#define KEYMNG_CLK_EN_S  0
+/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define KEYMNG_MEM_CG_FORCE_ON    (BIT(1))
+#define KEYMNG_MEM_CG_FORCE_ON_M  (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
+#define KEYMNG_MEM_CG_FORCE_ON_V  0x00000001U
+#define KEYMNG_MEM_CG_FORCE_ON_S  1
+
+/** KEYMNG_INT_RAW_REG register
+ *  Key Manager interrupt raw register, valid in level.
+ */
+#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
+/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_RAW    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_RAW_M  (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
+#define KEYMNG_PREP_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_RAW_S  0
+/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_RAW    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_RAW_M  (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
+#define KEYMNG_PROC_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_RAW_S  1
+/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_RAW    (BIT(2))
+#define KEYMNG_POST_DONE_INT_RAW_M  (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
+#define KEYMNG_POST_DONE_INT_RAW_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_RAW_S  2
+
+/** KEYMNG_INT_ST_REG register
+ *  Key Manager interrupt status register.
+ */
+#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
+/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ST    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ST_M  (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
+#define KEYMNG_PREP_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ST_S  0
+/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ST    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ST_M  (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
+#define KEYMNG_PROC_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ST_S  1
+/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ST    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ST_M  (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
+#define KEYMNG_POST_DONE_INT_ST_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ST_S  2
+
+/** KEYMNG_INT_ENA_REG register
+ *  Key Manager interrupt enable register.
+ */
+#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
+/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_ENA    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_ENA_M  (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
+#define KEYMNG_PREP_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_ENA_S  0
+/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_ENA    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_ENA_M  (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
+#define KEYMNG_PROC_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_ENA_S  1
+/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_ENA    (BIT(2))
+#define KEYMNG_POST_DONE_INT_ENA_M  (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
+#define KEYMNG_POST_DONE_INT_ENA_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_ENA_S  2
+
+/** KEYMNG_INT_CLR_REG register
+ *  Key Manager interrupt clear register.
+ */
+#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
+/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the km_prep_done_int interrupt
+ */
+#define KEYMNG_PREP_DONE_INT_CLR    (BIT(0))
+#define KEYMNG_PREP_DONE_INT_CLR_M  (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
+#define KEYMNG_PREP_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PREP_DONE_INT_CLR_S  0
+/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the km_proc_done_int interrupt
+ */
+#define KEYMNG_PROC_DONE_INT_CLR    (BIT(1))
+#define KEYMNG_PROC_DONE_INT_CLR_M  (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
+#define KEYMNG_PROC_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_PROC_DONE_INT_CLR_S  1
+/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the km_post_done_int interrupt
+ */
+#define KEYMNG_POST_DONE_INT_CLR    (BIT(2))
+#define KEYMNG_POST_DONE_INT_CLR_M  (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
+#define KEYMNG_POST_DONE_INT_CLR_V  0x00000001U
+#define KEYMNG_POST_DONE_INT_CLR_S  2
+
+/** KEYMNG_STATIC_REG register
+ *  Key Manager static configuration register
+ */
+#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
+
+/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set this bit to choose efuse key instead of key manager deployed key for xts_key.*/
+#define KEYMNG_USE_EFUSE_KEY_XTS    (BIT(1))
+#define KEYMNG_USE_EFUSE_KEY_XTS_M  ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S))
+#define KEYMNG_USE_EFUSE_KEY_XTS_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_XTS_S  1
+
+/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa_key.*/
+#define KEYMNG_USE_EFUSE_KEY_ECDSA    (BIT(0))
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_M  ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_S  0
+
+/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
+ *  The core clock cycle number to sample one rng input data. Please set it bigger than
+ *  the clock cycle ratio: T_rng/T_km
+ */
+#define KEYMNG_RND_SWITCH_CYCLE    0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_M  (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
+#define KEYMNG_RND_SWITCH_CYCLE_V  0x0000001FU
+#define KEYMNG_RND_SWITCH_CYCLE_S  4
+/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to use software written init key instead of efuse_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY    (BIT(9))
+#define KEYMNG_USE_SW_INIT_KEY_M  (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
+#define KEYMNG_USE_SW_INIT_KEY_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_S  9
+/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
+ *  xts-aes-128.
+ */
+#define KEYMNG_XTS_AES_KEY_LEN    (BIT(10))
+#define KEYMNG_XTS_AES_KEY_LEN_M  (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
+#define KEYMNG_XTS_AES_KEY_LEN_V  0x00000001U
+#define KEYMNG_XTS_AES_KEY_LEN_S  10
+
+/** KEYMNG_LOCK_REG register
+ *  Key Manager static configuration locker register
+ */
+#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
+
+/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ; bitpos:[1] ; default: 1'd0 ; */
+/* description: Set thus bit to choose efuse key instead of key manager deployed key for xts_key */
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS    (BIT(1))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_M  ((KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S  1
+
+/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W ; bitpos:[0] ; default: 1'd0 ; */
+/* description: Write 1 to lock ecdsa-key */
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA    (BIT(0))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M  ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S  0
+
+/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
+ *  Write 1 to lock reg_rnd_switch_cycle.
+ */
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK    (BIT(4))
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M  (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V  0x00000001U
+#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S  4
+/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
+ *  Write 1 to lock reg_use_sw_init_key.
+ */
+#define KEYMNG_USE_SW_INIT_KEY_LOCK    (BIT(5))
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_M  (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_V  0x00000001U
+#define KEYMNG_USE_SW_INIT_KEY_LOCK_S  5
+/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
+ *  Write 1 to lock reg_xts_aes_key_len.
+ */
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK    (BIT(6))
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M  (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V  0x00000001U
+#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S  6
+
+/** KEYMNG_CONF_REG register
+ *  Key Manager configuration register
+ */
+#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
+/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
+ *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
+ */
+#define KEYMNG_KGEN_MODE    0x00000007U
+#define KEYMNG_KGEN_MODE_M  (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
+#define KEYMNG_KGEN_MODE_V  0x00000007U
+#define KEYMNG_KGEN_MODE_S  0
+/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
+ *  Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
+ *  xts_256_2_key. 4. xts_128_key. others: reserved.
+ */
+#define KEYMNG_KEY_PURPOSE    0x0000000FU
+#define KEYMNG_KEY_PURPOSE_M  (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
+#define KEYMNG_KEY_PURPOSE_V  0x0000000FU
+#define KEYMNG_KEY_PURPOSE_S  3
+
+#define KEYMNG_KEY_PURPOSE_ECDSA    (BIT(0))
+#define KEYMNG_KEY_PURPOSE_ECDSA_M  (KEYMNG_KEY_PURPOSE_ECDSA_V << KEYMNG_KEY_PURPOSE_ECDSA_S)
+#define KEYMNG_KEY_PURPOSE_ECDSA_V  0x00000001U
+#define KEYMNG_KEY_PURPOSE_ECDSA_S  0
+
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1    (BIT(1))
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_M  (KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S)
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V  0x00000001U
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S  1
+
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2    (BIT(2))
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_M  (KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S)
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V  0x00000001U
+#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S  2
+
+/** KEYMNG_START_REG register
+ *  Key Manager control register
+ */
+#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
+/** KEYMNG_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
+ */
+#define KEYMNG_START    (BIT(0))
+#define KEYMNG_START_M  (KEYMNG_START_V << KEYMNG_START_S)
+#define KEYMNG_START_V  0x00000001U
+#define KEYMNG_START_S  0
+/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start Key Manager at IDLE state.
+ */
+#define KEYMNG_CONTINUE    (BIT(1))
+#define KEYMNG_CONTINUE_M  (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
+#define KEYMNG_CONTINUE_V  0x00000001U
+#define KEYMNG_CONTINUE_S  1
+
+/** KEYMNG_STATE_REG register
+ *  Key Manager state register
+ */
+#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
+/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define KEYMNG_STATE    0x00000003U
+#define KEYMNG_STATE_M  (KEYMNG_STATE_V << KEYMNG_STATE_S)
+#define KEYMNG_STATE_V  0x00000003U
+#define KEYMNG_STATE_S  0
+
+/** KEYMNG_RESULT_REG register
+ *  Key Manager operation result register
+ */
+#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
+/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
+ *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
+ */
+#define KEYMNG_PROC_RESULT    (BIT(0))
+#define KEYMNG_PROC_RESULT_M  (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
+#define KEYMNG_PROC_RESULT_V  0x00000001U
+#define KEYMNG_PROC_RESULT_S  0
+
+/** KEYMNG_KEY_VLD_REG register
+ *  Key Manager key status register
+ */
+#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
+/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
+ *  The status bit for key_ecdsa.   1: The key has been deployed correctly. 0: The key
+ *  has not been deployed yet.
+ */
+#define KEYMNG_KEY_ECDSA_VLD    (BIT(0))
+#define KEYMNG_KEY_ECDSA_VLD_M  (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
+#define KEYMNG_KEY_ECDSA_VLD_V  0x00000001U
+#define KEYMNG_KEY_ECDSA_VLD_S  0
+/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
+ *  The status bit for key_xts.        1: The key has been deployed correctly. 0: The
+ *  key has not been deployed yet.
+ */
+#define KEYMNG_KEY_XTS_VLD    (BIT(1))
+#define KEYMNG_KEY_XTS_VLD_M  (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
+#define KEYMNG_KEY_XTS_VLD_V  0x00000001U
+#define KEYMNG_KEY_XTS_VLD_S  1
+
+/** KEYMNG_HUK_VLD_REG register
+ *  Key Manager HUK status register
+ */
+#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
+/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
+ *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
+ */
+#define KEYMNG_HUK_VALID    (BIT(0))
+#define KEYMNG_HUK_VALID_M  (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
+#define KEYMNG_HUK_VALID_V  0x00000001U
+#define KEYMNG_HUK_VALID_S  0
+
+/** KEYMNG_DATE_REG register
+ *  Version control register
+ */
+#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
+/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
+ *  Key Manager version control register.
+ */
+#define KEYMNG_DATE    0x0FFFFFFFU
+#define KEYMNG_DATE_M  (KEYMNG_DATE_V << KEYMNG_DATE_S)
+#define KEYMNG_DATE_V  0x0FFFFFFFU
+#define KEYMNG_DATE_S  0
+
+/** KEYMNG_ASSIST_INFO_MEM register
+ *  The memory that stores assist key info.
+ */
+#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
+#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_PUBLIC_INFO_MEM register
+ *  The memory that stores public key info.
+ */
+#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
+#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
+
+/** KEYMNG_SW_INIT_KEY_MEM register
+ *  The memory that stores software written init key.
+ */
+#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
+#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/keymng_struct.h

@@ -0,0 +1,375 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Clock gate register */
+/** Type of clk register
+ *  Key Manager clock gate control register
+ */
+typedef union {
+    struct {
+        /** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t reg_cg_force_on:1;
+        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to force on memory clock gate.
+         */
+        uint32_t mem_cg_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} keymng_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Key Manager interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Key Manager interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Key Manager interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Key Manager interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the km_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the km_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the km_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} keymng_int_clr_reg_t;
+
+
+/** Group: Static configuration registers */
+/** Type of static register
+ *  Key Manager static configuration register
+ */
+typedef union {
+    struct {
+        /** use_efuse_key : R/W; bitpos: [4:0]; default: 0;
+         *  Set each bit to choose efuse key instead of key manager deployed key. Each bit
+         *  stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
+         *  bit 1 for flash_key; bit 0 for ecdsa_key
+         */
+        uint32_t use_efuse_key:5;
+        /** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15;
+         *  The core clock cycle number to sample one rng input data. Please set it bigger than
+         *  the clock cycle ratio: T_rng/T_km
+         */
+        uint32_t rnd_switch_cycle:5;
+        /** use_sw_init_key : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to use software written init key instead of efuse_init_key.
+         */
+        uint32_t use_sw_init_key:1;
+        /** flash_key_len : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
+         *  xts-aes-256. 0: use xts-aes-128.
+         */
+        uint32_t flash_key_len:1;
+        /** psram_key_len : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
+         *  xts-aes-256. 0: use xts-aes-128.
+         */
+        uint32_t psram_key_len:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} keymng_static_reg_t;
+
+/** Type of lock register
+ *  Key Manager static configuration locker register
+ */
+typedef union {
+    struct {
+        /** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0;
+         *  Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
+         *  reg_use_efuse_key.
+         */
+        uint32_t use_efuse_key_lock:5;
+        /** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0;
+         *  Write 1 to lock reg_rnd_switch_cycle.
+         */
+        uint32_t rnd_switch_cycle_lock:1;
+        /** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0;
+         *  Write 1 to lock reg_use_sw_init_key.
+         */
+        uint32_t use_sw_init_key_lock:1;
+        /** flash_key_len_lock : R/W1; bitpos: [7]; default: 0;
+         *  Write 1 to lock reg_flash_key_len.
+         */
+        uint32_t flash_key_len_lock:1;
+        /** psram_key_len_lock : R/W1; bitpos: [8]; default: 0;
+         *  Write 1 to lock reg_psram_key_len.
+         */
+        uint32_t psram_key_len_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} keymng_lock_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  Key Manager configuration register
+ */
+typedef union {
+    struct {
+        /** kgen_mode : R/W; bitpos: [2:0]; default: 0;
+         *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
+         *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
+         */
+        uint32_t kgen_mode:3;
+        /** key_purpose : R/W; bitpos: [6:3]; default: 0;
+         *  Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
+         *  flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
+         *  psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
+         *  ecdsa_key_384_h. Others: reserved.
+         */
+        uint32_t key_purpose:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} keymng_conf_reg_t;
+
+
+/** Group: Control registers */
+/** Type of start register
+ *  Key Manager control register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
+         */
+        uint32_t start:1;
+        /** continue : WT; bitpos: [1]; default: 0;
+         *  Write 1 to start Key Manager at IDLE state.
+         */
+        uint32_t conti:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} keymng_start_reg_t;
+
+
+/** Group: State registers */
+/** Type of state register
+ *  Key Manager state register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} keymng_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  Key Manager operation result register
+ */
+typedef union {
+    struct {
+        /** proc_result : RO/SS; bitpos: [0]; default: 0;
+         *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
+         *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
+         */
+        uint32_t proc_result:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} keymng_result_reg_t;
+
+/** Type of key_vld register
+ *  Key Manager key status register
+ */
+typedef union {
+    struct {
+        /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0;
+         *  The status bit for key_ecdsa_192.   1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ecdsa_192_vld:1;
+        /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0;
+         *  The status bit for key_ecdsa_256.   1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ecdsa_256_vld:1;
+        /** key_flash_vld : RO; bitpos: [2]; default: 0;
+         *  The status bit for key_flash.     1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_flash_vld:1;
+        /** key_hmac_vld : RO; bitpos: [3]; default: 0;
+         *  The status bit for key_hmac.    1: The key has been deployed correctly. 0: The key
+         *  has not been deployed yet.
+         */
+        uint32_t key_hmac_vld:1;
+        /** key_ds_vld : RO; bitpos: [4]; default: 0;
+         *  The status bit for key_ds.         1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ds_vld:1;
+        /** key_psram_vld : RO; bitpos: [5]; default: 0;
+         *  The status bit for key_psram.   1: The key has been deployed correctly. 0: The key
+         *  has not been deployed yet.
+         */
+        uint32_t key_psram_vld:1;
+        /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0;
+         *  The status bit for key_ecdsa_384.   1: The key has been deployed correctly. 0: The
+         *  key has not been deployed yet.
+         */
+        uint32_t key_ecdsa_384_vld:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} keymng_key_vld_reg_t;
+
+/** Type of huk_vld register
+ *  Key Manager HUK status register
+ */
+typedef union {
+    struct {
+        /** huk_valid : RO; bitpos: [0]; default: 0;
+         *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
+         */
+        uint32_t huk_valid:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} keymng_huk_vld_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37781824;
+         *  Key Manager version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} keymng_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile keymng_clk_reg_t clk;
+    volatile keymng_int_raw_reg_t int_raw;
+    volatile keymng_int_st_reg_t int_st;
+    volatile keymng_int_ena_reg_t int_ena;
+    volatile keymng_int_clr_reg_t int_clr;
+    volatile keymng_static_reg_t static_conf;
+    volatile keymng_lock_reg_t lock;
+    volatile keymng_conf_reg_t conf;
+    volatile keymng_start_reg_t start;
+    volatile keymng_state_reg_t state;
+    volatile keymng_result_reg_t result;
+    volatile keymng_key_vld_reg_t key_vld;
+    volatile keymng_huk_vld_reg_t huk_vld;
+    uint32_t reserved_038[49];
+    volatile keymng_date_reg_t date;
+    volatile uint32_t assist_info[16];
+    volatile uint32_t public_info[16];
+    volatile uint32_t sw_init_key[8];
+} keymng_dev_t;
+
+extern keymng_dev_t KEYMNG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_eco5_struct.h

@@ -0,0 +1,875 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: lcd configuration registers */
+/** Type of lcd_clock register
+ *  LCD clock config register.
+ */
+typedef union {
+    struct {
+        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
+         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+         */
+        uint32_t lcd_clkcnt_n:6;
+        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
+         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+         */
+        uint32_t lcd_clk_equ_sysclk:1;
+        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
+         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+         */
+        uint32_t lcd_ck_idle_edge:1;
+        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
+         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+         *  in the second half data cycle.
+         */
+        uint32_t lcd_ck_out_edge:1;
+        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral LCD clock divider value
+         */
+        uint32_t lcd_clkm_div_num:8;
+        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t lcd_clkm_div_b:6;
+        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t lcd_clkm_div_a:6;
+        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t lcd_clk_sel:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_clock_reg_t;
+
+/** Type of lcd_rgb_yuv register
+ *  LCD YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3;
+         *  0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled
+         */
+        uint32_t lcd_conv_rgb2rgb_mode:2;
+        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t lcd_conv_8bits_data_inv:1;
+        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
+         *  0: txtorx mode off. 1: txtorx mode on.
+         */
+        uint32_t lcd_conv_txtorx:1;
+        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422.  2: to yuv411. 1,3: disabled.  To enable yuv2yuv mode, trans_mode
+         *  must be set to 1.
+         */
+        uint32_t lcd_conv_yuv2yuv_mode:2;
+        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in
+         */
+        uint32_t lcd_conv_yuv_mode:2;
+        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t lcd_conv_protocol_mode:1;
+        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_out_mode:1;
+        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_in_mode:1;
+        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t lcd_conv_mode_8bits_on:1;
+        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t lcd_conv_trans_mode:1;
+        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t lcd_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_rgb_yuv_reg_t;
+
+/** Type of lcd_user register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
+         *  The output data cycles minus 1 of LCD module.
+         */
+        uint32_t lcd_dout_cyclelen:13;
+        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
+         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+         *  reg_lcd_reset is set.
+         */
+        uint32_t lcd_always_out_en:1;
+        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
+         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+         */
+        uint32_t lcd_dout_byte_swizzle_mode:3;
+        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
+         *  1: enable byte swizzle 0: disable
+         */
+        uint32_t lcd_dout_byte_swizzle_enable:1;
+        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
+         *  1: change bit order in every byte. 0: Not change.
+         */
+        uint32_t lcd_dout_bit_order:1;
+        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
+         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+         */
+        uint32_t lcd_byte_mode:2;
+        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
+         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t lcd_update_reg:1;
+        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
+         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t lcd_bit_order:1;
+        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t lcd_byte_order:1;
+        /** lcd_dout : R/W; bitpos: [24]; default: 0;
+         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dout:1;
+        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
+         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dummy:1;
+        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
+         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_cmd:1;
+        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
+         *  LCD start sending data enable signal, valid in high level.
+         */
+        uint32_t lcd_start:1;
+        /** lcd_reset : WT; bitpos: [28]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t lcd_reset:1;
+        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
+         *  The dummy cycle length minus 1.
+         */
+        uint32_t lcd_dummy_cyclelen:2;
+        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
+         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+         */
+        uint32_t lcd_cmd_2_cycle_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_user_reg_t;
+
+/** Type of lcd_misc register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+         */
+        uint32_t lcd_wire_mode:2;
+        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
+         *  The setup cycle length minus 1 in LCD non-RGB mode.
+         */
+        uint32_t lcd_vfk_cyclelen:6;
+        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
+         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+         *  time cycle length in LCD non-RGB mode.
+         */
+        uint32_t lcd_vbk_cyclelen:13;
+        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
+         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+         *  the current frame is sent out.
+         */
+        uint32_t lcd_next_frame_en:1;
+        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
+         *  1: Enable blank region when LCD sends data out. 0: No blank region.
+         */
+        uint32_t lcd_bk_en:1;
+        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
+         *  LCD AFIFO reset signal.
+         */
+        uint32_t lcd_afifo_reset:1;
+        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_data_set:1;
+        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_dummy_set:1;
+        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_cmd_set:1;
+        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
+         *  The default value of LCD_CD.
+         */
+        uint32_t lcd_cd_idle_edge:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_misc_reg_t;
+
+/** Type of lcd_ctrl register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
+         *  It is the horizontal blank front porch of a frame.
+         */
+        uint32_t lcd_hb_front:11;
+        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
+         *  It is the vertical active height of a frame.
+         */
+        uint32_t lcd_va_height:10;
+        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
+         *  It is the vertical total height of a frame.
+         */
+        uint32_t lcd_vt_height:10;
+        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
+         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+         */
+        uint32_t lcd_rgb_mode_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl_reg_t;
+
+/** Type of lcd_ctrl1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
+         *  It is the vertical blank front porch of a frame.
+         */
+        uint32_t lcd_vb_front:8;
+        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
+         *  It is the horizontal active width of a frame.
+         */
+        uint32_t lcd_ha_width:12;
+        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
+         *  It is the horizontal total width of a frame.
+         */
+        uint32_t lcd_ht_width:12;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl1_reg_t;
+
+/** Type of lcd_ctrl2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
+         *  It is the position of LCD_VSYNC active pulse in a line.
+         */
+        uint32_t lcd_vsync_width:7;
+        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
+         *  It is the idle value of LCD_VSYNC.
+         */
+        uint32_t lcd_vsync_idle_pol:1;
+        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
+         *  It is the idle value of LCD_DE.
+         */
+        uint32_t lcd_de_idle_pol:1;
+        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
+         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+         *  pulse is valid only in active region lines in RGB mode.
+         */
+        uint32_t lcd_hs_blank_en:1;
+        uint32_t reserved_10:6;
+        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_width:7;
+        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
+         *  It is the idle value of LCD_HSYNC.
+         */
+        uint32_t lcd_hsync_idle_pol:1;
+        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_position:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl2_reg_t;
+
+/** Type of lcd_first_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of first cmd cycle.
+         */
+        uint32_t lcd_first_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_first_cmd_val_reg_t;
+
+/** Type of lcd_latter_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of latter cmd cycle.
+         */
+        uint32_t lcd_latter_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_latter_cmd_val_reg_t;
+
+/** Type of lcd_dly_mode_cfg1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout16_mode:2;
+        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout17_mode:2;
+        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout18_mode:2;
+        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout19_mode:2;
+        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout20_mode:2;
+        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout21_mode:2;
+        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout22_mode:2;
+        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout23_mode:2;
+        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_cd_mode:2;
+        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_de_mode:2;
+        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_hsync_mode:2;
+        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_vsync_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg1_reg_t;
+
+/** Type of lcd_dly_mode_cfg2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout0_mode:2;
+        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout1_mode:2;
+        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout2_mode:2;
+        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout3_mode:2;
+        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout4_mode:2;
+        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout5_mode:2;
+        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout6_mode:2;
+        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout7_mode:2;
+        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout8_mode:2;
+        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout9_mode:2;
+        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout10_mode:2;
+        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout11_mode:2;
+        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout12_mode:2;
+        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout13_mode:2;
+        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout14_mode:2;
+        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout15_mode:2;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg2_reg_t;
+
+
+/** Group: cam configuration registers */
+/** Type of cam_ctrl register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+         */
+        uint32_t cam_stop_en:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
+         *  Filter threshold value for CAM_VSYNC signal.
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
+         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
+         *  1: invert data byte order. 0: Not change.
+         */
+        uint32_t cam_byte_order:1;
+        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t cam_bit_order:1;
+        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable to generate CAM_HS_INT. 0: Disable.
+         */
+        uint32_t cam_line_int_en:1;
+        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
+         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+         *  reg_cam_rec_data_cyclelen.
+         */
+        uint32_t cam_vs_eof_en:1;
+        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral Camera clock divider value
+         */
+        uint32_t cam_clkm_div_num:8;
+        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t cam_clkm_div_b:6;
+        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t cam_clkm_div_a:6;
+        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t cam_clk_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl_reg_t;
+
+/** Type of cam_ctrl1 register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
+         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+         */
+        uint32_t cam_rec_data_bytelen:16;
+        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
+         *  The line number minus 1 to generate cam_hs_int.
+         */
+        uint32_t cam_line_int_num:6;
+        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
+         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+         */
+        uint32_t cam_clk_inv:1;
+        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
+         *  1: Enable CAM_VSYNC filter function. 0: bypass.
+         */
+        uint32_t cam_vsync_filter_en:1;
+        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
+         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+         */
+        uint32_t cam_2byte_en:1;
+        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
+         *  CAM_DE invert enable signal, valid in high level.
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
+         *  CAM_HSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
+         *  CAM_VSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
+         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+         *  signals are CAM_DE and CAM_VSYNC.
+         */
+        uint32_t cam_vh_de_mode_en:1;
+        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
+         *  Camera module start signal.
+         */
+        uint32_t cam_start:1;
+        /** cam_reset : WT; bitpos: [30]; default: 0;
+         *  Camera module reset signal.
+         */
+        uint32_t cam_reset:1;
+        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
+         *  Camera AFIFO reset signal.
+         */
+        uint32_t cam_afifo_reset:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl1_reg_t;
+
+/** Type of cam_rgb_yuv register
+ *  CAM YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t cam_conv_8bits_data_inv:1;
+        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t cam_conv_yuv2yuv_mode:2;
+        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t cam_conv_yuv_mode:2;
+        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t cam_conv_protocol_mode:1;
+        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_out_mode:1;
+        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_in_mode:1;
+        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t cam_conv_mode_8bits_on:1;
+        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t cam_conv_trans_mode:1;
+        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t cam_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_cam_rgb_yuv_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of lc_dma_int_ena register
+ *  LCDCAM interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_ena:1;
+        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_ena:1;
+        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_ena:1;
+        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_ena:1;
+        /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_ena_reg_t;
+
+/** Type of lc_dma_int_raw register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_raw:1;
+        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_raw:1;
+        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_raw:1;
+        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_raw:1;
+        /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_raw_reg_t;
+
+/** Type of lc_dma_int_st register
+ *  LCDCAM interrupt status register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_st:1;
+        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_st:1;
+        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_st:1;
+        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for Camera transfer end interrupt.
+         */
+        uint32_t cam_hs_int_st:1;
+        /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_st_reg_t;
+
+/** Type of lc_dma_int_clr register
+ *  LCDCAM interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_clr:1;
+        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_clr:1;
+        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_clr:1;
+        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_clr:1;
+        /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_clr_reg_t;
+
+
+/** Group: Version register */
+/** Type of lc_reg_date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** lc_date : R/W; bitpos: [27:0]; default: 38806054;
+         *  LCD_CAM version control register
+         */
+        uint32_t lc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lcdcam_lc_reg_date_reg_t;
+
+
+typedef struct {
+    volatile lcdcam_lcd_clock_reg_t lcd_clock;
+    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
+    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
+    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
+    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
+    volatile lcdcam_lcd_user_reg_t lcd_user;
+    volatile lcdcam_lcd_misc_reg_t lcd_misc;
+    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
+    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
+    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
+    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
+    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
+    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
+    uint32_t reserved_034;
+    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
+    uint32_t reserved_03c[10];
+    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
+    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
+    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
+    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
+    uint32_t reserved_074[34];
+    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
+} lcdcam_dev_t;
+
+extern lcdcam_dev_t LCD_CAM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_struct.h

@@ -0,0 +1,857 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: lcd configuration registers */
+/** Type of lcd_clock register
+ *  LCD clock config register.
+ */
+typedef union {
+    struct {
+        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
+         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+         */
+        uint32_t lcd_clkcnt_n:6;
+        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
+         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+         */
+        uint32_t lcd_clk_equ_sysclk:1;
+        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
+         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+         */
+        uint32_t lcd_ck_idle_edge:1;
+        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
+         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
+         *  in the second half data cycle.
+         */
+        uint32_t lcd_ck_out_edge:1;
+        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral LCD clock divider value
+         */
+        uint32_t lcd_clkm_div_num:8;
+        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t lcd_clkm_div_b:6;
+        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t lcd_clkm_div_a:6;
+        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t lcd_clk_sel:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_clock_reg_t;
+
+/** Type of lcd_rgb_yuv register
+ *  LCD YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t lcd_conv_8bits_data_inv:1;
+        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
+         *  0: txtorx mode off. 1: txtorx mode on.
+         */
+        uint32_t lcd_conv_txtorx:1;
+        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t lcd_conv_yuv2yuv_mode:2;
+        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t lcd_conv_yuv_mode:2;
+        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t lcd_conv_protocol_mode:1;
+        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_out_mode:1;
+        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_in_mode:1;
+        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t lcd_conv_mode_8bits_on:1;
+        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t lcd_conv_trans_mode:1;
+        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t lcd_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_rgb_yuv_reg_t;
+
+/** Type of lcd_user register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
+         *  The output data cycles minus 1 of LCD module.
+         */
+        uint32_t lcd_dout_cyclelen:13;
+        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
+         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+         *  reg_lcd_reset is set.
+         */
+        uint32_t lcd_always_out_en:1;
+        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
+         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
+         */
+        uint32_t lcd_dout_byte_swizzle_mode:3;
+        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
+         *  1: enable byte swizzle 0: disable
+         */
+        uint32_t lcd_dout_byte_swizzle_enable:1;
+        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
+         *  1: change bit order in every byte. 0: Not change.
+         */
+        uint32_t lcd_dout_bit_order:1;
+        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
+         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
+         */
+        uint32_t lcd_byte_mode:2;
+        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
+         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t lcd_update_reg:1;
+        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
+         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t lcd_bit_order:1;
+        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t lcd_byte_order:1;
+        /** lcd_dout : R/W; bitpos: [24]; default: 0;
+         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dout:1;
+        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
+         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dummy:1;
+        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
+         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_cmd:1;
+        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
+         *  LCD start sending data enable signal, valid in high level.
+         */
+        uint32_t lcd_start:1;
+        /** lcd_reset : WT; bitpos: [28]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t lcd_reset:1;
+        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
+         *  The dummy cycle length minus 1.
+         */
+        uint32_t lcd_dummy_cyclelen:2;
+        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
+         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
+         */
+        uint32_t lcd_cmd_2_cycle_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_user_reg_t;
+
+/** Type of lcd_misc register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
+         */
+        uint32_t lcd_wire_mode:2;
+        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
+         *  The setup cycle length minus 1 in LCD non-RGB mode.
+         */
+        uint32_t lcd_vfk_cyclelen:6;
+        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
+         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+         *  time cycle length in LCD non-RGB mode.
+         */
+        uint32_t lcd_vbk_cyclelen:13;
+        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
+         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+         *  the current frame is sent out.
+         */
+        uint32_t lcd_next_frame_en:1;
+        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
+         *  1: Enable blank region when LCD sends data out. 0: No blank region.
+         */
+        uint32_t lcd_bk_en:1;
+        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
+         *  LCD AFIFO reset signal.
+         */
+        uint32_t lcd_afifo_reset:1;
+        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_data_set:1;
+        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_dummy_set:1;
+        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_cmd_set:1;
+        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
+         *  The default value of LCD_CD.
+         */
+        uint32_t lcd_cd_idle_edge:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_misc_reg_t;
+
+/** Type of lcd_ctrl register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
+         *  It is the horizontal blank front porch of a frame.
+         */
+        uint32_t lcd_hb_front:11;
+        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
+         *  It is the vertical active height of a frame.
+         */
+        uint32_t lcd_va_height:10;
+        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
+         *  It is the vertical total height of a frame.
+         */
+        uint32_t lcd_vt_height:10;
+        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
+         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
+         */
+        uint32_t lcd_rgb_mode_en:1;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl_reg_t;
+
+/** Type of lcd_ctrl1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
+         *  It is the vertical blank front porch of a frame.
+         */
+        uint32_t lcd_vb_front:8;
+        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
+         *  It is the horizontal active width of a frame.
+         */
+        uint32_t lcd_ha_width:12;
+        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
+         *  It is the horizontal total width of a frame.
+         */
+        uint32_t lcd_ht_width:12;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl1_reg_t;
+
+/** Type of lcd_ctrl2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
+         *  It is the position of LCD_VSYNC active pulse in a line.
+         */
+        uint32_t lcd_vsync_width:7;
+        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
+         *  It is the idle value of LCD_VSYNC.
+         */
+        uint32_t lcd_vsync_idle_pol:1;
+        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
+         *  It is the idle value of LCD_DE.
+         */
+        uint32_t lcd_de_idle_pol:1;
+        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
+         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+         *  pulse is valid only in active region lines in RGB mode.
+         */
+        uint32_t lcd_hs_blank_en:1;
+        uint32_t reserved_10:6;
+        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_width:7;
+        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
+         *  It is the idle value of LCD_HSYNC.
+         */
+        uint32_t lcd_hsync_idle_pol:1;
+        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_position:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_ctrl2_reg_t;
+
+/** Type of lcd_first_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of first cmd cycle.
+         */
+        uint32_t lcd_first_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_first_cmd_val_reg_t;
+
+/** Type of lcd_latter_cmd_val register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value of latter cmd cycle.
+         */
+        uint32_t lcd_latter_cmd_value:32;
+    };
+    uint32_t val;
+} lcdcam_lcd_latter_cmd_val_reg_t;
+
+/** Type of lcd_dly_mode_cfg1 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout16_mode:2;
+        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout17_mode:2;
+        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout18_mode:2;
+        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout19_mode:2;
+        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout20_mode:2;
+        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout21_mode:2;
+        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout22_mode:2;
+        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout23_mode:2;
+        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_cd_mode:2;
+        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_de_mode:2;
+        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_hsync_mode:2;
+        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_vsync_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg1_reg_t;
+
+/** Type of lcd_dly_mode_cfg2 register
+ *  LCD config register.
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout0_mode:2;
+        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout1_mode:2;
+        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout2_mode:2;
+        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout3_mode:2;
+        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout4_mode:2;
+        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout5_mode:2;
+        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout6_mode:2;
+        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout7_mode:2;
+        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout8_mode:2;
+        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout9_mode:2;
+        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout10_mode:2;
+        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout11_mode:2;
+        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout12_mode:2;
+        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout13_mode:2;
+        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout14_mode:2;
+        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout15_mode:2;
+    };
+    uint32_t val;
+} lcdcam_lcd_dly_mode_cfg2_reg_t;
+
+
+/** Group: cam configuration registers */
+/** Type of cam_ctrl register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+         */
+        uint32_t cam_stop_en:1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
+         *  Filter threshold value for CAM_VSYNC signal.
+         */
+        uint32_t cam_vsync_filter_thres:3;
+        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
+         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t cam_update_reg:1;
+        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t cam_byte_order:1;
+        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t cam_bit_order:1;
+        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable to generate CAM_HS_INT. 0: Disable.
+         */
+        uint32_t cam_line_int_en:1;
+        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
+         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+         *  reg_cam_rec_data_cyclelen.
+         */
+        uint32_t cam_vs_eof_en:1;
+        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral Camera clock divider value
+         */
+        uint32_t cam_clkm_div_num:8;
+        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t cam_clkm_div_b:6;
+        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t cam_clkm_div_a:6;
+        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t cam_clk_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl_reg_t;
+
+/** Type of cam_ctrl1 register
+ *  CAM config register.
+ */
+typedef union {
+    struct {
+        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
+         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+         */
+        uint32_t cam_rec_data_bytelen:16;
+        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
+         *  The line number minus 1 to generate cam_hs_int.
+         */
+        uint32_t cam_line_int_num:6;
+        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
+         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+         */
+        uint32_t cam_clk_inv:1;
+        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
+         *  1: Enable CAM_VSYNC filter function. 0: bypass.
+         */
+        uint32_t cam_vsync_filter_en:1;
+        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
+         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+         */
+        uint32_t cam_2byte_en:1;
+        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
+         *  CAM_DE invert enable signal, valid in high level.
+         */
+        uint32_t cam_de_inv:1;
+        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
+         *  CAM_HSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_hsync_inv:1;
+        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
+         *  CAM_VSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_vsync_inv:1;
+        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
+         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
+         *  signals are CAM_DE and CAM_VSYNC.
+         */
+        uint32_t cam_vh_de_mode_en:1;
+        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
+         *  Camera module start signal.
+         */
+        uint32_t cam_start:1;
+        /** cam_reset : WT; bitpos: [30]; default: 0;
+         *  Camera module reset signal.
+         */
+        uint32_t cam_reset:1;
+        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
+         *  Camera AFIFO reset signal.
+         */
+        uint32_t cam_afifo_reset:1;
+    };
+    uint32_t val;
+} lcdcam_cam_ctrl1_reg_t;
+
+/** Type of cam_rgb_yuv register
+ *  CAM YUV/RGB converter configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t cam_conv_8bits_data_inv:1;
+        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t cam_conv_yuv2yuv_mode:2;
+        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t cam_conv_yuv_mode:2;
+        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t cam_conv_protocol_mode:1;
+        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_out_mode:1;
+        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_in_mode:1;
+        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t cam_conv_mode_8bits_on:1;
+        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t cam_conv_trans_mode:1;
+        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t cam_conv_enable:1;
+    };
+    uint32_t val;
+} lcdcam_cam_rgb_yuv_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of lc_dma_int_ena register
+ *  LCDCAM interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_ena:1;
+        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_ena:1;
+        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_ena:1;
+        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_ena_reg_t;
+
+/** Type of lc_dma_int_raw register
+ *  LCDCAM interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_raw:1;
+        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_raw:1;
+        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_raw:1;
+        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_raw_reg_t;
+
+/** Type of lc_dma_int_st register
+ *  LCDCAM interrupt status register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_st:1;
+        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_st:1;
+        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_st:1;
+        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for Camera transfer end interrupt.
+         */
+        uint32_t cam_hs_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_st_reg_t;
+
+/** Type of lc_dma_int_clr register
+ *  LCDCAM interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_clr:1;
+        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_clr:1;
+        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_clr:1;
+        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lcdcam_lc_dma_int_clr_reg_t;
+
+
+/** Group: Version register */
+/** Type of lc_reg_date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** lc_date : R/W; bitpos: [27:0]; default: 36712592;
+         *  LCD_CAM version control register
+         */
+        uint32_t lc_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lcdcam_lc_reg_date_reg_t;
+
+
+typedef struct lcd_cam_dev_t {
+    volatile lcdcam_lcd_clock_reg_t lcd_clock;
+    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
+    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
+    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
+    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
+    volatile lcdcam_lcd_user_reg_t lcd_user;
+    volatile lcdcam_lcd_misc_reg_t lcd_misc;
+    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
+    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
+    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
+    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
+    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
+    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
+    uint32_t reserved_034;
+    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
+    uint32_t reserved_03c[10];
+    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
+    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
+    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
+    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
+    uint32_t reserved_074[34];
+    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
+} lcd_cam_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+#endif
+
+extern lcd_cam_dev_t LCD_CAM;
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_eco5_reg.h

@@ -0,0 +1,585 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_LP2HP_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_LP2HP_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_LP_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_PSRAM_ALLOW_M  (TEE_REG_LP_MM_PSRAM_ALLOW_V << TEE_REG_LP_MM_PSRAM_ALLOW_S)
+#define TEE_REG_LP_MM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_PSRAM_ALLOW_S  0
+/** TEE_REG_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_FLASH_ALLOW_M  (TEE_REG_LP_MM_FLASH_ALLOW_V << TEE_REG_LP_MM_FLASH_ALLOW_S)
+#define TEE_REG_LP_MM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_FLASH_ALLOW_S  1
+/** TEE_REG_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_L2MEM_ALLOW_M  (TEE_REG_LP_MM_L2MEM_ALLOW_V << TEE_REG_LP_MM_L2MEM_ALLOW_S)
+#define TEE_REG_LP_MM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_L2MEM_ALLOW_S  2
+/** TEE_REG_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_L2ROM_ALLOW_M  (TEE_REG_LP_MM_L2ROM_ALLOW_V << TEE_REG_LP_MM_L2ROM_ALLOW_S)
+#define TEE_REG_LP_MM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_L2ROM_ALLOW_S  3
+/** TEE_REG_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_TRACE0_ALLOW_M  (TEE_REG_LP_MM_TRACE0_ALLOW_V << TEE_REG_LP_MM_TRACE0_ALLOW_S)
+#define TEE_REG_LP_MM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_TRACE0_ALLOW_S  6
+/** TEE_REG_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_TRACE1_ALLOW_M  (TEE_REG_LP_MM_TRACE1_ALLOW_V << TEE_REG_LP_MM_TRACE1_ALLOW_S)
+#define TEE_REG_LP_MM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_TRACE1_ALLOW_S  7
+/** TEE_REG_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_M  (TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_M  (TEE_REG_LP_MM_L2MEM_MON_ALLOW_V << TEE_REG_LP_MM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_TCM_MON_ALLOW_M  (TEE_REG_LP_MM_TCM_MON_ALLOW_V << TEE_REG_LP_MM_TCM_MON_ALLOW_S)
+#define TEE_REG_LP_MM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_TCM_MON_ALLOW_S  10
+/** TEE_REG_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_CACHE_ALLOW_M  (TEE_REG_LP_MM_CACHE_ALLOW_V << TEE_REG_LP_MM_CACHE_ALLOW_S)
+#define TEE_REG_LP_MM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_CACHE_ALLOW_S  11
+
+/** TEE_LP_MM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_REG_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_M  (TEE_REG_LP_MM_HP_USBOTG_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_M  (TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW_M  (TEE_REG_LP_MM_HP_GDMA_ALLOW_V << TEE_REG_LP_MM_HP_GDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_M  (TEE_REG_LP_MM_HP_REGDMA_ALLOW_V << TEE_REG_LP_MM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_M  (TEE_REG_LP_MM_HP_SDMMC_ALLOW_V << TEE_REG_LP_MM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW_M  (TEE_REG_LP_MM_HP_JPEG_ALLOW_V << TEE_REG_LP_MM_HP_JPEG_ALLOW_S)
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_HP_PPA_ALLOW_M  (TEE_REG_LP_MM_HP_PPA_ALLOW_V << TEE_REG_LP_MM_HP_PPA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PPA_ALLOW_S  8
+/** TEE_REG_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_M  (TEE_REG_LP_MM_HP_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW_M  (TEE_REG_LP_MM_HP_FLASH_ALLOW_V << TEE_REG_LP_MM_HP_FLASH_ALLOW_S)
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_M  (TEE_REG_LP_MM_HP_PSRAM_ALLOW_V << TEE_REG_LP_MM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_M  (TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V << TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW_M  (TEE_REG_LP_MM_HP_GMAC_ALLOW_V << TEE_REG_LP_MM_HP_GMAC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_M  (TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V << TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_LP_MM_HP_PVT_ALLOW_M  (TEE_REG_LP_MM_HP_PVT_ALLOW_V << TEE_REG_LP_MM_HP_PVT_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PVT_ALLOW_S  17
+/** TEE_REG_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_M  (TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_M  (TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_LP_MM_HP_ISP_ALLOW_M  (TEE_REG_LP_MM_HP_ISP_ALLOW_V << TEE_REG_LP_MM_HP_ISP_ALLOW_S)
+#define TEE_REG_LP_MM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_ISP_ALLOW_S  20
+/** TEE_REG_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_M  (TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V << TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_LP_MM_HP_RMT_ALLOW_M  (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S)
+#define TEE_REG_LP_MM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_RMT_ALLOW_S  22
+/** TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_M  (TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_M  (TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW_M  (TEE_REG_LP_MM_DMA_PMS_ALLOW_V << TEE_REG_LP_MM_DMA_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_M  (TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_LP_MM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0xa4)
+/** TEE_REG_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_M  (TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_M  (TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW_M  (TEE_REG_LP_MM_HP_I2C0_ALLOW_V << TEE_REG_LP_MM_HP_I2C0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW_M  (TEE_REG_LP_MM_HP_I2C1_ALLOW_V << TEE_REG_LP_MM_HP_I2C1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW_M  (TEE_REG_LP_MM_HP_I2S0_ALLOW_V << TEE_REG_LP_MM_HP_I2S0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW_M  (TEE_REG_LP_MM_HP_I2S1_ALLOW_V << TEE_REG_LP_MM_HP_I2S1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW_M  (TEE_REG_LP_MM_HP_I2S2_ALLOW_V << TEE_REG_LP_MM_HP_I2S2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW_M  (TEE_REG_LP_MM_HP_PCNT_ALLOW_V << TEE_REG_LP_MM_HP_PCNT_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_HP_UART0_ALLOW_M  (TEE_REG_LP_MM_HP_UART0_ALLOW_V << TEE_REG_LP_MM_HP_UART0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART0_ALLOW_S  10
+/** TEE_REG_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_HP_UART1_ALLOW_M  (TEE_REG_LP_MM_HP_UART1_ALLOW_V << TEE_REG_LP_MM_HP_UART1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART1_ALLOW_S  11
+/** TEE_REG_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_LP_MM_HP_UART2_ALLOW_M  (TEE_REG_LP_MM_HP_UART2_ALLOW_V << TEE_REG_LP_MM_HP_UART2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART2_ALLOW_S  12
+/** TEE_REG_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_LP_MM_HP_UART3_ALLOW_M  (TEE_REG_LP_MM_HP_UART3_ALLOW_V << TEE_REG_LP_MM_HP_UART3_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART3_ALLOW_S  13
+/** TEE_REG_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_LP_MM_HP_UART4_ALLOW_M  (TEE_REG_LP_MM_HP_UART4_ALLOW_V << TEE_REG_LP_MM_HP_UART4_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UART4_ALLOW_S  14
+/** TEE_REG_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_M  (TEE_REG_LP_MM_HP_PARLIO_ALLOW_V << TEE_REG_LP_MM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_M  (TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_M  (TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_M  (TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW_M  (TEE_REG_LP_MM_HP_LEDC_ALLOW_V << TEE_REG_LP_MM_HP_LEDC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_LP_MM_HP_ETM_ALLOW_M  (TEE_REG_LP_MM_HP_ETM_ALLOW_V << TEE_REG_LP_MM_HP_ETM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_ETM_ALLOW_S  21
+/** TEE_REG_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_M  (TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V << TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_M  (TEE_REG_LP_MM_HP_TWAI0_ALLOW_V << TEE_REG_LP_MM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_M  (TEE_REG_LP_MM_HP_TWAI1_ALLOW_V << TEE_REG_LP_MM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_M  (TEE_REG_LP_MM_HP_TWAI2_ALLOW_V << TEE_REG_LP_MM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_M  (TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V << TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_M  (TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_M  (TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V << TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_LP_MM_HP_ADC_ALLOW_M  (TEE_REG_LP_MM_HP_ADC_ALLOW_V << TEE_REG_LP_MM_HP_ADC_ALLOW_S)
+#define TEE_REG_LP_MM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_ADC_ALLOW_S  30
+/** TEE_REG_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW_M  (TEE_REG_LP_MM_HP_UHCI_ALLOW_V << TEE_REG_LP_MM_HP_UHCI_ALLOW_S)
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_UHCI_ALLOW_S  31
+
+/** TEE_LP_MM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x11c)
+/** TEE_REG_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW_M  (TEE_REG_LP_MM_HP_GPIO_ALLOW_V << TEE_REG_LP_MM_HP_GPIO_ALLOW_S)
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_M  (TEE_REG_LP_MM_HP_IOMUX_ALLOW_V << TEE_REG_LP_MM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_M  (TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_M  (TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V << TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_M  (TEE_REG_LP_MM_HP_CLKRST_ALLOW_V << TEE_REG_LP_MM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_S  4
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_reg.h

@@ -0,0 +1,749 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_LP2HP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0)
+/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
+ *  Version control register.
+ */
+#define PMS_LP2HP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_LP2HP_PERI_PMS_DATE_M  (PMS_LP2HP_PERI_PMS_DATE_V << PMS_LP2HP_PERI_PMS_DATE_S)
+#define PMS_LP2HP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_LP2HP_PERI_PMS_DATE_S  0
+
+/** PMS_LP2HP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x4)
+/** PMS_LP2HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating.
+ *  1: Keep the clock always on.
+ */
+#define PMS_LP2HP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_LP2HP_PERI_PMS_CLK_EN_M  (PMS_LP2HP_PERI_PMS_CLK_EN_V << PMS_LP2HP_PERI_PMS_CLK_EN_S)
+#define PMS_LP2HP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_LP2HP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_LP_MM_PMS_REG0_REG register
+ *  Permission control register0 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG0_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x8)
+/** PMS_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_PSRAM_ALLOW    (BIT(0))
+#define PMS_LP_MM_PSRAM_ALLOW_M  (PMS_LP_MM_PSRAM_ALLOW_V << PMS_LP_MM_PSRAM_ALLOW_S)
+#define PMS_LP_MM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_PSRAM_ALLOW_S  0
+/** PMS_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access external
+ *  flash without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_FLASH_ALLOW    (BIT(1))
+#define PMS_LP_MM_FLASH_ALLOW_M  (PMS_LP_MM_FLASH_ALLOW_V << PMS_LP_MM_FLASH_ALLOW_S)
+#define PMS_LP_MM_FLASH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_FLASH_ALLOW_S  1
+/** PMS_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP L2M2M
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_L2MEM_ALLOW    (BIT(2))
+#define PMS_LP_MM_L2MEM_ALLOW_M  (PMS_LP_MM_L2MEM_ALLOW_V << PMS_LP_MM_L2MEM_ALLOW_S)
+#define PMS_LP_MM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_L2MEM_ALLOW_S  2
+/** PMS_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ROM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_L2ROM_ALLOW    (BIT(3))
+#define PMS_LP_MM_L2ROM_ALLOW_M  (PMS_LP_MM_L2ROM_ALLOW_V << PMS_LP_MM_L2ROM_ALLOW_S)
+#define PMS_LP_MM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_L2ROM_ALLOW_S  3
+/** PMS_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_TRACE0_ALLOW    (BIT(6))
+#define PMS_LP_MM_TRACE0_ALLOW_M  (PMS_LP_MM_TRACE0_ALLOW_V << PMS_LP_MM_TRACE0_ALLOW_S)
+#define PMS_LP_MM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_TRACE0_ALLOW_S  6
+/** PMS_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_TRACE1_ALLOW    (BIT(7))
+#define PMS_LP_MM_TRACE1_ALLOW_M  (PMS_LP_MM_TRACE1_ALLOW_V << PMS_LP_MM_TRACE1_ALLOW_S)
+#define PMS_LP_MM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_TRACE1_ALLOW_S  7
+/** PMS_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access CPU bus
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW_M  (PMS_LP_MM_CPU_BUS_MON_ALLOW_V << PMS_LP_MM_CPU_BUS_MON_ALLOW_S)
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_LP_MM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access L2MEM
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_LP_MM_L2MEM_MON_ALLOW_M  (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S)
+#define PMS_LP_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_LP_MM_L2MEM_MON_ALLOW_S  9
+/** PMS_LP_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_LP_MM_SPM_MON_ALLOW_M  (PMS_LP_MM_SPM_MON_ALLOW_V << PMS_LP_MM_SPM_MON_ALLOW_S)
+#define PMS_LP_MM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_LP_MM_SPM_MON_ALLOW_S  10
+/** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_CACHE_ALLOW    (BIT(11))
+#define PMS_LP_MM_CACHE_ALLOW_M  (PMS_LP_MM_CACHE_ALLOW_V << PMS_LP_MM_CACHE_ALLOW_S)
+#define PMS_LP_MM_CACHE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_CACHE_ALLOW_S  11
+
+/** PMS_LP_MM_PMS_REG1_REG register
+ *  Permission control register1 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG1_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x30)
+/** PMS_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  high-speed USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_LP_MM_HP_USBOTG_ALLOW_M  (PMS_LP_MM_HP_USBOTG_ALLOW_V << PMS_LP_MM_HP_USBOTG_ALLOW_S)
+#define PMS_LP_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBOTG_ALLOW_S  0
+/** PMS_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  full-speed USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_LP_MM_HP_USBOTG11_ALLOW_M  (PMS_LP_MM_HP_USBOTG11_ALLOW_V << PMS_LP_MM_HP_USBOTG11_ALLOW_S)
+#define PMS_LP_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBOTG11_ALLOW_S  1
+/** PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  full-speed USB 2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_LP_MM_HP_GDMA_ALLOW_M  (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S)
+#define PMS_LP_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GDMA_ALLOW_S  3
+/** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_LP_MM_HP_SDMMC_ALLOW_M  (PMS_LP_MM_HP_SDMMC_ALLOW_V << PMS_LP_MM_HP_SDMMC_ALLOW_S)
+#define PMS_LP_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_SDMMC_ALLOW_S  5
+/** PMS_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_M  (PMS_LP_MM_HP_AHB_PDMA_ALLOW_V << PMS_LP_MM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_LP_MM_HP_JPEG_ALLOW_M  (PMS_LP_MM_HP_JPEG_ALLOW_V << PMS_LP_MM_HP_JPEG_ALLOW_S)
+#define PMS_LP_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_JPEG_ALLOW_S  7
+/** PMS_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_LP_MM_HP_PPA_ALLOW_M  (PMS_LP_MM_HP_PPA_ALLOW_V << PMS_LP_MM_HP_PPA_ALLOW_S)
+#define PMS_LP_MM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PPA_ALLOW_S  8
+/** PMS_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_LP_MM_HP_DMA2D_ALLOW_M  (PMS_LP_MM_HP_DMA2D_ALLOW_V << PMS_LP_MM_HP_DMA2D_ALLOW_S)
+#define PMS_LP_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_DMA2D_ALLOW_S  9
+/** PMS_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP key
+ *  manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_M  (PMS_LP_MM_HP_KEY_MANAGER_ALLOW_V << PMS_LP_MM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_M  (PMS_LP_MM_HP_AXI_PDMA_ALLOW_V << PMS_LP_MM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP flash
+ *  MSPI controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_LP_MM_HP_FLASH_ALLOW_M  (PMS_LP_MM_HP_FLASH_ALLOW_V << PMS_LP_MM_HP_FLASH_ALLOW_S)
+#define PMS_LP_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_FLASH_ALLOW_S  12
+/** PMS_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PSRAM
+ *  MSPI controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_LP_MM_HP_PSRAM_ALLOW_M  (PMS_LP_MM_HP_PSRAM_ALLOW_V << PMS_LP_MM_HP_PSRAM_ALLOW_S)
+#define PMS_LP_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PSRAM_ALLOW_S  13
+/** PMS_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP CRYPTO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_LP_MM_HP_CRYPTO_ALLOW_M  (PMS_LP_MM_HP_CRYPTO_ALLOW_V << PMS_LP_MM_HP_CRYPTO_ALLOW_S)
+#define PMS_LP_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_CRYPTO_ALLOW_S  14
+/** PMS_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_LP_MM_HP_GMAC_ALLOW_M  (PMS_LP_MM_HP_GMAC_ALLOW_V << PMS_LP_MM_HP_GMAC_ALLOW_S)
+#define PMS_LP_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GMAC_ALLOW_S  15
+/** PMS_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  high-speed USB 2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_LP_MM_HP_USB_PHY_ALLOW_M  (PMS_LP_MM_HP_USB_PHY_ALLOW_V << PMS_LP_MM_HP_USB_PHY_ALLOW_S)
+#define PMS_LP_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USB_PHY_ALLOW_S  16
+/** PMS_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_MM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_LP_MM_HP_PVT_ALLOW_M  (PMS_LP_MM_HP_PVT_ALLOW_V << PMS_LP_MM_HP_PVT_ALLOW_S)
+#define PMS_LP_MM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PVT_ALLOW_S  17
+/** PMS_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW_M  (PMS_LP_MM_HP_CSI_HOST_ALLOW_V << PMS_LP_MM_HP_CSI_HOST_ALLOW_S)
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW_M  (PMS_LP_MM_HP_DSI_HOST_ALLOW_V << PMS_LP_MM_HP_DSI_HOST_ALLOW_S)
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ISP.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_LP_MM_HP_ISP_ALLOW_M  (PMS_LP_MM_HP_ISP_ALLOW_V << PMS_LP_MM_HP_ISP_ALLOW_S)
+#define PMS_LP_MM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_ISP_ALLOW_S  20
+/** PMS_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP H264
+ *  Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_LP_MM_HP_H264_CORE_ALLOW_M  (PMS_LP_MM_HP_H264_CORE_ALLOW_V << PMS_LP_MM_HP_H264_CORE_ALLOW_S)
+#define PMS_LP_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_H264_CORE_ALLOW_S  21
+/** PMS_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_LP_MM_HP_RMT_ALLOW_M  (PMS_LP_MM_HP_RMT_ALLOW_V << PMS_LP_MM_HP_RMT_ALLOW_S)
+#define PMS_LP_MM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_RMT_ALLOW_S  22
+/** PMS_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP bit
+ *  scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_M  (PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW_M  (PMS_LP_MM_HP_AXI_ICM_ALLOW_V << PMS_LP_MM_HP_AXI_ICM_ALLOW_S)
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW_M  (PMS_LP_MM_HP_PERI_PMS_ALLOW_V << PMS_LP_MM_HP_PERI_PMS_ALLOW_S)
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_M  (PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_LP_MM_DMA_PMS_ALLOW_M  (PMS_LP_MM_DMA_PMS_ALLOW_V << PMS_LP_MM_DMA_PMS_ALLOW_S)
+#define PMS_LP_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_DMA_PMS_ALLOW_S  27
+/** PMS_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_M  (PMS_LP_MM_HP_H264_DMA2D_ALLOW_V << PMS_LP_MM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_LP_MM_PMS_REG2_REG register
+ *  Permission control register2 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG2_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0xa4)
+/** PMS_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_LP_MM_HP_MCPWM0_ALLOW_M  (PMS_LP_MM_HP_MCPWM0_ALLOW_V << PMS_LP_MM_HP_MCPWM0_ALLOW_S)
+#define PMS_LP_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_MCPWM0_ALLOW_S  0
+/** PMS_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_LP_MM_HP_MCPWM1_ALLOW_M  (PMS_LP_MM_HP_MCPWM1_ALLOW_V << PMS_LP_MM_HP_MCPWM1_ALLOW_S)
+#define PMS_LP_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_MCPWM1_ALLOW_S  1
+/** PMS_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP timer
+ *  group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_M  (PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP timer
+ *  group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_M  (PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_LP_MM_HP_I2C0_ALLOW_M  (PMS_LP_MM_HP_I2C0_ALLOW_V << PMS_LP_MM_HP_I2C0_ALLOW_S)
+#define PMS_LP_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2C0_ALLOW_S  4
+/** PMS_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_LP_MM_HP_I2C1_ALLOW_M  (PMS_LP_MM_HP_I2C1_ALLOW_V << PMS_LP_MM_HP_I2C1_ALLOW_S)
+#define PMS_LP_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2C1_ALLOW_S  5
+/** PMS_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_LP_MM_HP_I2S0_ALLOW_M  (PMS_LP_MM_HP_I2S0_ALLOW_V << PMS_LP_MM_HP_I2S0_ALLOW_S)
+#define PMS_LP_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2S0_ALLOW_S  6
+/** PMS_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_LP_MM_HP_I2S1_ALLOW_M  (PMS_LP_MM_HP_I2S1_ALLOW_V << PMS_LP_MM_HP_I2S1_ALLOW_S)
+#define PMS_LP_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2S1_ALLOW_S  7
+/** PMS_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_LP_MM_HP_I2S2_ALLOW_M  (PMS_LP_MM_HP_I2S2_ALLOW_V << PMS_LP_MM_HP_I2S2_ALLOW_S)
+#define PMS_LP_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I2S2_ALLOW_S  8
+/** PMS_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_LP_MM_HP_PCNT_ALLOW_M  (PMS_LP_MM_HP_PCNT_ALLOW_V << PMS_LP_MM_HP_PCNT_ALLOW_S)
+#define PMS_LP_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PCNT_ALLOW_S  9
+/** PMS_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_LP_MM_HP_UART0_ALLOW_M  (PMS_LP_MM_HP_UART0_ALLOW_V << PMS_LP_MM_HP_UART0_ALLOW_S)
+#define PMS_LP_MM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART0_ALLOW_S  10
+/** PMS_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_LP_MM_HP_UART1_ALLOW_M  (PMS_LP_MM_HP_UART1_ALLOW_V << PMS_LP_MM_HP_UART1_ALLOW_S)
+#define PMS_LP_MM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART1_ALLOW_S  11
+/** PMS_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_LP_MM_HP_UART2_ALLOW_M  (PMS_LP_MM_HP_UART2_ALLOW_V << PMS_LP_MM_HP_UART2_ALLOW_S)
+#define PMS_LP_MM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART2_ALLOW_S  12
+/** PMS_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_LP_MM_HP_UART3_ALLOW_M  (PMS_LP_MM_HP_UART3_ALLOW_V << PMS_LP_MM_HP_UART3_ALLOW_S)
+#define PMS_LP_MM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART3_ALLOW_S  13
+/** PMS_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_LP_MM_HP_UART4_ALLOW_M  (PMS_LP_MM_HP_UART4_ALLOW_V << PMS_LP_MM_HP_UART4_ALLOW_S)
+#define PMS_LP_MM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UART4_ALLOW_S  14
+/** PMS_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_LP_MM_HP_PARLIO_ALLOW_M  (PMS_LP_MM_HP_PARLIO_ALLOW_V << PMS_LP_MM_HP_PARLIO_ALLOW_S)
+#define PMS_LP_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_PARLIO_ALLOW_S  15
+/** PMS_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_LP_MM_HP_GPSPI2_ALLOW_M  (PMS_LP_MM_HP_GPSPI2_ALLOW_V << PMS_LP_MM_HP_GPSPI2_ALLOW_S)
+#define PMS_LP_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GPSPI2_ALLOW_S  16
+/** PMS_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_LP_MM_HP_GPSPI3_ALLOW_M  (PMS_LP_MM_HP_GPSPI3_ALLOW_V << PMS_LP_MM_HP_GPSPI3_ALLOW_S)
+#define PMS_LP_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GPSPI3_ALLOW_S  17
+/** PMS_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP
+ *  USB/Serial JTAG Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW_M  (PMS_LP_MM_HP_USBDEVICE_ALLOW_V << PMS_LP_MM_HP_USBDEVICE_ALLOW_S)
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_LP_MM_HP_LEDC_ALLOW_M  (PMS_LP_MM_HP_LEDC_ALLOW_V << PMS_LP_MM_HP_LEDC_ALLOW_S)
+#define PMS_LP_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_LEDC_ALLOW_S  19
+/** PMS_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ETM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_LP_MM_HP_ETM_ALLOW_M  (PMS_LP_MM_HP_ETM_ALLOW_V << PMS_LP_MM_HP_ETM_ALLOW_S)
+#define PMS_LP_MM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_ETM_ALLOW_S  21
+/** PMS_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_LP_MM_HP_INTRMTX_ALLOW_M  (PMS_LP_MM_HP_INTRMTX_ALLOW_V << PMS_LP_MM_HP_INTRMTX_ALLOW_S)
+#define PMS_LP_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_INTRMTX_ALLOW_S  22
+/** PMS_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_LP_MM_HP_TWAI0_ALLOW_M  (PMS_LP_MM_HP_TWAI0_ALLOW_V << PMS_LP_MM_HP_TWAI0_ALLOW_S)
+#define PMS_LP_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TWAI0_ALLOW_S  23
+/** PMS_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_LP_MM_HP_TWAI1_ALLOW_M  (PMS_LP_MM_HP_TWAI1_ALLOW_V << PMS_LP_MM_HP_TWAI1_ALLOW_S)
+#define PMS_LP_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TWAI1_ALLOW_S  24
+/** PMS_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_LP_MM_HP_TWAI2_ALLOW_M  (PMS_LP_MM_HP_TWAI2_ALLOW_V << PMS_LP_MM_HP_TWAI2_ALLOW_S)
+#define PMS_LP_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_TWAI2_ALLOW_S  25
+/** PMS_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I3C
+ *  master controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_LP_MM_HP_I3C_MST_ALLOW_M  (PMS_LP_MM_HP_I3C_MST_ALLOW_V << PMS_LP_MM_HP_I3C_MST_ALLOW_S)
+#define PMS_LP_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I3C_MST_ALLOW_S  26
+/** PMS_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW_M  (PMS_LP_MM_HP_I3C_SLV_ALLOW_V << PMS_LP_MM_HP_I3C_SLV_ALLOW_S)
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_LP_MM_HP_LCDCAM_ALLOW_M  (PMS_LP_MM_HP_LCDCAM_ALLOW_V << PMS_LP_MM_HP_LCDCAM_ALLOW_S)
+#define PMS_LP_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_LCDCAM_ALLOW_S  28
+/** PMS_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_LP_MM_HP_ADC_ALLOW_M  (PMS_LP_MM_HP_ADC_ALLOW_V << PMS_LP_MM_HP_ADC_ALLOW_S)
+#define PMS_LP_MM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_ADC_ALLOW_S  30
+/** PMS_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_LP_MM_HP_UHCI_ALLOW_M  (PMS_LP_MM_HP_UHCI_ALLOW_V << PMS_LP_MM_HP_UHCI_ALLOW_S)
+#define PMS_LP_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_UHCI_ALLOW_S  31
+
+/** PMS_LP_MM_PMS_REG3_REG register
+ *  Permission control register3 for the LP CPU in machine mode
+ */
+#define PMS_LP_MM_PMS_REG3_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x11c)
+/** PMS_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP GPIO
+ *  Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_LP_MM_HP_GPIO_ALLOW_M  (PMS_LP_MM_HP_GPIO_ALLOW_V << PMS_LP_MM_HP_GPIO_ALLOW_S)
+#define PMS_LP_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_GPIO_ALLOW_S  0
+/** PMS_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_LP_MM_HP_IOMUX_ALLOW_M  (PMS_LP_MM_HP_IOMUX_ALLOW_V << PMS_LP_MM_HP_IOMUX_ALLOW_S)
+#define PMS_LP_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_IOMUX_ALLOW_S  1
+/** PMS_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP system
+ *  timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW_M  (PMS_LP_MM_HP_SYSTIMER_ALLOW_V << PMS_LP_MM_HP_SYSTIMER_ALLOW_S)
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_LP_MM_HP_SYS_REG_ALLOW_M  (PMS_LP_MM_HP_SYS_REG_ALLOW_V << PMS_LP_MM_HP_SYS_REG_ALLOW_S)
+#define PMS_LP_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_SYS_REG_ALLOW_S  3
+/** PMS_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether the LP CPU in machine mode has permission to access
+ *  HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_LP_MM_HP_CLKRST_ALLOW_M  (PMS_LP_MM_HP_CLKRST_ALLOW_V << PMS_LP_MM_HP_CLKRST_ALLOW_S)
+#define PMS_LP_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP_CLKRST_ALLOW_S  4
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_struct.h

@@ -0,0 +1,414 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE LP2HP PMS DATE REG */
+/** Type of lp2hp_pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_lp2hp_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE LP MM PMS REG0 REG */
+/** Type of lp_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_psram_allow:1;
+        /** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_flash_allow:1;
+        /** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_l2mem_allow:1;
+        /** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_trace0_allow:1;
+        /** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_trace1_allow:1;
+        /** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_cpu_bus_mon_allow:1;
+        /** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_l2mem_mon_allow:1;
+        /** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_tcm_mon_allow:1;
+        /** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE LP MM PMS REG1 REG */
+/** Type of lp_mm_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbotg_allow:1;
+        /** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbotg11_allow:1;
+        /** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1;
+        /** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gdma_allow:1;
+        /** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_regdma_allow:1;
+        /** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_sdmmc_allow:1;
+        /** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_ahb_pdma_allow:1;
+        /** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_jpeg_allow:1;
+        /** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_ppa_allow:1;
+        /** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_dma2d_allow:1;
+        /** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_key_manager_allow:1;
+        /** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_axi_pdma_allow:1;
+        /** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_flash_allow:1;
+        /** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_psram_allow:1;
+        /** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_crypto_allow:1;
+        /** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gmac_allow:1;
+        /** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usb_phy_allow:1;
+        /** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_pvt_allow:1;
+        /** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_csi_host_allow:1;
+        /** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_dsi_host_allow:1;
+        /** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_isp_allow:1;
+        /** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_h264_core_allow:1;
+        /** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_rmt_allow:1;
+        /** reg_lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_bitsrambler_allow:1;
+        /** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_axi_icm_allow:1;
+        /** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_peri_pms_allow:1;
+        /** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1;
+        /** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_dma_pms_allow:1;
+        /** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_h264_dma2d_allow:1;
+        /** reg_lp_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg1_reg_t;
+
+
+/** Group: TEE LP MM PMS REG2 REG */
+/** Type of lp_mm_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_mcpwm0_allow:1;
+        /** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_mcpwm1_allow:1;
+        /** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_timer_group0_allow:1;
+        /** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_timer_group1_allow:1;
+        /** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2c0_allow:1;
+        /** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2c1_allow:1;
+        /** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2s0_allow:1;
+        /** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2s1_allow:1;
+        /** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i2s2_allow:1;
+        /** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_pcnt_allow:1;
+        /** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart0_allow:1;
+        /** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart1_allow:1;
+        /** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart2_allow:1;
+        /** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart3_allow:1;
+        /** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uart4_allow:1;
+        /** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_parlio_allow:1;
+        /** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gpspi2_allow:1;
+        /** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gpspi3_allow:1;
+        /** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_usbdevice_allow:1;
+        /** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_etm_allow:1;
+        /** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_intrmtx_allow:1;
+        /** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_twai0_allow:1;
+        /** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_twai1_allow:1;
+        /** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_twai2_allow:1;
+        /** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i3c_mst_allow:1;
+        /** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_i3c_slv_allow:1;
+        /** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_adc_allow:1;
+        /** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg2_reg_t;
+
+
+/** Group: TEE LP MM PMS REG3 REG */
+/** Type of lp_mm_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_gpio_allow:1;
+        /** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_iomux_allow:1;
+        /** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_systimer_allow:1;
+        /** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_sys_reg_allow:1;
+        /** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg3_reg_t;
+
+
+typedef struct {
+    volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
+    uint32_t reserved_00c[9];
+    volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
+    uint32_t reserved_034[28];
+    volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
+    uint32_t reserved_0a8[29];
+    volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
+} tee_dev_t;
+
+extern tee_dev_t LP2HP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_adc_reg.h

@@ -0,0 +1,704 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTCADC_READER1_CTRL_REG register
+ *  Control the read operation of ADC1.
+ */
+#define RTCADC_READER1_CTRL_REG (DR_REG_RTCADC_BASE + 0x0)
+/** RTCADC_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
+ *  Clock divider.
+ */
+#define RTCADC_SAR1_CLK_DIV    0x000000FFU
+#define RTCADC_SAR1_CLK_DIV_M  (RTCADC_SAR1_CLK_DIV_V << RTCADC_SAR1_CLK_DIV_S)
+#define RTCADC_SAR1_CLK_DIV_V  0x000000FFU
+#define RTCADC_SAR1_CLK_DIV_S  0
+/** RTCADC_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0;
+ *  Invert SAR ADC1 data.
+ */
+#define RTCADC_SAR1_DATA_INV    (BIT(28))
+#define RTCADC_SAR1_DATA_INV_M  (RTCADC_SAR1_DATA_INV_V << RTCADC_SAR1_DATA_INV_S)
+#define RTCADC_SAR1_DATA_INV_V  0x00000001U
+#define RTCADC_SAR1_DATA_INV_S  28
+/** RTCADC_SAR1_INT_EN : R/W; bitpos: [29]; default: 1;
+ *  Enable saradc1 to send out interrupt.
+ */
+#define RTCADC_SAR1_INT_EN    (BIT(29))
+#define RTCADC_SAR1_INT_EN_M  (RTCADC_SAR1_INT_EN_V << RTCADC_SAR1_INT_EN_S)
+#define RTCADC_SAR1_INT_EN_V  0x00000001U
+#define RTCADC_SAR1_INT_EN_S  29
+/** RTCADC_SAR1_EN_PAD_FORCE_ENABLE : R/W; bitpos: [31:30]; default: 0;
+ *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+ */
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE    0x00000003U
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_M  (RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S)
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V  0x00000003U
+#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S  30
+
+/** RTCADC_MEAS1_CTRL2_REG register
+ *  ADC1 configuration registers.
+ */
+#define RTCADC_MEAS1_CTRL2_REG (DR_REG_RTCADC_BASE + 0xc)
+/** RTCADC_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0;
+ *  SAR ADC1 data.
+ */
+#define RTCADC_MEAS1_DATA_SAR    0x0000FFFFU
+#define RTCADC_MEAS1_DATA_SAR_M  (RTCADC_MEAS1_DATA_SAR_V << RTCADC_MEAS1_DATA_SAR_S)
+#define RTCADC_MEAS1_DATA_SAR_V  0x0000FFFFU
+#define RTCADC_MEAS1_DATA_SAR_S  0
+/** RTCADC_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0;
+ *  SAR ADC1 conversion done indication.
+ */
+#define RTCADC_MEAS1_DONE_SAR    (BIT(16))
+#define RTCADC_MEAS1_DONE_SAR_M  (RTCADC_MEAS1_DONE_SAR_V << RTCADC_MEAS1_DONE_SAR_S)
+#define RTCADC_MEAS1_DONE_SAR_V  0x00000001U
+#define RTCADC_MEAS1_DONE_SAR_S  16
+/** RTCADC_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0;
+ *  SAR ADC1 controller (in RTC) starts conversion.
+ */
+#define RTCADC_MEAS1_START_SAR    (BIT(17))
+#define RTCADC_MEAS1_START_SAR_M  (RTCADC_MEAS1_START_SAR_V << RTCADC_MEAS1_START_SAR_S)
+#define RTCADC_MEAS1_START_SAR_V  0x00000001U
+#define RTCADC_MEAS1_START_SAR_S  17
+/** RTCADC_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0;
+ *  1: SAR ADC1 controller (in RTC) is started by SW.
+ */
+#define RTCADC_MEAS1_START_FORCE    (BIT(18))
+#define RTCADC_MEAS1_START_FORCE_M  (RTCADC_MEAS1_START_FORCE_V << RTCADC_MEAS1_START_FORCE_S)
+#define RTCADC_MEAS1_START_FORCE_V  0x00000001U
+#define RTCADC_MEAS1_START_FORCE_S  18
+/** RTCADC_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0;
+ *  SAR ADC1 pad enable bitmap.
+ */
+#define RTCADC_SAR1_EN_PAD    0x00000FFFU
+#define RTCADC_SAR1_EN_PAD_M  (RTCADC_SAR1_EN_PAD_V << RTCADC_SAR1_EN_PAD_S)
+#define RTCADC_SAR1_EN_PAD_V  0x00000FFFU
+#define RTCADC_SAR1_EN_PAD_S  19
+/** RTCADC_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC1 pad enable bitmap is controlled by SW.
+ */
+#define RTCADC_SAR1_EN_PAD_FORCE    (BIT(31))
+#define RTCADC_SAR1_EN_PAD_FORCE_M  (RTCADC_SAR1_EN_PAD_FORCE_V << RTCADC_SAR1_EN_PAD_FORCE_S)
+#define RTCADC_SAR1_EN_PAD_FORCE_V  0x00000001U
+#define RTCADC_SAR1_EN_PAD_FORCE_S  31
+
+/** RTCADC_MEAS1_MUX_REG register
+ *  SAR ADC1 MUX register.
+ */
+#define RTCADC_MEAS1_MUX_REG (DR_REG_RTCADC_BASE + 0x10)
+/** RTCADC_SAR1_DIG_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC1 controlled by DIG ADC1 CTRL.
+ */
+#define RTCADC_SAR1_DIG_FORCE    (BIT(31))
+#define RTCADC_SAR1_DIG_FORCE_M  (RTCADC_SAR1_DIG_FORCE_V << RTCADC_SAR1_DIG_FORCE_S)
+#define RTCADC_SAR1_DIG_FORCE_V  0x00000001U
+#define RTCADC_SAR1_DIG_FORCE_S  31
+
+/** RTCADC_ATTEN1_REG register
+ *  ADC1 attenuation registers.
+ */
+#define RTCADC_ATTEN1_REG (DR_REG_RTCADC_BASE + 0x14)
+/** RTCADC_SAR1_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  2-bit attenuation for each pad.
+ */
+#define RTCADC_SAR1_ATTEN    0xFFFFFFFFU
+#define RTCADC_SAR1_ATTEN_M  (RTCADC_SAR1_ATTEN_V << RTCADC_SAR1_ATTEN_S)
+#define RTCADC_SAR1_ATTEN_V  0xFFFFFFFFU
+#define RTCADC_SAR1_ATTEN_S  0
+
+/** RTCADC_READER2_CTRL_REG register
+ *  Control the read operation of ADC2.
+ */
+#define RTCADC_READER2_CTRL_REG (DR_REG_RTCADC_BASE + 0x24)
+/** RTCADC_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
+ *  Clock divider.
+ */
+#define RTCADC_SAR2_CLK_DIV    0x000000FFU
+#define RTCADC_SAR2_CLK_DIV_M  (RTCADC_SAR2_CLK_DIV_V << RTCADC_SAR2_CLK_DIV_S)
+#define RTCADC_SAR2_CLK_DIV_V  0x000000FFU
+#define RTCADC_SAR2_CLK_DIV_S  0
+/** RTCADC_SAR2_WAIT_ARB_CYCLE : R/W; bitpos: [17:16]; default: 1;
+ *  Wait arbit stable after sar_done.
+ */
+#define RTCADC_SAR2_WAIT_ARB_CYCLE    0x00000003U
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_M  (RTCADC_SAR2_WAIT_ARB_CYCLE_V << RTCADC_SAR2_WAIT_ARB_CYCLE_S)
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_V  0x00000003U
+#define RTCADC_SAR2_WAIT_ARB_CYCLE_S  16
+/** RTCADC_SAR2_EN_PAD_FORCE_ENABLE : R/W; bitpos: [28:27]; default: 0;
+ *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+ */
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE    0x00000003U
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_M  (RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S)
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V  0x00000003U
+#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S  27
+/** RTCADC_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0;
+ *  Invert SAR ADC2 data.
+ */
+#define RTCADC_SAR2_DATA_INV    (BIT(29))
+#define RTCADC_SAR2_DATA_INV_M  (RTCADC_SAR2_DATA_INV_V << RTCADC_SAR2_DATA_INV_S)
+#define RTCADC_SAR2_DATA_INV_V  0x00000001U
+#define RTCADC_SAR2_DATA_INV_S  29
+/** RTCADC_SAR2_INT_EN : R/W; bitpos: [30]; default: 1;
+ *  Enable saradc2 to send out interrupt.
+ */
+#define RTCADC_SAR2_INT_EN    (BIT(30))
+#define RTCADC_SAR2_INT_EN_M  (RTCADC_SAR2_INT_EN_V << RTCADC_SAR2_INT_EN_S)
+#define RTCADC_SAR2_INT_EN_V  0x00000001U
+#define RTCADC_SAR2_INT_EN_S  30
+
+/** RTCADC_MEAS2_CTRL1_REG register
+ *  ADC2 configuration registers.
+ */
+#define RTCADC_MEAS2_CTRL1_REG (DR_REG_RTCADC_BASE + 0x2c)
+/** RTCADC_SAR2_CNTL_STATE : RO; bitpos: [2:0]; default: 0;
+ *  saradc2_cntl_fsm.
+ */
+#define RTCADC_SAR2_CNTL_STATE    0x00000007U
+#define RTCADC_SAR2_CNTL_STATE_M  (RTCADC_SAR2_CNTL_STATE_V << RTCADC_SAR2_CNTL_STATE_S)
+#define RTCADC_SAR2_CNTL_STATE_V  0x00000007U
+#define RTCADC_SAR2_CNTL_STATE_S  0
+/** RTCADC_SAR2_PWDET_CAL_EN : R/W; bitpos: [3]; default: 0;
+ *  RTC control pwdet enable.
+ */
+#define RTCADC_SAR2_PWDET_CAL_EN    (BIT(3))
+#define RTCADC_SAR2_PWDET_CAL_EN_M  (RTCADC_SAR2_PWDET_CAL_EN_V << RTCADC_SAR2_PWDET_CAL_EN_S)
+#define RTCADC_SAR2_PWDET_CAL_EN_V  0x00000001U
+#define RTCADC_SAR2_PWDET_CAL_EN_S  3
+/** RTCADC_SAR2_PKDET_CAL_EN : R/W; bitpos: [4]; default: 0;
+ *  RTC control pkdet enable.
+ */
+#define RTCADC_SAR2_PKDET_CAL_EN    (BIT(4))
+#define RTCADC_SAR2_PKDET_CAL_EN_M  (RTCADC_SAR2_PKDET_CAL_EN_V << RTCADC_SAR2_PKDET_CAL_EN_S)
+#define RTCADC_SAR2_PKDET_CAL_EN_V  0x00000001U
+#define RTCADC_SAR2_PKDET_CAL_EN_S  4
+/** RTCADC_SAR2_EN_TEST : R/W; bitpos: [5]; default: 0;
+ *  SAR2_EN_TEST.
+ */
+#define RTCADC_SAR2_EN_TEST    (BIT(5))
+#define RTCADC_SAR2_EN_TEST_M  (RTCADC_SAR2_EN_TEST_V << RTCADC_SAR2_EN_TEST_S)
+#define RTCADC_SAR2_EN_TEST_V  0x00000001U
+#define RTCADC_SAR2_EN_TEST_S  5
+
+/** RTCADC_MEAS2_CTRL2_REG register
+ *  ADC2 configuration registers.
+ */
+#define RTCADC_MEAS2_CTRL2_REG (DR_REG_RTCADC_BASE + 0x30)
+/** RTCADC_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0;
+ *  SAR ADC2 data.
+ */
+#define RTCADC_MEAS2_DATA_SAR    0x0000FFFFU
+#define RTCADC_MEAS2_DATA_SAR_M  (RTCADC_MEAS2_DATA_SAR_V << RTCADC_MEAS2_DATA_SAR_S)
+#define RTCADC_MEAS2_DATA_SAR_V  0x0000FFFFU
+#define RTCADC_MEAS2_DATA_SAR_S  0
+/** RTCADC_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0;
+ *  SAR ADC2 conversion done indication.
+ */
+#define RTCADC_MEAS2_DONE_SAR    (BIT(16))
+#define RTCADC_MEAS2_DONE_SAR_M  (RTCADC_MEAS2_DONE_SAR_V << RTCADC_MEAS2_DONE_SAR_S)
+#define RTCADC_MEAS2_DONE_SAR_V  0x00000001U
+#define RTCADC_MEAS2_DONE_SAR_S  16
+/** RTCADC_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0;
+ *  SAR ADC2 controller (in RTC) starts conversion.
+ */
+#define RTCADC_MEAS2_START_SAR    (BIT(17))
+#define RTCADC_MEAS2_START_SAR_M  (RTCADC_MEAS2_START_SAR_V << RTCADC_MEAS2_START_SAR_S)
+#define RTCADC_MEAS2_START_SAR_V  0x00000001U
+#define RTCADC_MEAS2_START_SAR_S  17
+/** RTCADC_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0;
+ *  1: SAR ADC2 controller (in RTC) is started by SW.
+ */
+#define RTCADC_MEAS2_START_FORCE    (BIT(18))
+#define RTCADC_MEAS2_START_FORCE_M  (RTCADC_MEAS2_START_FORCE_V << RTCADC_MEAS2_START_FORCE_S)
+#define RTCADC_MEAS2_START_FORCE_V  0x00000001U
+#define RTCADC_MEAS2_START_FORCE_S  18
+/** RTCADC_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0;
+ *  SAR ADC2 pad enable bitmap.
+ */
+#define RTCADC_SAR2_EN_PAD    0x00000FFFU
+#define RTCADC_SAR2_EN_PAD_M  (RTCADC_SAR2_EN_PAD_V << RTCADC_SAR2_EN_PAD_S)
+#define RTCADC_SAR2_EN_PAD_V  0x00000FFFU
+#define RTCADC_SAR2_EN_PAD_S  19
+/** RTCADC_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0;
+ *  1: SAR ADC2 pad enable bitmap is controlled by SW.
+ */
+#define RTCADC_SAR2_EN_PAD_FORCE    (BIT(31))
+#define RTCADC_SAR2_EN_PAD_FORCE_M  (RTCADC_SAR2_EN_PAD_FORCE_V << RTCADC_SAR2_EN_PAD_FORCE_S)
+#define RTCADC_SAR2_EN_PAD_FORCE_V  0x00000001U
+#define RTCADC_SAR2_EN_PAD_FORCE_S  31
+
+/** RTCADC_MEAS2_MUX_REG register
+ *  SAR ADC2 MUX register.
+ */
+#define RTCADC_MEAS2_MUX_REG (DR_REG_RTCADC_BASE + 0x34)
+/** RTCADC_SAR2_PWDET_CCT : R/W; bitpos: [30:28]; default: 0;
+ *  SAR2_PWDET_CCT.
+ */
+#define RTCADC_SAR2_PWDET_CCT    0x00000007U
+#define RTCADC_SAR2_PWDET_CCT_M  (RTCADC_SAR2_PWDET_CCT_V << RTCADC_SAR2_PWDET_CCT_S)
+#define RTCADC_SAR2_PWDET_CCT_V  0x00000007U
+#define RTCADC_SAR2_PWDET_CCT_S  28
+/** RTCADC_SAR2_RTC_FORCE : R/W; bitpos: [31]; default: 0;
+ *  In sleep, force to use rtc to control ADC.
+ */
+#define RTCADC_SAR2_RTC_FORCE    (BIT(31))
+#define RTCADC_SAR2_RTC_FORCE_M  (RTCADC_SAR2_RTC_FORCE_V << RTCADC_SAR2_RTC_FORCE_S)
+#define RTCADC_SAR2_RTC_FORCE_V  0x00000001U
+#define RTCADC_SAR2_RTC_FORCE_S  31
+
+/** RTCADC_ATTEN2_REG register
+ *  ADC1 attenuation registers.
+ */
+#define RTCADC_ATTEN2_REG (DR_REG_RTCADC_BASE + 0x38)
+/** RTCADC_SAR2_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  2-bit attenuation for each pad.
+ */
+#define RTCADC_SAR2_ATTEN    0xFFFFFFFFU
+#define RTCADC_SAR2_ATTEN_M  (RTCADC_SAR2_ATTEN_V << RTCADC_SAR2_ATTEN_S)
+#define RTCADC_SAR2_ATTEN_V  0xFFFFFFFFU
+#define RTCADC_SAR2_ATTEN_S  0
+
+/** RTCADC_FORCE_WPD_SAR_REG register
+ *  In sleep, force to use rtc to control ADC
+ */
+#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_RTCADC_BASE + 0x3c)
+/** RTCADC_FORCE_XPD_SAR1 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+ *  control.
+ */
+#define RTCADC_FORCE_XPD_SAR1    0x00000003U
+#define RTCADC_FORCE_XPD_SAR1_M  (RTCADC_FORCE_XPD_SAR1_V << RTCADC_FORCE_XPD_SAR1_S)
+#define RTCADC_FORCE_XPD_SAR1_V  0x00000003U
+#define RTCADC_FORCE_XPD_SAR1_S  0
+/** RTCADC_FORCE_XPD_SAR2 : R/W; bitpos: [3:2]; default: 0;
+ *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+ *  control.
+ */
+#define RTCADC_FORCE_XPD_SAR2    0x00000003U
+#define RTCADC_FORCE_XPD_SAR2_M  (RTCADC_FORCE_XPD_SAR2_V << RTCADC_FORCE_XPD_SAR2_S)
+#define RTCADC_FORCE_XPD_SAR2_V  0x00000003U
+#define RTCADC_FORCE_XPD_SAR2_S  2
+
+/** RTCADC_COCPU_INT_RAW_REG register
+ *  Interrupt raw registers.
+ */
+#define RTCADC_COCPU_INT_RAW_REG (DR_REG_RTCADC_BASE + 0x48)
+/** RTCADC_COCPU_SARADC1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_INT_RAW    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_RAW_M  (RTCADC_COCPU_SARADC1_INT_RAW_V << RTCADC_COCPU_SARADC1_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_RAW_S  0
+/** RTCADC_COCPU_SARADC2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_INT_RAW    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_RAW_M  (RTCADC_COCPU_SARADC2_INT_RAW_V << RTCADC_COCPU_SARADC2_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_RAW_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_M  (RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_M  (RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int raw.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_M  (RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int raw.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_M  (RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S  5
+
+/** RTCADC_INT_ENA_REG register
+ *  Interrupt enable registers.
+ */
+#define RTCADC_INT_ENA_REG (DR_REG_RTCADC_BASE + 0x4c)
+/** RTCADC_COCPU_SARADC1_INT_ENA : R/WTC; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_M  (RTCADC_COCPU_SARADC1_INT_ENA_V << RTCADC_COCPU_SARADC1_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA : R/WTC; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_M  (RTCADC_COCPU_SARADC2_INT_ENA_V << RTCADC_COCPU_SARADC2_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA : R/WTC; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA : R/WTC; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA : R/WTC; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA : R/WTC; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S  5
+
+/** RTCADC_INT_ST_REG register
+ *  Interrupt status registers.
+ */
+#define RTCADC_INT_ST_REG (DR_REG_RTCADC_BASE + 0x50)
+/** RTCADC_COCPU_SARADC1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int status.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ST    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ST_M  (RTCADC_COCPU_SARADC1_INT_ST_V << RTCADC_COCPU_SARADC1_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ST_S  0
+/** RTCADC_COCPU_SARADC2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int status.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ST    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ST_M  (RTCADC_COCPU_SARADC2_INT_ST_V << RTCADC_COCPU_SARADC2_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ST_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int status.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ST_V << RTCADC_COCPU_SARADC1_ERROR_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int status.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ST_V << RTCADC_COCPU_SARADC2_ERROR_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int status.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ST_V << RTCADC_COCPU_SARADC1_WAKE_INT_ST_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int status.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ST_V << RTCADC_COCPU_SARADC2_WAKE_INT_ST_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_S  5
+
+/** RTCADC_INT_CLR_REG register
+ *  Interrupt clear registers.
+ */
+#define RTCADC_INT_CLR_REG (DR_REG_RTCADC_BASE + 0x54)
+/** RTCADC_COCPU_SARADC1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_INT_CLR    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_CLR_M  (RTCADC_COCPU_SARADC1_INT_CLR_V << RTCADC_COCPU_SARADC1_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_CLR_S  0
+/** RTCADC_COCPU_SARADC2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_INT_CLR    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_CLR_M  (RTCADC_COCPU_SARADC2_INT_CLR_V << RTCADC_COCPU_SARADC2_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_CLR_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_M  (RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_M  (RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, int clear.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_M  (RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, int clear.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_M  (RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S  5
+
+/** RTCADC_INT_ENA_W1TS_REG register
+ *  Interrupt enable assert registers.
+ */
+#define RTCADC_INT_ENA_W1TS_REG (DR_REG_RTCADC_BASE + 0x58)
+/** RTCADC_COCPU_SARADC1_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA_W1TS : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, write 1 to assert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S  5
+
+/** RTCADC_INT_ENA_W1TC_REG register
+ *  Interrupt enable deassert registers.
+ */
+#define RTCADC_INT_ENA_W1TC_REG (DR_REG_RTCADC_BASE + 0x5c)
+/** RTCADC_COCPU_SARADC1_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
+ *  ADC1 Conversion is done, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC    (BIT(0))
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S  0
+/** RTCADC_COCPU_SARADC2_INT_ENA_W1TC : WT; bitpos: [1]; default: 0;
+ *  ADC2 Conversion is done, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC    (BIT(1))
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S  1
+/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC : WT; bitpos: [2]; default: 0;
+ *  An error occurs from ADC1, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC    (BIT(2))
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S  2
+/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC : WT; bitpos: [3]; default: 0;
+ *  An error occurs from ADC2, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC    (BIT(3))
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S  3
+/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC : WT; bitpos: [4]; default: 0;
+ *  A wakeup event is triggered from ADC1, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC    (BIT(4))
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S  4
+/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC : WT; bitpos: [5]; default: 0;
+ *  A wakeup event is triggered from ADC2, write 1 to deassert int enable.
+ */
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC    (BIT(5))
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_M  (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S)
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S  5
+
+/** RTCADC_WAKEUP1_REG register
+ *  ADC1 wakeup configuration registers.
+ */
+#define RTCADC_WAKEUP1_REG (DR_REG_RTCADC_BASE + 0x60)
+/** RTCADC_SAR1_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
+ *  Lower threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_TH_LOW    0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_LOW_M  (RTCADC_SAR1_WAKEUP_TH_LOW_V << RTCADC_SAR1_WAKEUP_TH_LOW_S)
+#define RTCADC_SAR1_WAKEUP_TH_LOW_V  0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_LOW_S  0
+/** RTCADC_SAR1_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
+ *  Upper threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_TH_HIGH    0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_M  (RTCADC_SAR1_WAKEUP_TH_HIGH_V << RTCADC_SAR1_WAKEUP_TH_HIGH_S)
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_V  0x00000FFFU
+#define RTCADC_SAR1_WAKEUP_TH_HIGH_S  14
+/** RTCADC_SAR1_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_M  (RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S)
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S  29
+/** RTCADC_SAR1_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Wakeup function enable.
+ */
+#define RTCADC_SAR1_WAKEUP_EN    (BIT(30))
+#define RTCADC_SAR1_WAKEUP_EN_M  (RTCADC_SAR1_WAKEUP_EN_V << RTCADC_SAR1_WAKEUP_EN_S)
+#define RTCADC_SAR1_WAKEUP_EN_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_EN_S  30
+/** RTCADC_SAR1_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define RTCADC_SAR1_WAKEUP_MODE    (BIT(31))
+#define RTCADC_SAR1_WAKEUP_MODE_M  (RTCADC_SAR1_WAKEUP_MODE_V << RTCADC_SAR1_WAKEUP_MODE_S)
+#define RTCADC_SAR1_WAKEUP_MODE_V  0x00000001U
+#define RTCADC_SAR1_WAKEUP_MODE_S  31
+
+/** RTCADC_WAKEUP2_REG register
+ *  ADC2 wakeup configuration registers.
+ */
+#define RTCADC_WAKEUP2_REG (DR_REG_RTCADC_BASE + 0x64)
+/** RTCADC_SAR2_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
+ *  Lower threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_TH_LOW    0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_LOW_M  (RTCADC_SAR2_WAKEUP_TH_LOW_V << RTCADC_SAR2_WAKEUP_TH_LOW_S)
+#define RTCADC_SAR2_WAKEUP_TH_LOW_V  0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_LOW_S  0
+/** RTCADC_SAR2_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095;
+ *  Upper threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_TH_HIGH    0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_M  (RTCADC_SAR2_WAKEUP_TH_HIGH_V << RTCADC_SAR2_WAKEUP_TH_HIGH_S)
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_V  0x00000FFFU
+#define RTCADC_SAR2_WAKEUP_TH_HIGH_S  14
+/** RTCADC_SAR2_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_M  (RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S)
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S  29
+/** RTCADC_SAR2_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Wakeup function enable.
+ */
+#define RTCADC_SAR2_WAKEUP_EN    (BIT(30))
+#define RTCADC_SAR2_WAKEUP_EN_M  (RTCADC_SAR2_WAKEUP_EN_V << RTCADC_SAR2_WAKEUP_EN_S)
+#define RTCADC_SAR2_WAKEUP_EN_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_EN_S  30
+/** RTCADC_SAR2_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define RTCADC_SAR2_WAKEUP_MODE    (BIT(31))
+#define RTCADC_SAR2_WAKEUP_MODE_M  (RTCADC_SAR2_WAKEUP_MODE_V << RTCADC_SAR2_WAKEUP_MODE_S)
+#define RTCADC_SAR2_WAKEUP_MODE_V  0x00000001U
+#define RTCADC_SAR2_WAKEUP_MODE_S  31
+
+/** RTCADC_WAKEUP_SEL_REG register
+ *  Wakeup source select register.
+ */
+#define RTCADC_WAKEUP_SEL_REG (DR_REG_RTCADC_BASE + 0x68)
+/** RTCADC_SAR_WAKEUP_SEL : R/W; bitpos: [0]; default: 0;
+ *  0: ADC1. 1: ADC2.
+ */
+#define RTCADC_SAR_WAKEUP_SEL    (BIT(0))
+#define RTCADC_SAR_WAKEUP_SEL_M  (RTCADC_SAR_WAKEUP_SEL_V << RTCADC_SAR_WAKEUP_SEL_S)
+#define RTCADC_SAR_WAKEUP_SEL_V  0x00000001U
+#define RTCADC_SAR_WAKEUP_SEL_S  0
+
+/** RTCADC_SAR1_HW_WAKEUP_REG register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x6c)
+/** RTCADC_ADC1_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
+ *  Enable hardware automatic sampling.
+ */
+#define RTCADC_ADC1_HW_READ_EN_I    (BIT(0))
+#define RTCADC_ADC1_HW_READ_EN_I_M  (RTCADC_ADC1_HW_READ_EN_I_V << RTCADC_ADC1_HW_READ_EN_I_S)
+#define RTCADC_ADC1_HW_READ_EN_I_V  0x00000001U
+#define RTCADC_ADC1_HW_READ_EN_I_S  0
+/** RTCADC_ADC1_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
+ *  Hardware automatic sampling rate.
+ */
+#define RTCADC_ADC1_HW_READ_RATE_I    0x0000FFFFU
+#define RTCADC_ADC1_HW_READ_RATE_I_M  (RTCADC_ADC1_HW_READ_RATE_I_V << RTCADC_ADC1_HW_READ_RATE_I_S)
+#define RTCADC_ADC1_HW_READ_RATE_I_V  0x0000FFFFU
+#define RTCADC_ADC1_HW_READ_RATE_I_S  1
+
+/** RTCADC_SAR2_HW_WAKEUP_REG register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x70)
+/** RTCADC_ADC2_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
+ *  Enable hardware automatic sampling.
+ */
+#define RTCADC_ADC2_HW_READ_EN_I    (BIT(0))
+#define RTCADC_ADC2_HW_READ_EN_I_M  (RTCADC_ADC2_HW_READ_EN_I_V << RTCADC_ADC2_HW_READ_EN_I_S)
+#define RTCADC_ADC2_HW_READ_EN_I_V  0x00000001U
+#define RTCADC_ADC2_HW_READ_EN_I_S  0
+/** RTCADC_ADC2_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100;
+ *  Hardware automatic sampling rate.
+ */
+#define RTCADC_ADC2_HW_READ_RATE_I    0x0000FFFFU
+#define RTCADC_ADC2_HW_READ_RATE_I_M  (RTCADC_ADC2_HW_READ_RATE_I_V << RTCADC_ADC2_HW_READ_RATE_I_S)
+#define RTCADC_ADC2_HW_READ_RATE_I_V  0x0000FFFFU
+#define RTCADC_ADC2_HW_READ_RATE_I_S  1
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_adc_struct.h

@@ -0,0 +1,603 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ADC1 control registers. */
+/** Type of reader1_ctrl register
+ *  Control the read operation of ADC1.
+ */
+typedef union {
+    struct {
+        /** sar1_clk_div : R/W; bitpos: [7:0]; default: 2;
+         *  Clock divider.
+         */
+        uint32_t sar1_clk_div:8;
+        uint32_t reserved_8:20;
+        /** sar1_data_inv : R/W; bitpos: [28]; default: 0;
+         *  Invert SAR ADC1 data.
+         */
+        uint32_t sar1_data_inv:1;
+        /** sar1_int_en : R/W; bitpos: [29]; default: 1;
+         *  Enable saradc1 to send out interrupt.
+         */
+        uint32_t sar1_int_en:1;
+        /** sar1_en_pad_force_enable : R/W; bitpos: [31:30]; default: 0;
+         *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+         */
+        uint32_t sar1_en_pad_force_enable:2;
+    };
+    uint32_t val;
+} rtcadc_reader1_ctrl_reg_t;
+
+/** Type of meas1_ctrl2 register
+ *  ADC1 configuration registers.
+ */
+typedef union {
+    struct {
+        /** meas1_data_sar : RO; bitpos: [15:0]; default: 0;
+         *  SAR ADC1 data.
+         */
+        uint32_t meas1_data_sar:16;
+        /** meas1_done_sar : RO; bitpos: [16]; default: 0;
+         *  SAR ADC1 conversion done indication.
+         */
+        uint32_t meas1_done_sar:1;
+        /** meas1_start_sar : R/W; bitpos: [17]; default: 0;
+         *  SAR ADC1 controller (in RTC) starts conversion.
+         */
+        uint32_t meas1_start_sar:1;
+        /** meas1_start_force : R/W; bitpos: [18]; default: 0;
+         *  1: SAR ADC1 controller (in RTC) is started by SW.
+         */
+        uint32_t meas1_start_force:1;
+        /** sar1_en_pad : R/W; bitpos: [30:19]; default: 0;
+         *  SAR ADC1 pad enable bitmap.
+         */
+        uint32_t sar1_en_pad:12;
+        /** sar1_en_pad_force : R/W; bitpos: [31]; default: 0;
+         *  1: SAR ADC1 pad enable bitmap is controlled by SW.
+         */
+        uint32_t sar1_en_pad_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas1_ctrl2_reg_t;
+
+/** Type of meas1_mux register
+ *  SAR ADC1 MUX register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** sar1_dig_force : R/W; bitpos: [31]; default: 0;
+         *  1: SAR ADC1 controlled by DIG ADC1 CTRL.
+         */
+        uint32_t sar1_dig_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas1_mux_reg_t;
+
+/** Type of atten1 register
+ *  ADC1 attenuation registers.
+ */
+typedef union {
+    struct {
+        /** sar1_atten : R/W; bitpos: [31:0]; default: 4294967295;
+         *  2-bit attenuation for each pad.
+         */
+        uint32_t sar1_atten:32;
+    };
+    uint32_t val;
+} rtcadc_atten1_reg_t;
+
+
+/** Group: ADC2 control registers. */
+/** Type of reader2_ctrl register
+ *  Control the read operation of ADC2.
+ */
+typedef union {
+    struct {
+        /** sar2_clk_div : R/W; bitpos: [7:0]; default: 2;
+         *  Clock divider.
+         */
+        uint32_t sar2_clk_div:8;
+        uint32_t reserved_8:8;
+        /** sar2_wait_arb_cycle : R/W; bitpos: [17:16]; default: 1;
+         *  Wait arbit stable after sar_done.
+         */
+        uint32_t sar2_wait_arb_cycle:2;
+        uint32_t reserved_18:9;
+        /** sar2_en_pad_force_enable : R/W; bitpos: [28:27]; default: 0;
+         *  Force enable adc en_pad to analog circuit 2'b11: force enable .
+         */
+        uint32_t sar2_en_pad_force_enable:2;
+        /** sar2_data_inv : R/W; bitpos: [29]; default: 0;
+         *  Invert SAR ADC2 data.
+         */
+        uint32_t sar2_data_inv:1;
+        /** sar2_int_en : R/W; bitpos: [30]; default: 1;
+         *  Enable saradc2 to send out interrupt.
+         */
+        uint32_t sar2_int_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} rtcadc_reader2_ctrl_reg_t;
+
+/** Type of meas2_ctrl1 register
+ *  ADC2 configuration registers.
+ */
+typedef union {
+    struct {
+        /** sar2_cntl_state : RO; bitpos: [2:0]; default: 0;
+         *  saradc2_cntl_fsm.
+         */
+        uint32_t sar2_cntl_state:3;
+        /** sar2_pwdet_cal_en : R/W; bitpos: [3]; default: 0;
+         *  RTC control pwdet enable.
+         */
+        uint32_t sar2_pwdet_cal_en:1;
+        /** sar2_pkdet_cal_en : R/W; bitpos: [4]; default: 0;
+         *  RTC control pkdet enable.
+         */
+        uint32_t sar2_pkdet_cal_en:1;
+        /** sar2_en_test : R/W; bitpos: [5]; default: 0;
+         *  SAR2_EN_TEST.
+         */
+        uint32_t sar2_en_test:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_meas2_ctrl1_reg_t;
+
+/** Type of meas2_ctrl2 register
+ *  ADC2 configuration registers.
+ */
+typedef union {
+    struct {
+        /** meas2_data_sar : RO; bitpos: [15:0]; default: 0;
+         *  SAR ADC2 data.
+         */
+        uint32_t meas2_data_sar:16;
+        /** meas2_done_sar : RO; bitpos: [16]; default: 0;
+         *  SAR ADC2 conversion done indication.
+         */
+        uint32_t meas2_done_sar:1;
+        /** meas2_start_sar : R/W; bitpos: [17]; default: 0;
+         *  SAR ADC2 controller (in RTC) starts conversion.
+         */
+        uint32_t meas2_start_sar:1;
+        /** meas2_start_force : R/W; bitpos: [18]; default: 0;
+         *  1: SAR ADC2 controller (in RTC) is started by SW.
+         */
+        uint32_t meas2_start_force:1;
+        /** sar2_en_pad : R/W; bitpos: [30:19]; default: 0;
+         *  SAR ADC2 pad enable bitmap.
+         */
+        uint32_t sar2_en_pad:12;
+        /** sar2_en_pad_force : R/W; bitpos: [31]; default: 0;
+         *  1: SAR ADC2 pad enable bitmap is controlled by SW.
+         */
+        uint32_t sar2_en_pad_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas2_ctrl2_reg_t;
+
+/** Type of meas2_mux register
+ *  SAR ADC2 MUX register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** sar2_pwdet_cct : R/W; bitpos: [30:28]; default: 0;
+         *  SAR2_PWDET_CCT.
+         */
+        uint32_t sar2_pwdet_cct:3;
+        /** sar2_rtc_force : R/W; bitpos: [31]; default: 0;
+         *  In sleep, force to use rtc to control ADC.
+         */
+        uint32_t sar2_rtc_force:1;
+    };
+    uint32_t val;
+} rtcadc_meas2_mux_reg_t;
+
+/** Type of atten2 register
+ *  ADC1 attenuation registers.
+ */
+typedef union {
+    struct {
+        /** sar2_atten : R/W; bitpos: [31:0]; default: 4294967295;
+         *  2-bit attenuation for each pad.
+         */
+        uint32_t sar2_atten:32;
+    };
+    uint32_t val;
+} rtcadc_atten2_reg_t;
+
+
+/** Group: ADC XPD control. */
+/** Type of force_wpd_sar register
+ *  In sleep, force to use rtc to control ADC
+ */
+typedef union {
+    struct {
+        /** force_xpd_sar1 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+         *  control.
+         */
+        uint32_t force_xpd_sar1:2;
+        /** force_xpd_sar2 : R/W; bitpos: [3:2]; default: 0;
+         *  2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
+         *  control.
+         */
+        uint32_t force_xpd_sar2:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} rtcadc_force_wpd_sar_reg_t;
+
+
+/** Group: RTCADC interrupt registers. */
+/** Type of cocpu_int_raw register
+ *  Interrupt raw registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int raw.
+         */
+        uint32_t cocpu_saradc1_int_raw:1;
+        /** cocpu_saradc2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int raw.
+         */
+        uint32_t cocpu_saradc2_int_raw:1;
+        /** cocpu_saradc1_error_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int raw.
+         */
+        uint32_t cocpu_saradc1_error_int_raw:1;
+        /** cocpu_saradc2_error_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int raw.
+         */
+        uint32_t cocpu_saradc2_error_int_raw:1;
+        /** cocpu_saradc1_wake_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int raw.
+         */
+        uint32_t cocpu_saradc1_wake_int_raw:1;
+        /** cocpu_saradc2_wake_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int raw.
+         */
+        uint32_t cocpu_saradc2_wake_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_cocpu_int_raw_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_ena : R/WTC; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int enable.
+         */
+        uint32_t cocpu_saradc1_int_ena:1;
+        /** cocpu_saradc2_int_ena : R/WTC; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int enable.
+         */
+        uint32_t cocpu_saradc2_int_ena:1;
+        /** cocpu_saradc1_error_int_ena : R/WTC; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int enable.
+         */
+        uint32_t cocpu_saradc1_error_int_ena:1;
+        /** cocpu_saradc2_error_int_ena : R/WTC; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int enable.
+         */
+        uint32_t cocpu_saradc2_error_int_ena:1;
+        /** cocpu_saradc1_wake_int_ena : R/WTC; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int enable.
+         */
+        uint32_t cocpu_saradc1_wake_int_ena:1;
+        /** cocpu_saradc2_wake_int_ena : R/WTC; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int enable.
+         */
+        uint32_t cocpu_saradc2_wake_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_ena_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_st : RO; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int status.
+         */
+        uint32_t cocpu_saradc1_int_st:1;
+        /** cocpu_saradc2_int_st : RO; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int status.
+         */
+        uint32_t cocpu_saradc2_int_st:1;
+        /** cocpu_saradc1_error_int_st : RO; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int status.
+         */
+        uint32_t cocpu_saradc1_error_int_st:1;
+        /** cocpu_saradc2_error_int_st : RO; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int status.
+         */
+        uint32_t cocpu_saradc2_error_int_st:1;
+        /** cocpu_saradc1_wake_int_st : RO; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int status.
+         */
+        uint32_t cocpu_saradc1_wake_int_st:1;
+        /** cocpu_saradc2_wake_int_st : RO; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int status.
+         */
+        uint32_t cocpu_saradc2_wake_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_clr : WT; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, int clear.
+         */
+        uint32_t cocpu_saradc1_int_clr:1;
+        /** cocpu_saradc2_int_clr : WT; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, int clear.
+         */
+        uint32_t cocpu_saradc2_int_clr:1;
+        /** cocpu_saradc1_error_int_clr : WT; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, int clear.
+         */
+        uint32_t cocpu_saradc1_error_int_clr:1;
+        /** cocpu_saradc2_error_int_clr : WT; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, int clear.
+         */
+        uint32_t cocpu_saradc2_error_int_clr:1;
+        /** cocpu_saradc1_wake_int_clr : WT; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, int clear.
+         */
+        uint32_t cocpu_saradc1_wake_int_clr:1;
+        /** cocpu_saradc2_wake_int_clr : WT; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, int clear.
+         */
+        uint32_t cocpu_saradc2_wake_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_clr_reg_t;
+
+/** Type of int_ena_w1ts register
+ *  Interrupt enable assert registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_ena_w1ts : WT; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc1_int_ena_w1ts:1;
+        /** cocpu_saradc2_int_ena_w1ts : WT; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc2_int_ena_w1ts:1;
+        /** cocpu_saradc1_error_int_ena_w1ts : WT; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc1_error_int_ena_w1ts:1;
+        /** cocpu_saradc2_error_int_ena_w1ts : WT; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc2_error_int_ena_w1ts:1;
+        /** cocpu_saradc1_wake_int_ena_w1ts : WT; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc1_wake_int_ena_w1ts:1;
+        /** cocpu_saradc2_wake_int_ena_w1ts : WT; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, write 1 to assert int enable.
+         */
+        uint32_t cocpu_saradc2_wake_int_ena_w1ts:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_ena_w1ts_reg_t;
+
+/** Type of int_ena_w1tc register
+ *  Interrupt enable deassert registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_saradc1_int_ena_w1tc : WT; bitpos: [0]; default: 0;
+         *  ADC1 Conversion is done, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc1_int_ena_w1tc:1;
+        /** cocpu_saradc2_int_ena_w1tc : WT; bitpos: [1]; default: 0;
+         *  ADC2 Conversion is done, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc2_int_ena_w1tc:1;
+        /** cocpu_saradc1_error_int_ena_w1tc : WT; bitpos: [2]; default: 0;
+         *  An error occurs from ADC1, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc1_error_int_ena_w1tc:1;
+        /** cocpu_saradc2_error_int_ena_w1tc : WT; bitpos: [3]; default: 0;
+         *  An error occurs from ADC2, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc2_error_int_ena_w1tc:1;
+        /** cocpu_saradc1_wake_int_ena_w1tc : WT; bitpos: [4]; default: 0;
+         *  A wakeup event is triggered from ADC1, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc1_wake_int_ena_w1tc:1;
+        /** cocpu_saradc2_wake_int_ena_w1tc : WT; bitpos: [5]; default: 0;
+         *  A wakeup event is triggered from ADC2, write 1 to deassert int enable.
+         */
+        uint32_t cocpu_saradc2_wake_int_ena_w1tc:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtcadc_int_ena_w1tc_reg_t;
+
+
+/** Group: RTCADC wakeup control registers. */
+/** Type of wakeup1 register
+ *  ADC1 wakeup configuration registers.
+ */
+typedef union {
+    struct {
+        /** sar1_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t sar1_wakeup_th_low:12;
+        uint32_t reserved_12:2;
+        /** sar1_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
+         *  Upper threshold.
+         */
+        uint32_t sar1_wakeup_th_high:12;
+        uint32_t reserved_26:3;
+        /** sar1_wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t sar1_wakeup_over_upper_th:1;
+        /** sar1_wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Wakeup function enable.
+         */
+        uint32_t sar1_wakeup_en:1;
+        /** sar1_wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t sar1_wakeup_mode:1;
+    };
+    uint32_t val;
+} rtcadc_wakeup1_reg_t;
+
+/** Type of wakeup2 register
+ *  ADC2 wakeup configuration registers.
+ */
+typedef union {
+    struct {
+        /** sar2_wakeup_th_low : R/W; bitpos: [11:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t sar2_wakeup_th_low:12;
+        uint32_t reserved_12:2;
+        /** sar2_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095;
+         *  Upper threshold.
+         */
+        uint32_t sar2_wakeup_th_high:12;
+        uint32_t reserved_26:3;
+        /** sar2_wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t sar2_wakeup_over_upper_th:1;
+        /** sar2_wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Wakeup function enable.
+         */
+        uint32_t sar2_wakeup_en:1;
+        /** sar2_wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t sar2_wakeup_mode:1;
+    };
+    uint32_t val;
+} rtcadc_wakeup2_reg_t;
+
+/** Type of wakeup_sel register
+ *  Wakeup source select register.
+ */
+typedef union {
+    struct {
+        /** sar_wakeup_sel : R/W; bitpos: [0]; default: 0;
+         *  0: ADC1. 1: ADC2.
+         */
+        uint32_t sar_wakeup_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rtcadc_wakeup_sel_reg_t;
+
+/** Type of sar1_hw_wakeup register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+typedef union {
+    struct {
+        /** adc1_hw_read_en_i : R/W; bitpos: [0]; default: 0;
+         *  Enable hardware automatic sampling.
+         */
+        uint32_t adc1_hw_read_en_i:1;
+        /** adc1_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t adc1_hw_read_rate_i:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} rtcadc_sar1_hw_wakeup_reg_t;
+
+/** Type of sar2_hw_wakeup register
+ *  Hardware automatic sampling registers for wakeup function.
+ */
+typedef union {
+    struct {
+        /** adc2_hw_read_en_i : R/W; bitpos: [0]; default: 0;
+         *  Enable hardware automatic sampling.
+         */
+        uint32_t adc2_hw_read_en_i:1;
+        /** adc2_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t adc2_hw_read_rate_i:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} rtcadc_sar2_hw_wakeup_reg_t;
+
+
+typedef struct {
+    volatile rtcadc_reader1_ctrl_reg_t reader1_ctrl;
+    uint32_t reserved_004[2];
+    volatile rtcadc_meas1_ctrl2_reg_t meas1_ctrl2;
+    volatile rtcadc_meas1_mux_reg_t meas1_mux;
+    volatile rtcadc_atten1_reg_t atten1;
+    uint32_t reserved_018[3];
+    volatile rtcadc_reader2_ctrl_reg_t reader2_ctrl;
+    uint32_t reserved_028;
+    volatile rtcadc_meas2_ctrl1_reg_t meas2_ctrl1;
+    volatile rtcadc_meas2_ctrl2_reg_t meas2_ctrl2;
+    volatile rtcadc_meas2_mux_reg_t meas2_mux;
+    volatile rtcadc_atten2_reg_t atten2;
+    volatile rtcadc_force_wpd_sar_reg_t force_wpd_sar;
+    uint32_t reserved_040[2];
+    volatile rtcadc_cocpu_int_raw_reg_t cocpu_int_raw;
+    volatile rtcadc_int_ena_reg_t int_ena;
+    volatile rtcadc_int_st_reg_t int_st;
+    volatile rtcadc_int_clr_reg_t int_clr;
+    volatile rtcadc_int_ena_w1ts_reg_t int_ena_w1ts;
+    volatile rtcadc_int_ena_w1tc_reg_t int_ena_w1tc;
+    volatile rtcadc_wakeup1_reg_t wakeup1;
+    volatile rtcadc_wakeup2_reg_t wakeup2;
+    volatile rtcadc_wakeup_sel_reg_t wakeup_sel;
+    volatile rtcadc_sar1_hw_wakeup_reg_t sar1_hw_wakeup;
+    volatile rtcadc_sar2_hw_wakeup_reg_t sar2_hw_wakeup;
+} rtcadc_dev_t;
+
+extern rtcadc_dev_t LP_ADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtcadc_dev_t) == 0x74, "Invalid size of rtcadc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_struct.h

@@ -0,0 +1,885 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13424
+
+/** Group: configure_register */
+/** Type of bod_mode0_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_close_flash_ena:1;
+        /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_pd_rf_ena:1;
+        /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
+         *  need_des
+         */
+        uint32_t bod_mode0_intr_wait:10;
+        /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
+         *  need_des
+         */
+        uint32_t bod_mode0_reset_wait:10;
+        /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_cnt_clr:1;
+        /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_intr_ena:1;
+        /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_reset_sel:1;
+        /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_reset_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_bod_mode0_cntl_reg_t;
+
+/** Type of bod_mode1_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode1_reset_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_bod_mode1_cntl_reg_t;
+
+/** Type of vdd_source_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** detmode_sel : R/W; bitpos: [7:0]; default: 255;
+         *  need_des
+         */
+        uint32_t detmode_sel:8;
+        /** vgood_event_record : RO; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t vgood_event_record:8;
+        /** vbat_event_record_clr : WT; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t vbat_event_record_clr:8;
+        /** bod_source_ena : R/W; bitpos: [31:24]; default: 4;
+         *  need_des
+         */
+        uint32_t bod_source_ena:8;
+    };
+    uint32_t val;
+} lp_analog_peri_vdd_source_cntl_reg_t;
+
+/** Type of vddbat_bod_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_flag:1;
+        uint32_t reserved_1:9;
+        /** vddbat_charger : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charger:1;
+        /** vddbat_cnt_clr : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_cnt_clr:1;
+        /** vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_target:10;
+        /** vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_target:10;
+    };
+    uint32_t val;
+} lp_analog_peri_vddbat_bod_cntl_reg_t;
+
+/** Type of vddbat_charge_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_flag:1;
+        uint32_t reserved_1:9;
+        /** vddbat_charge_charger : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_charger:1;
+        /** vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_cnt_clr:1;
+        /** vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_target:10;
+        /** vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_target:10;
+    };
+    uint32_t val;
+} lp_analog_peri_vddbat_charge_cntl_reg_t;
+
+/** Type of pg_glitch_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** power_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t power_glitch_reset_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_pg_glitch_cntl_reg_t;
+
+/** Type of fib_enable register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
+         *  need_des
+         */
+        uint32_t ana_fib_ena:32;
+    };
+    uint32_t val;
+} lp_analog_peri_fib_enable_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_raw:1;
+        /** vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_raw:1;
+        /** vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_raw:1;
+        /** vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_raw:1;
+        /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_raw:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_st:1;
+        /** vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_st:1;
+        /** vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_st:1;
+        /** vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_st:1;
+        /** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_st:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_ena:1;
+        /** vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_ena:1;
+        /** vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_ena:1;
+        /** vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_ena:1;
+        /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_upvoltage_int_clr:1;
+        /** vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_charge_undervoltage_int_clr:1;
+        /** vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_upvoltage_int_clr:1;
+        /** vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t vddbat_undervoltage_int_clr:1;
+        /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_int_clr:1;
+    };
+    uint32_t val;
+} lp_analog_peri_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t bod_mode0_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_analog_peri_lp_int_clr_reg_t;
+
+/** Type of touch_approach_work_meas_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_approach_meas_num2 : R/W; bitpos: [9:0]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_approach_meas_num2:10;
+        /** touch_approach_meas_num1 : R/W; bitpos: [19:10]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_approach_meas_num1:10;
+        /** touch_approach_meas_num0 : R/W; bitpos: [29:20]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_approach_meas_num0:10;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_approach_work_meas_num_reg_t;
+
+/** Type of touch_scan_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_shield_pad_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_shield_pad_en:1;
+        /** touch_inactive_connection : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_inactive_connection:1;
+        /** touch_scan_pad_map : R/W; bitpos: [16:2]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_scan_pad_map:15;
+        /** touch_xpd_wait : R/W; bitpos: [31:17]; default: 4;
+         *  need_des
+         */
+        uint32_t touch_xpd_wait:15;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_scan_ctrl1_reg_t;
+
+/** Type of touch_scan_ctrl2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** touch_timeout_num : R/W; bitpos: [21:6]; default: 65535;
+         *  need_des
+         */
+        uint32_t touch_timeout_num:16;
+        /** touch_timeout_en : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_timeout_en:1;
+        /** touch_out_ring : R/W; bitpos: [26:23]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_out_ring:4;
+        /** freq_scan_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t freq_scan_en:1;
+        /** freq_scan_cnt_limit : R/W; bitpos: [29:28]; default: 3;
+         *  need_des
+         */
+        uint32_t freq_scan_cnt_limit:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_scan_ctrl2_reg_t;
+
+/** Type of touch_work register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** div_num2 : R/W; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t div_num2:3;
+        /** div_num1 : R/W; bitpos: [21:19]; default: 0;
+         *  need_des
+         */
+        uint32_t div_num1:3;
+        /** div_num0 : R/W; bitpos: [24:22]; default: 0;
+         *  need_des
+         */
+        uint32_t div_num0:3;
+        /** touch_out_sel : R/W; bitpos: [25]; default: 0;
+         *  0: Select the output of the touch as data
+         *  1: Select the output of the touch as clock
+         */
+        uint32_t touch_out_sel:1;
+        /** touch_out_reset : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_out_reset:1;
+        /** touch_out_gate : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_out_gate:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_work_reg_t;
+
+/** Type of touch_work_meas_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_meas_num2 : R/W; bitpos: [9:0]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_meas_num2:10;
+        /** touch_meas_num1 : R/W; bitpos: [19:10]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_meas_num1:10;
+        /** touch_meas_num0 : R/W; bitpos: [29:20]; default: 100;
+         *  need_des
+         */
+        uint32_t touch_meas_num0:10;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_work_meas_num_reg_t;
+
+/** Type of touch_filter1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_nn_disupdate_benchmark_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t touch_nn_disupdate_benchmark_en:1;
+        /** touch_hysteresis : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_hysteresis:2;
+        /** touch_nn_thres : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_nn_thres:2;
+        /** touch_noise_thres : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_noise_thres:2;
+        /** touch_smooth_lvl : R/W; bitpos: [8:7]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_smooth_lvl:2;
+        /** touch_jitter_step : R/W; bitpos: [12:9]; default: 1;
+         *  need_des
+         */
+        uint32_t touch_jitter_step:4;
+        /** touch_filter_mode : R/W; bitpos: [15:13]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_filter_mode:3;
+        /** touch_filter_en : R/W; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_filter_en:1;
+        /** touch_nn_limit : R/W; bitpos: [20:17]; default: 5;
+         *  need_des
+         */
+        uint32_t touch_nn_limit:4;
+        /** touch_approach_limit : R/W; bitpos: [28:21]; default: 80;
+         *  need_des
+         */
+        uint32_t touch_approach_limit:8;
+        /** touch_debounce_limit : R/W; bitpos: [31:29]; default: 3;
+         *  need_des
+         */
+        uint32_t touch_debounce_limit:3;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_filter1_reg_t;
+
+/** Type of touch_filter2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:15;
+        /** touch_outen : R/W; bitpos: [29:15]; default: 16383;
+         *  need_des
+         */
+        uint32_t touch_outen:15;
+        /** touch_bypass_noise_thres : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_bypass_noise_thres:1;
+        /** touch_bypass_nn_thres : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_bypass_nn_thres:1;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_filter2_reg_t;
+
+/** Type of touch_filter3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_benchmark_sw : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_benchmark_sw:16;
+        /** touch_update_benchmark_sw : WT; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_update_benchmark_sw:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_filter3_reg_t;
+
+/** Type of touch_slp0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_slp_th0 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_th0:16;
+        /** touch_slp_channel_clr : WT; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_channel_clr:1;
+        /** touch_slp_pad : R/W; bitpos: [20:17]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_slp_pad:4;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_slp0_reg_t;
+
+/** Type of touch_slp1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_slp_th2 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_th2:16;
+        /** touch_slp_th1 : R/W; bitpos: [31:16]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_th1:16;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_slp1_reg_t;
+
+/** Type of touch_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_channel_clr : WT; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_channel_clr:15;
+        /** touch_status_clr : WT; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_status_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_clr_reg_t;
+
+/** Type of touch_approach register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_approach_pad0 : R/W; bitpos: [3:0]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_approach_pad0:4;
+        /** touch_approach_pad1 : R/W; bitpos: [7:4]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_approach_pad1:4;
+        /** touch_approach_pad2 : R/W; bitpos: [11:8]; default: 15;
+         *  need_des
+         */
+        uint32_t touch_approach_pad2:4;
+        /** touch_slp_approach_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t touch_slp_approach_en:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_approach_reg_t;
+
+/** Type of touch_freq_scan_para register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_freq_dcap_lpf : R/W; bitpos: [6:0]; default: 0;
+         *  Capacity of the RC low pass filter
+         *  0 ~ 2.54 pF, step 20fF
+         */
+        uint32_t touch_freq_dcap_lpf:7;
+        /** touch_freq_dres_lpf : R/W; bitpos: [8:7]; default: 0;
+         *  Resistance of the RC low pass filter
+         *  0 ~ 4.5 K, step 1.5 K
+         */
+        uint32_t touch_freq_dres_lpf:2;
+        /** touch_freq_drv_ls : R/W; bitpos: [12:9]; default: 0;
+         *  Low speed touch driver, effective when high speed driver is disabled
+         */
+        uint32_t touch_freq_drv_ls:4;
+        /** touch_freq_drv_hs : R/W; bitpos: [17:13]; default: 0;
+         *  High speed touch driver
+         */
+        uint32_t touch_freq_drv_hs:5;
+        /** touch_bypass_shield : R/W; bitpos: [18]; default: 0;
+         *  bypass the shield channel output (only available since ECO1)
+         */
+        uint32_t touch_bypass_shield:1;
+        /** touch_freq_dbias : R/W; bitpos: [22:19]; default: 0;
+         *  Internal LDO voltage
+         */
+        uint32_t touch_freq_dbias:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_freq_scan_para_reg_t;
+
+/** Type of touch_ana_para register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_touch_buf_drv : R/W; bitpos: [2:0]; default: 0;
+         *  The driver of water proof touch buff
+         */
+        uint32_t touch_touch_buf_drv:3;
+        /** touch_touch_en_cal : R/W; bitpos: [3]; default: 0;
+         *  Enable internal loop. Need to turn off touch pad.
+         *  Tuning 'dcap_cal' to change the frequency
+         */
+        uint32_t touch_touch_en_cal:1;
+        /** touch_touch_dcap_cal : R/W; bitpos: [10:4]; default: 0;
+         *  The internal capacitor connected to the touch pad. Effective when 'en_cal' enabled
+         *  Normally set to 0
+         */
+        uint32_t touch_touch_dcap_cal:7;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_ana_para_reg_t;
+
+/** Type of touch_mux0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** touch_data_sel : R/W; bitpos: [9:8]; default: 0;
+         *  The type of the output data for debugging
+         *  0/1: raw data
+         *  2: benchmark
+         *  3: smooth data
+         */
+        uint32_t touch_data_sel:2;
+        /** touch_freq_sel : R/W; bitpos: [11:10]; default: 0;
+         *  The frequency id of the output data for debugging
+         *  0: invalid
+         *  1: Frequency 1
+         *  2: Frequency 2
+         *  3: Frequency 3
+         */
+        uint32_t touch_freq_sel:2;
+        /** touch_bufsel : R/W; bitpos: [26:12]; default: 0;
+         *  The bitmap of the shield pad
+         */
+        uint32_t touch_bufsel:15;
+        /** touch_done_en : R/W; bitpos: [27]; default: 0;
+         *  Force to terminate the touch by software
+         */
+        uint32_t touch_done_en:1;
+        /** touch_done_force : R/W; bitpos: [28]; default: 0;
+         *  0: Select touch_meas_done as the touch timer input
+         *  1: Select software termination as the touch timer input
+         */
+        uint32_t touch_done_force:1;
+        /** touch_fsm_en : R/W; bitpos: [29]; default: 1;
+         *  0: Select software configured parameters for ana
+         *  1: Select hardware calculated parameters for ana
+         */
+        uint32_t touch_fsm_en:1;
+        /** touch_start_en : R/W; bitpos: [30]; default: 0;
+         *  Force to start the touch by software
+         */
+        uint32_t touch_start_en:1;
+        /** touch_start_force : R/W; bitpos: [31]; default: 0;
+         *  0: Select the touch timer to start the touch scanning
+         *  1: Select the software to start the touch scanning
+         */
+        uint32_t touch_start_force:1;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_mux0_reg_t;
+
+/** Type of touch_mux1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** touch_start : R/W; bitpos: [14:0]; default: 0;
+         *  The bitmap of the start touch channels
+         */
+        uint32_t touch_start:15;
+        /** touch_xpd : R/W; bitpos: [29:15]; default: 0;
+         *  The bitmap of the power on touch channels
+         */
+        uint32_t touch_xpd:15;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_mux1_reg_t;
+
+/** Type of touch_pad0_th0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** touch_pad_th : R/W; bitpos: [31:16]; default: 0;
+         *  The threshold to activate a touch channel
+         */
+        uint32_t threshold:16;
+    };
+    uint32_t val;
+} lp_analog_peri_touch_pad_thn_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2294816;
+         *  need_des
+         */
+        uint32_t lp_analog_peri_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_analog_peri_date_reg_t;
+
+
+typedef struct {
+    volatile lp_analog_peri_touch_pad_thn_reg_t thresh[3];
+} lp_analog_peri_touch_padx_thn_reg_t;
+
+typedef struct {
+    volatile lp_analog_peri_bod_mode0_cntl_reg_t bod_mode0_cntl;
+    volatile lp_analog_peri_bod_mode1_cntl_reg_t bod_mode1_cntl;
+    volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl;
+    volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
+    volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
+    uint32_t reserved_014;
+    volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl;
+    volatile lp_analog_peri_fib_enable_reg_t fib_enable;
+    volatile lp_analog_peri_int_raw_reg_t int_raw;
+    volatile lp_analog_peri_int_st_reg_t int_st;
+    volatile lp_analog_peri_int_ena_reg_t int_ena;
+    volatile lp_analog_peri_int_clr_reg_t int_clr;
+    volatile lp_analog_peri_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_analog_peri_lp_int_st_reg_t lp_int_st;
+    volatile lp_analog_peri_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_analog_peri_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_040[47];
+    volatile lp_analog_peri_touch_approach_work_meas_num_reg_t touch_approach_work_meas_num;
+    volatile lp_analog_peri_touch_scan_ctrl1_reg_t touch_scan_ctrl1;
+    volatile lp_analog_peri_touch_scan_ctrl2_reg_t touch_scan_ctrl2;
+    volatile lp_analog_peri_touch_work_reg_t touch_work;
+    volatile lp_analog_peri_touch_work_meas_num_reg_t touch_work_meas_num;
+    volatile lp_analog_peri_touch_filter1_reg_t touch_filter1;
+    volatile lp_analog_peri_touch_filter2_reg_t touch_filter2;
+    volatile lp_analog_peri_touch_filter3_reg_t touch_filter3;
+    volatile lp_analog_peri_touch_slp0_reg_t touch_slp0;
+    volatile lp_analog_peri_touch_slp1_reg_t touch_slp1;
+    volatile lp_analog_peri_touch_clr_reg_t touch_clr;
+    volatile lp_analog_peri_touch_approach_reg_t touch_approach;
+    volatile lp_analog_peri_touch_freq_scan_para_reg_t touch_freq_scan_para[3];
+    volatile lp_analog_peri_touch_ana_para_reg_t touch_ana_para;
+    volatile lp_analog_peri_touch_mux0_reg_t touch_mux0;
+    volatile lp_analog_peri_touch_mux1_reg_t touch_mux1;
+    volatile lp_analog_peri_touch_padx_thn_reg_t touch_padx_thn[15];
+    uint32_t reserved_1f8[129];
+    volatile lp_analog_peri_date_reg_t date;
+} lp_analog_peri_dev_t;
+
+extern lp_analog_peri_dev_t LP_ANA_PERI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_analog_peri_dev_t) == 0x400, "Invalid size of lp_analog_peri_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_struct.h

@@ -0,0 +1,796 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_clk_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slow_clk_sel:2;
+        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_clk_sel:2;
+        /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_peri_div_num:6;
+        /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_sel_ref_pll8m:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_clk_conf_reg_t;
+
+/** Type of lp_clk_po_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_core_efuse_oen:1;
+        /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_lp_bus_oen:1;
+        /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_aon_slow_oen:1;
+        /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_aon_fast_oen:1;
+        /** clk_slow_oen : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_slow_oen:1;
+        /** clk_fast_oen : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_fast_oen:1;
+        /** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_fosc_oen:1;
+        /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_rc32k_oen:1;
+        /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_sxtal_oen:1;
+        /** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
+         *  1'b1: probe sosc clk on
+         *  1'b0: probe sosc clk off
+         */
+        uint32_t clk_sosc_oen:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_clk_po_en_reg_t;
+
+/** Type of lp_clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_rtc_xtal_force_on:1;
+        /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_ram:1;
+        /** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t etm_event_tick_en:1;
+        /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t pll8m_clk_force_on:1;
+        /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t xtal_clk_force_on:1;
+        /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t fosc_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_clk_en_reg_t;
+
+/** Type of lp_rst_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_huk:1;
+        /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_anaperi:1;
+        /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_wdt:1;
+        /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_timer:1;
+        /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rtc:1;
+        /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_mailbox:1;
+        /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_aonefusereg:1;
+        /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_ram:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_lp_rst_en_reg_t;
+
+/** Type of reset_cause register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
+         *  6'h1: POR reset
+         *  6'h9: PMU LP PERI power down reset
+         *  6'ha: PMU LP CPU reset
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: software reset
+         */
+        uint32_t lpcore_reset_cause:6;
+        /** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_flag:1;
+        /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore0_reset_cause:6;
+        /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag:1;
+        /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore1_reset_cause:6;
+        /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag:1;
+        uint32_t reserved_21:4;
+        /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
+         *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+         *  pmu_lp_cpu_reset reset_cause
+         */
+        uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
+        /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_cause_clr:1;
+        /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_flag_clr:1;
+        /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_cause_clr:1;
+        /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag_clr:1;
+        /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_cause_clr:1;
+        /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag_clr:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_reset_cause_reg_t;
+
+/** Type of hpcpu_reset_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+         *  reset feature
+         */
+        uint32_t hpcore0_lockup_reset_en:1;
+        /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore0_reset_length:3;
+        /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+         *  hpcore0 feature
+         */
+        uint32_t lp_wdt_hpcore0_reset_en:1;
+        /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_stall_wait:7;
+        /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_stall_en:1;
+        /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_sw_reset:1;
+        /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_ocd_halt_on_reset:1;
+        /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore0_stat_vector_sel:1;
+        /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
+         *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+         *  reset feature
+         */
+        uint32_t hpcore1_lockup_reset_en:1;
+        /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore1_reset_length:3;
+        /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+         *  hpcore1 feature
+         */
+        uint32_t lp_wdt_hpcore1_reset_en:1;
+        /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_wait:7;
+        /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_en:1;
+        /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_sw_reset:1;
+        /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_ocd_halt_on_reset:1;
+        /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore1_stat_vector_sel:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t;
+
+/** Type of hpcpu_reset_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
+         *  HP core0 software stall when set to 8'h86
+         */
+        uint32_t hpcore0_sw_stall_code:8;
+        /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
+         *  HP core1 software stall when set to 8'h86
+         */
+        uint32_t hpcore1_sw_stall_code:8;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t;
+
+/** Type of fosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
+         *  need_des
+         */
+        uint32_t fosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_aonclkrst_fosc_cntl_reg_t;
+
+/** Type of rc32k_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
+         *  need_des
+         */
+        uint32_t rc32k_dfreq:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_rc32k_cntl_reg_t;
+
+/** Type of sosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  need_des
+         */
+        uint32_t sosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_aonclkrst_sosc_cntl_reg_t;
+
+/** Type of clk_to_hp register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_xtal32k:1;
+        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_sosc:1;
+        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_osc32k:1;
+        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_fosc:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_clk_to_hp_reg_t;
+
+/** Type of lpmem_force register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t lpmem_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_lpmem_force_reg_t;
+
+/** Type of xtal32k register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
+         *  need_des
+         */
+        uint32_t dres_xtal32k:3;
+        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
+         *  need_des
+         */
+        uint32_t dgm_xtal32k:3;
+        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t dbuf_xtal32k:1;
+        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
+         *  need_des
+         */
+        uint32_t dac_xtal32k:3;
+    };
+    uint32_t val;
+} lp_aonclkrst_xtal32k_reg_t;
+
+/** Type of mux_hpsys_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t mux_hpsys_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t;
+
+/** Type of hpsys_0_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_0_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpsys_0_reset_bypass_reg_t;
+
+/** Type of hpsys_apm_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_apm_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t;
+
+/** Type of hp_clk_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+         */
+        uint32_t hp_root_clk_src_sel:2;
+        /** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
+         *  HP SoC Root Clock Enable.
+         */
+        uint32_t hp_root_clk_en:1;
+        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
+         *  PARLIO TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_tx_clk_en:1;
+        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
+         *  PARLIO RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_rx_clk_en:1;
+        /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
+         *  UART4 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart4_slp_clk_en:1;
+        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
+         *  UART3 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart3_slp_clk_en:1;
+        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
+         *  UART2 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart2_slp_clk_en:1;
+        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
+         *  UART1 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart1_slp_clk_en:1;
+        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
+         *  UART0 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart0_slp_clk_en:1;
+        /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
+         *  I2S2 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s2_mclk_en:1;
+        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
+         *  I2S1 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s1_mclk_en:1;
+        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
+         *  I2S0 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s0_mclk_en:1;
+        /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
+         *  EMAC RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_tx_clk_en:1;
+        /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
+         *  EMAC TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_rx_clk_en:1;
+        /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
+         *  EMAC TXRX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_txrx_clk_en:1;
+        /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
+         *  XTAL 32K Clock Enable.
+         */
+        uint32_t hp_xtal_32k_clk_en:1;
+        /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
+         *  RC 32K Clock Enable.
+         */
+        uint32_t hp_rc_32k_clk_en:1;
+        /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
+         *  SOSC 150K Clock Enable.
+         */
+        uint32_t hp_sosc_150k_clk_en:1;
+        /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
+         *  PLL 8M Clock Enable.
+         */
+        uint32_t hp_pll_8m_clk_en:1;
+        /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
+         *  AUDIO PLL Clock Enable.
+         */
+        uint32_t hp_audio_pll_clk_en:1;
+        /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
+         *  SDIO PLL2 Clock Enable.
+         */
+        uint32_t hp_sdio_pll2_clk_en:1;
+        /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
+         *  SDIO PLL1 Clock Enable.
+         */
+        uint32_t hp_sdio_pll1_clk_en:1;
+        /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
+         *  SDIO PLL0 Clock Enable.
+         */
+        uint32_t hp_sdio_pll0_clk_en:1;
+        /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
+         *  FOSC 20M Clock Enable.
+         */
+        uint32_t hp_fosc_20m_clk_en:1;
+        /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
+         *  XTAL 40M Clock Enable.
+         */
+        uint32_t hp_xtal_40m_clk_en:1;
+        /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
+         *  CPLL 400M Clock Enable.
+         */
+        uint32_t hp_cpll_400m_clk_en:1;
+        /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  SPLL 480M Clock Enable.
+         */
+        uint32_t hp_spll_480m_clk_en:1;
+        /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  MPLL 500M Clock Enable.
+         */
+        uint32_t hp_mpll_500m_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_clk_ctrl_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl0 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg20_sleep_mode:1;
+        /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg20_bk_sys_clk_en:1;
+        /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg11_sleep_mode:1;
+        /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg11_bk_sys_clk_en:1;
+        /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  usb otg11 fs phy clock enable.
+         */
+        uint32_t usb_otg11_48m_clk_en:1;
+        /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
+         *  usb device fs phy clock enable.
+         */
+        uint32_t usb_device_48m_clk_en:1;
+        /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
+         *  usb 480m to 25m divide number.
+         */
+        uint32_t usb_48m_div_num:8;
+        /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
+         *  usb 500m to 25m divide number.
+         */
+        uint32_t usb_25m_div_num:8;
+        /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
+         *  usb 480m to 12m divide number.
+         */
+        uint32_t usb_12m_div_num:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl1 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
+         *  usb otg20 adp reset en
+         */
+        uint32_t rst_en_usb_otg20_adp:1;
+        /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
+         *  usb otg20 phy reset en
+         */
+        uint32_t rst_en_usb_otg20_phy:1;
+        /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
+         *  usb otg20 reset en
+         */
+        uint32_t rst_en_usb_otg20:1;
+        /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
+         *  usb org11 reset en
+         */
+        uint32_t rst_en_usb_otg11:1;
+        /** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
+         *  usb device reset en
+         */
+        uint32_t rst_en_usb_device:1;
+        uint32_t reserved_5:23;
+        /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
+         *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+         */
+        uint32_t usb_otg20_phyref_clk_src_sel:2;
+        /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
+         *  usb otg20 hs phy refclk enable.
+         */
+        uint32_t usb_otg20_phyref_clk_en:1;
+        /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
+         *  usb otg20 ulpi clock enable.
+         */
+        uint32_t usb_otg20_ulpi_clk_en:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t;
+
+/** Type of hp_sdmmc_emac_rst_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
+         *  hp sdmmc reset en
+         */
+        uint32_t rst_en_sdmmc:1;
+        /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
+         *  hp sdmmc force norst
+         */
+        uint32_t force_norst_sdmmc:1;
+        /** rst_en_emac : R/W; bitpos: [30]; default: 0;
+         *  hp emac reset en
+         */
+        uint32_t rst_en_emac:1;
+        /** force_norst_emac : R/W; bitpos: [31]; default: 0;
+         *  hp emac force norst
+         */
+        uint32_t force_norst_emac:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_aonclkrst_date_reg_t;
+
+
+typedef struct {
+    volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf;
+    volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en;
+    volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en;
+    volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en;
+    volatile lp_aonclkrst_reset_cause_reg_t reset_cause;
+    volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
+    volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
+    volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl;
+    volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl;
+    volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl;
+    volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp;
+    volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force;
+    volatile lp_aonclkrst_xtal32k_reg_t xtal32k;
+    volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
+    volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
+    volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
+    volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
+    volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
+    volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
+    volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
+    uint32_t reserved_050[235];
+    volatile lp_aonclkrst_date_reg_t date;
+} lp_aonclkrst_dev_t;
+
+extern lp_aonclkrst_dev_t LP_AON_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_sig_map.h

@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define LP_I2C_SCL_PAD_IN_IDX                   0
+#define LP_I2C_SCL_PAD_OUT_IDX                  0
+#define LP_I2C_SDA_PAD_IN_IDX                   1
+#define LP_I2C_SDA_PAD_OUT_IDX                  1
+#define LP_UART_RXD_PAD_IN_IDX                  2
+#define LP_UART_TXD_PAD_OUT_IDX                 2
+#define LP_UART_CTSN_PAD_IN_IDX                 3
+#define LP_UART_RTSN_PAD_OUT_IDX                3
+#define LP_UART_DSRN_PAD_IN_IDX                 4
+#define LP_UART_DTRN_PAD_OUT_IDX                4
+#define LP_SPI_CK_PAD_IN_IDX                    5
+#define LP_SPI_CK_PAD_OUT_IDX                   5
+#define LP_SPI_CS_PAD_IN_IDX                    6
+#define LP_SPI_CS_PAD_OUT_IDX                   6
+#define LP_SPI_D_PAD_IN_IDX                     7
+#define LP_SPI_D_PAD_OUT_IDX                    7
+#define LP_SPI_Q_PAD_IN_IDX                     8
+#define LP_SPI_Q_PAD_OUT_IDX                    8
+#define LP_I2S_I_BCK_PAD_IN_IDX                 9
+#define LP_I2S_I_BCK_PAD_OUT_IDX                9
+#define LP_I2S_I_SD_PAD_IN_IDX                  10
+#define LP_I2S_O_SD_PAD_OUT_IDX                 10
+#define LP_I2S_I_WS_PAD_IN_IDX                  11
+#define LP_I2S_I_WS_PAD_OUT_IDX                 11
+#define LP_I2S_O_BCK_PAD_IN_IDX                 12
+#define LP_I2S_O_BCK_PAD_OUT_IDX                12
+#define LP_I2S_O_WS_PAD_IN_IDX                  13
+#define LP_I2S_O_WS_PAD_OUT_IDX                 13
+#define LP_PROBE_TOP_OUT0_IDX                   14
+#define LP_PROBE_TOP_OUT1_IDX                   15
+#define LP_PROBE_TOP_OUT2_IDX                   16
+#define LP_PROBE_TOP_OUT3_IDX                   17
+#define LP_PROBE_TOP_OUT4_IDX                   18
+#define LP_PROBE_TOP_OUT5_IDX                   19
+#define LP_PROBE_TOP_OUT6_IDX                   20
+#define LP_PROBE_TOP_OUT7_IDX                   21
+#define LP_PROBE_TOP_OUT8_IDX                   22
+#define LP_PROBE_TOP_OUT9_IDX                   23
+#define LP_PROBE_TOP_OUT10_IDX                  24
+#define LP_PROBE_TOP_OUT11_IDX                  25
+#define LP_PROBE_TOP_OUT12_IDX                  26
+#define LP_PROBE_TOP_OUT13_IDX                  27
+#define LP_PROBE_TOP_OUT14_IDX                  28
+#define LP_PROBE_TOP_OUT15_IDX                  29
+#define PROBE_CHAIN_CLK_PAD_OUT_IDX             30
+// version date 230323
+#define SIG_GPIO_OUT_IDX                        128

components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_struct.h

@@ -0,0 +1,329 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_gpio_clk_en_reg_t;
+
+
+/** Group: ver_date */
+/** Type of ver_date register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [27:0]; default: 2294563;
+         *  Reserved
+         */
+        uint32_t reg_ver_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_gpio_ver_date_reg_t;
+
+
+/** Group: out */
+/** Type of out register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_out_data : R/W/WTC; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_out_data:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_out_reg_t;
+
+
+/** Group: out_w1ts */
+/** Type of out_w1ts register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_out_data_w1ts : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_out_data_w1ts:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_out_w1ts_reg_t;
+
+
+/** Group: out_w1tc */
+/** Type of out_w1tc register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_out_data_w1tc : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_out_data_w1tc:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_out_w1tc_reg_t;
+
+
+/** Group: enable */
+/** Type of enable register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_enable_data : R/W/WTC; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_enable_data:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_enable_reg_t;
+
+
+/** Group: enable_w1ts */
+/** Type of enable_w1ts register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_enable_data_w1ts : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_enable_data_w1ts:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_enable_w1ts_reg_t;
+
+
+/** Group: enable_w1tc */
+/** Type of enable_w1tc register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_enable_data_w1tc : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_enable_data_w1tc:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_enable_w1tc_reg_t;
+
+
+/** Group: status */
+/** Type of status register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_data : R/W/WTC; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_data:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_reg_t;
+
+
+/** Group: status_w1ts */
+/** Type of status_w1ts register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_data_w1ts : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_data_w1ts:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_w1ts_reg_t;
+
+
+/** Group: status_w1tc */
+/** Type of status_w1tc register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_data_w1tc : WT; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_data_w1tc:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_w1tc_reg_t;
+
+
+/** Group: in */
+/** Type of status_next register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_status_interrupt_next : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_status_interrupt_next:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_status_next_reg_t;
+
+/** Type of in register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpio_in_data_next : RO; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpio_in_data_next:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_gpio_in_reg_t;
+
+
+/** Group: pin */
+/** Type of pin register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** wakeup_enable : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t wakeup_enable:1;
+        /** int_type : R/W; bitpos: [3:1]; default: 0;
+         *  Reserved
+         */
+        uint32_t int_type:3;
+        /** pad_driver : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t pad_driver:1;
+        /** edge_wakeup_clr : WT; bitpos: [5]; default: 0;
+         *  need des
+         */
+        uint32_t edge_wakeup_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_gpio_pin_reg_t;
+
+
+/** Group: func_in_sel_cfg */
+/** Type of func_in_sel_cfg register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** in_inv_sel : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t sig_in_sel:1;
+        /** func_in_sel : R/W; bitpos: [7:2]; default: 48 (for func0/1/3/4) 32 (for the rest);
+         *  func_in_sel[5:4]==2'b11 (s=0x30) -> constant 1
+         *  func_in_sel[5:4]==2'b10 (s=0x20) -> constant 0
+         */
+        uint32_t func_in_sel:6;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_gpio_func_in_sel_cfg_reg_t;
+
+
+/** Group: func_out_sel_cfg */
+/** Type of func0_out_sel_cfg register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** oe_inv_sel : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t oe_inv_sel:1;
+        /** oe_sel : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t oe_sel:1;
+        /** out_inv_sel : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t out_inv_sel:1;
+        /** func_out_sel : R/W; bitpos: [8:3]; default: 32;
+         *  func_out_sel[5:1]==16 (s=32) -> output gpio register value to pad
+         */
+        uint32_t func_out_sel:6;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_gpio_func_out_sel_cfg_reg_t;
+
+
+typedef struct lp_gpio_dev_t {
+    volatile lp_gpio_clk_en_reg_t clk_en;
+    volatile lp_gpio_ver_date_reg_t ver_date;
+    volatile lp_gpio_out_reg_t out;
+    volatile lp_gpio_out_w1ts_reg_t out_w1ts;
+    volatile lp_gpio_out_w1tc_reg_t out_w1tc;
+    volatile lp_gpio_enable_reg_t enable;
+    volatile lp_gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile lp_gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile lp_gpio_status_reg_t status;
+    volatile lp_gpio_status_w1ts_reg_t status_w1ts;
+    volatile lp_gpio_status_w1tc_reg_t status_w1tc;
+    volatile lp_gpio_status_next_reg_t status_next;
+    volatile lp_gpio_in_reg_t in;
+    volatile lp_gpio_pin_reg_t pin[16];
+    volatile lp_gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[14];
+    uint32_t reserved_0ac[18];
+    volatile lp_gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[16];
+} lp_gpio_dev_t;
+
+extern lp_gpio_dev_t LP_GPIO;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_gpio_dev_t) == 0x134, "Invalid size of lp_gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_struct.h

@@ -0,0 +1,949 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: VAD registers */
+/** Type of vad_conf register
+ *  I2S VAD Configure register
+ */
+typedef union {
+    struct {
+        /** vad_en : R/W; bitpos: [0]; default: 0;
+         *  VAD enable register
+         */
+        uint32_t vad_en:1;
+        /** vad_reset : WT; bitpos: [1]; default: 0;
+         *  VAD reset register
+         */
+        uint32_t vad_reset:1;
+        /** vad_force_start : WT; bitpos: [2]; default: 0;
+         *  VAD force start register.
+         */
+        uint32_t vad_force_start:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_i2s_vad_conf_reg_t;
+
+/** Type of vad_result register
+ *  I2S VAD Result register
+ */
+typedef union {
+    struct {
+        /** vad_flag : RO; bitpos: [0]; default: 0;
+         *  Reg vad flag observe signal
+         */
+        uint32_t vad_flag:1;
+        /** energy_enough : RO; bitpos: [1]; default: 0;
+         *  Reg energy enough observe signal
+         */
+        uint32_t energy_enough:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_i2s_vad_result_reg_t;
+
+/** Type of vad_param0 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_min_energy : R/W; bitpos: [15:0]; default: 5000;
+         *  VAD parameter
+         */
+        uint32_t param_min_energy:16;
+        /** param_init_frame_num : R/W; bitpos: [24:16]; default: 200;
+         *  VAD parameter
+         */
+        uint32_t param_init_frame_num:9;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} lp_i2s_vad_param0_reg_t;
+
+/** Type of vad_param1 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_min_speech_count : R/W; bitpos: [3:0]; default: 3;
+         *  VAD parameter
+         */
+        uint32_t param_min_speech_count:4;
+        /** param_max_speech_count : R/W; bitpos: [10:4]; default: 100;
+         *  VAD parameter
+         */
+        uint32_t param_max_speech_count:7;
+        /** param_hangover_speech : R/W; bitpos: [15:11]; default: 3;
+         *  VAD parameter
+         */
+        uint32_t param_hangover_speech:5;
+        /** param_hangover_silent : R/W; bitpos: [23:16]; default: 30;
+         *  VAD parameter
+         */
+        uint32_t param_hangover_silent:8;
+        /** param_max_offset : R/W; bitpos: [30:24]; default: 40;
+         *  VAD parameter
+         */
+        uint32_t param_max_offset:7;
+        /** param_skip_band_energy : R/W; bitpos: [31]; default: 0;
+         *  Set 1 to skip band energy check.
+         */
+        uint32_t param_skip_band_energy:1;
+    };
+    uint32_t val;
+} lp_i2s_vad_param1_reg_t;
+
+/** Type of vad_param2 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_amp_down : R/W; bitpos: [15:0]; default: 26214;
+         *  VAD parameter
+         */
+        uint32_t param_noise_amp_down:16;
+        /** param_noise_amp_up : R/W; bitpos: [31:16]; default: 32440;
+         *  VAD parameter
+         */
+        uint32_t param_noise_amp_up:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param2_reg_t;
+
+/** Type of vad_param3 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_spe_up0 : R/W; bitpos: [15:0]; default: 32735;
+         *  VAD parameter
+         */
+        uint32_t param_noise_spe_up0:16;
+        /** param_noise_spe_up1 : R/W; bitpos: [31:16]; default: 32113;
+         *  VAD parameter
+         */
+        uint32_t param_noise_spe_up1:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param3_reg_t;
+
+/** Type of vad_param4 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_spe_down : R/W; bitpos: [15:0]; default: 26214;
+         *  VAD parameter
+         */
+        uint32_t param_noise_spe_down:16;
+        /** param_noise_mean_down : R/W; bitpos: [31:16]; default: 31130;
+         *  VAD parameter
+         */
+        uint32_t param_noise_mean_down:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param4_reg_t;
+
+/** Type of vad_param5 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_mean_up0 : R/W; bitpos: [15:0]; default: 32113;
+         *  VAD parameter
+         */
+        uint32_t param_noise_mean_up0:16;
+        /** param_noise_mean_up1 : R/W; bitpos: [31:16]; default: 31784;
+         *  VAD parameter
+         */
+        uint32_t param_noise_mean_up1:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param5_reg_t;
+
+/** Type of vad_param6 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_noise_std_fs_thsl : R/W; bitpos: [15:0]; default: 32000;
+         *  Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to
+         *  ((noise_std_max)>>11)^2*5
+         */
+        uint32_t param_noise_std_fs_thsl:16;
+        /** param_noise_std_fs_thsh : R/W; bitpos: [31:16]; default: 46080;
+         *  Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to
+         *  ((noise_std_max)>>11)^2*5
+         */
+        uint32_t param_noise_std_fs_thsh:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param6_reg_t;
+
+/** Type of vad_param7 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_thres_upd_base : R/W; bitpos: [15:0]; default: 32440;
+         *  VAD parameter
+         */
+        uint32_t param_thres_upd_base:16;
+        /** param_thres_upd_vary : R/W; bitpos: [31:16]; default: 328;
+         *  VAD parameter
+         */
+        uint32_t param_thres_upd_vary:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param7_reg_t;
+
+/** Type of vad_param8 register
+ *  I2S VAD Parameter register
+ */
+typedef union {
+    struct {
+        /** param_thres_upd_bdl : R/W; bitpos: [7:0]; default: 64;
+         *  Noise_std boundary low when updating threshold.
+         */
+        uint32_t param_thres_upd_bdl:8;
+        /** param_thres_upd_bdh : R/W; bitpos: [15:8]; default: 80;
+         *  Noise_std boundary high when updating threshold.
+         */
+        uint32_t param_thres_upd_bdh:8;
+        /** param_feature_burst : R/W; bitpos: [31:16]; default: 8192;
+         *  VAD parameter
+         */
+        uint32_t param_feature_burst:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_param8_reg_t;
+
+/** Type of vad_ob0 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** speech_count_ob : RO; bitpos: [7:0]; default: 0;
+         *  Reg silent count observe
+         */
+        uint32_t speech_count_ob:8;
+        /** silent_count_ob : RO; bitpos: [15:8]; default: 0;
+         *  Reg speech count observe
+         */
+        uint32_t silent_count_ob:8;
+        /** max_signal0_ob : RO; bitpos: [31:16]; default: 0;
+         *  Reg max signal0 observe
+         */
+        uint32_t max_signal0_ob:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob0_reg_t;
+
+/** Type of vad_ob1 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** max_signal1_ob : RO; bitpos: [15:0]; default: 0;
+         *  Reg max signal1 observe
+         */
+        uint32_t max_signal1_ob:16;
+        /** max_signal2_ob : RO; bitpos: [31:16]; default: 0;
+         *  Reg max signal2 observe
+         */
+        uint32_t max_signal2_ob:16;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob1_reg_t;
+
+/** Type of vad_ob2 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** noise_amp_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg noise_amp observe signal
+         */
+        uint32_t noise_amp_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob2_reg_t;
+
+/** Type of vad_ob3 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** noise_mean_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg noise_mean observe signal
+         */
+        uint32_t noise_mean_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob3_reg_t;
+
+/** Type of vad_ob4 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** noise_std_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg noise_std observe signal
+         */
+        uint32_t noise_std_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob4_reg_t;
+
+/** Type of vad_ob5 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** offset_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg offset observe signal
+         */
+        uint32_t offset_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob5_reg_t;
+
+/** Type of vad_ob6 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** threshold_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg threshold observe signal
+         */
+        uint32_t threshold_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob6_reg_t;
+
+/** Type of vad_ob7 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** energy_low_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg energy bit 31~0 observe signal
+         */
+        uint32_t energy_low_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob7_reg_t;
+
+/** Type of vad_ob8 register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** energy_high_ob : RO; bitpos: [31:0]; default: 0;
+         *  Reg energy bit 63~32 observe signal
+         */
+        uint32_t energy_high_ob:32;
+    };
+    uint32_t val;
+} lp_i2s_vad_ob8_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_mem_conf register
+ *  I2S VAD Observe register
+ */
+typedef union {
+    struct {
+        /** rx_mem_fifo_cnt : RO; bitpos: [8:0]; default: 0;
+         *  The number of data in the rx mem
+         */
+        uint32_t rx_mem_fifo_cnt:9;
+        /** rx_mem_threshold : R/W; bitpos: [16:9]; default: 63;
+         *  I2S rx mem will trigger an interrupt when the data in the mem is over(not including
+         *  equal) reg_rx_mem_threshold
+         */
+        uint32_t rx_mem_threshold:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_i2s_rx_mem_conf_reg_t;
+
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_fifomem_reset : WT; bitpos: [4]; default: 0;
+         *  Set this bit to reset Rx Syncfifomem
+         */
+        uint32_t rx_fifomem_reset:1;
+        /** rx_mono : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        uint32_t reserved_6:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_stop_mode : R/W; bitpos: [14:13]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} lp_i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
+         *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+         */
+        uint32_t rx_tdm_ws_width:7;
+        /** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        /** rx_bits_mod : R/W; bitpos: [17:13]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:6;
+        /** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+        /** rx_msb_shift : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_i2s_rx_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        uint32_t reserved_2:14;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rxeof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_i2s_rxeof_num_reg_t;
+
+/** Type of rx_pdm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} lp_i2s_rx_pdm_conf_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** rx_fifomem_udf_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_raw:1;
+        /** vad_done_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_raw:1;
+        /** vad_reset_done_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit  for the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_raw:1;
+        /** rx_mem_threshold_int_raw : RO/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit  for the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** rx_fifomem_udf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_st:1;
+        /** vad_done_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_st:1;
+        /** vad_reset_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit  for the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_st:1;
+        /** rx_mem_threshold_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit  for the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** rx_fifomem_udf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_ena:1;
+        /** vad_done_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_ena:1;
+        /** vad_reset_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit  for the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_ena:1;
+        /** rx_mem_threshold_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit  for the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** rx_fifomem_udf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_fifomem_udf_int interrupt
+         */
+        uint32_t rx_fifomem_udf_int_clr:1;
+        /** vad_done_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the vad_done_int interrupt
+         */
+        uint32_t vad_done_int_clr:1;
+        /** vad_reset_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the vad_reset_done_int interrupt
+         */
+        uint32_t vad_reset_done_int_clr:1;
+        /** rx_mem_threshold_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the rx_mem_threshold_int interrupt
+         */
+        uint32_t rx_mem_threshold_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} lp_i2s_int_clr_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:14;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_i2s_rx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_sigle_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} lp_i2s_conf_sigle_data_reg_t;
+
+
+/** Group: ECO registers */
+/** Type of eco_low register
+ *  I2S ECO register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  logic low eco registers
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} lp_i2s_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  I2S ECO register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  logic high eco registers
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} lp_i2s_eco_high_reg_t;
+
+/** Type of eco_conf register
+ *  I2S ECO register
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  enable rdn counter bit
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  rdn result
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} lp_i2s_eco_conf_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        /** vad_cg_force_on : R/W; bitpos: [1]; default: 1;
+         *  VAD clock gate force on register
+         */
+        uint32_t vad_cg_force_on:1;
+        /** rx_mem_cg_force_on : R/W; bitpos: [2]; default: 0;
+         *  I2S rx mem clock gate force on register
+         */
+        uint32_t rx_mem_cg_force_on:1;
+        /** rx_reg_cg_force_on : R/W; bitpos: [3]; default: 1;
+         *  I2S rx reg clock gate force on register
+         */
+        uint32_t rx_reg_cg_force_on:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720704;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_i2s_date_reg_t;
+
+
+typedef struct lp_i2s_dev_t {
+    volatile lp_i2s_vad_conf_reg_t vad_conf;
+    volatile lp_i2s_vad_result_reg_t vad_result;
+    volatile lp_i2s_rx_mem_conf_reg_t rx_mem_conf;
+    volatile lp_i2s_int_raw_reg_t int_raw;
+    volatile lp_i2s_int_st_reg_t int_st;
+    volatile lp_i2s_int_ena_reg_t int_ena;
+    volatile lp_i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile lp_i2s_rx_conf_reg_t rx_conf;
+    uint32_t reserved_024;
+    volatile lp_i2s_rx_conf1_reg_t rx_conf1;
+    uint32_t reserved_02c[9];
+    volatile lp_i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    uint32_t reserved_054;
+    volatile lp_i2s_rx_timing_reg_t rx_timing;
+    uint32_t reserved_05c;
+    volatile lp_i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile lp_i2s_rxeof_num_reg_t rxeof_num;
+    volatile lp_i2s_conf_sigle_data_reg_t conf_sigle_data;
+    uint32_t reserved_06c;
+    volatile lp_i2s_rx_pdm_conf_reg_t rx_pdm_conf;
+    volatile lp_i2s_eco_low_reg_t eco_low;
+    volatile lp_i2s_eco_high_reg_t eco_high;
+    volatile lp_i2s_eco_conf_reg_t eco_conf;
+    volatile lp_i2s_vad_param0_reg_t vad_param0;
+    volatile lp_i2s_vad_param1_reg_t vad_param1;
+    volatile lp_i2s_vad_param2_reg_t vad_param2;
+    volatile lp_i2s_vad_param3_reg_t vad_param3;
+    volatile lp_i2s_vad_param4_reg_t vad_param4;
+    volatile lp_i2s_vad_param5_reg_t vad_param5;
+    volatile lp_i2s_vad_param6_reg_t vad_param6;
+    volatile lp_i2s_vad_param7_reg_t vad_param7;
+    volatile lp_i2s_vad_param8_reg_t vad_param8;
+    uint32_t reserved_0a4[3];
+    volatile lp_i2s_vad_ob0_reg_t vad_ob0;
+    volatile lp_i2s_vad_ob1_reg_t vad_ob1;
+    volatile lp_i2s_vad_ob2_reg_t vad_ob2;
+    volatile lp_i2s_vad_ob3_reg_t vad_ob3;
+    volatile lp_i2s_vad_ob4_reg_t vad_ob4;
+    volatile lp_i2s_vad_ob5_reg_t vad_ob5;
+    volatile lp_i2s_vad_ob6_reg_t vad_ob6;
+    volatile lp_i2s_vad_ob7_reg_t vad_ob7;
+    volatile lp_i2s_vad_ob8_reg_t vad_ob8;
+    uint32_t reserved_0d4[9];
+    volatile lp_i2s_clk_gate_reg_t clk_gate;
+    volatile lp_i2s_date_reg_t date;
+} lp_i2s_dev_t;
+
+extern lp_i2s_dev_t LP_I2S;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_i2s_dev_t) == 0x100, "Invalid size of lp_i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_intr_reg.h

@@ -0,0 +1,235 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LPINTR_SW_INT_RAW_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_RAW_REG (DR_REG_LPINTR_BASE + 0x0)
+/** LPINTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_RAW    (BIT(31))
+#define LPINTR_LP_SW_INT_RAW_M  (LPINTR_LP_SW_INT_RAW_V << LPINTR_LP_SW_INT_RAW_S)
+#define LPINTR_LP_SW_INT_RAW_V  0x00000001U
+#define LPINTR_LP_SW_INT_RAW_S  31
+
+/** LPINTR_SW_INT_ST_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_ST_REG (DR_REG_LPINTR_BASE + 0x4)
+/** LPINTR_LP_SW_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_ST    (BIT(31))
+#define LPINTR_LP_SW_INT_ST_M  (LPINTR_LP_SW_INT_ST_V << LPINTR_LP_SW_INT_ST_S)
+#define LPINTR_LP_SW_INT_ST_V  0x00000001U
+#define LPINTR_LP_SW_INT_ST_S  31
+
+/** LPINTR_SW_INT_ENA_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_ENA_REG (DR_REG_LPINTR_BASE + 0x8)
+/** LPINTR_LP_SW_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_ENA    (BIT(31))
+#define LPINTR_LP_SW_INT_ENA_M  (LPINTR_LP_SW_INT_ENA_V << LPINTR_LP_SW_INT_ENA_S)
+#define LPINTR_LP_SW_INT_ENA_V  0x00000001U
+#define LPINTR_LP_SW_INT_ENA_S  31
+
+/** LPINTR_SW_INT_CLR_REG register
+ *  need_des
+ */
+#define LPINTR_SW_INT_CLR_REG (DR_REG_LPINTR_BASE + 0xc)
+/** LPINTR_LP_SW_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INT_CLR    (BIT(31))
+#define LPINTR_LP_SW_INT_CLR_M  (LPINTR_LP_SW_INT_CLR_V << LPINTR_LP_SW_INT_CLR_S)
+#define LPINTR_LP_SW_INT_CLR_V  0x00000001U
+#define LPINTR_LP_SW_INT_CLR_S  31
+
+/** LPINTR_STATUS_REG register
+ *  need_des
+ */
+#define LPINTR_STATUS_REG (DR_REG_LPINTR_BASE + 0x10)
+/** LPINTR_LP_HUK_INTR_ST : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_HUK_INTR_ST    (BIT(10))
+#define LPINTR_LP_HUK_INTR_ST_M  (LPINTR_LP_HUK_INTR_ST_V << LPINTR_LP_HUK_INTR_ST_S)
+#define LPINTR_LP_HUK_INTR_ST_V  0x00000001U
+#define LPINTR_LP_HUK_INTR_ST_S  10
+/** LPINTR_SYSREG_INTR_ST : RO; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LPINTR_SYSREG_INTR_ST    (BIT(11))
+#define LPINTR_SYSREG_INTR_ST_M  (LPINTR_SYSREG_INTR_ST_V << LPINTR_SYSREG_INTR_ST_S)
+#define LPINTR_SYSREG_INTR_ST_V  0x00000001U
+#define LPINTR_SYSREG_INTR_ST_S  11
+/** LPINTR_LP_SW_INTR_ST : RO; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SW_INTR_ST    (BIT(12))
+#define LPINTR_LP_SW_INTR_ST_M  (LPINTR_LP_SW_INTR_ST_V << LPINTR_LP_SW_INTR_ST_S)
+#define LPINTR_LP_SW_INTR_ST_V  0x00000001U
+#define LPINTR_LP_SW_INTR_ST_S  12
+/** LPINTR_LP_EFUSE_INTR_ST : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_EFUSE_INTR_ST    (BIT(13))
+#define LPINTR_LP_EFUSE_INTR_ST_M  (LPINTR_LP_EFUSE_INTR_ST_V << LPINTR_LP_EFUSE_INTR_ST_S)
+#define LPINTR_LP_EFUSE_INTR_ST_V  0x00000001U
+#define LPINTR_LP_EFUSE_INTR_ST_S  13
+/** LPINTR_LP_UART_INTR_ST : RO; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_UART_INTR_ST    (BIT(14))
+#define LPINTR_LP_UART_INTR_ST_M  (LPINTR_LP_UART_INTR_ST_V << LPINTR_LP_UART_INTR_ST_S)
+#define LPINTR_LP_UART_INTR_ST_V  0x00000001U
+#define LPINTR_LP_UART_INTR_ST_S  14
+/** LPINTR_LP_TSENS_INTR_ST : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TSENS_INTR_ST    (BIT(15))
+#define LPINTR_LP_TSENS_INTR_ST_M  (LPINTR_LP_TSENS_INTR_ST_V << LPINTR_LP_TSENS_INTR_ST_S)
+#define LPINTR_LP_TSENS_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TSENS_INTR_ST_S  15
+/** LPINTR_LP_TOUCH_INTR_ST : RO; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TOUCH_INTR_ST    (BIT(16))
+#define LPINTR_LP_TOUCH_INTR_ST_M  (LPINTR_LP_TOUCH_INTR_ST_V << LPINTR_LP_TOUCH_INTR_ST_S)
+#define LPINTR_LP_TOUCH_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TOUCH_INTR_ST_S  16
+/** LPINTR_LP_SPI_INTR_ST : RO; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_SPI_INTR_ST    (BIT(17))
+#define LPINTR_LP_SPI_INTR_ST_M  (LPINTR_LP_SPI_INTR_ST_V << LPINTR_LP_SPI_INTR_ST_S)
+#define LPINTR_LP_SPI_INTR_ST_V  0x00000001U
+#define LPINTR_LP_SPI_INTR_ST_S  17
+/** LPINTR_LP_I2S_INTR_ST : RO; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_I2S_INTR_ST    (BIT(18))
+#define LPINTR_LP_I2S_INTR_ST_M  (LPINTR_LP_I2S_INTR_ST_V << LPINTR_LP_I2S_INTR_ST_S)
+#define LPINTR_LP_I2S_INTR_ST_V  0x00000001U
+#define LPINTR_LP_I2S_INTR_ST_S  18
+/** LPINTR_LP_I2C_INTR_ST : RO; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_I2C_INTR_ST    (BIT(19))
+#define LPINTR_LP_I2C_INTR_ST_M  (LPINTR_LP_I2C_INTR_ST_V << LPINTR_LP_I2C_INTR_ST_S)
+#define LPINTR_LP_I2C_INTR_ST_V  0x00000001U
+#define LPINTR_LP_I2C_INTR_ST_S  19
+/** LPINTR_LP_GPIO_INTR_ST : RO; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_GPIO_INTR_ST    (BIT(20))
+#define LPINTR_LP_GPIO_INTR_ST_M  (LPINTR_LP_GPIO_INTR_ST_V << LPINTR_LP_GPIO_INTR_ST_S)
+#define LPINTR_LP_GPIO_INTR_ST_V  0x00000001U
+#define LPINTR_LP_GPIO_INTR_ST_S  20
+/** LPINTR_LP_ADC_INTR_ST : RO; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_ADC_INTR_ST    (BIT(21))
+#define LPINTR_LP_ADC_INTR_ST_M  (LPINTR_LP_ADC_INTR_ST_V << LPINTR_LP_ADC_INTR_ST_S)
+#define LPINTR_LP_ADC_INTR_ST_V  0x00000001U
+#define LPINTR_LP_ADC_INTR_ST_S  21
+/** LPINTR_ANAPERI_INTR_ST : RO; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define LPINTR_ANAPERI_INTR_ST    (BIT(22))
+#define LPINTR_ANAPERI_INTR_ST_M  (LPINTR_ANAPERI_INTR_ST_V << LPINTR_ANAPERI_INTR_ST_S)
+#define LPINTR_ANAPERI_INTR_ST_V  0x00000001U
+#define LPINTR_ANAPERI_INTR_ST_S  22
+/** LPINTR_PMU_REG_1_INTR_ST : RO; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define LPINTR_PMU_REG_1_INTR_ST    (BIT(23))
+#define LPINTR_PMU_REG_1_INTR_ST_M  (LPINTR_PMU_REG_1_INTR_ST_V << LPINTR_PMU_REG_1_INTR_ST_S)
+#define LPINTR_PMU_REG_1_INTR_ST_V  0x00000001U
+#define LPINTR_PMU_REG_1_INTR_ST_S  23
+/** LPINTR_PMU_REG_0_INTR_ST : RO; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LPINTR_PMU_REG_0_INTR_ST    (BIT(24))
+#define LPINTR_PMU_REG_0_INTR_ST_M  (LPINTR_PMU_REG_0_INTR_ST_V << LPINTR_PMU_REG_0_INTR_ST_S)
+#define LPINTR_PMU_REG_0_INTR_ST_V  0x00000001U
+#define LPINTR_PMU_REG_0_INTR_ST_S  24
+/** LPINTR_MB_LP_INTR_ST : RO; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LPINTR_MB_LP_INTR_ST    (BIT(25))
+#define LPINTR_MB_LP_INTR_ST_M  (LPINTR_MB_LP_INTR_ST_V << LPINTR_MB_LP_INTR_ST_S)
+#define LPINTR_MB_LP_INTR_ST_V  0x00000001U
+#define LPINTR_MB_LP_INTR_ST_S  25
+/** LPINTR_MB_HP_INTR_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LPINTR_MB_HP_INTR_ST    (BIT(26))
+#define LPINTR_MB_HP_INTR_ST_M  (LPINTR_MB_HP_INTR_ST_V << LPINTR_MB_HP_INTR_ST_S)
+#define LPINTR_MB_HP_INTR_ST_V  0x00000001U
+#define LPINTR_MB_HP_INTR_ST_S  26
+/** LPINTR_LP_TIMER_REG_1_INTR_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TIMER_REG_1_INTR_ST    (BIT(27))
+#define LPINTR_LP_TIMER_REG_1_INTR_ST_M  (LPINTR_LP_TIMER_REG_1_INTR_ST_V << LPINTR_LP_TIMER_REG_1_INTR_ST_S)
+#define LPINTR_LP_TIMER_REG_1_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TIMER_REG_1_INTR_ST_S  27
+/** LPINTR_LP_TIMER_REG_0_INTR_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_TIMER_REG_0_INTR_ST    (BIT(28))
+#define LPINTR_LP_TIMER_REG_0_INTR_ST_M  (LPINTR_LP_TIMER_REG_0_INTR_ST_V << LPINTR_LP_TIMER_REG_0_INTR_ST_S)
+#define LPINTR_LP_TIMER_REG_0_INTR_ST_V  0x00000001U
+#define LPINTR_LP_TIMER_REG_0_INTR_ST_S  28
+/** LPINTR_LP_WDT_INTR_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_WDT_INTR_ST    (BIT(29))
+#define LPINTR_LP_WDT_INTR_ST_M  (LPINTR_LP_WDT_INTR_ST_V << LPINTR_LP_WDT_INTR_ST_S)
+#define LPINTR_LP_WDT_INTR_ST_V  0x00000001U
+#define LPINTR_LP_WDT_INTR_ST_S  29
+/** LPINTR_LP_RTC_INTR_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LPINTR_LP_RTC_INTR_ST    (BIT(30))
+#define LPINTR_LP_RTC_INTR_ST_M  (LPINTR_LP_RTC_INTR_ST_V << LPINTR_LP_RTC_INTR_ST_S)
+#define LPINTR_LP_RTC_INTR_ST_V  0x00000001U
+#define LPINTR_LP_RTC_INTR_ST_S  30
+/** LPINTR_HP_INTR_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_HP_INTR_ST    (BIT(31))
+#define LPINTR_HP_INTR_ST_M  (LPINTR_HP_INTR_ST_V << LPINTR_HP_INTR_ST_S)
+#define LPINTR_HP_INTR_ST_V  0x00000001U
+#define LPINTR_HP_INTR_ST_S  31
+
+/** LPINTR_DATE_REG register
+ *  need_des
+ */
+#define LPINTR_DATE_REG (DR_REG_LPINTR_BASE + 0x3fc)
+/** LPINTR_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPINTR_CLK_EN    (BIT(31))
+#define LPINTR_CLK_EN_M  (LPINTR_CLK_EN_V << LPINTR_CLK_EN_S)
+#define LPINTR_CLK_EN_V  0x00000001U
+#define LPINTR_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_intr_struct.h

@@ -0,0 +1,205 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of sw_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_raw : R/W/WTC; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_raw:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_raw_reg_t;
+
+/** Type of sw_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_st:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_st_reg_t;
+
+/** Type of sw_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_ena:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_ena_reg_t;
+
+/** Type of sw_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lp_sw_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_int_clr:1;
+    };
+    uint32_t val;
+} lpintr_sw_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** lp_huk_intr_st : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_huk_intr_st:1;
+        /** sysreg_intr_st : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t sysreg_intr_st:1;
+        /** lp_sw_intr_st : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_sw_intr_st:1;
+        /** lp_efuse_intr_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_efuse_intr_st:1;
+        /** lp_uart_intr_st : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_intr_st:1;
+        /** lp_tsens_intr_st : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_tsens_intr_st:1;
+        /** lp_touch_intr_st : RO; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_touch_intr_st:1;
+        /** lp_spi_intr_st : RO; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_spi_intr_st:1;
+        /** lp_i2s_intr_st : RO; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_intr_st:1;
+        /** lp_i2c_intr_st : RO; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2c_intr_st:1;
+        /** lp_gpio_intr_st : RO; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_gpio_intr_st:1;
+        /** lp_adc_intr_st : RO; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_adc_intr_st:1;
+        /** anaperi_intr_st : RO; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t anaperi_intr_st:1;
+        /** pmu_reg_1_intr_st : RO; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_reg_1_intr_st:1;
+        /** pmu_reg_0_intr_st : RO; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t pmu_reg_0_intr_st:1;
+        /** mb_lp_intr_st : RO; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t mb_lp_intr_st:1;
+        /** mb_hp_intr_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t mb_hp_intr_st:1;
+        /** lp_timer_reg_1_intr_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_timer_reg_1_intr_st:1;
+        /** lp_timer_reg_0_intr_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_timer_reg_0_intr_st:1;
+        /** lp_wdt_intr_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_intr_st:1;
+        /** lp_rtc_intr_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_rtc_intr_st:1;
+        /** hp_intr_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_intr_st:1;
+    };
+    uint32_t val;
+} lpintr_status_reg_t;
+
+
+/** Group: configure_register */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lpintr_date_reg_t;
+
+
+typedef struct {
+    volatile lpintr_sw_int_raw_reg_t sw_int_raw;
+    volatile lpintr_sw_int_st_reg_t sw_int_st;
+    volatile lpintr_sw_int_ena_reg_t sw_int_ena;
+    volatile lpintr_sw_int_clr_reg_t sw_int_clr;
+    volatile lpintr_status_reg_t status;
+    uint32_t reserved_014[250];
+    volatile lpintr_date_reg_t date;
+} lpintr_dev_t;
+
+extern lpintr_dev_t LP_INTR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lpintr_dev_t) == 0x400, "Invalid size of lpintr_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_struct.h

@@ -0,0 +1,166 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_iomux_clk_en_reg_t;
+
+
+/** Group: ver_date */
+/** Type of ver_date register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [27:0]; default: 2294547;
+         *  Reserved
+         */
+        uint32_t reg_ver_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_iomux_ver_date_reg_t;
+
+
+/** Group: pad */
+/** Type of pad register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** drv : R/W; bitpos: [1:0]; default: 2;
+         *  Reserved
+         */
+        uint32_t drv:2;
+        /** rde : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t rde:1;
+        /** rue : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t rue:1;
+        /** mux_sel : R/W; bitpos: [4]; default: 0;
+         *  1:use LP GPIO,0: use digital GPIO
+         */
+        uint32_t mux_sel:1;
+        /** fun_sel : R/W; bitpos: [6:5]; default: 0;
+         *  function sel
+         */
+        uint32_t fun_sel:2;
+        /** slp_sel : R/W; bitpos: [7]; default: 0;
+         *  1: enable sleep mode during sleep,0: no sleep mode
+         */
+        uint32_t slp_sel:1;
+        /** slp_ie : R/W; bitpos: [8]; default: 0;
+         *  input enable in sleep mode
+         */
+        uint32_t slp_ie:1;
+        /** slp_oe : R/W; bitpos: [9]; default: 0;
+         *  output enable in sleep mode
+         */
+        uint32_t slp_oe:1;
+        /** fun_ie : R/W; bitpos: [10]; default: 0;
+         *  input enable in work mode
+        */
+        uint32_t fun_ie:1;
+        /** filter_en : R/W; bitpos: [11]; default: 0;
+         *  need des
+         */
+        uint32_t filter_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_iomux_pad_reg_t;
+
+
+/** Group: ext_wakeup0_sel */
+/** Type of ext_wakeup0_sel register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_xtl_ext_ctr_sel : R/W; bitpos: [4:0]; default: 0;
+         *  select LP GPIO 0 ~ 15 to control XTAL
+         */
+        uint32_t reg_xtl_ext_ctr_sel:5;
+        /** reg_ext_wakeup0_sel : R/W; bitpos: [9:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ext_wakeup0_sel:5;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} lp_iomux_ext_wakeup0_sel_reg_t;
+
+
+/** Group: lp_pad_hold */
+/** Type of lp_pad_hold register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lp_gpio_hold:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_iomux_lp_pad_hold_reg_t;
+
+
+/** Group: lp_pad_hys */
+/** Type of lp_pad_hys register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_lp_gpio_hys : R/W; bitpos: [15:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lp_gpio_hys:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_iomux_lp_pad_hys_reg_t;
+
+
+typedef struct lp_iomux_dev_t {
+    volatile lp_iomux_clk_en_reg_t clk_en;
+    volatile lp_iomux_ver_date_reg_t ver_date;
+    volatile lp_iomux_pad_reg_t pad[16];
+    volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
+    volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
+    volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
+} lp_iomux_dev_t;
+
+extern lp_iomux_dev_t LP_IOMUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_iomux_dev_t) == 0x54, "Invalid size of lp_iomux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_struct.h

@@ -0,0 +1,867 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of massege_0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_0:32;
+    };
+    uint32_t val;
+} mb_massege_0_reg_t;
+
+/** Type of massege_1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_1:32;
+    };
+    uint32_t val;
+} mb_massege_1_reg_t;
+
+/** Type of massege_2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_2 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_2:32;
+    };
+    uint32_t val;
+} mb_massege_2_reg_t;
+
+/** Type of massege_3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_3 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_3:32;
+    };
+    uint32_t val;
+} mb_massege_3_reg_t;
+
+/** Type of massege_4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_4 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_4:32;
+    };
+    uint32_t val;
+} mb_massege_4_reg_t;
+
+/** Type of massege_5 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_5 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_5:32;
+    };
+    uint32_t val;
+} mb_massege_5_reg_t;
+
+/** Type of massege_6 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_6 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_6:32;
+    };
+    uint32_t val;
+} mb_massege_6_reg_t;
+
+/** Type of massege_7 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_7 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_7:32;
+    };
+    uint32_t val;
+} mb_massege_7_reg_t;
+
+/** Type of massege_8 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_8 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_8:32;
+    };
+    uint32_t val;
+} mb_massege_8_reg_t;
+
+/** Type of massege_9 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_9 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_9:32;
+    };
+    uint32_t val;
+} mb_massege_9_reg_t;
+
+/** Type of massege_10 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_10 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_10:32;
+    };
+    uint32_t val;
+} mb_massege_10_reg_t;
+
+/** Type of massege_11 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_11 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_11:32;
+    };
+    uint32_t val;
+} mb_massege_11_reg_t;
+
+/** Type of massege_12 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_12 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_12:32;
+    };
+    uint32_t val;
+} mb_massege_12_reg_t;
+
+/** Type of massege_13 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_13 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_13:32;
+    };
+    uint32_t val;
+} mb_massege_13_reg_t;
+
+/** Type of massege_14 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_14 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_14:32;
+    };
+    uint32_t val;
+} mb_massege_14_reg_t;
+
+/** Type of massege_15 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** massege_15 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t massege_15:32;
+    };
+    uint32_t val;
+} mb_massege_15_reg_t;
+
+/** Type of reg_clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mb_reg_clk_en_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_raw : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_0_int_raw:1;
+        /** lp_1_int_raw : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_1_int_raw:1;
+        /** lp_2_int_raw : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_2_int_raw:1;
+        /** lp_3_int_raw : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_3_int_raw:1;
+        /** lp_4_int_raw : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_4_int_raw:1;
+        /** lp_5_int_raw : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_5_int_raw:1;
+        /** lp_6_int_raw : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_6_int_raw:1;
+        /** lp_7_int_raw : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_7_int_raw:1;
+        /** lp_8_int_raw : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_raw:1;
+        /** lp_9_int_raw : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_raw:1;
+        /** lp_10_int_raw : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_raw:1;
+        /** lp_11_int_raw : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_raw:1;
+        /** lp_12_int_raw : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_raw:1;
+        /** lp_13_int_raw : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_raw:1;
+        /** lp_14_int_raw : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_raw:1;
+        /** lp_15_int_raw : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_0_int_st:1;
+        /** lp_1_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_1_int_st:1;
+        /** lp_2_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_2_int_st:1;
+        /** lp_3_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_3_int_st:1;
+        /** lp_4_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_4_int_st:1;
+        /** lp_5_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_5_int_st:1;
+        /** lp_6_int_st : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_6_int_st:1;
+        /** lp_7_int_st : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_7_int_st:1;
+        /** lp_8_int_st : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_st:1;
+        /** lp_9_int_st : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_st:1;
+        /** lp_10_int_st : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_st:1;
+        /** lp_11_int_st : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_st:1;
+        /** lp_12_int_st : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_st:1;
+        /** lp_13_int_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_st:1;
+        /** lp_14_int_st : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_st:1;
+        /** lp_15_int_st : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_ena : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_0_int_ena:1;
+        /** lp_1_int_ena : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_1_int_ena:1;
+        /** lp_2_int_ena : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_2_int_ena:1;
+        /** lp_3_int_ena : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_3_int_ena:1;
+        /** lp_4_int_ena : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_4_int_ena:1;
+        /** lp_5_int_ena : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_5_int_ena:1;
+        /** lp_6_int_ena : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_6_int_ena:1;
+        /** lp_7_int_ena : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_7_int_ena:1;
+        /** lp_8_int_ena : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_ena:1;
+        /** lp_9_int_ena : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_ena:1;
+        /** lp_10_int_ena : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_ena:1;
+        /** lp_11_int_ena : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_ena:1;
+        /** lp_12_int_ena : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_ena:1;
+        /** lp_13_int_ena : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_ena:1;
+        /** lp_14_int_ena : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_ena:1;
+        /** lp_15_int_ena : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_0_int_clr : WO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_0_int_clr:1;
+        /** lp_1_int_clr : WO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_1_int_clr:1;
+        /** lp_2_int_clr : WO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_2_int_clr:1;
+        /** lp_3_int_clr : WO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_3_int_clr:1;
+        /** lp_4_int_clr : WO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_4_int_clr:1;
+        /** lp_5_int_clr : WO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_5_int_clr:1;
+        /** lp_6_int_clr : WO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_6_int_clr:1;
+        /** lp_7_int_clr : WO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_7_int_clr:1;
+        /** lp_8_int_clr : WO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_8_int_clr:1;
+        /** lp_9_int_clr : WO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_9_int_clr:1;
+        /** lp_10_int_clr : WO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_10_int_clr:1;
+        /** lp_11_int_clr : WO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_11_int_clr:1;
+        /** lp_12_int_clr : WO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_12_int_clr:1;
+        /** lp_13_int_clr : WO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_13_int_clr:1;
+        /** lp_14_int_clr : WO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_14_int_clr:1;
+        /** lp_15_int_clr : WO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_15_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_lp_int_clr_reg_t;
+
+/** Type of hp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_raw : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_0_int_raw:1;
+        /** hp_1_int_raw : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_1_int_raw:1;
+        /** hp_2_int_raw : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_2_int_raw:1;
+        /** hp_3_int_raw : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_3_int_raw:1;
+        /** hp_4_int_raw : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_4_int_raw:1;
+        /** hp_5_int_raw : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_5_int_raw:1;
+        /** hp_6_int_raw : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_6_int_raw:1;
+        /** hp_7_int_raw : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_7_int_raw:1;
+        /** hp_8_int_raw : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_raw:1;
+        /** hp_9_int_raw : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_raw:1;
+        /** hp_10_int_raw : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_raw:1;
+        /** hp_11_int_raw : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_raw:1;
+        /** hp_12_int_raw : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_raw:1;
+        /** hp_13_int_raw : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_raw:1;
+        /** hp_14_int_raw : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_raw:1;
+        /** hp_15_int_raw : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_raw_reg_t;
+
+/** Type of hp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_0_int_st:1;
+        /** hp_1_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_1_int_st:1;
+        /** hp_2_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_2_int_st:1;
+        /** hp_3_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_3_int_st:1;
+        /** hp_4_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_4_int_st:1;
+        /** hp_5_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_5_int_st:1;
+        /** hp_6_int_st : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_6_int_st:1;
+        /** hp_7_int_st : RO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_7_int_st:1;
+        /** hp_8_int_st : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_st:1;
+        /** hp_9_int_st : RO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_st:1;
+        /** hp_10_int_st : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_st:1;
+        /** hp_11_int_st : RO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_st:1;
+        /** hp_12_int_st : RO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_st:1;
+        /** hp_13_int_st : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_st:1;
+        /** hp_14_int_st : RO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_st:1;
+        /** hp_15_int_st : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_st_reg_t;
+
+/** Type of hp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_ena : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_0_int_ena:1;
+        /** hp_1_int_ena : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_1_int_ena:1;
+        /** hp_2_int_ena : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_2_int_ena:1;
+        /** hp_3_int_ena : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_3_int_ena:1;
+        /** hp_4_int_ena : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_4_int_ena:1;
+        /** hp_5_int_ena : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_5_int_ena:1;
+        /** hp_6_int_ena : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_6_int_ena:1;
+        /** hp_7_int_ena : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t hp_7_int_ena:1;
+        /** hp_8_int_ena : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_ena:1;
+        /** hp_9_int_ena : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_ena:1;
+        /** hp_10_int_ena : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_ena:1;
+        /** hp_11_int_ena : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_ena:1;
+        /** hp_12_int_ena : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_ena:1;
+        /** hp_13_int_ena : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_ena:1;
+        /** hp_14_int_ena : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_ena:1;
+        /** hp_15_int_ena : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_ena_reg_t;
+
+/** Type of hp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hp_0_int_clr : WO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_0_int_clr:1;
+        /** hp_1_int_clr : WO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_1_int_clr:1;
+        /** hp_2_int_clr : WO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_2_int_clr:1;
+        /** hp_3_int_clr : WO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_3_int_clr:1;
+        /** hp_4_int_clr : WO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_4_int_clr:1;
+        /** hp_5_int_clr : WO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_5_int_clr:1;
+        /** hp_6_int_clr : WO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_6_int_clr:1;
+        /** hp_7_int_clr : WO; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_7_int_clr:1;
+        /** hp_8_int_clr : WO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_8_int_clr:1;
+        /** hp_9_int_clr : WO; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_9_int_clr:1;
+        /** hp_10_int_clr : WO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_10_int_clr:1;
+        /** hp_11_int_clr : WO; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_11_int_clr:1;
+        /** hp_12_int_clr : WO; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_12_int_clr:1;
+        /** hp_13_int_clr : WO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_13_int_clr:1;
+        /** hp_14_int_clr : WO; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_14_int_clr:1;
+        /** hp_15_int_clr : WO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t hp_15_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mb_hp_int_clr_reg_t;
+
+
+typedef struct {
+    volatile mb_massege_0_reg_t massege_0;
+    volatile mb_massege_1_reg_t massege_1;
+    volatile mb_massege_2_reg_t massege_2;
+    volatile mb_massege_3_reg_t massege_3;
+    volatile mb_massege_4_reg_t massege_4;
+    volatile mb_massege_5_reg_t massege_5;
+    volatile mb_massege_6_reg_t massege_6;
+    volatile mb_massege_7_reg_t massege_7;
+    volatile mb_massege_8_reg_t massege_8;
+    volatile mb_massege_9_reg_t massege_9;
+    volatile mb_massege_10_reg_t massege_10;
+    volatile mb_massege_11_reg_t massege_11;
+    volatile mb_massege_12_reg_t massege_12;
+    volatile mb_massege_13_reg_t massege_13;
+    volatile mb_massege_14_reg_t massege_14;
+    volatile mb_massege_15_reg_t massege_15;
+    volatile mb_lp_int_raw_reg_t lp_int_raw;
+    volatile mb_lp_int_st_reg_t lp_int_st;
+    volatile mb_lp_int_ena_reg_t lp_int_ena;
+    volatile mb_lp_int_clr_reg_t lp_int_clr;
+    volatile mb_hp_int_raw_reg_t hp_int_raw;
+    volatile mb_hp_int_st_reg_t hp_int_st;
+    volatile mb_hp_int_ena_reg_t hp_int_ena;
+    volatile mb_hp_int_clr_reg_t hp_int_clr;
+    volatile mb_reg_clk_en_reg_t reg_clk_en;
+} mb_dev_t;
+
+extern mb_dev_t LP_MAILBOX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mb_dev_t) == 0x64, "Invalid size of mb_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_eco5_reg.h

@@ -0,0 +1,492 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_LP_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M  (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M  (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_LP_MM_LP_PMU_ALLOW_M  (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S)
+#define TEE_REG_LP_MM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_PMU_ALLOW_S  4
+/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_LP_MM_LP_WDT_ALLOW_M  (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S)
+#define TEE_REG_LP_MM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_WDT_ALLOW_S  5
+/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_LP_MM_LP_RTC_ALLOW_M  (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S)
+#define TEE_REG_LP_MM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_RTC_ALLOW_S  7
+/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_LP_MM_LP_UART_ALLOW_M  (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S)
+#define TEE_REG_LP_MM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_UART_ALLOW_S  9
+/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_LP_MM_LP_I2C_ALLOW_M  (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S)
+#define TEE_REG_LP_MM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_I2C_ALLOW_S  10
+/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_LP_MM_LP_SPI_ALLOW_M  (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S)
+#define TEE_REG_LP_MM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_SPI_ALLOW_S  11
+/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M  (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_LP_MM_LP_I2S_ALLOW_M  (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S)
+#define TEE_REG_LP_MM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_I2S_ALLOW_S  13
+/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_LP_MM_LP_ADC_ALLOW_M  (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S)
+#define TEE_REG_LP_MM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_ADC_ALLOW_S  14
+/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M  (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M  (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_LP_MM_LP_INTR_ALLOW_M  (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S)
+#define TEE_REG_LP_MM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_INTR_ALLOW_S  17
+/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M  (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_LP_MM_LP_PMS_ALLOW_M  (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_PMS_ALLOW_S  19
+/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M  (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_LP_MM_LP_HUK_ALLOW_M  (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S)
+#define TEE_REG_LP_MM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_HUK_ALLOW_S  22
+/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW_M  (TEE_REG_LP_MM_LP_TRNG_ALLOW_V << TEE_REG_LP_MM_LP_TRNG_ALLOW_S)
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_LP_MM_LP_TRNG_ALLOW_S  24
+
+/** TEE_PERI_REGION0_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION0_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_LOW_M  (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S)
+#define TEE_REG_PERI_REGION0_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_LOW_S  2
+
+/** TEE_PERI_REGION0_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION0_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_HIGH_M  (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S)
+#define TEE_REG_PERI_REGION0_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION0_HIGH_S  2
+
+/** TEE_PERI_REGION1_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION1_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_LOW_M  (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S)
+#define TEE_REG_PERI_REGION1_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_LOW_S  2
+
+/** TEE_PERI_REGION1_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION1_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_HIGH_M  (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S)
+#define TEE_REG_PERI_REGION1_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION1_HIGH_S  2
+
+/** TEE_PERI_REGION_PMS_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c)
+/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
+ *  NA
+ */
+#define TEE_REG_LP_CORE_REGION_PMS    0x00000003U
+#define TEE_REG_LP_CORE_REGION_PMS_M  (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S)
+#define TEE_REG_LP_CORE_REGION_PMS_V  0x00000003U
+#define TEE_REG_LP_CORE_REGION_PMS_S  0
+/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE0_UM_REGION_PMS_M  (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S)
+#define TEE_REG_HP_CORE0_UM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE0_UM_REGION_PMS_S  2
+/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE0_MM_REGION_PMS_M  (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S)
+#define TEE_REG_HP_CORE0_MM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE0_MM_REGION_PMS_S  4
+/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE1_UM_REGION_PMS_M  (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S)
+#define TEE_REG_HP_CORE1_UM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE1_UM_REGION_PMS_S  6
+/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_REGION_PMS    0x00000003U
+#define TEE_REG_HP_CORE1_MM_REGION_PMS_M  (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S)
+#define TEE_REG_HP_CORE1_MM_REGION_PMS_V  0x00000003U
+#define TEE_REG_HP_CORE1_MM_REGION_PMS_S  8
+
+/** TEE_PERI_REGION_2_TO_7_PMS_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION_2_TO_7_PMS_REG (DR_REG_TEE_BASE + 0x20)
+/** TEE_REG_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63;
+ *  NA
+ */
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_M  (TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V << TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S)
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S  0
+/** TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S  6
+/** TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S  12
+/** TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S  18
+/** TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS    0x0000003FU
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_M  (TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S)
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V  0x0000003FU
+#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S  24
+
+/** TEE_PERI_REGION2_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION2_LOW_REG (DR_REG_TEE_BASE + 0x24)
+/** TEE_REG_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION2_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_LOW_M  (TEE_REG_PERI_REGION2_LOW_V << TEE_REG_PERI_REGION2_LOW_S)
+#define TEE_REG_PERI_REGION2_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_LOW_S  2
+
+/** TEE_PERI_REGION2_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION2_HIGH_REG (DR_REG_TEE_BASE + 0x28)
+/** TEE_REG_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION2_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_HIGH_M  (TEE_REG_PERI_REGION2_HIGH_V << TEE_REG_PERI_REGION2_HIGH_S)
+#define TEE_REG_PERI_REGION2_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION2_HIGH_S  2
+
+/** TEE_PERI_REGION3_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION3_LOW_REG (DR_REG_TEE_BASE + 0x2c)
+/** TEE_REG_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION3_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_LOW_M  (TEE_REG_PERI_REGION3_LOW_V << TEE_REG_PERI_REGION3_LOW_S)
+#define TEE_REG_PERI_REGION3_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_LOW_S  2
+
+/** TEE_PERI_REGION3_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION3_HIGH_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_REG_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION3_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_HIGH_M  (TEE_REG_PERI_REGION3_HIGH_V << TEE_REG_PERI_REGION3_HIGH_S)
+#define TEE_REG_PERI_REGION3_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION3_HIGH_S  2
+
+/** TEE_PERI_REGION4_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION4_LOW_REG (DR_REG_TEE_BASE + 0x34)
+/** TEE_REG_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION4_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_LOW_M  (TEE_REG_PERI_REGION4_LOW_V << TEE_REG_PERI_REGION4_LOW_S)
+#define TEE_REG_PERI_REGION4_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_LOW_S  2
+
+/** TEE_PERI_REGION4_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION4_HIGH_REG (DR_REG_TEE_BASE + 0x38)
+/** TEE_REG_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION4_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_HIGH_M  (TEE_REG_PERI_REGION4_HIGH_V << TEE_REG_PERI_REGION4_HIGH_S)
+#define TEE_REG_PERI_REGION4_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION4_HIGH_S  2
+
+/** TEE_PERI_REGION5_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION5_LOW_REG (DR_REG_TEE_BASE + 0x3c)
+/** TEE_REG_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION5_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_LOW_M  (TEE_REG_PERI_REGION5_LOW_V << TEE_REG_PERI_REGION5_LOW_S)
+#define TEE_REG_PERI_REGION5_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_LOW_S  2
+
+/** TEE_PERI_REGION5_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION5_HIGH_REG (DR_REG_TEE_BASE + 0x40)
+/** TEE_REG_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION5_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_HIGH_M  (TEE_REG_PERI_REGION5_HIGH_V << TEE_REG_PERI_REGION5_HIGH_S)
+#define TEE_REG_PERI_REGION5_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION5_HIGH_S  2
+
+/** TEE_PERI_REGION6_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION6_LOW_REG (DR_REG_TEE_BASE + 0x44)
+/** TEE_REG_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION6_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_LOW_M  (TEE_REG_PERI_REGION6_LOW_V << TEE_REG_PERI_REGION6_LOW_S)
+#define TEE_REG_PERI_REGION6_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_LOW_S  2
+
+/** TEE_PERI_REGION6_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION6_HIGH_REG (DR_REG_TEE_BASE + 0x48)
+/** TEE_REG_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION6_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_HIGH_M  (TEE_REG_PERI_REGION6_HIGH_V << TEE_REG_PERI_REGION6_HIGH_S)
+#define TEE_REG_PERI_REGION6_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION6_HIGH_S  2
+
+/** TEE_PERI_REGION7_LOW_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION7_LOW_REG (DR_REG_TEE_BASE + 0x4c)
+/** TEE_REG_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION7_LOW    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_LOW_M  (TEE_REG_PERI_REGION7_LOW_V << TEE_REG_PERI_REGION7_LOW_S)
+#define TEE_REG_PERI_REGION7_LOW_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_LOW_S  2
+
+/** TEE_PERI_REGION7_HIGH_REG register
+ *  NA
+ */
+#define TEE_PERI_REGION7_HIGH_REG (DR_REG_TEE_BASE + 0x50)
+/** TEE_REG_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  NA
+ */
+#define TEE_REG_PERI_REGION7_HIGH    0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_HIGH_M  (TEE_REG_PERI_REGION7_HIGH_V << TEE_REG_PERI_REGION7_HIGH_S)
+#define TEE_REG_PERI_REGION7_HIGH_V  0x3FFFFFFFU
+#define TEE_REG_PERI_REGION7_HIGH_S  2
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_reg.h

@@ -0,0 +1,377 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_LP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0)
+/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
+ *  Version control register
+ */
+#define PMS_LP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_LP_PERI_PMS_DATE_M  (PMS_LP_PERI_PMS_DATE_V << PMS_LP_PERI_PMS_DATE_S)
+#define PMS_LP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_LP_PERI_PMS_DATE_S  0
+
+/** PMS_LP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_LP_PERI_PMS_BASE + 0x4)
+/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
+ */
+#define PMS_LP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_LP_PERI_PMS_CLK_EN_M  (PMS_LP_PERI_PMS_CLK_EN_V << PMS_LP_PERI_PMS_CLK_EN_S)
+#define PMS_LP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_LP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for LP CPU in machine mode
+ */
+#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_LP_PERI_PMS_BASE + 0x8)
+/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP system
+ *  registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_LP_MM_LP_SYSREG_ALLOW_M  (PMS_LP_MM_LP_SYSREG_ALLOW_V << PMS_LP_MM_LP_SYSREG_ALLOW_S)
+#define PMS_LP_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
+ *  always-on clock and reset).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_M  (PMS_LP_MM_LP_AONCLKRST_ALLOW_V << PMS_LP_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_LP_MM_LP_TIMER_ALLOW_M  (PMS_LP_MM_LP_TIMER_ALLOW_V << PMS_LP_MM_LP_TIMER_ALLOW_S)
+#define PMS_LP_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TIMER_ALLOW_S  2
+/** PMS_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP ANAPERI
+ *  (analog peripherals).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_M  (PMS_LP_MM_LP_ANAPERI_ALLOW_V << PMS_LP_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP PMU (Power
+ *  Management Unit).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_LP_MM_LP_PMU_ALLOW_M  (PMS_LP_MM_LP_PMU_ALLOW_V << PMS_LP_MM_LP_PMU_ALLOW_S)
+#define PMS_LP_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PMU_ALLOW_S  4
+/** PMS_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
+ *  timer).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_LP_MM_LP_WDT_ALLOW_M  (PMS_LP_MM_LP_WDT_ALLOW_V << PMS_LP_MM_LP_WDT_ALLOW_S)
+#define PMS_LP_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_WDT_ALLOW_S  5
+/** PMS_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_M  (PMS_LP_MM_LP_MAILBOX_ALLOW_V << PMS_LP_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_LP_MM_LP_RTC_ALLOW_M  (PMS_LP_MM_LP_RTC_ALLOW_V << PMS_LP_MM_LP_RTC_ALLOW_S)
+#define PMS_LP_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_RTC_ALLOW_S  7
+/** PMS_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access  LP PREICLKRST
+ *  (peripheral clock and reset).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_M  (PMS_LP_MM_LP_PERICLKRST_ALLOW_V << PMS_LP_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access  LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_LP_MM_LP_UART_ALLOW_M  (PMS_LP_MM_LP_UART_ALLOW_V << PMS_LP_MM_LP_UART_ALLOW_S)
+#define PMS_LP_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_UART_ALLOW_S  9
+/** PMS_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_LP_MM_LP_I2C_ALLOW_M  (PMS_LP_MM_LP_I2C_ALLOW_V << PMS_LP_MM_LP_I2C_ALLOW_S)
+#define PMS_LP_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2C_ALLOW_S  10
+/** PMS_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_LP_MM_LP_SPI_ALLOW_M  (PMS_LP_MM_LP_SPI_ALLOW_V << PMS_LP_MM_LP_SPI_ALLOW_S)
+#define PMS_LP_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SPI_ALLOW_S  11
+/** PMS_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_LP_MM_LP_I2CMST_ALLOW_M  (PMS_LP_MM_LP_I2CMST_ALLOW_V << PMS_LP_MM_LP_I2CMST_ALLOW_S)
+#define PMS_LP_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_LP_MM_LP_I2S_ALLOW_M  (PMS_LP_MM_LP_I2S_ALLOW_V << PMS_LP_MM_LP_I2S_ALLOW_S)
+#define PMS_LP_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2S_ALLOW_S  13
+/** PMS_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_LP_MM_LP_ADC_ALLOW_M  (PMS_LP_MM_LP_ADC_ALLOW_V << PMS_LP_MM_LP_ADC_ALLOW_S)
+#define PMS_LP_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_ADC_ALLOW_S  14
+/** PMS_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_LP_MM_LP_TOUCH_ALLOW_M  (PMS_LP_MM_LP_TOUCH_ALLOW_V << PMS_LP_MM_LP_TOUCH_ALLOW_S)
+#define PMS_LP_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_LP_MM_LP_IOMUX_ALLOW_M  (PMS_LP_MM_LP_IOMUX_ALLOW_V << PMS_LP_MM_LP_IOMUX_ALLOW_S)
+#define PMS_LP_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP INTR
+ *  (interrupt).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_LP_MM_LP_INTR_ALLOW_M  (PMS_LP_MM_LP_INTR_ALLOW_V << PMS_LP_MM_LP_INTR_ALLOW_S)
+#define PMS_LP_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_INTR_ALLOW_S  17
+/** PMS_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_LP_MM_LP_EFUSE_ALLOW_M  (PMS_LP_MM_LP_EFUSE_ALLOW_V << PMS_LP_MM_LP_EFUSE_ALLOW_S)
+#define PMS_LP_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_LP_MM_LP_PMS_ALLOW_M  (PMS_LP_MM_LP_PMS_ALLOW_V << PMS_LP_MM_LP_PMS_ALLOW_S)
+#define PMS_LP_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PMS_ALLOW_S  19
+/** PMS_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_M  (PMS_LP_MM_HP2LP_PMS_ALLOW_V << PMS_LP_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_LP_MM_LP_TSENS_ALLOW_M  (PMS_LP_MM_LP_TSENS_ALLOW_V << PMS_LP_MM_LP_TSENS_ALLOW_S)
+#define PMS_LP_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TSENS_ALLOW_S  21
+/** PMS_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
+ *  Unique Key).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_LP_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_LP_MM_LP_HUK_ALLOW_M  (PMS_LP_MM_LP_HUK_ALLOW_V << PMS_LP_MM_LP_HUK_ALLOW_S)
+#define PMS_LP_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_HUK_ALLOW_S  22
+/** PMS_LP_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_LP_MM_LP_SRAM_ALLOW_M  (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S)
+#define PMS_LP_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SRAM_ALLOW_S  23
+
+/** PMS_PERI_REGION0_LOW_REG register
+ *  Region0 start address configuration register
+ */
+#define PMS_PERI_REGION0_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0xc)
+/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  Configures the high 30 bits of the start address of peripheral register's region0.
+ */
+#define PMS_PERI_REGION0_LOW    0x3FFFFFFFU
+#define PMS_PERI_REGION0_LOW_M  (PMS_PERI_REGION0_LOW_V << PMS_PERI_REGION0_LOW_S)
+#define PMS_PERI_REGION0_LOW_V  0x3FFFFFFFU
+#define PMS_PERI_REGION0_LOW_S  2
+
+/** PMS_PERI_REGION0_HIGH_REG register
+ *  Region0 end address configuration register
+ */
+#define PMS_PERI_REGION0_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x10)
+/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  Configures the high 30 bits of the end address of peripheral register's region0.
+ */
+#define PMS_PERI_REGION0_HIGH    0x3FFFFFFFU
+#define PMS_PERI_REGION0_HIGH_M  (PMS_PERI_REGION0_HIGH_V << PMS_PERI_REGION0_HIGH_S)
+#define PMS_PERI_REGION0_HIGH_V  0x3FFFFFFFU
+#define PMS_PERI_REGION0_HIGH_S  2
+
+/** PMS_PERI_REGION1_LOW_REG register
+ *  Region1 start address configuration register
+ */
+#define PMS_PERI_REGION1_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x14)
+/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  Configures the high 30 bits of the start address of peripheral register's region1.
+ */
+#define PMS_PERI_REGION1_LOW    0x3FFFFFFFU
+#define PMS_PERI_REGION1_LOW_M  (PMS_PERI_REGION1_LOW_V << PMS_PERI_REGION1_LOW_S)
+#define PMS_PERI_REGION1_LOW_V  0x3FFFFFFFU
+#define PMS_PERI_REGION1_LOW_S  2
+
+/** PMS_PERI_REGION1_HIGH_REG register
+ *  Region1 end address configuration register
+ */
+#define PMS_PERI_REGION1_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x18)
+/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  Configures the high 30 bits of the end address of peripheral register's region1.
+ */
+#define PMS_PERI_REGION1_HIGH    0x3FFFFFFFU
+#define PMS_PERI_REGION1_HIGH_M  (PMS_PERI_REGION1_HIGH_V << PMS_PERI_REGION1_HIGH_S)
+#define PMS_PERI_REGION1_HIGH_V  0x3FFFFFFFU
+#define PMS_PERI_REGION1_HIGH_S  2
+
+/** PMS_PERI_REGION_PMS_REG register
+ *  Permission register of  region
+ */
+#define PMS_PERI_REGION_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x1c)
+/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
+ *  Configures whether LP core in machine mode has permission to access address region0
+ *  and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_LP_CORE_REGION_PMS    0x00000003U
+#define PMS_LP_CORE_REGION_PMS_M  (PMS_LP_CORE_REGION_PMS_V << PMS_LP_CORE_REGION_PMS_S)
+#define PMS_LP_CORE_REGION_PMS_V  0x00000003U
+#define PMS_LP_CORE_REGION_PMS_S  0
+/** PMS_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
+ *  Configures whether HP CPU0 in user mode has permission to access address region0
+ *  and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_UM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE0_UM_REGION_PMS_M  (PMS_HP_CORE0_UM_REGION_PMS_V << PMS_HP_CORE0_UM_REGION_PMS_S)
+#define PMS_HP_CORE0_UM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE0_UM_REGION_PMS_S  2
+/** PMS_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
+ *  Configures whether HP CPU0 in machine mode has permission to access address region0
+ *  and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_MM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE0_MM_REGION_PMS_M  (PMS_HP_CORE0_MM_REGION_PMS_V << PMS_HP_CORE0_MM_REGION_PMS_S)
+#define PMS_HP_CORE0_MM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE0_MM_REGION_PMS_S  4
+/** PMS_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
+ *  Configures whether HP CPU1 in user mode has permission to access address region0
+ *  and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_UM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE1_UM_REGION_PMS_M  (PMS_HP_CORE1_UM_REGION_PMS_V << PMS_HP_CORE1_UM_REGION_PMS_S)
+#define PMS_HP_CORE1_UM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE1_UM_REGION_PMS_S  6
+/** PMS_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
+ *  Configures whether HP CPU1 in machine mode has permission to access address region0
+ *  and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_MM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE1_MM_REGION_PMS_M  (PMS_HP_CORE1_MM_REGION_PMS_V << PMS_HP_CORE1_MM_REGION_PMS_S)
+#define PMS_HP_CORE1_MM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE1_MM_REGION_PMS_S  8
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_struct.h

@@ -0,0 +1,508 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE PMS DATE REG */
+/** Type of pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE LP MM PMS REG0 REG */
+/** Type of lp_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_sysreg_allow:1;
+        /** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_aonclkrst_allow:1;
+        /** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_timer_allow:1;
+        /** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_anaperi_allow:1;
+        /** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_pmu_allow:1;
+        /** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_wdt_allow:1;
+        /** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_mailbox_allow:1;
+        /** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_rtc_allow:1;
+        /** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_periclkrst_allow:1;
+        /** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_uart_allow:1;
+        /** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_i2c_allow:1;
+        /** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_spi_allow:1;
+        /** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_i2cmst_allow:1;
+        /** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_i2s_allow:1;
+        /** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_adc_allow:1;
+        /** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_touch_allow:1;
+        /** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_iomux_allow:1;
+        /** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_intr_allow:1;
+        /** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_efuse_allow:1;
+        /** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_pms_allow:1;
+        /** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_hp2lp_pms_allow:1;
+        /** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_tsens_allow:1;
+        /** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_huk_allow:1;
+        /** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_tcm_ram_allow:1;
+        /** reg_lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_lp_mm_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_lp_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE PERI REGION0 LOW REG */
+/** Type of peri_region0_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region0_low:30;
+    };
+    uint32_t val;
+} tee_peri_region0_low_reg_t;
+
+
+/** Group: TEE PERI REGION0 HIGH REG */
+/** Type of peri_region0_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region0_high:30;
+    };
+    uint32_t val;
+} tee_peri_region0_high_reg_t;
+
+
+/** Group: TEE PERI REGION1 LOW REG */
+/** Type of peri_region1_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region1_low:30;
+    };
+    uint32_t val;
+} tee_peri_region1_low_reg_t;
+
+
+/** Group: TEE PERI REGION1 HIGH REG */
+/** Type of peri_region1_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region1_high:30;
+    };
+    uint32_t val;
+} tee_peri_region1_high_reg_t;
+
+
+/** Group: TEE PERI REGION PMS REG */
+/** Type of peri_region_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
+         *  NA
+         */
+        uint32_t reg_lp_core_region_pms:2;
+        /** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_region_pms:2;
+        /** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_region_pms:2;
+        /** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_region_pms:2;
+        /** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_region_pms:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} tee_peri_region_pms_reg_t;
+
+
+/** Group: TEE PERI REGION 2 TO 7 PMS REG */
+/** Type of peri_region_2_to_7_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_lp_core_region_2_to_7_pms : R/W; bitpos: [5:0]; default: 63;
+         *  NA
+         */
+        uint32_t reg_lp_core_region_2_to_7_pms:6;
+        /** reg_hp_core0_um_region_2_to_7_pms : R/W; bitpos: [11:6]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_region_2_to_7_pms:6;
+        /** reg_hp_core0_mm_region_2_to_7_pms : R/W; bitpos: [17:12]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_region_2_to_7_pms:6;
+        /** reg_hp_core1_um_region_2_to_7_pms : R/W; bitpos: [23:18]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_region_2_to_7_pms:6;
+        /** reg_hp_core1_mm_region_2_to_7_pms : R/W; bitpos: [29:24]; default: 63;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_region_2_to_7_pms:6;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_peri_region_2_to_7_pms_reg_t;
+
+
+/** Group: TEE PERI REGION2 LOW REG */
+/** Type of peri_region2_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region2_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region2_low:30;
+    };
+    uint32_t val;
+} tee_peri_region2_low_reg_t;
+
+
+/** Group: TEE PERI REGION2 HIGH REG */
+/** Type of peri_region2_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region2_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region2_high:30;
+    };
+    uint32_t val;
+} tee_peri_region2_high_reg_t;
+
+
+/** Group: TEE PERI REGION3 LOW REG */
+/** Type of peri_region3_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region3_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region3_low:30;
+    };
+    uint32_t val;
+} tee_peri_region3_low_reg_t;
+
+
+/** Group: TEE PERI REGION3 HIGH REG */
+/** Type of peri_region3_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region3_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region3_high:30;
+    };
+    uint32_t val;
+} tee_peri_region3_high_reg_t;
+
+
+/** Group: TEE PERI REGION4 LOW REG */
+/** Type of peri_region4_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region4_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region4_low:30;
+    };
+    uint32_t val;
+} tee_peri_region4_low_reg_t;
+
+
+/** Group: TEE PERI REGION4 HIGH REG */
+/** Type of peri_region4_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region4_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region4_high:30;
+    };
+    uint32_t val;
+} tee_peri_region4_high_reg_t;
+
+
+/** Group: TEE PERI REGION5 LOW REG */
+/** Type of peri_region5_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region5_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region5_low:30;
+    };
+    uint32_t val;
+} tee_peri_region5_low_reg_t;
+
+
+/** Group: TEE PERI REGION5 HIGH REG */
+/** Type of peri_region5_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region5_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region5_high:30;
+    };
+    uint32_t val;
+} tee_peri_region5_high_reg_t;
+
+
+/** Group: TEE PERI REGION6 LOW REG */
+/** Type of peri_region6_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region6_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region6_low:30;
+    };
+    uint32_t val;
+} tee_peri_region6_low_reg_t;
+
+
+/** Group: TEE PERI REGION6 HIGH REG */
+/** Type of peri_region6_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region6_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region6_high:30;
+    };
+    uint32_t val;
+} tee_peri_region6_high_reg_t;
+
+
+/** Group: TEE PERI REGION7 LOW REG */
+/** Type of peri_region7_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region7_low : R/W; bitpos: [31:2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_peri_region7_low:30;
+    };
+    uint32_t val;
+} tee_peri_region7_low_reg_t;
+
+
+/** Group: TEE PERI REGION7 HIGH REG */
+/** Type of peri_region7_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_peri_region7_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  NA
+         */
+        uint32_t reg_peri_region7_high:30;
+    };
+    uint32_t val;
+} tee_peri_region7_high_reg_t;
+
+
+typedef struct {
+    volatile tee_pms_date_reg_t pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
+    volatile tee_peri_region0_low_reg_t peri_region0_low;
+    volatile tee_peri_region0_high_reg_t peri_region0_high;
+    volatile tee_peri_region1_low_reg_t peri_region1_low;
+    volatile tee_peri_region1_high_reg_t peri_region1_high;
+    volatile tee_peri_region_pms_reg_t peri_region_pms;
+    volatile tee_peri_region_2_to_7_pms_reg_t peri_region_2_to_7_pms;
+    volatile tee_peri_region2_low_reg_t peri_region2_low;
+    volatile tee_peri_region2_high_reg_t peri_region2_high;
+    volatile tee_peri_region3_low_reg_t peri_region3_low;
+    volatile tee_peri_region3_high_reg_t peri_region3_high;
+    volatile tee_peri_region4_low_reg_t peri_region4_low;
+    volatile tee_peri_region4_high_reg_t peri_region4_high;
+    volatile tee_peri_region5_low_reg_t peri_region5_low;
+    volatile tee_peri_region5_high_reg_t peri_region5_high;
+    volatile tee_peri_region6_low_reg_t peri_region6_low;
+    volatile tee_peri_region6_high_reg_t peri_region6_high;
+    volatile tee_peri_region7_low_reg_t peri_region7_low;
+    volatile tee_peri_region7_high_reg_t peri_region7_high;
+} tee_dev_t;
+
+extern tee_dev_t LP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x54, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_timer_eco5_struct.h

@@ -0,0 +1,363 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of tar0_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_low0:32;
+    };
+    uint32_t val;
+} lp_timer_tar0_low_reg_t;
+
+/** Type of tar0_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_high0:16;
+        uint32_t reserved_16:15;
+        /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_en0:1;
+    };
+    uint32_t val;
+} lp_timer_tar0_high_reg_t;
+
+/** Type of tar1_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_low1:32;
+    };
+    uint32_t val;
+} lp_timer_tar1_low_reg_t;
+
+/** Type of tar1_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_high1:16;
+        uint32_t reserved_16:15;
+        /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_tar_en1:1;
+    };
+    uint32_t val;
+} lp_timer_tar1_high_reg_t;
+
+/** Type of update register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** main_timer_update : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_update:1;
+        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_xtal_off:1;
+        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_stall:1;
+        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_rst:1;
+    };
+    uint32_t val;
+} lp_timer_update_reg_t;
+
+/** Type of main_buf0_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf0_low:32;
+    };
+    uint32_t val;
+} lp_timer_main_buf0_low_reg_t;
+
+/** Type of main_buf0_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf0_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_timer_main_buf0_high_reg_t;
+
+/** Type of main_buf1_low register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf1_low:32;
+    };
+    uint32_t val;
+} lp_timer_main_buf1_low_reg_t;
+
+/** Type of main_buf1_high register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_buf1_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_timer_main_buf1_high_reg_t;
+
+/** Type of main_overflow register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_alarm_load:1;
+    };
+    uint32_t val;
+} lp_timer_main_overflow_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_raw:1;
+        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_st:1;
+        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_ena:1;
+        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_clr:1;
+        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_raw:1;
+        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_st:1;
+        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_ena:1;
+        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_clr:1;
+        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 34672976;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_timer_date_reg_t;
+
+
+typedef struct {
+    volatile lp_timer_tar0_low_reg_t tar0_low;
+    volatile lp_timer_tar0_high_reg_t tar0_high;
+    volatile lp_timer_tar1_low_reg_t tar1_low;
+    volatile lp_timer_tar1_high_reg_t tar1_high;
+    volatile lp_timer_update_reg_t update;
+    volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
+    volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
+    volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
+    volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
+    volatile lp_timer_main_overflow_reg_t main_overflow;
+    volatile lp_timer_int_raw_reg_t int_raw;
+    volatile lp_timer_int_st_reg_t int_st;
+    volatile lp_timer_int_ena_reg_t int_ena;
+    volatile lp_timer_int_clr_reg_t int_clr;
+    volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_timer_lp_int_st_reg_t lp_int_st;
+    volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_048[237];
+    volatile lp_timer_date_reg_t date;
+} lp_timer_dev_t;
+
+extern lp_timer_dev_t LP_TIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_timer_reg.h

@@ -0,0 +1,342 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTC_TIMER_TAR0_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0)
+/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M  (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S  0
+
+/** RTC_TIMER_TAR0_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4)
+/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M  (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S  0
+/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M  (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S  31
+
+/** RTC_TIMER_TAR1_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8)
+/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M  (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S  0
+
+/** RTC_TIMER_TAR1_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc)
+/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M  (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S  0
+/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M  (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S)
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S  31
+
+/** RTC_TIMER_UPDATE_REG register
+ *  need_des
+ */
+#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10)
+/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_UPDATE    (BIT(28))
+#define RTC_TIMER_MAIN_TIMER_UPDATE_M  (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S)
+#define RTC_TIMER_MAIN_TIMER_UPDATE_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_UPDATE_S  28
+/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF    (BIT(29))
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M  (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S)
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S  29
+/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M  (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S)
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S  30
+/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_SYS_RST    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_SYS_RST_M  (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S)
+#define RTC_TIMER_MAIN_TIMER_SYS_RST_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_SYS_RST_S  31
+
+/** RTC_TIMER_MAIN_BUF0_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14)
+/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M  (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S)
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S  0
+
+/** RTC_TIMER_MAIN_BUF0_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18)
+/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M  (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S)
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S  0
+
+/** RTC_TIMER_MAIN_BUF1_LOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c)
+/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW    0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M  (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S)
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V  0xFFFFFFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S  0
+
+/** RTC_TIMER_MAIN_BUF1_HIGH_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20)
+/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH    0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M  (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S)
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V  0x0000FFFFU
+#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S  0
+
+/** RTC_TIMER_MAIN_OVERFLOW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24)
+/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M  (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S)
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S  31
+
+/** RTC_TIMER_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28)
+/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_RAW    (BIT(30))
+#define RTC_TIMER_OVERFLOW_RAW_M  (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S)
+#define RTC_TIMER_OVERFLOW_RAW_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_RAW_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M  (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S  31
+
+/** RTC_TIMER_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c)
+/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_ST    (BIT(30))
+#define RTC_TIMER_OVERFLOW_ST_M  (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S)
+#define RTC_TIMER_OVERFLOW_ST_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_ST_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_ST    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_ST_M  (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_ST_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_ST_S  31
+
+/** RTC_TIMER_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30)
+/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_ENA    (BIT(30))
+#define RTC_TIMER_OVERFLOW_ENA_M  (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S)
+#define RTC_TIMER_OVERFLOW_ENA_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_ENA_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M  (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S  31
+
+/** RTC_TIMER_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34)
+/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_OVERFLOW_CLR    (BIT(30))
+#define RTC_TIMER_OVERFLOW_CLR_M  (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S)
+#define RTC_TIMER_OVERFLOW_CLR_V  0x00000001U
+#define RTC_TIMER_OVERFLOW_CLR_S  30
+/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR    (BIT(31))
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M  (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S)
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V  0x00000001U
+#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S  31
+
+/** RTC_TIMER_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M  (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S  31
+
+/** RTC_TIMER_LP_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M  (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S  31
+
+/** RTC_TIMER_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M  (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S  31
+
+/** RTC_TIMER_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44)
+/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR    (BIT(30))
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M  (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S  30
+/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR    (BIT(31))
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M  (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S)
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V  0x00000001U
+#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S  31
+
+/** RTC_TIMER_DATE_REG register
+ *  need_des
+ */
+#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc)
+/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
+ *  need_des
+ */
+#define RTC_TIMER_DATE    0x7FFFFFFFU
+#define RTC_TIMER_DATE_M  (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S)
+#define RTC_TIMER_DATE_V  0x7FFFFFFFU
+#define RTC_TIMER_DATE_S  0
+/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TIMER_CLK_EN    (BIT(31))
+#define RTC_TIMER_CLK_EN_M  (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S)
+#define RTC_TIMER_CLK_EN_V  0x00000001U
+#define RTC_TIMER_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_timer_struct.h

@@ -0,0 +1,274 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    union {
+        struct {
+            uint32_t target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            uint32_t target_hi: 16;
+            uint32_t reserved0: 15;
+            uint32_t enable   : 1;
+        };
+        uint32_t val;
+    } hi;
+} lp_timer_target_reg_t;
+
+/** Type of update register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** main_timer_update : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_update:1;
+        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_xtal_off:1;
+        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_stall:1;
+        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_sys_rst:1;
+    };
+    uint32_t val;
+} lp_timer_update_reg_t;
+
+typedef struct {
+    union {
+        struct {
+            uint32_t counter_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            uint32_t counter_hi: 16;
+            uint32_t reserved0 : 16;
+        };
+        uint32_t val;
+    } hi;
+} lp_timer_counter_reg_t;
+
+
+/** Type of main_overflow register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_alarm_load:1;
+    };
+    uint32_t val;
+} lp_timer_main_overflow_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_raw:1;
+        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_st:1;
+        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_ena:1;
+        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** overflow_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t overflow_clr:1;
+        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t soc_wakeup_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_int_clr_reg_t;
+
+/** Type of lp_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_raw:1;
+        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_raw:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_raw_reg_t;
+
+/** Type of lp_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_st:1;
+        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_st:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_st_reg_t;
+
+/** Type of lp_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_ena:1;
+        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_ena:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_ena_reg_t;
+
+/** Type of lp_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_overflow_lp_int_clr:1;
+        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t main_timer_lp_int_clr:1;
+    };
+    uint32_t val;
+} lp_timer_lp_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 34672976;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_timer_date_reg_t;
+
+
+typedef struct {
+    volatile lp_timer_target_reg_t          target[2];
+    volatile lp_timer_update_reg_t          update;
+    volatile lp_timer_counter_reg_t         counter[2];
+    volatile lp_timer_main_overflow_reg_t main_overflow;
+    volatile lp_timer_int_raw_reg_t int_raw;
+    volatile lp_timer_int_st_reg_t int_st;
+    volatile lp_timer_int_ena_reg_t int_ena;
+    volatile lp_timer_int_clr_reg_t int_clr;
+    volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_timer_lp_int_st_reg_t lp_int_st;
+    volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
+    uint32_t reserved_048[237];
+    volatile lp_timer_date_reg_t date;
+} lp_timer_dev_t;
+
+extern lp_timer_dev_t LP_TIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_reg.h

@@ -0,0 +1,324 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_WDT_CONFIG0_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
+/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_PAUSE_IN_SLP    (BIT(9))
+#define LP_WDT_WDT_PAUSE_IN_SLP_M  (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
+#define LP_WDT_WDT_PAUSE_IN_SLP_V  0x00000001U
+#define LP_WDT_WDT_PAUSE_IN_SLP_S  9
+/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_APPCPU_RESET_EN    (BIT(10))
+#define LP_WDT_WDT_APPCPU_RESET_EN_M  (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
+#define LP_WDT_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define LP_WDT_WDT_APPCPU_RESET_EN_S  10
+/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_PROCPU_RESET_EN    (BIT(11))
+#define LP_WDT_WDT_PROCPU_RESET_EN_M  (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
+#define LP_WDT_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define LP_WDT_WDT_PROCPU_RESET_EN_S  11
+/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN    (BIT(12))
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M  (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S  12
+/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_SYS_RESET_LENGTH    0x00000007U
+#define LP_WDT_WDT_SYS_RESET_LENGTH_M  (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
+#define LP_WDT_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define LP_WDT_WDT_SYS_RESET_LENGTH_S  13
+/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
+ *  need_des
+ */
+#define LP_WDT_WDT_CPU_RESET_LENGTH    0x00000007U
+#define LP_WDT_WDT_CPU_RESET_LENGTH_M  (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
+#define LP_WDT_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define LP_WDT_WDT_CPU_RESET_LENGTH_S  16
+/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG3    0x00000007U
+#define LP_WDT_WDT_STG3_M  (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
+#define LP_WDT_WDT_STG3_V  0x00000007U
+#define LP_WDT_WDT_STG3_S  19
+/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG2    0x00000007U
+#define LP_WDT_WDT_STG2_M  (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
+#define LP_WDT_WDT_STG2_V  0x00000007U
+#define LP_WDT_WDT_STG2_S  22
+/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG1    0x00000007U
+#define LP_WDT_WDT_STG1_M  (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
+#define LP_WDT_WDT_STG1_V  0x00000007U
+#define LP_WDT_WDT_STG1_S  25
+/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG0    0x00000007U
+#define LP_WDT_WDT_STG0_M  (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
+#define LP_WDT_WDT_STG0_V  0x00000007U
+#define LP_WDT_WDT_STG0_S  28
+/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_EN    (BIT(31))
+#define LP_WDT_WDT_EN_M  (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
+#define LP_WDT_WDT_EN_V  0x00000001U
+#define LP_WDT_WDT_EN_S  31
+
+/** LP_WDT_CONFIG1_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
+/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG0_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG0_HOLD_M  (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
+#define LP_WDT_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG0_HOLD_S  0
+
+/** LP_WDT_CONFIG2_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
+/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG1_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG1_HOLD_M  (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
+#define LP_WDT_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG1_HOLD_S  0
+
+/** LP_WDT_CONFIG3_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
+/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG2_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG2_HOLD_M  (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
+#define LP_WDT_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG2_HOLD_S  0
+
+/** LP_WDT_CONFIG4_REG register
+ *  need_des
+ */
+#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
+/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ *  need_des
+ */
+#define LP_WDT_WDT_STG3_HOLD    0xFFFFFFFFU
+#define LP_WDT_WDT_STG3_HOLD_M  (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
+#define LP_WDT_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define LP_WDT_WDT_STG3_HOLD_S  0
+
+/** LP_WDT_FEED_REG register
+ *  need_des
+ */
+#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
+/** LP_WDT_FEED : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_FEED    (BIT(31))
+#define LP_WDT_FEED_M  (LP_WDT_FEED_V << LP_WDT_FEED_S)
+#define LP_WDT_FEED_V  0x00000001U
+#define LP_WDT_FEED_S  31
+
+/** LP_WDT_WPROTECT_REG register
+ *  need_des
+ */
+#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
+/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_WDT_WKEY    0xFFFFFFFFU
+#define LP_WDT_WDT_WKEY_M  (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
+#define LP_WDT_WDT_WKEY_V  0xFFFFFFFFU
+#define LP_WDT_WDT_WKEY_S  0
+
+/** LP_WDT_SWD_CONFIG_REG register
+ *  need_des
+ */
+#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
+/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_RESET_FLAG    (BIT(0))
+#define LP_WDT_SWD_RESET_FLAG_M  (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
+#define LP_WDT_SWD_RESET_FLAG_V  0x00000001U
+#define LP_WDT_SWD_RESET_FLAG_S  0
+/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_AUTO_FEED_EN    (BIT(18))
+#define LP_WDT_SWD_AUTO_FEED_EN_M  (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
+#define LP_WDT_SWD_AUTO_FEED_EN_V  0x00000001U
+#define LP_WDT_SWD_AUTO_FEED_EN_S  18
+/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_RST_FLAG_CLR    (BIT(19))
+#define LP_WDT_SWD_RST_FLAG_CLR_M  (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
+#define LP_WDT_SWD_RST_FLAG_CLR_V  0x00000001U
+#define LP_WDT_SWD_RST_FLAG_CLR_S  19
+/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
+ *  need_des
+ */
+#define LP_WDT_SWD_SIGNAL_WIDTH    0x000003FFU
+#define LP_WDT_SWD_SIGNAL_WIDTH_M  (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
+#define LP_WDT_SWD_SIGNAL_WIDTH_V  0x000003FFU
+#define LP_WDT_SWD_SIGNAL_WIDTH_S  20
+/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_DISABLE    (BIT(30))
+#define LP_WDT_SWD_DISABLE_M  (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
+#define LP_WDT_SWD_DISABLE_V  0x00000001U
+#define LP_WDT_SWD_DISABLE_S  30
+/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_FEED    (BIT(31))
+#define LP_WDT_SWD_FEED_M  (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
+#define LP_WDT_SWD_FEED_V  0x00000001U
+#define LP_WDT_SWD_FEED_S  31
+
+/** LP_WDT_SWD_WPROTECT_REG register
+ *  need_des
+ */
+#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
+/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SWD_WKEY    0xFFFFFFFFU
+#define LP_WDT_SWD_WKEY_M  (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
+#define LP_WDT_SWD_WKEY_V  0xFFFFFFFFU
+#define LP_WDT_SWD_WKEY_S  0
+
+/** LP_WDT_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
+/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_RAW    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_RAW_M  (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
+#define LP_WDT_SUPER_WDT_INT_RAW_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_RAW_S  30
+/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_RAW    (BIT(31))
+#define LP_WDT_LP_WDT_INT_RAW_M  (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
+#define LP_WDT_LP_WDT_INT_RAW_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_RAW_S  31
+
+/** LP_WDT_INT_ST_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
+/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_ST    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_ST_M  (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
+#define LP_WDT_SUPER_WDT_INT_ST_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_ST_S  30
+/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_ST    (BIT(31))
+#define LP_WDT_LP_WDT_INT_ST_M  (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
+#define LP_WDT_LP_WDT_INT_ST_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_ST_S  31
+
+/** LP_WDT_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
+/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_ENA    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_ENA_M  (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
+#define LP_WDT_SUPER_WDT_INT_ENA_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_ENA_S  30
+/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_ENA    (BIT(31))
+#define LP_WDT_LP_WDT_INT_ENA_M  (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
+#define LP_WDT_LP_WDT_INT_ENA_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_ENA_S  31
+
+/** LP_WDT_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
+/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_SUPER_WDT_INT_CLR    (BIT(30))
+#define LP_WDT_SUPER_WDT_INT_CLR_M  (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
+#define LP_WDT_SUPER_WDT_INT_CLR_V  0x00000001U
+#define LP_WDT_SUPER_WDT_INT_CLR_S  30
+/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_INT_CLR    (BIT(31))
+#define LP_WDT_LP_WDT_INT_CLR_M  (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
+#define LP_WDT_LP_WDT_INT_CLR_V  0x00000001U
+#define LP_WDT_LP_WDT_INT_CLR_S  31
+
+/** LP_WDT_DATE_REG register
+ *  need_des
+ */
+#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
+/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 35725408;
+ *  need_des
+ */
+#define LP_WDT_LP_WDT_DATE    0x7FFFFFFFU
+#define LP_WDT_LP_WDT_DATE_M  (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
+#define LP_WDT_LP_WDT_DATE_V  0x7FFFFFFFU
+#define LP_WDT_LP_WDT_DATE_S  0
+/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_WDT_CLK_EN    (BIT(31))
+#define LP_WDT_CLK_EN_M  (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
+#define LP_WDT_CLK_EN_V  0x00000001U
+#define LP_WDT_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_struct.h

@@ -0,0 +1,310 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of config0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_pause_in_slp:1;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_appcpu_reset_en:1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_procpu_reset_en:1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_flashboot_mod_en:1;
+        /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_sys_reset_length:3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
+         *  need_des
+         */
+        uint32_t wdt_cpu_reset_length:3;
+        /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg3:3;
+        /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg2:3;
+        /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg1:3;
+        /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_stg0:3;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_en:1;
+    };
+    uint32_t val;
+} rtc_wdt_config0_reg_t;
+
+/** Type of config1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
+         *  need_des
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config1_reg_t;
+
+/** Type of config2 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
+         *  need_des
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config2_reg_t;
+
+/** Type of config3 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config3_reg_t;
+
+/** Type of config4 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} rtc_wdt_config4_reg_t;
+
+/** Type of feed register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** feed : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t feed:1;
+    };
+    uint32_t val;
+} rtc_wdt_feed_reg_t;
+
+/** Type of wprotect register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} rtc_wdt_wprotect_reg_t;
+
+/** Type of swd_config register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** swd_reset_flag : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_reset_flag:1;
+        uint32_t reserved_1:17;
+        /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_auto_feed_en:1;
+        /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_rst_flag_clr:1;
+        /** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
+         *  need_des
+         */
+        uint32_t swd_signal_width:10;
+        /** swd_disable : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_disable:1;
+        /** swd_feed : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_feed:1;
+    };
+    uint32_t val;
+} rtc_wdt_swd_config_reg_t;
+
+/** Type of swd_wprotect register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** swd_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  need_des
+         */
+        uint32_t swd_wkey:32;
+    };
+    uint32_t val;
+} rtc_wdt_swd_wprotect_reg_t;
+
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_raw:1;
+        /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_raw:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_st:1;
+        /** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_st:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_ena:1;
+        /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_ena:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t super_wdt_int_clr:1;
+        /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_wdt_int_clr:1;
+    };
+    uint32_t val;
+} rtc_wdt_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_wdt_date : R/W; bitpos: [30:0]; default: 35725408;
+         *  need_des
+         */
+        uint32_t lp_wdt_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtc_wdt_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_wdt_config0_reg_t config0;
+    volatile rtc_wdt_config1_reg_t config1;
+    volatile rtc_wdt_config2_reg_t config2;
+    volatile rtc_wdt_config3_reg_t config3;
+    volatile rtc_wdt_config4_reg_t config4;
+    volatile rtc_wdt_feed_reg_t feed;
+    volatile rtc_wdt_wprotect_reg_t wprotect;
+    volatile rtc_wdt_swd_config_reg_t swd_config;
+    volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect;
+    volatile rtc_wdt_int_raw_reg_t int_raw;
+    volatile rtc_wdt_int_st_reg_t int_st;
+    volatile rtc_wdt_int_ena_reg_t int_ena;
+    volatile rtc_wdt_int_clr_reg_t int_clr;
+    uint32_t reserved_034[242];
+    volatile rtc_wdt_date_reg_t date;
+} lp_wdt_dev_t;
+
+extern lp_wdt_dev_t LP_WDT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lpperi_reg.h

@@ -0,0 +1,470 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LPPERI_CLK_EN_REG register
+ *  need_des
+ */
+#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
+/** LPPERI_CK_EN_RNG : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_RNG    (BIT(16))
+#define LPPERI_CK_EN_RNG_M  (LPPERI_CK_EN_RNG_V << LPPERI_CK_EN_RNG_S)
+#define LPPERI_CK_EN_RNG_V  0x00000001U
+#define LPPERI_CK_EN_RNG_S  16
+/** LPPERI_CK_EN_LP_TSENS : R/W; bitpos: [17]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_TSENS    (BIT(17))
+#define LPPERI_CK_EN_LP_TSENS_M  (LPPERI_CK_EN_LP_TSENS_V << LPPERI_CK_EN_LP_TSENS_S)
+#define LPPERI_CK_EN_LP_TSENS_V  0x00000001U
+#define LPPERI_CK_EN_LP_TSENS_S  17
+/** LPPERI_CK_EN_LP_PMS : R/W; bitpos: [18]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_PMS    (BIT(18))
+#define LPPERI_CK_EN_LP_PMS_M  (LPPERI_CK_EN_LP_PMS_V << LPPERI_CK_EN_LP_PMS_S)
+#define LPPERI_CK_EN_LP_PMS_V  0x00000001U
+#define LPPERI_CK_EN_LP_PMS_S  18
+/** LPPERI_CK_EN_LP_EFUSE : R/W; bitpos: [19]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_EFUSE    (BIT(19))
+#define LPPERI_CK_EN_LP_EFUSE_M  (LPPERI_CK_EN_LP_EFUSE_V << LPPERI_CK_EN_LP_EFUSE_S)
+#define LPPERI_CK_EN_LP_EFUSE_V  0x00000001U
+#define LPPERI_CK_EN_LP_EFUSE_S  19
+/** LPPERI_CK_EN_LP_IOMUX : R/W; bitpos: [20]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_IOMUX    (BIT(20))
+#define LPPERI_CK_EN_LP_IOMUX_M  (LPPERI_CK_EN_LP_IOMUX_V << LPPERI_CK_EN_LP_IOMUX_S)
+#define LPPERI_CK_EN_LP_IOMUX_V  0x00000001U
+#define LPPERI_CK_EN_LP_IOMUX_S  20
+/** LPPERI_CK_EN_LP_TOUCH : R/W; bitpos: [21]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_TOUCH    (BIT(21))
+#define LPPERI_CK_EN_LP_TOUCH_M  (LPPERI_CK_EN_LP_TOUCH_V << LPPERI_CK_EN_LP_TOUCH_S)
+#define LPPERI_CK_EN_LP_TOUCH_V  0x00000001U
+#define LPPERI_CK_EN_LP_TOUCH_S  21
+/** LPPERI_CK_EN_LP_SPI : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_SPI    (BIT(22))
+#define LPPERI_CK_EN_LP_SPI_M  (LPPERI_CK_EN_LP_SPI_V << LPPERI_CK_EN_LP_SPI_S)
+#define LPPERI_CK_EN_LP_SPI_V  0x00000001U
+#define LPPERI_CK_EN_LP_SPI_S  22
+/** LPPERI_CK_EN_LP_ADC : R/W; bitpos: [23]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_ADC    (BIT(23))
+#define LPPERI_CK_EN_LP_ADC_M  (LPPERI_CK_EN_LP_ADC_V << LPPERI_CK_EN_LP_ADC_S)
+#define LPPERI_CK_EN_LP_ADC_V  0x00000001U
+#define LPPERI_CK_EN_LP_ADC_S  23
+/** LPPERI_CK_EN_LP_I2S_TX : R/W; bitpos: [24]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2S_TX    (BIT(24))
+#define LPPERI_CK_EN_LP_I2S_TX_M  (LPPERI_CK_EN_LP_I2S_TX_V << LPPERI_CK_EN_LP_I2S_TX_S)
+#define LPPERI_CK_EN_LP_I2S_TX_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2S_TX_S  24
+/** LPPERI_CK_EN_LP_I2S_RX : R/W; bitpos: [25]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2S_RX    (BIT(25))
+#define LPPERI_CK_EN_LP_I2S_RX_M  (LPPERI_CK_EN_LP_I2S_RX_V << LPPERI_CK_EN_LP_I2S_RX_S)
+#define LPPERI_CK_EN_LP_I2S_RX_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2S_RX_S  25
+/** LPPERI_CK_EN_LP_I2S : R/W; bitpos: [26]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2S    (BIT(26))
+#define LPPERI_CK_EN_LP_I2S_M  (LPPERI_CK_EN_LP_I2S_V << LPPERI_CK_EN_LP_I2S_S)
+#define LPPERI_CK_EN_LP_I2S_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2S_S  26
+/** LPPERI_CK_EN_LP_I2CMST : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2CMST    (BIT(27))
+#define LPPERI_CK_EN_LP_I2CMST_M  (LPPERI_CK_EN_LP_I2CMST_V << LPPERI_CK_EN_LP_I2CMST_S)
+#define LPPERI_CK_EN_LP_I2CMST_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2CMST_S  27
+/** LPPERI_CK_EN_LP_I2C : R/W; bitpos: [28]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_I2C    (BIT(28))
+#define LPPERI_CK_EN_LP_I2C_M  (LPPERI_CK_EN_LP_I2C_V << LPPERI_CK_EN_LP_I2C_S)
+#define LPPERI_CK_EN_LP_I2C_V  0x00000001U
+#define LPPERI_CK_EN_LP_I2C_S  28
+/** LPPERI_CK_EN_LP_UART : R/W; bitpos: [29]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_UART    (BIT(29))
+#define LPPERI_CK_EN_LP_UART_M  (LPPERI_CK_EN_LP_UART_V << LPPERI_CK_EN_LP_UART_S)
+#define LPPERI_CK_EN_LP_UART_V  0x00000001U
+#define LPPERI_CK_EN_LP_UART_S  29
+/** LPPERI_CK_EN_LP_INTR : R/W; bitpos: [30]; default: 1;
+ *  need_des
+ */
+#define LPPERI_CK_EN_LP_INTR    (BIT(30))
+#define LPPERI_CK_EN_LP_INTR_M  (LPPERI_CK_EN_LP_INTR_V << LPPERI_CK_EN_LP_INTR_S)
+#define LPPERI_CK_EN_LP_INTR_V  0x00000001U
+#define LPPERI_CK_EN_LP_INTR_S  30
+/** LPPERI_CK_EN_LP_CORE : R/W; bitpos: [31]; default: 0;
+ *  write 1 to force on lp_core clk
+ */
+#define LPPERI_CK_EN_LP_CORE    (BIT(31))
+#define LPPERI_CK_EN_LP_CORE_M  (LPPERI_CK_EN_LP_CORE_V << LPPERI_CK_EN_LP_CORE_S)
+#define LPPERI_CK_EN_LP_CORE_V  0x00000001U
+#define LPPERI_CK_EN_LP_CORE_S  31
+
+/** LPPERI_CORE_CLK_SEL_REG register
+ *  need_des
+ */
+#define LPPERI_CORE_CLK_SEL_REG (DR_REG_LPPERI_BASE + 0x4)
+/** LPPERI_LP_I2S_TX_CLK_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLK_SEL    0x00000003U
+#define LPPERI_LP_I2S_TX_CLK_SEL_M  (LPPERI_LP_I2S_TX_CLK_SEL_V << LPPERI_LP_I2S_TX_CLK_SEL_S)
+#define LPPERI_LP_I2S_TX_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_I2S_TX_CLK_SEL_S  24
+/** LPPERI_LP_I2S_RX_CLK_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLK_SEL    0x00000003U
+#define LPPERI_LP_I2S_RX_CLK_SEL_M  (LPPERI_LP_I2S_RX_CLK_SEL_V << LPPERI_LP_I2S_RX_CLK_SEL_S)
+#define LPPERI_LP_I2S_RX_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_I2S_RX_CLK_SEL_S  26
+/** LPPERI_LP_I2C_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2C_CLK_SEL    0x00000003U
+#define LPPERI_LP_I2C_CLK_SEL_M  (LPPERI_LP_I2C_CLK_SEL_V << LPPERI_LP_I2C_CLK_SEL_S)
+#define LPPERI_LP_I2C_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_I2C_CLK_SEL_S  28
+/** LPPERI_LP_UART_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_CLK_SEL    0x00000003U
+#define LPPERI_LP_UART_CLK_SEL_M  (LPPERI_LP_UART_CLK_SEL_V << LPPERI_LP_UART_CLK_SEL_S)
+#define LPPERI_LP_UART_CLK_SEL_V  0x00000003U
+#define LPPERI_LP_UART_CLK_SEL_S  30
+
+/** LPPERI_RESET_EN_REG register
+ *  need_des
+ */
+#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x8)
+/** LPPERI_RST_EN_LP_RNG : R/W; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_RNG    (BIT(17))
+#define LPPERI_RST_EN_LP_RNG_M  (LPPERI_RST_EN_LP_RNG_V << LPPERI_RST_EN_LP_RNG_S)
+#define LPPERI_RST_EN_LP_RNG_V  0x00000001U
+#define LPPERI_RST_EN_LP_RNG_S  17
+/** LPPERI_RST_EN_LP_TSENS : R/W; bitpos: [18]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_TSENS    (BIT(18))
+#define LPPERI_RST_EN_LP_TSENS_M  (LPPERI_RST_EN_LP_TSENS_V << LPPERI_RST_EN_LP_TSENS_S)
+#define LPPERI_RST_EN_LP_TSENS_V  0x00000001U
+#define LPPERI_RST_EN_LP_TSENS_S  18
+/** LPPERI_RST_EN_LP_PMS : R/W; bitpos: [19]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_PMS    (BIT(19))
+#define LPPERI_RST_EN_LP_PMS_M  (LPPERI_RST_EN_LP_PMS_V << LPPERI_RST_EN_LP_PMS_S)
+#define LPPERI_RST_EN_LP_PMS_V  0x00000001U
+#define LPPERI_RST_EN_LP_PMS_S  19
+/** LPPERI_RST_EN_LP_EFUSE : R/W; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_EFUSE    (BIT(20))
+#define LPPERI_RST_EN_LP_EFUSE_M  (LPPERI_RST_EN_LP_EFUSE_V << LPPERI_RST_EN_LP_EFUSE_S)
+#define LPPERI_RST_EN_LP_EFUSE_V  0x00000001U
+#define LPPERI_RST_EN_LP_EFUSE_S  20
+/** LPPERI_RST_EN_LP_IOMUX : R/W; bitpos: [21]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_IOMUX    (BIT(21))
+#define LPPERI_RST_EN_LP_IOMUX_M  (LPPERI_RST_EN_LP_IOMUX_V << LPPERI_RST_EN_LP_IOMUX_S)
+#define LPPERI_RST_EN_LP_IOMUX_V  0x00000001U
+#define LPPERI_RST_EN_LP_IOMUX_S  21
+/** LPPERI_RST_EN_LP_TOUCH : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_TOUCH    (BIT(22))
+#define LPPERI_RST_EN_LP_TOUCH_M  (LPPERI_RST_EN_LP_TOUCH_V << LPPERI_RST_EN_LP_TOUCH_S)
+#define LPPERI_RST_EN_LP_TOUCH_V  0x00000001U
+#define LPPERI_RST_EN_LP_TOUCH_S  22
+/** LPPERI_RST_EN_LP_SPI : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_SPI    (BIT(23))
+#define LPPERI_RST_EN_LP_SPI_M  (LPPERI_RST_EN_LP_SPI_V << LPPERI_RST_EN_LP_SPI_S)
+#define LPPERI_RST_EN_LP_SPI_V  0x00000001U
+#define LPPERI_RST_EN_LP_SPI_S  23
+/** LPPERI_RST_EN_LP_ADC : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_ADC    (BIT(24))
+#define LPPERI_RST_EN_LP_ADC_M  (LPPERI_RST_EN_LP_ADC_V << LPPERI_RST_EN_LP_ADC_S)
+#define LPPERI_RST_EN_LP_ADC_V  0x00000001U
+#define LPPERI_RST_EN_LP_ADC_S  24
+/** LPPERI_RST_EN_LP_I2S : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_I2S    (BIT(25))
+#define LPPERI_RST_EN_LP_I2S_M  (LPPERI_RST_EN_LP_I2S_V << LPPERI_RST_EN_LP_I2S_S)
+#define LPPERI_RST_EN_LP_I2S_V  0x00000001U
+#define LPPERI_RST_EN_LP_I2S_S  25
+/** LPPERI_RST_EN_LP_I2CMST : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_I2CMST    (BIT(26))
+#define LPPERI_RST_EN_LP_I2CMST_M  (LPPERI_RST_EN_LP_I2CMST_V << LPPERI_RST_EN_LP_I2CMST_S)
+#define LPPERI_RST_EN_LP_I2CMST_V  0x00000001U
+#define LPPERI_RST_EN_LP_I2CMST_S  26
+/** LPPERI_RST_EN_LP_I2C : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_I2C    (BIT(27))
+#define LPPERI_RST_EN_LP_I2C_M  (LPPERI_RST_EN_LP_I2C_V << LPPERI_RST_EN_LP_I2C_S)
+#define LPPERI_RST_EN_LP_I2C_V  0x00000001U
+#define LPPERI_RST_EN_LP_I2C_S  27
+/** LPPERI_RST_EN_LP_UART : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_UART    (BIT(28))
+#define LPPERI_RST_EN_LP_UART_M  (LPPERI_RST_EN_LP_UART_V << LPPERI_RST_EN_LP_UART_S)
+#define LPPERI_RST_EN_LP_UART_V  0x00000001U
+#define LPPERI_RST_EN_LP_UART_S  28
+/** LPPERI_RST_EN_LP_INTR : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_INTR    (BIT(29))
+#define LPPERI_RST_EN_LP_INTR_M  (LPPERI_RST_EN_LP_INTR_V << LPPERI_RST_EN_LP_INTR_S)
+#define LPPERI_RST_EN_LP_INTR_V  0x00000001U
+#define LPPERI_RST_EN_LP_INTR_S  29
+/** LPPERI_RST_EN_LP_ROM : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_ROM    (BIT(30))
+#define LPPERI_RST_EN_LP_ROM_M  (LPPERI_RST_EN_LP_ROM_V << LPPERI_RST_EN_LP_ROM_S)
+#define LPPERI_RST_EN_LP_ROM_V  0x00000001U
+#define LPPERI_RST_EN_LP_ROM_S  30
+/** LPPERI_RST_EN_LP_CORE : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPPERI_RST_EN_LP_CORE    (BIT(31))
+#define LPPERI_RST_EN_LP_CORE_M  (LPPERI_RST_EN_LP_CORE_V << LPPERI_RST_EN_LP_CORE_S)
+#define LPPERI_RST_EN_LP_CORE_V  0x00000001U
+#define LPPERI_RST_EN_LP_CORE_S  31
+
+/** LPPERI_CPU_REG register
+ *  need_des
+ */
+#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
+/** LPPERI_LPCORE_DBGM_UNAVAILABLE : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE    (BIT(31))
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE_M  (LPPERI_LPCORE_DBGM_UNAVAILABLE_V << LPPERI_LPCORE_DBGM_UNAVAILABLE_S)
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE_V  0x00000001U
+#define LPPERI_LPCORE_DBGM_UNAVAILABLE_S  31
+
+/** LPPERI_MEM_CTRL_REG register
+ *  need_des
+ */
+#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x28)
+/** LPPERI_LP_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR    (BIT(0))
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_M  (LPPERI_LP_UART_WAKEUP_FLAG_CLR_V << LPPERI_LP_UART_WAKEUP_FLAG_CLR_S)
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_V  0x00000001U
+#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_S  0
+/** LPPERI_LP_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_WAKEUP_FLAG    (BIT(1))
+#define LPPERI_LP_UART_WAKEUP_FLAG_M  (LPPERI_LP_UART_WAKEUP_FLAG_V << LPPERI_LP_UART_WAKEUP_FLAG_S)
+#define LPPERI_LP_UART_WAKEUP_FLAG_V  0x00000001U
+#define LPPERI_LP_UART_WAKEUP_FLAG_S  1
+/** LPPERI_LP_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_WAKEUP_EN    (BIT(29))
+#define LPPERI_LP_UART_WAKEUP_EN_M  (LPPERI_LP_UART_WAKEUP_EN_V << LPPERI_LP_UART_WAKEUP_EN_S)
+#define LPPERI_LP_UART_WAKEUP_EN_V  0x00000001U
+#define LPPERI_LP_UART_WAKEUP_EN_S  29
+/** LPPERI_LP_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_UART_MEM_FORCE_PD    (BIT(30))
+#define LPPERI_LP_UART_MEM_FORCE_PD_M  (LPPERI_LP_UART_MEM_FORCE_PD_V << LPPERI_LP_UART_MEM_FORCE_PD_S)
+#define LPPERI_LP_UART_MEM_FORCE_PD_V  0x00000001U
+#define LPPERI_LP_UART_MEM_FORCE_PD_S  30
+/** LPPERI_LP_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LP_UART_MEM_FORCE_PU    (BIT(31))
+#define LPPERI_LP_UART_MEM_FORCE_PU_M  (LPPERI_LP_UART_MEM_FORCE_PU_V << LPPERI_LP_UART_MEM_FORCE_PU_S)
+#define LPPERI_LP_UART_MEM_FORCE_PU_V  0x00000001U
+#define LPPERI_LP_UART_MEM_FORCE_PU_S  31
+
+/** LPPERI_ADC_CTRL_REG register
+ *  need_des
+ */
+#define LPPERI_ADC_CTRL_REG (DR_REG_LPPERI_BASE + 0x2c)
+/** LPPERI_SAR2_CLK_FORCE_ON : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LPPERI_SAR2_CLK_FORCE_ON    (BIT(6))
+#define LPPERI_SAR2_CLK_FORCE_ON_M  (LPPERI_SAR2_CLK_FORCE_ON_V << LPPERI_SAR2_CLK_FORCE_ON_S)
+#define LPPERI_SAR2_CLK_FORCE_ON_V  0x00000001U
+#define LPPERI_SAR2_CLK_FORCE_ON_S  6
+/** LPPERI_SAR1_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LPPERI_SAR1_CLK_FORCE_ON    (BIT(7))
+#define LPPERI_SAR1_CLK_FORCE_ON_M  (LPPERI_SAR1_CLK_FORCE_ON_V << LPPERI_SAR1_CLK_FORCE_ON_S)
+#define LPPERI_SAR1_CLK_FORCE_ON_V  0x00000001U
+#define LPPERI_SAR1_CLK_FORCE_ON_S  7
+/** LPPERI_LPADC_FUNC_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
+ *  need_des
+ */
+#define LPPERI_LPADC_FUNC_DIV_NUM    0x000000FFU
+#define LPPERI_LPADC_FUNC_DIV_NUM_M  (LPPERI_LPADC_FUNC_DIV_NUM_V << LPPERI_LPADC_FUNC_DIV_NUM_S)
+#define LPPERI_LPADC_FUNC_DIV_NUM_V  0x000000FFU
+#define LPPERI_LPADC_FUNC_DIV_NUM_S  8
+/** LPPERI_LPADC_SAR2_DIV_NUM : R/W; bitpos: [23:16]; default: 4;
+ *  need_des
+ */
+#define LPPERI_LPADC_SAR2_DIV_NUM    0x000000FFU
+#define LPPERI_LPADC_SAR2_DIV_NUM_M  (LPPERI_LPADC_SAR2_DIV_NUM_V << LPPERI_LPADC_SAR2_DIV_NUM_S)
+#define LPPERI_LPADC_SAR2_DIV_NUM_V  0x000000FFU
+#define LPPERI_LPADC_SAR2_DIV_NUM_S  16
+/** LPPERI_LPADC_SAR1_DIV_NUM : R/W; bitpos: [31:24]; default: 4;
+ *  need_des
+ */
+#define LPPERI_LPADC_SAR1_DIV_NUM    0x000000FFU
+#define LPPERI_LPADC_SAR1_DIV_NUM_M  (LPPERI_LPADC_SAR1_DIV_NUM_V << LPPERI_LPADC_SAR1_DIV_NUM_S)
+#define LPPERI_LPADC_SAR1_DIV_NUM_V  0x000000FFU
+#define LPPERI_LPADC_SAR1_DIV_NUM_S  24
+
+/** LPPERI_LP_I2S_RXCLK_DIV_NUM_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x30)
+/** LPPERI_LP_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_M  (LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S  24
+
+/** LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x34)
+/** LPPERI_LP_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1    (BIT(4))
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_M  (LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S  4
+/** LPPERI_LP_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_M  (LPPERI_LP_I2S_RX_CLKM_DIV_Z_V << LPPERI_LP_I2S_RX_CLKM_DIV_Z_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_S  5
+/** LPPERI_LP_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_M  (LPPERI_LP_I2S_RX_CLKM_DIV_Y_V << LPPERI_LP_I2S_RX_CLKM_DIV_Y_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_S  14
+/** LPPERI_LP_I2S_RX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X    0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X_M  (LPPERI_LP_I2S_RX_CLKM_DIV_X_V << LPPERI_LP_I2S_RX_CLKM_DIV_X_S)
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define LPPERI_LP_I2S_RX_CLKM_DIV_X_S  23
+
+/** LPPERI_LP_I2S_TXCLK_DIV_NUM_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x38)
+/** LPPERI_LP_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_M  (LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S  24
+
+/** LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG register
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x3c)
+/** LPPERI_LP_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1    (BIT(4))
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_M  (LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S  4
+/** LPPERI_LP_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_M  (LPPERI_LP_I2S_TX_CLKM_DIV_Z_V << LPPERI_LP_I2S_TX_CLKM_DIV_Z_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_S  5
+/** LPPERI_LP_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_M  (LPPERI_LP_I2S_TX_CLKM_DIV_Y_V << LPPERI_LP_I2S_TX_CLKM_DIV_Y_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_S  14
+/** LPPERI_LP_I2S_TX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0;
+ *  need_des
+ */
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X    0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X_M  (LPPERI_LP_I2S_TX_CLKM_DIV_X_V << LPPERI_LP_I2S_TX_CLKM_DIV_X_S)
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define LPPERI_LP_I2S_TX_CLKM_DIV_X_S  23
+
+/** LPPERI_DATE_REG register
+ *  need_des
+ */
+#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
+/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPPERI_CLK_EN    (BIT(31))
+#define LPPERI_CLK_EN_M  (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
+#define LPPERI_CLK_EN_V  0x00000001U
+#define LPPERI_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/lpperi_struct.h

@@ -0,0 +1,379 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** ck_en_rng : R/W; bitpos: [16]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_rng:1;
+        /** ck_en_lp_tsens : R/W; bitpos: [17]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_tsens:1;
+        /** ck_en_lp_pms : R/W; bitpos: [18]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_pms:1;
+        /** ck_en_lp_efuse : R/W; bitpos: [19]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_efuse:1;
+        /** ck_en_lp_iomux : R/W; bitpos: [20]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_iomux:1;
+        /** ck_en_lp_touch : R/W; bitpos: [21]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_touch:1;
+        /** ck_en_lp_spi : R/W; bitpos: [22]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_spi:1;
+        /** ck_en_lp_adc : R/W; bitpos: [23]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_adc:1;
+        /** ck_en_lp_i2s_tx : R/W; bitpos: [24]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2s_tx:1;
+        /** ck_en_lp_i2s_rx : R/W; bitpos: [25]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2s_rx:1;
+        /** ck_en_lp_i2s : R/W; bitpos: [26]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2s:1;
+        /** ck_en_lp_i2cmst : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2cmst:1;
+        /** ck_en_lp_i2c : R/W; bitpos: [28]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_i2c:1;
+        /** ck_en_lp_uart : R/W; bitpos: [29]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_uart:1;
+        /** ck_en_lp_intr : R/W; bitpos: [30]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_intr:1;
+        /** ck_en_lp_core : R/W; bitpos: [31]; default: 0;
+         *  write 1 to force on lp_core clk
+         */
+        uint32_t ck_en_lp_core:1;
+    };
+    uint32_t val;
+} lpperi_clk_en_reg_t;
+
+/** Type of core_clk_sel register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** lp_i2s_tx_clk_sel : R/W; bitpos: [25:24]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clk_sel:2;
+        /** lp_i2s_rx_clk_sel : R/W; bitpos: [27:26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clk_sel:2;
+        /** lp_i2c_clk_sel : R/W; bitpos: [29:28]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2c_clk_sel:2;
+        /** lp_uart_clk_sel : R/W; bitpos: [31:30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_clk_sel:2;
+    };
+    uint32_t val;
+} lpperi_core_clk_sel_reg_t;
+
+/** Type of reset_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:17;
+        /** rst_en_lp_rng : R/W; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rng:1;
+        /** rst_en_lp_tsens : R/W; bitpos: [18]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_tsens:1;
+        /** rst_en_lp_pms : R/W; bitpos: [19]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_pms:1;
+        /** rst_en_lp_efuse : R/W; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_efuse:1;
+        /** rst_en_lp_iomux : R/W; bitpos: [21]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_iomux:1;
+        /** rst_en_lp_touch : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_touch:1;
+        /** rst_en_lp_spi : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_spi:1;
+        /** rst_en_lp_adc : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_adc:1;
+        /** rst_en_lp_i2s : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_i2s:1;
+        /** rst_en_lp_i2cmst : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_i2cmst:1;
+        /** rst_en_lp_i2c : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_i2c:1;
+        /** rst_en_lp_uart : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_uart:1;
+        /** rst_en_lp_intr : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_intr:1;
+        /** rst_en_lp_rom : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rom:1;
+        /** rst_en_lp_core : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_core:1;
+    };
+    uint32_t val;
+} lpperi_reset_en_reg_t;
+
+/** Type of cpu register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpcore_dbgm_unavailable : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t lpcore_dbgm_unavailable:1;
+    };
+    uint32_t val;
+} lpperi_cpu_reg_t;
+
+/** Type of mem_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lp_uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_wakeup_flag_clr:1;
+        /** lp_uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_wakeup_flag:1;
+        uint32_t reserved_2:27;
+        /** lp_uart_wakeup_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_wakeup_en:1;
+        /** lp_uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_uart_mem_force_pd:1;
+        /** lp_uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_uart_mem_force_pu:1;
+    };
+    uint32_t val;
+} lpperi_mem_ctrl_reg_t;
+
+/** Type of adc_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** sar2_clk_force_on : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_clk_force_on:1;
+        /** sar1_clk_force_on : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_clk_force_on:1;
+        /** lpadc_func_div_num : R/W; bitpos: [15:8]; default: 4;
+         *  need_des
+         */
+        uint32_t lpadc_func_div_num:8;
+        /** lpadc_sar2_div_num : R/W; bitpos: [23:16]; default: 4;
+         *  need_des
+         */
+        uint32_t lpadc_sar2_div_num:8;
+        /** lpadc_sar1_div_num : R/W; bitpos: [31:24]; default: 4;
+         *  need_des
+         */
+        uint32_t lpadc_sar1_div_num:8;
+    };
+    uint32_t val;
+} lpperi_adc_ctrl_reg_t;
+
+/** Type of lp_i2s_rxclk_div_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** lp_i2s_rx_clkm_div_num : R/W; bitpos: [31:24]; default: 2;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_num:8;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_rxclk_div_num_reg_t;
+
+/** Type of lp_i2s_rxclk_div_xyz register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lp_i2s_rx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_yn1:1;
+        /** lp_i2s_rx_clkm_div_z : R/W; bitpos: [13:5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_z:9;
+        /** lp_i2s_rx_clkm_div_y : R/W; bitpos: [22:14]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_y:9;
+        /** lp_i2s_rx_clkm_div_x : R/W; bitpos: [31:23]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_rx_clkm_div_x:9;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_rxclk_div_xyz_reg_t;
+
+/** Type of lp_i2s_txclk_div_num register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** lp_i2s_tx_clkm_div_num : R/W; bitpos: [31:24]; default: 2;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_num:8;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_txclk_div_num_reg_t;
+
+/** Type of lp_i2s_txclk_div_xyz register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** lp_i2s_tx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_yn1:1;
+        /** lp_i2s_tx_clkm_div_z : R/W; bitpos: [13:5]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_z:9;
+        /** lp_i2s_tx_clkm_div_y : R/W; bitpos: [22:14]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_y:9;
+        /** lp_i2s_tx_clkm_div_x : R/W; bitpos: [31:23]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_i2s_tx_clkm_div_x:9;
+    };
+    uint32_t val;
+} lpperi_lp_i2s_txclk_div_xyz_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lpperi_date_reg_t;
+
+
+typedef struct {
+    volatile lpperi_clk_en_reg_t clk_en;
+    volatile lpperi_core_clk_sel_reg_t core_clk_sel;
+    volatile lpperi_reset_en_reg_t reset_en;
+    volatile lpperi_cpu_reg_t cpu;
+    uint32_t reserved_010[6];
+    volatile lpperi_mem_ctrl_reg_t mem_ctrl;
+    volatile lpperi_adc_ctrl_reg_t adc_ctrl;
+    volatile lpperi_lp_i2s_rxclk_div_num_reg_t lp_i2s_rxclk_div_num;
+    volatile lpperi_lp_i2s_rxclk_div_xyz_reg_t lp_i2s_rxclk_div_xyz;
+    volatile lpperi_lp_i2s_txclk_div_num_reg_t lp_i2s_txclk_div_num;
+    volatile lpperi_lp_i2s_txclk_div_xyz_reg_t lp_i2s_txclk_div_xyz;
+    uint32_t reserved_040[239];
+    volatile lpperi_date_reg_t date;
+} lpperi_dev_t;
+
+extern lpperi_dev_t LPPERI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_reg.h

@@ -0,0 +1,217 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MEM_MONITOR_LOG_SETTING_REG register
+ *  log config register
+ */
+#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
+/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
+ *  Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
+ *  monitor
+ */
+#define MEM_MONITOR_LOG_MODE    0x0000000FU
+#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
+#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
+#define MEM_MONITOR_LOG_MODE_S  0
+/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
+ *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(4))
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  4
+/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
+ *  enable core log
+ */
+#define MEM_MONITOR_LOG_CORE_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_CORE_ENA_M  (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
+#define MEM_MONITOR_LOG_CORE_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_CORE_ENA_S  8
+/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
+ *  enable dma_0 log
+ */
+#define MEM_MONITOR_LOG_DMA_0_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_0_ENA_M  (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
+#define MEM_MONITOR_LOG_DMA_0_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_0_ENA_S  16
+/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
+ *  enable dma_1 log
+ */
+#define MEM_MONITOR_LOG_DMA_1_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_1_ENA_M  (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
+#define MEM_MONITOR_LOG_DMA_1_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_1_ENA_S  24
+
+/** MEM_MONITOR_LOG_SETTING1_REG register
+ *  log config register
+ */
+#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
+/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
+ *  enable dma_2 log
+ */
+#define MEM_MONITOR_LOG_DMA_2_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_2_ENA_M  (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
+#define MEM_MONITOR_LOG_DMA_2_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_2_ENA_S  0
+/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
+ *  enable dma_3 log
+ */
+#define MEM_MONITOR_LOG_DMA_3_ENA    0x000000FFU
+#define MEM_MONITOR_LOG_DMA_3_ENA_M  (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
+#define MEM_MONITOR_LOG_DMA_3_ENA_V  0x000000FFU
+#define MEM_MONITOR_LOG_DMA_3_ENA_S  8
+
+/** MEM_MONITOR_LOG_CHECK_DATA_REG register
+ *  check data register
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
+/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The special check data, when write this special data, it will trigger logging.
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
+#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_S  0
+
+/** MEM_MONITOR_LOG_DATA_MASK_REG register
+ *  check data mask register
+ */
+#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
+/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
+ *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+ *  mask second byte, and so on.
+ */
+#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
+#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_S  0
+
+/** MEM_MONITOR_LOG_MIN_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
+/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  the min address of log range
+ */
+#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
+#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_S  0
+
+/** MEM_MONITOR_LOG_MAX_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
+/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  the max address of log range
+ */
+#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
+#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_S  0
+
+/** MEM_MONITOR_LOG_MEM_START_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
+/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
+ *  the start address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
+#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_S  0
+
+/** MEM_MONITOR_LOG_MEM_END_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
+/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
+ *  the end address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
+#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_S  0
+
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
+ *  current writing address.
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  means next writing address
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
+
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
+ *  writing address update
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+ *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
+
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
+ *  full flag status register
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
+ *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
+/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
+ *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+ */
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
+
+/** MEM_MONITOR_CLOCK_GATE_REG register
+ *  clock gate force on register
+ */
+#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
+/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to force on the clk of mem_monitor register
+ */
+#define MEM_MONITOR_CLK_EN    (BIT(0))
+#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
+#define MEM_MONITOR_CLK_EN_V  0x00000001U
+#define MEM_MONITOR_CLK_EN_S  0
+
+/** MEM_MONITOR_DATE_REG register
+ *  version register
+ */
+#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
+/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36708896;
+ *  version register
+ */
+#define MEM_MONITOR_DATE    0x0FFFFFFFU
+#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
+#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
+#define MEM_MONITOR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_struct.h

@@ -0,0 +1,247 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration registers */
+/** Type of log_setting register
+ *  log config register
+ */
+typedef union {
+    struct {
+        /** log_mode : R/W; bitpos: [3:0]; default: 0;
+         *  Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
+         *  monitor
+         */
+        uint32_t log_mode:4;
+        /** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
+         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_loop_enable:1;
+        uint32_t reserved_5:3;
+        /** log_core_ena : R/W; bitpos: [15:8]; default: 0;
+         *  enable core log
+         */
+        uint32_t log_core_ena:8;
+        /** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
+         *  enable dma_0 log
+         */
+        uint32_t log_dma_0_ena:8;
+        /** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
+         *  enable dma_1 log
+         */
+        uint32_t log_dma_1_ena:8;
+    };
+    uint32_t val;
+} mem_monitor_log_setting_reg_t;
+
+/** Type of log_setting1 register
+ *  log config register
+ */
+typedef union {
+    struct {
+        /** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
+         *  enable dma_2 log
+         */
+        uint32_t log_dma_2_ena:8;
+        /** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
+         *  enable dma_3 log
+         */
+        uint32_t log_dma_3_ena:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mem_monitor_log_setting1_reg_t;
+
+/** Type of log_check_data register
+ *  check data register
+ */
+typedef union {
+    struct {
+        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
+         *  The special check data, when write this special data, it will trigger logging.
+         */
+        uint32_t log_check_data:32;
+    };
+    uint32_t val;
+} mem_monitor_log_check_data_reg_t;
+
+/** Type of log_data_mask register
+ *  check data mask register
+ */
+typedef union {
+    struct {
+        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
+         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+         *  mask second byte, and so on.
+         */
+        uint32_t log_data_mask:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} mem_monitor_log_data_mask_reg_t;
+
+/** Type of log_min register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_min : R/W; bitpos: [31:0]; default: 0;
+         *  the min address of log range
+         */
+        uint32_t log_min:32;
+    };
+    uint32_t val;
+} mem_monitor_log_min_reg_t;
+
+/** Type of log_max register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_max : R/W; bitpos: [31:0]; default: 0;
+         *  the max address of log range
+         */
+        uint32_t log_max:32;
+    };
+    uint32_t val;
+} mem_monitor_log_max_reg_t;
+
+/** Type of log_mem_start register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
+         *  the start address of writing logging message
+         */
+        uint32_t log_mem_start:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_start_reg_t;
+
+/** Type of log_mem_end register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
+         *  the end address of writing logging message
+         */
+        uint32_t log_mem_end:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_end_reg_t;
+
+/** Type of log_mem_current_addr register
+ *  current writing address.
+ */
+typedef union {
+    struct {
+        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  means next writing address
+         */
+        uint32_t log_mem_current_addr:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_current_addr_reg_t;
+
+/** Type of log_mem_addr_update register
+ *  writing address update
+ */
+typedef union {
+    struct {
+        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
+         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+         */
+        uint32_t log_mem_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_addr_update_reg_t;
+
+/** Type of log_mem_full_flag register
+ *  full flag status register
+ */
+typedef union {
+    struct {
+        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
+         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_full_flag:1;
+        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
+         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+         */
+        uint32_t clr_log_mem_full_flag:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_full_flag_reg_t;
+
+
+/** Group: clk register */
+/** Type of clock_gate register
+ *  clock gate force on register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to force on the clk of mem_monitor register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_clock_gate_reg_t;
+
+
+/** Group: version register */
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36708896;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mem_monitor_date_reg_t;
+
+
+typedef struct {
+    volatile mem_monitor_log_setting_reg_t log_setting;
+    volatile mem_monitor_log_setting1_reg_t log_setting1;
+    volatile mem_monitor_log_check_data_reg_t log_check_data;
+    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
+    volatile mem_monitor_log_min_reg_t log_min;
+    volatile mem_monitor_log_max_reg_t log_max;
+    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
+    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
+    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
+    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
+    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
+    volatile mem_monitor_clock_gate_reg_t clock_gate;
+    uint32_t reserved_030[243];
+    volatile mem_monitor_date_reg_t date;
+} mem_monitor_dev_t;
+
+extern mem_monitor_dev_t MEM_MONITOR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_eco5_struct.h

@@ -0,0 +1,452 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: csi bridge regbank clock gating control register. */
+/** Type of clk_en register
+ *  csi bridge register mapping unit clock gating.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  0: enable clock gating. 1: disable clock gating, clock always on.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_brg_clk_en_reg_t;
+
+
+/** Group: csi bridge control registers. */
+/** Type of csi_en register
+ *  csi bridge enable.
+ */
+typedef union {
+    struct {
+        /** csi_brg_en : R/W; bitpos: [0]; default: 0;
+         *  0: disable csi bridge. 1: enable csi bridge.
+         */
+        uint32_t csi_brg_en:1;
+        /** csi_brg_rst : R/W; bitpos: [1]; default: 0;
+         *  0: release csi bridge reset. 1: enable csi bridge reset.
+         */
+        uint32_t csi_brg_rst:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_brg_csi_en_reg_t;
+
+/** Type of buf_flow_ctl register
+ *  csi bridge buffer control.
+ */
+typedef union {
+    struct {
+        /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040;
+         *  buffer almost full threshold.
+         */
+        uint32_t csi_buf_afull_thrd:14;
+        uint32_t reserved_14:2;
+        /** csi_buf_depth : RO; bitpos: [29:16]; default: 0;
+         *  buffer data count.
+         */
+        uint32_t csi_buf_depth:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} csi_brg_buf_flow_ctl_reg_t;
+
+
+/** Group: csi bridge dma control registers. */
+/** Type of dma_req_cfg register
+ *  dma request configuration.
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  DMA burst length.
+         */
+        uint32_t dma_burst_len:12;
+        /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
+         *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
+         *  updated by frame.
+         */
+        uint32_t dma_cfg_upd_by_blk:1;
+        uint32_t reserved_13:3;
+        /** dma_force_rd_status : R/W; bitpos: [16]; default: 0;
+         *  1: mask dma request when reading frame info. 0: disable mask.
+         */
+        uint32_t dma_force_rd_status:1;
+        /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1;
+         *  0: dma as flow controller. 1: csi_bridge as flow controller
+         */
+        uint32_t csi_dma_flow_controller:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} csi_brg_dma_req_cfg_reg_t;
+
+/** Type of dma_req_interval register
+ *  DMA interval configuration.
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_brg_dma_req_interval_reg_t;
+
+/** Type of dmablk_size register
+ *  DMA block size configuration.
+ */
+typedef union {
+    struct {
+        /** dmablk_size : R/W; bitpos: [12:0]; default: 8191;
+         *  the number of reg_dma_burst_len in a block
+         */
+        uint32_t dmablk_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} csi_brg_dmablk_size_reg_t;
+
+
+/** Group: csi bridge frame format configuration registers. */
+/** Type of data_type_cfg register
+ *  pixel data type configuration.
+ */
+typedef union {
+    struct {
+        /** data_type_min : R/W; bitpos: [5:0]; default: 24;
+         *  the min value of data type used for pixel filter.
+         */
+        uint32_t data_type_min:6;
+        uint32_t reserved_6:2;
+        /** data_type_max : R/W; bitpos: [13:8]; default: 47;
+         *  the max value of data type used for pixel filter.
+         */
+        uint32_t data_type_max:6;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_data_type_cfg_reg_t;
+
+/** Type of frame_cfg register
+ *  frame configuration.
+ */
+typedef union {
+    struct {
+        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
+         *  vadr of frame data.
+         */
+        uint32_t vadr_num:12;
+        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
+         *  hadr of frame data.
+         */
+        uint32_t hadr_num:12;
+        /** has_hsync_e : R/W; bitpos: [24]; default: 1;
+         *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
+         */
+        uint32_t has_hsync_e:1;
+        /** vadr_num_check : R/W; bitpos: [25]; default: 0;
+         *  0: disable vadr check. 1: enable vadr check.
+         */
+        uint32_t vadr_num_check:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} csi_brg_frame_cfg_reg_t;
+
+/** Type of endian_mode register
+ *  data endianness order configuration.
+ */
+typedef union {
+    struct {
+        /** byte_endian_order : R/W; bitpos: [0]; default: 0;
+         *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
+         *  when isp is bapassed.
+         */
+        uint32_t byte_endian_order:1;
+        /** bit_endian_order : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t bit_endian_order:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_brg_endian_mode_reg_t;
+
+
+/** Group: csi bridge interrupt registers. */
+/** Type of int_raw register
+ *  csi bridge interrupt raw.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt raw.
+         */
+        uint32_t vadr_num_gt_int_raw:1;
+        /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt raw.
+         */
+        uint32_t vadr_num_lt_int_raw:1;
+        /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt raw.
+         */
+        uint32_t discard_int_raw:1;
+        /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt raw.
+         */
+        uint32_t csi_buf_overrun_int_raw:1;
+        /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt raw.
+         */
+        uint32_t csi_async_fifo_ovf_int_raw:1;
+        /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt raw.
+         */
+        uint32_t dma_cfg_has_updated_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  csi bridge interrupt clr.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt clr.
+         */
+        uint32_t vadr_num_gt_real_int_clr:1;
+        /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt clr.
+         */
+        uint32_t vadr_num_lt_real_int_clr:1;
+        /** discard_int_clr : WT; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt clr.
+         */
+        uint32_t discard_int_clr:1;
+        /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt clr.
+         */
+        uint32_t csi_buf_overrun_int_clr:1;
+        /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt clr.
+         */
+        uint32_t csi_async_fifo_ovf_int_clr:1;
+        /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt clr.
+         */
+        uint32_t dma_cfg_has_updated_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_clr_reg_t;
+
+/** Type of int_st register
+ *  csi bridge interrupt st.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt st.
+         */
+        uint32_t vadr_num_gt_int_st:1;
+        /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt st.
+         */
+        uint32_t vadr_num_lt_int_st:1;
+        /** discard_int_st : RO; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt st.
+         */
+        uint32_t discard_int_st:1;
+        /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt st.
+         */
+        uint32_t csi_buf_overrun_int_st:1;
+        /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt st.
+         */
+        uint32_t csi_async_fifo_ovf_int_st:1;
+        /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt st.
+         */
+        uint32_t dma_cfg_has_updated_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_st_reg_t;
+
+/** Type of int_ena register
+ *  csi bridge interrupt enable.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt enable.
+         */
+        uint32_t vadr_num_gt_int_ena:1;
+        /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt enable.
+         */
+        uint32_t vadr_num_lt_int_ena:1;
+        /** discard_int_ena : R/W; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt enable.
+         */
+        uint32_t discard_int_ena:1;
+        /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt enable.
+         */
+        uint32_t csi_buf_overrun_int_ena:1;
+        /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt enable.
+         */
+        uint32_t csi_async_fifo_ovf_int_ena:1;
+        /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt enable.
+         */
+        uint32_t dma_cfg_has_updated_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_ena_reg_t;
+
+
+/** Group: csi-host control registers from csi bridge regbank. */
+/** Type of host_ctrl register
+ *  csi host control by csi bridge.
+ */
+typedef union {
+    struct {
+        /** csi_enableclk : R/W; bitpos: [0]; default: 1;
+         *  enable clock lane module of csi phy.
+         */
+        uint32_t csi_enableclk:1;
+        /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
+         *  enable cfg_clk of csi host module.
+         */
+        uint32_t csi_cfg_clk_en:1;
+        /** loopbk_test_en : R/W; bitpos: [2]; default: 0;
+         *  for phy test by loopback dsi phy to csi phy.
+         */
+        uint32_t loopbk_test_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} csi_brg_host_ctrl_reg_t;
+
+
+/** Group: csi host color mode control registers. */
+/** Type of host_cm_ctrl register
+ *  CSI HOST color mode convert configuration.
+ */
+typedef union {
+    struct {
+        /** csi_host_cm_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to enable cm output
+         */
+        uint32_t csi_host_cm_en:1;
+        /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_bypass:1;
+        /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx:2;
+        /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx_rgb_format:3;
+        /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx_yuv422_format:2;
+        /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_tx:2;
+        /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1;
+         *  Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1:
+         *  2-lane
+         */
+        uint32_t csi_host_cm_lane_num:1;
+        /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to swap idi32 high and low 16-bit
+         */
+        uint32_t csi_host_cm_16bit_swap:1;
+        /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0;
+         *  Configures whether to swap idi32 high and low 8-bit
+         */
+        uint32_t csi_host_cm_8bit_swap:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_host_cm_ctrl_reg_t;
+
+/** Type of host_size_ctrl register
+ *  CSI HOST color mode convert configuration.
+ */
+typedef union {
+    struct {
+        /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0;
+         *  Configures idi32 image size in y-direction, row_num - 1, valid only when
+         *  yuv422_to_yuv420_en = 1
+         */
+        uint32_t csi_host_cm_vnum:12;
+        /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0;
+         *  Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid
+         *  only when yuv422_to_yuv420_en = 1
+         */
+        uint32_t csi_host_cm_hnum:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} csi_brg_host_size_ctrl_reg_t;
+
+
+typedef struct {
+    volatile csi_brg_clk_en_reg_t clk_en;
+    volatile csi_brg_csi_en_reg_t csi_en;
+    volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl;
+    volatile csi_brg_data_type_cfg_reg_t data_type_cfg;
+    volatile csi_brg_frame_cfg_reg_t frame_cfg;
+    volatile csi_brg_endian_mode_reg_t endian_mode;
+    volatile csi_brg_int_raw_reg_t int_raw;
+    volatile csi_brg_int_clr_reg_t int_clr;
+    volatile csi_brg_int_st_reg_t int_st;
+    volatile csi_brg_int_ena_reg_t int_ena;
+    volatile csi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile csi_brg_dmablk_size_reg_t dmablk_size;
+    uint32_t reserved_034[3];
+    volatile csi_brg_host_ctrl_reg_t host_ctrl;
+    uint32_t reserved_044;
+    volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl;
+    volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl;
+} csi_brg_dev_t;
+
+extern csi_brg_dev_t MIPI_CSI_BRIDGE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_reg.h

@@ -0,0 +1,500 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CSI_BRIG_CLK_EN_REG register
+ *  csi bridge register mapping unit clock gating.
+ */
+#define CSI_BRIG_CLK_EN_REG (DR_REG_CSI_BRIG_BASE + 0x0)
+/** CSI_BRIG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  0: enable clock gating. 1: disable clock gating, clock always on.
+ */
+#define CSI_BRIG_CLK_EN    (BIT(0))
+#define CSI_BRIG_CLK_EN_M  (CSI_BRIG_CLK_EN_V << CSI_BRIG_CLK_EN_S)
+#define CSI_BRIG_CLK_EN_V  0x00000001U
+#define CSI_BRIG_CLK_EN_S  0
+
+/** CSI_BRIG_CSI_EN_REG register
+ *  csi bridge enable.
+ */
+#define CSI_BRIG_CSI_EN_REG (DR_REG_CSI_BRIG_BASE + 0x4)
+/** CSI_BRIG_CSI_BRIG_EN : R/W; bitpos: [0]; default: 0;
+ *  0: disable csi bridge. 1: enable csi bridge.
+ */
+#define CSI_BRIG_CSI_BRIG_EN    (BIT(0))
+#define CSI_BRIG_CSI_BRIG_EN_M  (CSI_BRIG_CSI_BRIG_EN_V << CSI_BRIG_CSI_BRIG_EN_S)
+#define CSI_BRIG_CSI_BRIG_EN_V  0x00000001U
+#define CSI_BRIG_CSI_BRIG_EN_S  0
+/** CSI_BRIG_CSI_BRIG_RST : R/W; bitpos: [1]; default: 0;
+ *  0: release csi bridge reset. 1: enable csi bridge reset.
+ */
+#define CSI_BRIG_CSI_BRIG_RST    (BIT(1))
+#define CSI_BRIG_CSI_BRIG_RST_M  (CSI_BRIG_CSI_BRIG_RST_V << CSI_BRIG_CSI_BRIG_RST_S)
+#define CSI_BRIG_CSI_BRIG_RST_V  0x00000001U
+#define CSI_BRIG_CSI_BRIG_RST_S  1
+
+/** CSI_BRIG_DMA_REQ_CFG_REG register
+ *  dma request configuration.
+ */
+#define CSI_BRIG_DMA_REQ_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x8)
+/** CSI_BRIG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128;
+ *  DMA burst length.
+ */
+#define CSI_BRIG_DMA_BURST_LEN    0x00000FFFU
+#define CSI_BRIG_DMA_BURST_LEN_M  (CSI_BRIG_DMA_BURST_LEN_V << CSI_BRIG_DMA_BURST_LEN_S)
+#define CSI_BRIG_DMA_BURST_LEN_V  0x00000FFFU
+#define CSI_BRIG_DMA_BURST_LEN_S  0
+/** CSI_BRIG_DMA_CFG_UPD_BY_BLK : R/W; bitpos: [12]; default: 0;
+ *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
+ *  updated by frame.
+ */
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK    (BIT(12))
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_M  (CSI_BRIG_DMA_CFG_UPD_BY_BLK_V << CSI_BRIG_DMA_CFG_UPD_BY_BLK_S)
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_S  12
+/** CSI_BRIG_DMA_FORCE_RD_STATUS : R/W; bitpos: [16]; default: 0;
+ *  1: mask dma request when reading frame info. 0: disable mask.
+ */
+#define CSI_BRIG_DMA_FORCE_RD_STATUS    (BIT(16))
+#define CSI_BRIG_DMA_FORCE_RD_STATUS_M  (CSI_BRIG_DMA_FORCE_RD_STATUS_V << CSI_BRIG_DMA_FORCE_RD_STATUS_S)
+#define CSI_BRIG_DMA_FORCE_RD_STATUS_V  0x00000001U
+#define CSI_BRIG_DMA_FORCE_RD_STATUS_S  16
+/** CSI_BRIG_CSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [17]; default: 1;
+ *  0: dma as flow controller. 1: csi_bridge as flow controller
+ */
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER    (BIT(17))
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_M  (CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_V << CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_S)
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_V  0x00000001U
+#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_S  17
+
+/** CSI_BRIG_BUF_FLOW_CTL_REG register
+ *  csi bridge buffer control.
+ */
+#define CSI_BRIG_BUF_FLOW_CTL_REG (DR_REG_CSI_BRIG_BASE + 0xc)
+/** CSI_BRIG_CSI_BUF_AFULL_THRD : R/W; bitpos: [13:0]; default: 2040;
+ *  buffer almost full threshold.
+ */
+#define CSI_BRIG_CSI_BUF_AFULL_THRD    0x00003FFFU
+#define CSI_BRIG_CSI_BUF_AFULL_THRD_M  (CSI_BRIG_CSI_BUF_AFULL_THRD_V << CSI_BRIG_CSI_BUF_AFULL_THRD_S)
+#define CSI_BRIG_CSI_BUF_AFULL_THRD_V  0x00003FFFU
+#define CSI_BRIG_CSI_BUF_AFULL_THRD_S  0
+/** CSI_BRIG_CSI_BUF_DEPTH : RO; bitpos: [29:16]; default: 0;
+ *  buffer data count.
+ */
+#define CSI_BRIG_CSI_BUF_DEPTH    0x00003FFFU
+#define CSI_BRIG_CSI_BUF_DEPTH_M  (CSI_BRIG_CSI_BUF_DEPTH_V << CSI_BRIG_CSI_BUF_DEPTH_S)
+#define CSI_BRIG_CSI_BUF_DEPTH_V  0x00003FFFU
+#define CSI_BRIG_CSI_BUF_DEPTH_S  16
+
+/** CSI_BRIG_DATA_TYPE_CFG_REG register
+ *  pixel data type configuration.
+ */
+#define CSI_BRIG_DATA_TYPE_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x10)
+/** CSI_BRIG_DATA_TYPE_MIN : R/W; bitpos: [5:0]; default: 24;
+ *  the min value of data type used for pixel filter.
+ */
+#define CSI_BRIG_DATA_TYPE_MIN    0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MIN_M  (CSI_BRIG_DATA_TYPE_MIN_V << CSI_BRIG_DATA_TYPE_MIN_S)
+#define CSI_BRIG_DATA_TYPE_MIN_V  0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MIN_S  0
+/** CSI_BRIG_DATA_TYPE_MAX : R/W; bitpos: [13:8]; default: 47;
+ *  the max value of data type used for pixel filter.
+ */
+#define CSI_BRIG_DATA_TYPE_MAX    0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MAX_M  (CSI_BRIG_DATA_TYPE_MAX_V << CSI_BRIG_DATA_TYPE_MAX_S)
+#define CSI_BRIG_DATA_TYPE_MAX_V  0x0000003FU
+#define CSI_BRIG_DATA_TYPE_MAX_S  8
+
+/** CSI_BRIG_FRAME_CFG_REG register
+ *  frame configuration.
+ */
+#define CSI_BRIG_FRAME_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x14)
+/** CSI_BRIG_VADR_NUM : R/W; bitpos: [11:0]; default: 480;
+ *  vadr of frame data.
+ */
+#define CSI_BRIG_VADR_NUM    0x00000FFFU
+#define CSI_BRIG_VADR_NUM_M  (CSI_BRIG_VADR_NUM_V << CSI_BRIG_VADR_NUM_S)
+#define CSI_BRIG_VADR_NUM_V  0x00000FFFU
+#define CSI_BRIG_VADR_NUM_S  0
+/** CSI_BRIG_HADR_NUM : R/W; bitpos: [23:12]; default: 480;
+ *  hadr of frame data.
+ */
+#define CSI_BRIG_HADR_NUM    0x00000FFFU
+#define CSI_BRIG_HADR_NUM_M  (CSI_BRIG_HADR_NUM_V << CSI_BRIG_HADR_NUM_S)
+#define CSI_BRIG_HADR_NUM_V  0x00000FFFU
+#define CSI_BRIG_HADR_NUM_S  12
+/** CSI_BRIG_HAS_HSYNC_E : R/W; bitpos: [24]; default: 1;
+ *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
+ */
+#define CSI_BRIG_HAS_HSYNC_E    (BIT(24))
+#define CSI_BRIG_HAS_HSYNC_E_M  (CSI_BRIG_HAS_HSYNC_E_V << CSI_BRIG_HAS_HSYNC_E_S)
+#define CSI_BRIG_HAS_HSYNC_E_V  0x00000001U
+#define CSI_BRIG_HAS_HSYNC_E_S  24
+/** CSI_BRIG_VADR_NUM_CHECK : R/W; bitpos: [25]; default: 0;
+ *  0: disable vadr check. 1: enable vadr check.
+ */
+#define CSI_BRIG_VADR_NUM_CHECK    (BIT(25))
+#define CSI_BRIG_VADR_NUM_CHECK_M  (CSI_BRIG_VADR_NUM_CHECK_V << CSI_BRIG_VADR_NUM_CHECK_S)
+#define CSI_BRIG_VADR_NUM_CHECK_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_CHECK_S  25
+
+/** CSI_BRIG_ENDIAN_MODE_REG register
+ *  data endianness order configuration.
+ */
+#define CSI_BRIG_ENDIAN_MODE_REG (DR_REG_CSI_BRIG_BASE + 0x18)
+/** CSI_BRIG_BYTE_ENDIAN_ORDER : R/W; bitpos: [0]; default: 0;
+ *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
+ *  when isp is bapassed.
+ */
+#define CSI_BRIG_BYTE_ENDIAN_ORDER    (BIT(0))
+#define CSI_BRIG_BYTE_ENDIAN_ORDER_M  (CSI_BRIG_BYTE_ENDIAN_ORDER_V << CSI_BRIG_BYTE_ENDIAN_ORDER_S)
+#define CSI_BRIG_BYTE_ENDIAN_ORDER_V  0x00000001U
+#define CSI_BRIG_BYTE_ENDIAN_ORDER_S  0
+/** CSI_BRIG_BIT_ENDIAN_ORDER : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define CSI_BRIG_BIT_ENDIAN_ORDER    (BIT(1))
+#define CSI_BRIG_BIT_ENDIAN_ORDER_M  (CSI_BRIG_BIT_ENDIAN_ORDER_V << CSI_BRIG_BIT_ENDIAN_ORDER_S)
+#define CSI_BRIG_BIT_ENDIAN_ORDER_V  0x00000001U
+#define CSI_BRIG_BIT_ENDIAN_ORDER_S  1
+
+/** CSI_BRIG_INT_RAW_REG register
+ *  csi bridge interrupt raw.
+ */
+#define CSI_BRIG_INT_RAW_REG (DR_REG_CSI_BRIG_BASE + 0x1c)
+/** CSI_BRIG_VADR_NUM_GT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt raw.
+ */
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW_M  (CSI_BRIG_VADR_NUM_GT_INT_RAW_V << CSI_BRIG_VADR_NUM_GT_INT_RAW_S)
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_INT_RAW_S  0
+/** CSI_BRIG_VADR_NUM_LT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt raw.
+ */
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW_M  (CSI_BRIG_VADR_NUM_LT_INT_RAW_V << CSI_BRIG_VADR_NUM_LT_INT_RAW_S)
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_INT_RAW_S  1
+/** CSI_BRIG_DISCARD_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt raw.
+ */
+#define CSI_BRIG_DISCARD_INT_RAW    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_RAW_M  (CSI_BRIG_DISCARD_INT_RAW_V << CSI_BRIG_DISCARD_INT_RAW_S)
+#define CSI_BRIG_DISCARD_INT_RAW_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_RAW_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt raw.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt raw.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt raw.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S  5
+
+/** CSI_BRIG_INT_CLR_REG register
+ *  csi bridge interrupt clr.
+ */
+#define CSI_BRIG_INT_CLR_REG (DR_REG_CSI_BRIG_BASE + 0x20)
+/** CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt clr.
+ */
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_M  (CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S)
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S  0
+/** CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt clr.
+ */
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_M  (CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S)
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S  1
+/** CSI_BRIG_DISCARD_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt clr.
+ */
+#define CSI_BRIG_DISCARD_INT_CLR    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_CLR_M  (CSI_BRIG_DISCARD_INT_CLR_V << CSI_BRIG_DISCARD_INT_CLR_S)
+#define CSI_BRIG_DISCARD_INT_CLR_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_CLR_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt clr.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt clr.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt clr.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S  5
+
+/** CSI_BRIG_INT_ST_REG register
+ *  csi bridge interrupt st.
+ */
+#define CSI_BRIG_INT_ST_REG (DR_REG_CSI_BRIG_BASE + 0x24)
+/** CSI_BRIG_VADR_NUM_GT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt st.
+ */
+#define CSI_BRIG_VADR_NUM_GT_INT_ST    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_INT_ST_M  (CSI_BRIG_VADR_NUM_GT_INT_ST_V << CSI_BRIG_VADR_NUM_GT_INT_ST_S)
+#define CSI_BRIG_VADR_NUM_GT_INT_ST_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_INT_ST_S  0
+/** CSI_BRIG_VADR_NUM_LT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt st.
+ */
+#define CSI_BRIG_VADR_NUM_LT_INT_ST    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_INT_ST_M  (CSI_BRIG_VADR_NUM_LT_INT_ST_V << CSI_BRIG_VADR_NUM_LT_INT_ST_S)
+#define CSI_BRIG_VADR_NUM_LT_INT_ST_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_INT_ST_S  1
+/** CSI_BRIG_DISCARD_INT_ST : RO; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt st.
+ */
+#define CSI_BRIG_DISCARD_INT_ST    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_ST_M  (CSI_BRIG_DISCARD_INT_ST_V << CSI_BRIG_DISCARD_INT_ST_S)
+#define CSI_BRIG_DISCARD_INT_ST_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_ST_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt st.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt st.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST : RO; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt st.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S  5
+
+/** CSI_BRIG_INT_ENA_REG register
+ *  csi bridge interrupt enable.
+ */
+#define CSI_BRIG_INT_ENA_REG (DR_REG_CSI_BRIG_BASE + 0x28)
+/** CSI_BRIG_VADR_NUM_GT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  reg_vadr_num is greater than real interrupt enable.
+ */
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA    (BIT(0))
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA_M  (CSI_BRIG_VADR_NUM_GT_INT_ENA_V << CSI_BRIG_VADR_NUM_GT_INT_ENA_S)
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_GT_INT_ENA_S  0
+/** CSI_BRIG_VADR_NUM_LT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  reg_vadr_num is less than real interrupt enable.
+ */
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA    (BIT(1))
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA_M  (CSI_BRIG_VADR_NUM_LT_INT_ENA_V << CSI_BRIG_VADR_NUM_LT_INT_ENA_S)
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA_V  0x00000001U
+#define CSI_BRIG_VADR_NUM_LT_INT_ENA_S  1
+/** CSI_BRIG_DISCARD_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  an incomplete frame of data was sent interrupt enable.
+ */
+#define CSI_BRIG_DISCARD_INT_ENA    (BIT(2))
+#define CSI_BRIG_DISCARD_INT_ENA_M  (CSI_BRIG_DISCARD_INT_ENA_V << CSI_BRIG_DISCARD_INT_ENA_S)
+#define CSI_BRIG_DISCARD_INT_ENA_V  0x00000001U
+#define CSI_BRIG_DISCARD_INT_ENA_S  2
+/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  buffer overrun interrupt enable.
+ */
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA    (BIT(3))
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_M  (CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S)
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V  0x00000001U
+#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S  3
+/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  buffer overflow interrupt enable.
+ */
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA    (BIT(4))
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_M  (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S)
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V  0x00000001U
+#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S  4
+/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  dma configuration update complete interrupt enable.
+ */
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA    (BIT(5))
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_M  (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S)
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V  0x00000001U
+#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S  5
+
+/** CSI_BRIG_DMA_REQ_INTERVAL_REG register
+ *  DMA interval configuration.
+ */
+#define CSI_BRIG_DMA_REQ_INTERVAL_REG (DR_REG_CSI_BRIG_BASE + 0x2c)
+/** CSI_BRIG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1;
+ *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
+ */
+#define CSI_BRIG_DMA_REQ_INTERVAL    0x0000FFFFU
+#define CSI_BRIG_DMA_REQ_INTERVAL_M  (CSI_BRIG_DMA_REQ_INTERVAL_V << CSI_BRIG_DMA_REQ_INTERVAL_S)
+#define CSI_BRIG_DMA_REQ_INTERVAL_V  0x0000FFFFU
+#define CSI_BRIG_DMA_REQ_INTERVAL_S  0
+
+/** CSI_BRIG_DMABLK_SIZE_REG register
+ *  DMA block size configuration.
+ */
+#define CSI_BRIG_DMABLK_SIZE_REG (DR_REG_CSI_BRIG_BASE + 0x30)
+/** CSI_BRIG_DMABLK_SIZE : R/W; bitpos: [12:0]; default: 8191;
+ *  the number of reg_dma_burst_len in a block
+ */
+#define CSI_BRIG_DMABLK_SIZE    0x00001FFFU
+#define CSI_BRIG_DMABLK_SIZE_M  (CSI_BRIG_DMABLK_SIZE_V << CSI_BRIG_DMABLK_SIZE_S)
+#define CSI_BRIG_DMABLK_SIZE_V  0x00001FFFU
+#define CSI_BRIG_DMABLK_SIZE_S  0
+
+/** CSI_BRIG_HOST_CTRL_REG register
+ *  csi host control by csi bridge.
+ */
+#define CSI_BRIG_HOST_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x40)
+/** CSI_BRIG_CSI_ENABLECLK : R/W; bitpos: [0]; default: 1;
+ *  enable clock lane module of csi phy.
+ */
+#define CSI_BRIG_CSI_ENABLECLK    (BIT(0))
+#define CSI_BRIG_CSI_ENABLECLK_M  (CSI_BRIG_CSI_ENABLECLK_V << CSI_BRIG_CSI_ENABLECLK_S)
+#define CSI_BRIG_CSI_ENABLECLK_V  0x00000001U
+#define CSI_BRIG_CSI_ENABLECLK_S  0
+/** CSI_BRIG_CSI_CFG_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  enable cfg_clk of csi host module.
+ */
+#define CSI_BRIG_CSI_CFG_CLK_EN    (BIT(1))
+#define CSI_BRIG_CSI_CFG_CLK_EN_M  (CSI_BRIG_CSI_CFG_CLK_EN_V << CSI_BRIG_CSI_CFG_CLK_EN_S)
+#define CSI_BRIG_CSI_CFG_CLK_EN_V  0x00000001U
+#define CSI_BRIG_CSI_CFG_CLK_EN_S  1
+/** CSI_BRIG_LOOPBK_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  for phy test by loopback dsi phy to csi phy.
+ */
+#define CSI_BRIG_LOOPBK_TEST_EN    (BIT(2))
+#define CSI_BRIG_LOOPBK_TEST_EN_M  (CSI_BRIG_LOOPBK_TEST_EN_V << CSI_BRIG_LOOPBK_TEST_EN_S)
+#define CSI_BRIG_LOOPBK_TEST_EN_V  0x00000001U
+#define CSI_BRIG_LOOPBK_TEST_EN_S  2
+
+/** CSI_BRIG_HOST_CM_CTRL_REG register
+ *  CSI HOST color mode convert configuration.
+ */
+#define CSI_BRIG_HOST_CM_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x48)
+/** CSI_BRIG_CSI_HOST_CM_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to enable cm output
+ */
+#define CSI_BRIG_CSI_HOST_CM_EN    (BIT(0))
+#define CSI_BRIG_CSI_HOST_CM_EN_M  (CSI_BRIG_CSI_HOST_CM_EN_V << CSI_BRIG_CSI_HOST_CM_EN_S)
+#define CSI_BRIG_CSI_HOST_CM_EN_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_EN_S  0
+/** CSI_BRIG_CSI_HOST_CM_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_BYPASS    (BIT(1))
+#define CSI_BRIG_CSI_HOST_CM_BYPASS_M  (CSI_BRIG_CSI_HOST_CM_BYPASS_V << CSI_BRIG_CSI_HOST_CM_BYPASS_S)
+#define CSI_BRIG_CSI_HOST_CM_BYPASS_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_BYPASS_S  1
+/** CSI_BRIG_CSI_HOST_CM_RX : R/W; bitpos: [3:2]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_RX    0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_M  (CSI_BRIG_CSI_HOST_CM_RX_V << CSI_BRIG_CSI_HOST_CM_RX_S)
+#define CSI_BRIG_CSI_HOST_CM_RX_V  0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_S  2
+/** CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT : R/W; bitpos: [6:4]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT    0x00000007U
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_M  (CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_V << CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_S)
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_V  0x00000007U
+#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_S  4
+/** CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT : R/W; bitpos: [8:7]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT    0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_M  (CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_V << CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_S)
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_V  0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_S  7
+/** CSI_BRIG_CSI_HOST_CM_TX : R/W; bitpos: [10:9]; default: 0;
+ *  Configures whether to bypass cm
+ */
+#define CSI_BRIG_CSI_HOST_CM_TX    0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_TX_M  (CSI_BRIG_CSI_HOST_CM_TX_V << CSI_BRIG_CSI_HOST_CM_TX_S)
+#define CSI_BRIG_CSI_HOST_CM_TX_V  0x00000003U
+#define CSI_BRIG_CSI_HOST_CM_TX_S  9
+/** CSI_BRIG_CSI_HOST_CM_LANE_NUM : R/W; bitpos: [11]; default: 1;
+ *  Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1:
+ *  2-lane
+ */
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM    (BIT(11))
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_M  (CSI_BRIG_CSI_HOST_CM_LANE_NUM_V << CSI_BRIG_CSI_HOST_CM_LANE_NUM_S)
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_S  11
+/** CSI_BRIG_CSI_HOST_CM_16BIT_SWAP : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to swap idi32 high and low 16-bit
+ */
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP    (BIT(12))
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_M  (CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_V << CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_S)
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_S  12
+/** CSI_BRIG_CSI_HOST_CM_8BIT_SWAP : R/W; bitpos: [13]; default: 0;
+ *  Configures whether to swap idi32 high and low 8-bit
+ */
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP    (BIT(13))
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_M  (CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_V << CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_S)
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_V  0x00000001U
+#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_S  13
+
+/** CSI_BRIG_HOST_SIZE_CTRL_REG register
+ *  CSI HOST color mode convert configuration.
+ */
+#define CSI_BRIG_HOST_SIZE_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x4c)
+/** CSI_BRIG_CSI_HOST_CM_VNUM : R/W; bitpos: [11:0]; default: 0;
+ *  Configures idi32 image size in y-direction, row_num - 1, valid only when
+ *  yuv422_to_yuv420_en = 1
+ */
+#define CSI_BRIG_CSI_HOST_CM_VNUM    0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_VNUM_M  (CSI_BRIG_CSI_HOST_CM_VNUM_V << CSI_BRIG_CSI_HOST_CM_VNUM_S)
+#define CSI_BRIG_CSI_HOST_CM_VNUM_V  0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_VNUM_S  0
+/** CSI_BRIG_CSI_HOST_CM_HNUM : R/W; bitpos: [23:12]; default: 0;
+ *  Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid
+ *  only when yuv422_to_yuv420_en = 1
+ */
+#define CSI_BRIG_CSI_HOST_CM_HNUM    0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_HNUM_M  (CSI_BRIG_CSI_HOST_CM_HNUM_V << CSI_BRIG_CSI_HOST_CM_HNUM_S)
+#define CSI_BRIG_CSI_HOST_CM_HNUM_V  0x00000FFFU
+#define CSI_BRIG_CSI_HOST_CM_HNUM_S  12
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_struct.h

@@ -0,0 +1,372 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: csi bridge regbank clock gating control register. */
+/** Type of clk_en register
+ *  csi bridge register mapping unit clock gating.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  0: enable clock gating. 1: disable clock gating, clock always on.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_brg_clk_en_reg_t;
+
+
+/** Group: csi bridge control registers. */
+/** Type of csi_en register
+ *  csi bridge enable.
+ */
+typedef union {
+    struct {
+        /** csi_brg_en : R/W; bitpos: [0]; default: 0;
+         *  0: disable csi bridge. 1: enable csi bridge.
+         */
+        uint32_t csi_brg_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} csi_brg_csi_en_reg_t;
+
+/** Type of buf_flow_ctl register
+ *  csi bridge buffer control.
+ */
+typedef union {
+    struct {
+        /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040;
+         *  buffer almost full threshold.
+         */
+        uint32_t csi_buf_afull_thrd:14;
+        uint32_t reserved_14:2;
+        /** csi_buf_depth : RO; bitpos: [29:16]; default: 0;
+         *  buffer data count.
+         */
+        uint32_t csi_buf_depth:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} csi_brg_buf_flow_ctl_reg_t;
+
+
+/** Group: csi bridge dma control registers. */
+/** Type of dma_req_cfg register
+ *  dma request configuration.
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  DMA burst length.
+         */
+        uint32_t dma_burst_len:12;
+        /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
+         *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
+         *  updated by frame.
+         */
+        uint32_t dma_cfg_upd_by_blk:1;
+        uint32_t reserved_13:3;
+        /** dma_force_rd_status : R/W; bitpos: [16]; default: 0;
+         *  1: mask dma request when reading frame info. 0: disable mask.
+         */
+        uint32_t dma_force_rd_status:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} csi_brg_dma_req_cfg_reg_t;
+
+/** Type of dma_req_interval register
+ *  DMA interval configuration.
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} csi_brg_dma_req_interval_reg_t;
+
+/** Type of dmablk_size register
+ *  DMA block size configuration.
+ */
+typedef union {
+    struct {
+        /** dmablk_size : R/W; bitpos: [12:0]; default: 8191;
+         *  the number of reg_dma_burst_len in a block
+         */
+        uint32_t dmablk_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} csi_brg_dmablk_size_reg_t;
+
+
+/** Group: csi bridge frame format configuration registers. */
+/** Type of data_type_cfg register
+ *  pixel data type configuration.
+ */
+typedef union {
+    struct {
+        /** data_type_min : R/W; bitpos: [5:0]; default: 24;
+         *  the min value of data type used for pixel filter.
+         */
+        uint32_t data_type_min:6;
+        uint32_t reserved_6:2;
+        /** data_type_max : R/W; bitpos: [13:8]; default: 47;
+         *  the max value of data type used for pixel filter.
+         */
+        uint32_t data_type_max:6;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_data_type_cfg_reg_t;
+
+/** Type of frame_cfg register
+ *  frame configuration.
+ */
+typedef union {
+    struct {
+        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
+         *  vadr of frame data.
+         */
+        uint32_t vadr_num:12;
+        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
+         *  hadr of frame data.
+         */
+        uint32_t hadr_num:12;
+        /** has_hsync_e : R/W; bitpos: [24]; default: 1;
+         *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
+         */
+        uint32_t has_hsync_e:1;
+        /** vadr_num_check : R/W; bitpos: [25]; default: 0;
+         *  0: disable vadr check. 1: enable vadr check.
+         */
+        uint32_t vadr_num_check:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} csi_brg_frame_cfg_reg_t;
+
+/** Type of endian_mode register
+ *  data endianness order configuration.
+ */
+typedef union {
+    struct {
+        /** byte_endian_order : R/W; bitpos: [0]; default: 0;
+         *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
+         *  when isp is bapassed.
+         */
+        uint32_t byte_endian_order:1;    //byte_swap_en
+        /** bit_endian_order : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t bit_endian_order:1;     //reserved
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} csi_brg_endian_mode_reg_t;
+
+
+/** Group: csi bridge interrupt registers. */
+/** Type of int_raw register
+ *  csi bridge interrupt raw.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt raw.
+         */
+        uint32_t vadr_num_gt_int_raw:1;
+        /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt raw.
+         */
+        uint32_t vadr_num_lt_int_raw:1;
+        /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt raw.
+         */
+        uint32_t discard_int_raw:1;
+        /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt raw.
+         */
+        uint32_t csi_buf_overrun_int_raw:1;
+        /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt raw.
+         */
+        uint32_t csi_async_fifo_ovf_int_raw:1;
+        /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt raw.
+         */
+        uint32_t dma_cfg_has_updated_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  csi bridge interrupt clr.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt clr.
+         */
+        uint32_t vadr_num_gt_real_int_clr:1;
+        /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt clr.
+         */
+        uint32_t vadr_num_lt_real_int_clr:1;
+        /** discard_int_clr : WT; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt clr.
+         */
+        uint32_t discard_int_clr:1;
+        /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt clr.
+         */
+        uint32_t csi_buf_overrun_int_clr:1;
+        /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt clr.
+         */
+        uint32_t csi_async_fifo_ovf_int_clr:1;
+        /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt clr.
+         */
+        uint32_t dma_cfg_has_updated_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_clr_reg_t;
+
+/** Type of int_st register
+ *  csi bridge interrupt st.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt st.
+         */
+        uint32_t vadr_num_gt_int_st:1;
+        /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt st.
+         */
+        uint32_t vadr_num_lt_int_st:1;
+        /** discard_int_st : RO; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt st.
+         */
+        uint32_t discard_int_st:1;
+        /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt st.
+         */
+        uint32_t csi_buf_overrun_int_st:1;
+        /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt st.
+         */
+        uint32_t csi_async_fifo_ovf_int_st:1;
+        /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt st.
+         */
+        uint32_t dma_cfg_has_updated_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_st_reg_t;
+
+/** Type of int_ena register
+ *  csi bridge interrupt enable.
+ */
+typedef union {
+    struct {
+        /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0;
+         *  reg_vadr_num is greater than real interrupt enable.
+         */
+        uint32_t vadr_num_gt_int_ena:1;
+        /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0;
+         *  reg_vadr_num is less than real interrupt enable.
+         */
+        uint32_t vadr_num_lt_int_ena:1;
+        /** discard_int_ena : R/W; bitpos: [2]; default: 0;
+         *  an incomplete frame of data was sent interrupt enable.
+         */
+        uint32_t discard_int_ena:1;
+        /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  buffer overrun interrupt enable.
+         */
+        uint32_t csi_buf_overrun_int_ena:1;
+        /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  buffer overflow interrupt enable.
+         */
+        uint32_t csi_async_fifo_ovf_int_ena:1;
+        /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0;
+         *  dma configuration update complete interrupt enable.
+         */
+        uint32_t dma_cfg_has_updated_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} csi_brg_int_ena_reg_t;
+
+
+/** Group: csi-host control registers from csi bridge regbank. */
+/** Type of host_ctrl register
+ *  csi host control by csi bridge.
+ */
+typedef union {
+    struct {
+        /** csi_enableclk : R/W; bitpos: [0]; default: 1;
+         *  enable clock lane module of csi phy.
+         */
+        uint32_t csi_enableclk:1;
+        /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
+         *  enable cfg_clk of csi host module.
+         */
+        uint32_t csi_cfg_clk_en:1;
+        /** loopbk_test_en : R/W; bitpos: [2]; default: 0;
+         *  for phy test by loopback dsi phy to csi phy.
+         */
+        uint32_t loopbk_test_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} csi_brg_host_ctrl_reg_t;
+
+
+typedef struct csi_brg_dev_t {
+    volatile csi_brg_clk_en_reg_t clk_en;
+    volatile csi_brg_csi_en_reg_t csi_en;
+    volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl;
+    volatile csi_brg_data_type_cfg_reg_t data_type_cfg;
+    volatile csi_brg_frame_cfg_reg_t frame_cfg;
+    volatile csi_brg_endian_mode_reg_t endian_mode;
+    volatile csi_brg_int_raw_reg_t int_raw;
+    volatile csi_brg_int_clr_reg_t int_clr;
+    volatile csi_brg_int_st_reg_t int_st;
+    volatile csi_brg_int_ena_reg_t int_ena;
+    volatile csi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile csi_brg_dmablk_size_reg_t dmablk_size;
+    uint32_t reserved_034[3];
+    volatile csi_brg_host_ctrl_reg_t host_ctrl;
+} csi_brg_dev_t;
+
+extern csi_brg_dev_t MIPI_CSI_BRIDGE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(csi_brg_dev_t) == 0x44, "Invalid size of csi_brg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif