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feat: add i2s & etm sleep retention entry on H4

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This commit is contained in:
laokaiyao
2025-07-16 12:08:09 +08:00
parent 424991faaf
commit 263a056486
31 changed files with 317 additions and 233 deletions
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1
components/esp_driver_i2s/CMakeLists.txt
View File

@@ -37,4 +37,5 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${include}
PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
LDFRAGMENTS linker.lf
)

10
components/esp_driver_i2s/i2s_common.c
View File

@@ -575,7 +575,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
}
#if SOC_GDMA_SUPPORTED
static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
static bool i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
{
i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
BaseType_t need_yield1 = 0;
@@ -606,7 +606,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
return need_yield1 | need_yield2 | user_need_yield;
}
static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
static bool i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
{
i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
BaseType_t need_yield1 = 0;
@@ -653,7 +653,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
#else
static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
static void i2s_dma_rx_callback(void *arg)
{
BaseType_t need_yield1 = 0;
BaseType_t need_yield2 = 0;
@@ -691,7 +691,7 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
}
}
static void IRAM_ATTR i2s_dma_tx_callback(void *arg)
static void i2s_dma_tx_callback(void *arg)
{
BaseType_t need_yield1 = 0;
BaseType_t need_yield2 = 0;
@@ -1485,7 +1485,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle)
}
#endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT
#if SOC_I2S_SUPPORTS_ETM_SYNC
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle)
{
return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev);

6
components/esp_driver_i2s/i2s_etm.c
View File

@@ -84,9 +84,9 @@ esp_err_t i2s_new_etm_task(i2s_chan_handle_t handle, const i2s_etm_task_config_t
{
ESP_RETURN_ON_FALSE(handle && config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(config->task_type < I2S_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type");
#if SOC_I2S_SUPPORTS_ETM_SYNC
ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_CHECK || handle->dir == I2S_DIR_TX,
ESP_ERR_NOT_SUPPORTED, TAG, "rx is not supported");
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_FIFO || handle->dir == I2S_DIR_TX,
ESP_ERR_NOT_SUPPORTED, TAG, "rx does not support sync check");
#endif
i2s_etm_task_t *task = heap_caps_calloc(1, sizeof(i2s_etm_task_t), ETM_MEM_ALLOC_CAPS);

7
components/esp_driver_i2s/include/esp_private/i2s_sync.h
View File

@@ -21,6 +21,7 @@
#include <stdint.h>
#include "driver/i2s_types.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
@@ -31,7 +32,7 @@ extern "C" {
/**
* @brief Get the counter number of BCLK ticks
* @note The BCLK tick count reflects the real data that have sent on line
* @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered
* @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered
*
* @param[in] tx_handle The I2S tx channel handle
* @return
@@ -44,7 +45,7 @@ uint32_t i2s_sync_get_bclk_count(i2s_chan_handle_t tx_handle);
* @note The FIFO count reflects how many slots have processed
* Normally, fifo_cnt = slot_bit_width * bclk_cnt
* If fifo_cnt < slot_bit_width * bclk_cnt, that means some data are still stuck in the I2S controller
* @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered
* @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered
*
* @param[in] tx_handle The I2S tx channel handle
* @return
@@ -68,7 +69,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle);
#endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT
#if SOC_I2S_SUPPORTS_ETM_SYNC
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
/**
* @brief I2S hardware FIFO synchronization supplement mode
* @note When the FIFO sync difference count is out of threshold, the hardware will supplement data automatically

5
components/esp_driver_i2s/linker.lf
View File

@@ -1,13 +1,16 @@
[mapping:i2s_driver]
archive: libesp_driver_i2s.a
entries:
if I2S_ISR_IRAM_SAFE = y:
i2s_common: i2s_dma_rx_callback (noflash)
i2s_common: i2s_dma_tx_callback (noflash)
if I2S_CTRL_FUNC_IN_IRAM = y:
if SOC_I2S_SUPPORTS_TX_SYNC_CNT = y:
i2s_common: i2s_sync_get_bclk_count (noflash)
i2s_common: i2s_sync_get_fifo_count (noflash)
i2s_common: i2s_sync_reset_bclk_count (noflash)
i2s_common: i2s_sync_reset_fifo_count (noflash)
if SOC_I2S_SUPPORTS_ETM_SYNC = y:
if SOC_I2S_SUPPORTS_TX_FIFO_SYNC = y:
i2s_common: i2s_sync_get_fifo_sync_diff_count (noflash)
i2s_common: i2s_sync_reset_fifo_sync_diff_count (noflash)
i2s_common: i2s_sync_enable_hw_fifo_sync (noflash)

1
components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe
View File

@@ -1,5 +1,6 @@
CONFIG_COMPILER_DUMP_RTL_FILES=y
CONFIG_I2S_ISR_IRAM_SAFE=y
CONFIG_I2S_CTRL_FUNC_IN_IRAM=y
CONFIG_COMPILER_OPTIMIZATION_NONE=y
# silent the error check, as the error string are stored in rodata, causing RTL check failure
CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y

6
components/hal/esp32h4/include/hal/i2s_ll.h
View File

@@ -60,12 +60,12 @@ extern "C" {
[I2S_DIR_RX - 1] = { \
[I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \
[I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \
[I2S_ETM_TASK_SYNC_CHECK] = -1, \
[I2S_ETM_TASK_SYNC_FIFO] = -1, \
}, \
[I2S_DIR_TX - 1] = { \
[I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \
[I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_TX, \
[I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \
[I2S_ETM_TASK_SYNC_FIFO] = I2S0_TASK_SYNC_CHECK, \
}}}[i2s_port][(chan_dir) - 1][task]
#define I2S_LL_ETM_MAX_THRESH_NUM (0x3FFFUL)
@@ -1344,7 +1344,7 @@ static inline void i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(i2s_dev_t *hw, u
* @brief Set the TX ETM synchronization ideal count
*
* @param hw Peripheral I2S hardware instance address.
* @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_CHECK triggered.
* @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_FIFO triggered.
*/
__attribute__((always_inline))
static inline void i2s_ll_tx_set_etm_sync_ideal_cnt(i2s_dev_t *hw, uint32_t ideal_cnt)

4
components/hal/include/hal/i2s_types.h
View File

@@ -233,8 +233,8 @@ typedef enum {
typedef enum {
I2S_ETM_TASK_START, /*!< Start the I2S channel */
I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */
#if SOC_I2S_SUPPORTS_ETM_SYNC
I2S_ETM_TASK_SYNC_CHECK, /*!< Check the I2S TX channel sync status */
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
I2S_ETM_TASK_SYNC_FIFO, /*!< Check the I2S TX channel sync status */
#endif
I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */
} i2s_etm_task_type_t;

17
components/soc/esp32/register/soc/i2s_reg.h
View File

@@ -1,15 +1,17 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
#ifdef __cplusplus
extern "C" {
#endif
#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008)
/* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */
@@ -1511,7 +1513,6 @@
#define I2S_I2SDATE_V 0xFFFFFFFF
#define I2S_I2SDATE_S 0
#endif /*_SOC_I2S_REG_H_ */
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c3/include/soc/soc.h
View File

@@ -20,7 +20,6 @@
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI

14
components/soc/esp32c3/register/soc/i2s_reg.h
View File

@@ -1,16 +1,18 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/soc.h"
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
@@ -1037,7 +1039,3 @@ T12_5[2:0]).*/
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */

1
components/soc/esp32c5/include/soc/soc.h
View File

@@ -18,7 +18,6 @@
#define REG_UHCI_BASE(i) (DR_REG_UHCI_BASE) // only one UHCI on C5
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5

2
components/soc/esp32c5/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32c6/include/soc/soc.h
View File

@@ -20,7 +20,6 @@
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6

2
components/soc/esp32c6/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32c61/include/soc/soc.h
View File

@@ -19,7 +19,6 @@
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61

2
components/soc/esp32c61/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32h2/include/soc/soc.h
View File

@@ -20,7 +20,6 @@
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI

2
components/soc/esp32h2/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

36
components/soc/esp32h4/etm_periph.c
View File

@@ -7,4 +7,38 @@
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
// TODO: [ESP32H4] IDF-12356 Support sleep retention
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};

43
components/soc/esp32h4/i2s_periph.c
View File

@@ -32,3 +32,46 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.irq = ETS_I2S_INTR_SOURCE,
}
};
/**
* I2S Registers to be saved during sleep retention
* - I2S_INT_ENA_REG
* - I2S_RX_CONF_REG
* - I2S_TX_CONF_REG
* - I2S_RX_CONF1_REG
* - I2S_TX_CONF1_REG
* - I2S_TX_PCM2PDM_CONF_REG
* - I2S_TX_PCM2PDM_CONF1_REG
* - I2S_RX_TDM_CTRL_REG
* - I2S_TX_TDM_CTRL_REG
* - I2S_RXEOF_NUM_REG
* - I2S_ETM_CONF_REG
* - I2S_IDEAL_CNT_REG
* - I2S_SYNC_SW_THRES_REG
* - I2S_SYNC_HW_THRES_REG
* - I2S_HW_SYNC_CONF_REG
* - I2S_HW_SYNC_DATA_REG
*/
#define I2S_RETENTION_REGS_CNT 16
#define I2S_RETENTION_REGS_BASE(i) (I2S_INT_ENA_REG(i))
static const uint32_t i2s_regs_map[4] = {0xf191b079, 0x0, 0x0, 0x0};
#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) { \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
REGDMA_I2S_LINK(0x00), \
I2S_RETENTION_REGS_BASE(i2s_port), \
I2S_RETENTION_REGS_BASE(i2s_port), \
I2S_RETENTION_REGS_CNT, 0, 0, \
i2s_regs_map[0], i2s_regs_map[1], \
i2s_regs_map[2], i2s_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2) }, \
};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
.array_size = ARRAY_SIZE(i2s0_regs_retention)
},
};

20
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -227,6 +227,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
int
default 50
config SOC_ETM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_GPIO_PORT
int
default 1
@@ -335,10 +339,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_ETM_SYNC
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
@@ -375,6 +375,10 @@ config SOC_I2S_SUPPORTS_TX_SYNC_CNT
bool
default y
config SOC_I2S_SUPPORTS_TX_FIFO_SYNC
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
@@ -391,6 +395,10 @@ config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
@@ -503,10 +511,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_SYSTIMER_SUPPORT_ETM
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y

7
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -198,7 +198,7 @@
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12356 Support sleep retention
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-H4 has 1 GPIO peripheral
@@ -272,7 +272,6 @@
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_ETM_SYNC (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F96M (1)
#define SOC_I2S_SUPPORTS_PLL_F64M (1)
@@ -282,13 +281,13 @@
#define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter
#define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data
#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
#define SOC_I2S_SUPPORTS_TX_FIFO_SYNC (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
// TODO: [ESP32H4] IDF-12386
// #define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)

60
components/soc/esp32h4/register/soc/i2s_reg.h
View File

@@ -11,10 +11,12 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S0_BASE) // only one I2S on H4
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/
#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the i2s_rx_done_int interrupt
*/
@@ -54,7 +56,7 @@ extern "C" {
/** I2S_INT_ST_REG register
* I2S interrupt status register.
*/
#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the i2s_rx_done_int interrupt
*/
@@ -94,7 +96,7 @@ extern "C" {
/** I2S_INT_ENA_REG register
* I2S interrupt enable register.
*/
#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the i2s_rx_done_int interrupt
*/
@@ -134,7 +136,7 @@ extern "C" {
/** I2S_INT_CLR_REG register
* I2S interrupt clear register.
*/
#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the i2s_rx_done_int interrupt
*/
@@ -174,7 +176,7 @@ extern "C" {
/** I2S_RX_CONF_REG register
* I2S RX configure register
*/
#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset receiver
*/
@@ -326,7 +328,7 @@ extern "C" {
/** I2S_TX_CONF_REG register
* I2S TX configure register
*/
#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset transmitter
*/
@@ -502,7 +504,7 @@ extern "C" {
/** I2S_RX_CONF1_REG register
* I2S RX configure register 1
*/
#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
* The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
* T_bck
@@ -539,7 +541,7 @@ extern "C" {
/** I2S_TX_CONF1_REG register
* I2S TX configure register 1
*/
#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
* The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
* T_bck
@@ -576,7 +578,7 @@ extern "C" {
/** I2S_TX_PCM2PDM_CONF_REG register
* I2S TX PCM2PDM configuration register
*/
#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x44)
#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x44)
/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
@@ -658,7 +660,7 @@ extern "C" {
/** I2S_TX_PCM2PDM_CONF1_REG register
* I2S TX PCM2PDM configuration register
*/
#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x48)
#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x48)
/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
@@ -693,7 +695,7 @@ extern "C" {
/** I2S_RX_TDM_CTRL_REG register
* I2S TX TDM mode control register
*/
#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
* 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
* input 0 in this channel.
@@ -833,7 +835,7 @@ extern "C" {
/** I2S_TX_TDM_CTRL_REG register
* I2S TX TDM mode control register
*/
#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
* 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
* 0 in this channel.
@@ -982,7 +984,7 @@ extern "C" {
/** I2S_RX_TIMING_REG register
* I2S RX timing control register
*/
#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
* The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
@@ -1051,7 +1053,7 @@ extern "C" {
/** I2S_TX_TIMING_REG register
* I2S TX timing control register
*/
#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
* The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
@@ -1104,7 +1106,7 @@ extern "C" {
/** I2S_LC_HUNG_CONF_REG register
* I2S HUNG configure register.
*/
#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
* the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
* when fifo hung counter is equal to this value
@@ -1132,7 +1134,7 @@ extern "C" {
/** I2S_RXEOF_NUM_REG register
* I2S RX data number control register.
*/
#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
/** I2S_RX_EOF_NUM : R/W; bitpos: [15:0]; default: 64;
* The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0])
* . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
@@ -1145,7 +1147,7 @@ extern "C" {
/** I2S_CONF_SIGLE_DATA_REG register
* I2S signal data register
*/
#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
* The configured constant channel data to be sent out.
*/
@@ -1157,7 +1159,7 @@ extern "C" {
/** I2S_STATE_REG register
* I2S TX status register
*/
#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
* 1: i2s_tx is idle state. 0: i2s_tx is working.
*/
@@ -1169,7 +1171,7 @@ extern "C" {
/** I2S_ETM_CONF_REG register
* I2S ETM configure register
*/
#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [13:0]; default: 64;
* I2S ETM send x words event. When sending word number of
* reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event.
@@ -1190,7 +1192,7 @@ extern "C" {
/** I2S_IDEAL_CNT_REG register
* I2S sync counter register
*/
#define I2S_IDEAL_CNT_REG (DR_REG_I2S_BASE + 0x74)
#define I2S_IDEAL_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
/** I2S_TX_IDEAL_CNT : R/W; bitpos: [30:0]; default: 0;
* tx fifo counter ideal value.
*/
@@ -1202,7 +1204,7 @@ extern "C" {
/** I2S_FIFO_CNT_REG register
* I2S sync counter register
*/
#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x78)
#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
* tx fifo counter value.
*/
@@ -1221,7 +1223,7 @@ extern "C" {
/** I2S_BCK_CNT_REG register
* I2S sync counter register
*/
#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x7c)
#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x7c)
/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
* tx bck counter value.
*/
@@ -1240,7 +1242,7 @@ extern "C" {
/** I2S_CNT_DIFF_REG register
* I2S sync counter register
*/
#define I2S_CNT_DIFF_REG (DR_REG_I2S_BASE + 0x80)
#define I2S_CNT_DIFF_REG(i) (REG_I2S_BASE(i) + 0x80)
/** I2S_TX_CNT_DIFF : RO; bitpos: [30:0]; default: 0;
* tx bck counter value.
*/
@@ -1259,7 +1261,7 @@ extern "C" {
/** I2S_SYNC_SW_THRES_REG register
* I2S sync counter register
*/
#define I2S_SYNC_SW_THRES_REG (DR_REG_I2S_BASE + 0x84)
#define I2S_SYNC_SW_THRES_REG(i) (REG_I2S_BASE(i) + 0x84)
/** I2S_TX_CNT_DIFF_SW_THRES : R/W; bitpos: [30:0]; default: 0;
* tx fifo counter difference software threshold value, when difference larger than
* this threshold, interrupt will occur and hardware sync will not be executed.
@@ -1272,7 +1274,7 @@ extern "C" {
/** I2S_SYNC_HW_THRES_REG register
* I2S sync counter register
*/
#define I2S_SYNC_HW_THRES_REG (DR_REG_I2S_BASE + 0x88)
#define I2S_SYNC_HW_THRES_REG(i) (REG_I2S_BASE(i) + 0x88)
/** I2S_TX_CNT_DIFF_HW_THRES : R/W; bitpos: [30:0]; default: 0;
* tx fifo counter difference hardware threshold value, which means that only when
* difference larger than this threshold will hardware start hardware sync.
@@ -1285,7 +1287,7 @@ extern "C" {
/** I2S_HW_SYNC_CONF_REG register
* I2S TX hardware sync function configuration register
*/
#define I2S_HW_SYNC_CONF_REG (DR_REG_I2S_BASE + 0x8c)
#define I2S_HW_SYNC_CONF_REG(i) (REG_I2S_BASE(i) + 0x8c)
/** I2S_TX_HW_SYNC_EN : R/W; bitpos: [0]; default: 0;
* Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable
*/
@@ -1305,7 +1307,7 @@ extern "C" {
/** I2S_HW_SYNC_DATA_REG register
* I2S TX hardware sync function configuration register
*/
#define I2S_HW_SYNC_DATA_REG (DR_REG_I2S_BASE + 0x90)
#define I2S_HW_SYNC_DATA_REG(i) (REG_I2S_BASE(i) + 0x90)
/** I2S_TX_HW_SYNC_SUPPL_DATA : R/W; bitpos: [31:0]; default: 0;
* Configure the i2s tx hardware sync supplementation data when
* I2S_TX_HW_SYNC_SUPPL_MODE is 1.
@@ -1318,7 +1320,7 @@ extern "C" {
/** I2S_CLK_GATE_REG register
* Clock gate register
*/
#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0xf8)
#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0xf8)
/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
* set this bit to enable clock gate
*/
@@ -1330,7 +1332,7 @@ extern "C" {
/** I2S_DATE_REG register
* Version control register
*/
#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc)
#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0xfc)
/** I2S_DATE : R/W; bitpos: [27:0]; default: 37818432;
* I2S version control register
*/

268
components/soc/esp32h4/register/soc/soc_etm_reg.h
View File

File diff suppressed because it is too large Load Diff

1
components/soc/esp32p4/include/soc/soc.h
View File

@@ -19,7 +19,6 @@
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
#define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3

2
components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32s2/include/soc/soc.h
View File

@@ -22,7 +22,6 @@
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3

14
components/soc/esp32s2/register/soc/i2s_reg.h
View File

@@ -1,16 +1,18 @@
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/soc.h"
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008)
/* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
@@ -1378,7 +1380,3 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */

1
components/soc/esp32s3/include/soc/soc.h
View File

@@ -30,7 +30,6 @@
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3

13
components/soc/esp32s3/register/soc/i2s_reg.h
View File

@@ -1,17 +1,18 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xC)
/* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/
@@ -1092,7 +1093,3 @@ when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */