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feat(gpio): add gpio support on ESP32C5 MP version

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This commit is contained in:
gaoxu
2024-05-16 14:54:27 +08:00
parent ea010f84ef
commit 2cad39aee5
19 changed files with 287 additions and 4351 deletions
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4
components/esp_driver_gpio/test_apps/.build-test-rules.yml
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@ -1,10 +1,6 @@
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
components/esp_driver_gpio/test_apps:
disable:
- if: IDF_TARGET == "esp32c5"
temporary: true
reason: not support yet # TODO: [ESP32C5] IDF-8717
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true

4
components/esp_driver_gpio/test_apps/gpio/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

4
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@ -535,6 +535,8 @@ TEST_CASE("GPIO_set_output_level_get_input_level_test", "[gpio]")
TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "get level error! the level should be high!");
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
// C5 on FPGA do not support GPIO pull down
// This test routes constant-high/low signal to pins, another way is to directly connect TEST_GPIO_EXT_IN_IO to
// 3.3v or GND pin
TEST_CASE("GPIO_get_level_from_fixed_voltage_test", "[gpio]")
@ -662,6 +664,8 @@ TEST_CASE("GPIO_mode_test", "[gpio]")
TEST_ASSERT_EQUAL_INT_MESSAGE(!level, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT set error, it gives incorrect output");
}
#endif
static void prompt_to_continue(const char *str)
{
printf("%s , please press \"Enter\" to go on!\n", str);

3
components/esp_pm/Kconfig
View File

@ -2,7 +2,8 @@ menu "Power Management"
config PM_ENABLE
bool "Support for power management"
# SMP FreeRTOS currently does not support power management IDF-4997
depends on !FREERTOS_SMP || __DOXYGEN__
# Power Management is not supported on ESP32C5 MP IDF-8643
depends on (!FREERTOS_SMP || __DOXYGEN__) && !IDF_TARGET_ESP32C5
default n
help
If enabled, application is compiled with support for power management.

225
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -22,23 +22,17 @@
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
#include "soc/io_mux_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "soc/usb_serial_jtag_struct.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "soc/lp_io_struct.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/lp_gpio_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#endif
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
@ -69,15 +63,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
{
*pu = IOMUX.gpio[gpio_num].fun_wpu;
*pd = IOMUX.gpio[gpio_num].fun_wpd;
*ie = IOMUX.gpio[gpio_num].fun_ie;
*pu = IO_MUX.gpio[gpio_num].fun_wpu;
*pd = IO_MUX.gpio[gpio_num].fun_wpd;
*ie = IO_MUX.gpio[gpio_num].fun_ie;
*oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
*od = hw->pin[gpio_num].pad_driver;
*drv = IOMUX.gpio[gpio_num].fun_drv;
*fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
*drv = IO_MUX.gpio[gpio_num].fun_drv;
*fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*slp_sel = IOMUX.gpio[gpio_num].slp_sel;
*slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
}
/**
@ -88,12 +82,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpu = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
abort();
#endif
IO_MUX.gpio[gpio_num].fun_wpu = 1;
}
/**
@ -105,12 +94,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpu = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
abort();
#endif
IO_MUX.gpio[gpio_num].fun_wpu = 0;
}
/**
@ -121,12 +105,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpd = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
abort();
#endif
IO_MUX.gpio[gpio_num].fun_wpd = 1;
}
/**
@ -143,20 +122,11 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
// Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IOMUX.gpio[gpio_num].fun_wpd = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
// SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
// }
// REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
abort();
#endif
IO_MUX.gpio[gpio_num].fun_wpd = 0;
}
/**
@ -182,11 +152,7 @@ __attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
(void)core_id;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
*status = hw->pcpu_int.procpu_int;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@ -261,12 +227,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_ie = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].fun_ie = 0;
}
/**
@ -277,12 +238,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_ie = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].fun_ie = 1;
}
/**
@ -293,12 +249,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].filter_en = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].filter_en = 1;
}
/**
@ -309,15 +260,9 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].filter_en = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].filter_en = 0;
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Enable GPIO hysteresis
*
@ -330,8 +275,8 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
// We are not going to use the hardware control in IDF for C5.
// Therefore, we need to always switch to use software control first.
// i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
IOMUX.gpio[gpio_num].hys_sel = 1;
IOMUX.gpio[gpio_num].hys_en = 1;
IO_MUX.gpio[gpio_num].hys_sel = 1;
IO_MUX.gpio[gpio_num].hys_en = 1;
}
/**
@ -342,10 +287,9 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
*/
static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].hys_sel = 1;
IOMUX.gpio[gpio_num].hys_en = 0;
IO_MUX.gpio[gpio_num].hys_sel = 1;
IO_MUX.gpio[gpio_num].hys_en = 0;
}
#endif
/**
* @brief Disable output mode on GPIO.
@ -461,12 +405,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_drv = strength;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
abort();
#endif
IO_MUX.gpio[gpio_num].fun_drv = strength;
}
/**
@ -478,12 +417,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
*strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
abort();
#endif
*strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
}
/**
@ -527,7 +461,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
}
/**
* @brief Set pad input to a peripheral signal through the IOMUX.
* @brief Set pad input to a peripheral signal through the IO_MUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number of the pad.
@ -537,7 +471,7 @@ __attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
{
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
IOMUX.gpio[gpio].fun_ie = 1;
IO_MUX.gpio[gpio].fun_ie = 1;
}
/**
@ -554,11 +488,10 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
abort();
// Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO13_REG || pin_name == IO_MUX_GPIO14_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
#endif
PIN_FUNC_SELECT(pin_name, func);
}
@ -590,19 +523,18 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IOMUX.gpio[gpio_num].mcu_sel = func;
IO_MUX.gpio[gpio_num].mcu_sel = func;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
// PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
abort();
// Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IO_MUX.gpio[gpio_num].mcu_sel = func;
#endif
}
/**
* @brief Set peripheral output to an GPIO pad through the IOMUX.
* @brief Set peripheral output to an GPIO pad through the IO_MUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num gpio_num GPIO number of the pad.
@ -625,7 +557,6 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
{
switch (src) {
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
break;
@ -635,14 +566,6 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
break;
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
break;
#endif
default:
// Unsupported IO_MUX clock source
HAL_ASSERT(false);
@ -694,12 +617,7 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].slp_sel = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].slp_sel = 1;
}
/**
@ -711,12 +629,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].slp_sel = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].slp_sel = 0;
}
/**
@ -727,12 +640,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpu = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_wpu = 0;
}
/**
@ -743,12 +651,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpu = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_wpu = 1;
}
/**
@ -759,12 +662,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpd = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_wpd = 1;
}
/**
@ -775,12 +673,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpd = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_wpd = 0;
}
/**
@ -791,12 +684,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_ie = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_ie = 0;
}
/**
@ -807,12 +695,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_ie = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_ie = 1;
}
/**
@ -823,12 +706,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_oe = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_oe = 0;
}
/**
@ -839,12 +717,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_oe = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
IO_MUX.gpio[gpio_num].mcu_oe = 1;
}
#ifdef __cplusplus

60
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -64,15 +64,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
{
uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32);
uint32_t bit_mask = 1 << bit_shift;
*pu = IOMUX.gpio[gpio_num].fun_wpu;
*pd = IOMUX.gpio[gpio_num].fun_wpd;
*ie = IOMUX.gpio[gpio_num].fun_ie;
*pu = IO_MUX.gpio[gpio_num].fun_wpu;
*pd = IO_MUX.gpio[gpio_num].fun_wpd;
*ie = IO_MUX.gpio[gpio_num].fun_ie;
*oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift;
*od = hw->pin[gpio_num].pad_driver;
*drv = IOMUX.gpio[gpio_num].fun_drv;
*fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
*drv = IO_MUX.gpio[gpio_num].fun_drv;
*fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*slp_sel = IOMUX.gpio[gpio_num].slp_sel;
*slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
}
/**
@ -83,7 +83,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].fun_wpu = 1;
IO_MUX.gpio[gpio_num].fun_wpu = 1;
}
/**
@ -95,7 +95,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].fun_wpu = 0;
IO_MUX.gpio[gpio_num].fun_wpu = 0;
}
/**
@ -106,7 +106,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].fun_wpd = 1;
IO_MUX.gpio[gpio_num].fun_wpd = 1;
}
/**
@ -133,7 +133,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
USB_WRAP.otg_conf.pad_pull_override = 1;
USB_WRAP.otg_conf.dp_pullup = 0;
}
IOMUX.gpio[gpio_num].fun_wpd = 0;
IO_MUX.gpio[gpio_num].fun_wpd = 0;
}
/**
@ -235,7 +235,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].fun_ie = 0;
IO_MUX.gpio[gpio_num].fun_ie = 0;
}
/**
@ -246,7 +246,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].fun_ie = 1;
IO_MUX.gpio[gpio_num].fun_ie = 1;
}
/**
@ -257,7 +257,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].filter_en = 1;
IO_MUX.gpio[gpio_num].filter_en = 1;
}
/**
@ -268,7 +268,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].filter_en = 0;
IO_MUX.gpio[gpio_num].filter_en = 0;
}
/**
@ -451,7 +451,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
IOMUX.gpio[gpio_num].fun_drv = strength;
IO_MUX.gpio[gpio_num].fun_drv = strength;
}
/**
@ -463,7 +463,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
*strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
*strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
}
/**
@ -547,7 +547,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
}
/**
* @brief Set pad input to a peripheral signal through the IOMUX.
* @brief Set pad input to a peripheral signal through the IO_MUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number of the pad.
@ -557,7 +557,7 @@ __attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
{
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
IOMUX.gpio[gpio].fun_ie = 1;
IO_MUX.gpio[gpio].fun_ie = 1;
}
/**
@ -597,11 +597,11 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
} else if (gpio_num == USB_OTG_INT_PHY_DM_GPIO_NUM || gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
USB_WRAP.otg_conf.usb_pad_enable = 0;
}
IOMUX.gpio[gpio_num].mcu_sel = func;
IO_MUX.gpio[gpio_num].mcu_sel = func;
}
/**
* @brief Set peripheral output to an GPIO pad through the IOMUX.
* @brief Set peripheral output to an GPIO pad through the IO_MUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num gpio_num GPIO number of the pad.
@ -685,7 +685,7 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].slp_sel = 1;
IO_MUX.gpio[gpio_num].slp_sel = 1;
}
/**
@ -697,7 +697,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].slp_sel = 0;
IO_MUX.gpio[gpio_num].slp_sel = 0;
}
/**
@ -708,7 +708,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_wpu = 0;
IO_MUX.gpio[gpio_num].mcu_wpu = 0;
}
/**
@ -719,7 +719,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_wpu = 1;
IO_MUX.gpio[gpio_num].mcu_wpu = 1;
}
/**
@ -730,7 +730,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_wpd = 1;
IO_MUX.gpio[gpio_num].mcu_wpd = 1;
}
/**
@ -741,7 +741,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_wpd = 0;
IO_MUX.gpio[gpio_num].mcu_wpd = 0;
}
/**
@ -752,7 +752,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_ie = 0;
IO_MUX.gpio[gpio_num].mcu_ie = 0;
}
/**
@ -763,7 +763,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_ie = 1;
IO_MUX.gpio[gpio_num].mcu_ie = 1;
}
/**
@ -774,7 +774,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_oe = 0;
IO_MUX.gpio[gpio_num].mcu_oe = 0;
}
/**
@ -785,7 +785,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].mcu_oe = 1;
IO_MUX.gpio[gpio_num].mcu_oe = 1;
}
#ifdef __cplusplus

22
components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
View File

@ -34,7 +34,7 @@ typedef union {
uint32_t reserved_15:17;
};
uint32_t val;
} iomux_pin_ctrl_reg_t;
} io_mux_pin_ctrl_reg_t;
/** Type of gpio register
* IO MUX Configure Register for pad XTAL_32K_P
@ -102,13 +102,13 @@ typedef union {
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling siganl from slftware. 0: Select enabling signal from efuse hardware.
* enabling signal from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} iomux_gpio_reg_t;
} io_mux_gpio_reg_t;
/** Type of date register
* IO MUX Version Control Register
@ -122,20 +122,20 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} iomux_date_reg_t;
} io_mux_date_reg_t;
typedef struct iomux_dev_t {
volatile iomux_pin_ctrl_reg_t pin_ctrl;
volatile iomux_gpio_reg_t gpio[27];
typedef struct io_mux_dev_t {
volatile io_mux_pin_ctrl_reg_t pin_ctrl;
volatile io_mux_gpio_reg_t gpio[27];
uint32_t reserved_070[35];
volatile iomux_date_reg_t date;
} iomux_dev_t;
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern iomux_dev_t IOMUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(iomux_dev_t) == 0x100, "Invalid size of iomux_dev_t structure");
_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus

2
components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
View File

@ -41,7 +41,7 @@ PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( SDM = 0x60091f00 );

28
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
View File

@ -111,17 +111,41 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 29
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 30
default 28
config SOC_GPIO_OUT_RANGE_MAX
int
default 30
default 28
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000001FFFF00
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool

4216
components/soc/esp32c5/mp/include/soc/io_mux_reg.h
View File

File diff suppressed because it is too large Load Diff

2
components/soc/esp32c5/mp/include/soc/io_mux_struct.h
View File

@ -134,7 +134,7 @@ typedef struct {
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IOMUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");

20
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@ -174,35 +174,35 @@
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- GPIO CAPS ---------------------------------------*/
// TODO: [ESP32C5] IDF-8717
// ESP32-C5 has 1 GPIO peripheral
// #define SOC_GPIO_PORT 1U
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 29
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem
// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: [ESP32C5] IDF-8719
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_IN_RANGE_MAX 28
#define SOC_GPIO_OUT_RANGE_MAX 28
// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
// #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
// Support to force hold all IOs
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

2
components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
View File

@ -39,7 +39,7 @@ PROVIDE ( ECC = 0x6008B000 );
PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( MEM_MONITOR = 0x60092000 );

26
components/soc/esp32p4/include/soc/io_mux_struct.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,7 +11,7 @@ extern "C" {
#endif
/** Type of GPIO register
* IOMUX gpio configuration register
* IO MUX gpio configuration register
*/
typedef union {
struct {
@ -36,7 +36,7 @@ typedef union {
*/
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [5:6]; default: 0;
* select drive strenth on sleep mode
* select drive strength on sleep mode
*/
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
@ -52,7 +52,7 @@ typedef union {
*/
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [10:11]; default: 2;
* select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
* select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
*/
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [12:14]; default: 0;
@ -66,10 +66,10 @@ typedef union {
uint32_t reserved16 :16;
};
uint32_t val;
} iomux_gpio_reg_t;
} io_mux_gpio_reg_t;
/** Type of date register
* IOMUX version register
* IO_MUX version register
*/
typedef union {
struct {
@ -80,20 +80,20 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} iomux_date_reg_t;
} io_mux_date_reg_t;
typedef struct iomux_dev_t {
typedef struct io_mux_dev_t {
uint32_t reserved_0;
volatile iomux_gpio_reg_t gpio[57];
volatile io_mux_gpio_reg_t gpio[57];
uint32_t reserved_e8[7];
volatile iomux_date_reg_t date;
} iomux_dev_t;
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern iomux_dev_t IOMUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(iomux_dev_t) == 0x108, "Invalid size of iomux_dev_t structure");
_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus

4
examples/peripherals/.build-test-rules.yml
View File

@ -39,10 +39,6 @@ examples/peripherals/dac/dac_cosine_wave:
- esp_driver_dac
examples/peripherals/gpio:
disable:
- if: IDF_TARGET == "esp32c5"
temporary: true
reason: GPIO is not supported on ESP32-C5 # TODO: [ESP32C5] IDF-8717
depends_components:
- esp_driver_gpio

4
examples/peripherals/gpio/generic_gpio/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Example: GPIO

4
examples/storage/.build-test-rules.yml
View File

@ -46,10 +46,6 @@ examples/storage/nvs_rw_blob:
depends_components:
- nvs_flash
- driver
disable:
- if: IDF_TARGET == "esp32c5"
temporary: true
reason: not supported yet # TODO: [ESP32C5] IDF-8717
disable_test:
- if: IDF_TARGET not in ["esp32", "esp32c3"]
reason: only one target per arch needed

4
examples/storage/nvs_rw_blob/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Non-Volatile Storage (NVS) Read and Write Example

4
examples/system/.build-test-rules.yml
View File

@ -79,10 +79,6 @@ examples/system/freertos:
- freertos
examples/system/gcov:
disable:
- if: IDF_TARGET == "esp32c5"
temporary: true
reason: not supported yet #TODO: IDF-8717
disable_test:
- if: IDF_TARGET != "esp32"
temporary: true