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Merge branch 'bugfix/riscv_ulp_linker_script_reset_vector_v4.3' into 'release/v4.3'

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Fix RISC-V ULP failure to start (v4.3)

See merge request espressif/esp-idf!13464
This commit is contained in:
Angus Gratton
2021-05-07 23:28:43 +00:00
parent e45be4dd4a f6d96f33bb
commit 2e64d234c4
3 changed files with 11 additions and 1 deletions
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1
components/ulp/cmake/CMakeLists.txt
View File

@@ -149,3 +149,4 @@ add_custom_target(build
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
target_link_libraries(${ULP_APP_NAME} -T${CMAKE_CURRENT_BINARY_DIR}/${ULP_LD_SCRIPT} ${EXTRA_LINKER_ARGS}) target_link_libraries(${ULP_APP_NAME} -T${CMAKE_CURRENT_BINARY_DIR}/${ULP_LD_SCRIPT} ${EXTRA_LINKER_ARGS})
set_target_properties(${ULP_APP_NAME} PROPERTIES LINK_DEPENDS ${ULP_LD_SCRIPT})

7
components/ulp/ld/esp32s2.ulp.riscv.ld
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@@ -12,10 +12,17 @@ SECTIONS
. = ORIGIN(ram); . = ORIGIN(ram);
.text : .text :
{ {
*start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
*(.text) *(.text)
*(.text*) *(.text*)
} >ram } >ram
.rodata ALIGN(4):
{
*(.rodata)
*(.rodata*)
} > ram
.data ALIGN(4): .data ALIGN(4):
{ {
*(.data) *(.data)

4
components/ulp/ulp_riscv/start.S
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@@ -1,4 +1,4 @@
.section .text .section .text.vectors
.global irq_vector .global irq_vector
.global reset_vector .global reset_vector
@@ -11,6 +11,8 @@ reset_vector:
irq_vector: irq_vector:
ret ret
.section .text
__start: __start:
/* setup the stack pointer */ /* setup the stack pointer */
la sp, __stack_top la sp, __stack_top