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test(psram): re-enable 80M psram tests on C5 ECO2

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This commit is contained in:
armando
2025-05-22 14:52:40 +08:00
parent 1d12eb4124
commit 2f8cd616cc
5 changed files with 5 additions and 3 deletions
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1
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
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@ -55,6 +55,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
// MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
}

1
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
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@ -52,6 +52,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
// MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
}

2
components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5
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@ -1,3 +1,3 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_40M=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0

2
components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5
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@ -1,3 +1,3 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_40M=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0

2
examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5
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@ -1,5 +1,5 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_40M=y
CONFIG_SPIRAM_SPEED_80M=y
# Enabling the following configurations can help increase the PCLK frequency in the case when
# the Frame Buffer is allocated from the PSRAM and fetched by EDMA
CONFIG_SPIRAM_XIP_FROM_PSRAM=y