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spi: fix cs num support for different SPI hosts.

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For esp32, all SPI hosts have 3 CS pins, however, on ESP32, SPIMEM1 has
two CS pins, FSPI has six, while HSPI has three.
This commit is contained in:
Michael (XIAO Xufeng)
2020-04-07 22:58:26 +08:00
parent 4bad988317
commit 30fa716376
7 changed files with 21 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/soc/include/hal/spi_flash_hal.h
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@@ -48,7 +48,7 @@ typedef struct {
/// Configuration structure for the SPI driver.
typedef struct {
spi_host_device_t host_id; ///< SPI peripheral ID.
int cs_num; ///< Which cs pin is used, 0-2.
int cs_num; ///< Which cs pin is used, 0-(SOC_SPI_PERIPH_CS_NUM-1).
bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
esp_flash_speed_t speed;///< SPI flash clock speed to work at.

2
components/soc/soc/esp32s2/include/soc/spi_caps.h
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@@ -16,7 +16,7 @@
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 27

6
components/soc/src/esp32/include/hal/spi_flash_ll.h
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@@ -238,9 +238,9 @@ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
*/
static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
{
dev->pin.cs0_dis = (pin == 0) ? 0 : 1;
dev->pin.cs1_dis = (pin == 1) ? 0 : 1;
dev->pin.cs2_dis = (pin == 2) ? 0 : 1;
dev->pin.cs0_dis = (pin != 0);
dev->pin.cs1_dis = (pin != 1);
dev->pin.cs2_dis = (pin != 2);
}
/**

8
components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h
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@@ -185,8 +185,12 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
*/
static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
{
dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
dev->misc.cs0_dis = (pin != 0);
dev->misc.cs1_dis = (pin != 1);
dev->misc.cs2_dis = (pin != 2);
dev->misc.cs3_dis = (pin != 3);
dev->misc.cs4_dis = (pin != 4);
dev->misc.cs5_dis = (pin != 5);
}
/**

3
components/soc/src/esp32s2/include/hal/spi_ll.h
View File

@@ -576,6 +576,9 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1;
hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1;
hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1;
hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1;
hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1;
hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1;
}
/*------------------------------------------------------------------------------

6
components/soc/src/esp32s2/include/hal/spimem_flash_ll.h
View File

@@ -227,12 +227,12 @@ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
* Select which pin to use for the flash
*
* @param dev Beginning address of the peripheral registers.
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
* @param pin Pin ID to use, 0-1. Set to other values to disable all the CS pins.
*/
static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
{
dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
dev->misc.cs0_dis = (pin != 0);
dev->misc.cs1_dis = (pin != 1);
}
/**

4
components/soc/src/hal/spi_flash_hal.c
View File

@@ -15,6 +15,7 @@
#include <stdlib.h>
#include "hal/spi_flash_hal.h"
#include "string.h"
#include "soc/spi_caps.h"
#include "hal/hal_defs.h"
#define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
@@ -68,6 +69,9 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
if (!esp_ptr_internal(data_out)) {
return ESP_ERR_INVALID_ARG;
}
if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
return ESP_ERR_INVALID_ARG;
}
spi_flash_hal_clock_config_t clock_cfg = spi_flash_clk_cfg_reg[cfg->speed];