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https://github.com/espressif/esp-idf.git
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Merge branch 'feat/mipi_dsi_p4_eco5' into 'master'
ESP32P4 ECO5 register update: DSI/TIMG/ETM/DW_GDMA Closes IDF-13735, IDF-13429, IDF-13422, and IDF-13428 See merge request espressif/esp-idf!41568
This commit is contained in:
morris
@@ -19,7 +19,6 @@
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#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
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#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
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#define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
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#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
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#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
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#define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000)
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@@ -11,6 +11,8 @@
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extern "C" {
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#endif
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#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000)
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/** TIMG_T0CONFIG_REG register
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* Timer 0 configuration register
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*/
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File diff suppressed because it is too large
Load Diff
@@ -1,868 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Registers */
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/** Type of clk_en register
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* dsi bridge clk control register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 0;
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* this bit configures force_on of dsi_bridge register clock gate
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} dsi_brg_clk_en_reg_t;
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/** Type of en register
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* dsi bridge en register
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*/
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typedef union {
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struct {
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/** dsi_en : R/W; bitpos: [0]; default: 0;
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* this bit configures module enable of dsi_bridge. 0: disable, 1: enable
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*/
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uint32_t dsi_en:1;
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/** dsi_brig_rst : R/W; bitpos: [1]; default: 0;
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* Configures software reset of dsi_bridge. 0: release reset, 1: reset
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*/
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uint32_t dsi_brig_rst:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} dsi_brg_en_reg_t;
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/** Type of dma_req_cfg register
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* dsi bridge dma burst len register
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*/
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typedef union {
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struct {
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/** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
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* this field configures the num of 64-bit in one dma burst transfer, valid only when
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* dsi_bridge as flow controller
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*/
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uint32_t dma_burst_len:12;
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uint32_t reserved_12:20;
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};
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uint32_t val;
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} dsi_brg_dma_req_cfg_reg_t;
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/** Type of raw_num_cfg register
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* dsi bridge raw number control register
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*/
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typedef union {
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struct {
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/** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
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* this field configures number of total pix bits/64
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*/
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uint32_t raw_num_total:22;
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/** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
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* this field configures whether the total pix bits is a multiple of 64bits. 0: align
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* to 64-bit, 1: unalign to 64-bit
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*/
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uint32_t unalign_64bit_en:1;
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uint32_t reserved_23:8;
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/** raw_num_total_set : WT; bitpos: [31]; default: 0;
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* this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
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* 1: enable. valid only when dsi_bridge as flow controller
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*/
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uint32_t raw_num_total_set:1;
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};
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uint32_t val;
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} dsi_brg_raw_num_cfg_reg_t;
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/** Type of raw_buf_credit_ctl register
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* dsi bridge credit register
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*/
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typedef union {
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struct {
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/** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
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* this field configures the threshold whether dsi_bridge fifo can receive one more
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* 64-bit, valid only when dsi_bridge as flow controller
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*/
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uint32_t credit_thrd:15;
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uint32_t reserved_15:1;
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/** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
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* this field configures the threshold whether dsi_bridge fifo can receive one more
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* dma burst, valid only when dsi_bridge as flow controller
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*/
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uint32_t credit_burst_thrd:15;
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/** credit_reset : R/W; bitpos: [31]; default: 0;
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* this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
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* dsi_bridge as flow controller
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*/
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uint32_t credit_reset:1;
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};
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uint32_t val;
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} dsi_brg_raw_buf_credit_ctl_reg_t;
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/** Type of pixel_type register
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* dsi bridge dpi type control register
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*/
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typedef union {
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struct {
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/** raw_type : R/W; bitpos: [3:0]; default: 0;
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* this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
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* 9:yuv422, 10:yuv420, 12:gray
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*/
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uint32_t raw_type:4;
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/** dpi_config : R/W; bitpos: [5:4]; default: 0;
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* this field configures the pixel arrange type of dpi interface
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*/
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uint32_t dpi_config:2;
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/** data_in_type : R/W; bitpos: [6]; default: 0;
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* input data type, 0: not yuv, 1: yuv
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*/
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uint32_t data_in_type:1;
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/** dpi_type : R/W; bitpos: [10:7]; default: 0;
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* this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
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*/
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uint32_t dpi_type:4;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} dsi_brg_pixel_type_reg_t;
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/** Type of dma_block_interval register
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* dsi bridge dma block interval control register
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*/
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typedef union {
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struct {
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/** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
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* this field configures the max block_slot_cnt
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*/
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uint32_t dma_block_slot:10;
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/** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
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* this field configures the max block_interval_cnt, block_interval_cnt increased by 1
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* when block_slot_cnt if full
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*/
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uint32_t dma_block_interval:18;
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/** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
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* this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
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*/
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uint32_t raw_num_total_auto_reload:1;
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/** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
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* this bit configures enable of interval between dma block transfer, 0: disable, 1:
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* enable
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*/
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uint32_t dma_block_interval_en:1;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} dsi_brg_dma_block_interval_reg_t;
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/** Type of dma_req_interval register
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* dsi bridge dma req interval control register
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*/
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typedef union {
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struct {
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/** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
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* this field configures the interval between dma req events
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*/
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uint32_t dma_req_interval:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} dsi_brg_dma_req_interval_reg_t;
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/** Type of dpi_lcd_ctl register
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* dsi bridge dpi signal control register
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*/
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typedef union {
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struct {
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/** dpishutdn : R/W; bitpos: [0]; default: 0;
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* this bit configures dpishutdn signal in dpi interface
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*/
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uint32_t dpishutdn:1;
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/** dpicolorm : R/W; bitpos: [1]; default: 0;
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* this bit configures dpicolorm signal in dpi interface
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*/
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uint32_t dpicolorm:1;
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/** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
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* this bit configures dpiupdatecfg signal in dpi interface
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*/
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uint32_t dpiupdatecfg:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} dsi_brg_dpi_lcd_ctl_reg_t;
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/** Type of dpi_rsv_dpi_data register
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* dsi bridge dpi reserved data register
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*/
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typedef union {
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struct {
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/** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
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* this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
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*/
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uint32_t dpi_rsv_data:30;
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/** dpi_dbg_en : R/W; bitpos: [30]; default: 0;
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* Configures data debug feature enable. 0: disable, 1: enable
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*/
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uint32_t dpi_dbg_en:1;
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uint32_t reserved_31:1;
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};
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uint32_t val;
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} dsi_brg_dpi_rsv_dpi_data_reg_t;
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/** Type of dpi_v_cfg0 register
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* dsi bridge dpi v config register 0
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*/
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typedef union {
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struct {
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/** vtotal : R/W; bitpos: [11:0]; default: 525;
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* this field configures the total length of one frame (by line) for dpi output, must
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* meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
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*/
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uint32_t vtotal:12;
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uint32_t reserved_12:4;
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/** vdisp : R/W; bitpos: [27:16]; default: 480;
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* this field configures the length of valid line (by line) for dpi output
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*/
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uint32_t vdisp:12;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} dsi_brg_dpi_v_cfg0_reg_t;
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/** Type of dpi_v_cfg1 register
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* dsi bridge dpi v config register 1
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*/
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typedef union {
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struct {
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/** vbank : R/W; bitpos: [11:0]; default: 33;
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* this field configures the length between vsync and valid line (by line) for dpi
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* output
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*/
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uint32_t vbank:12;
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uint32_t reserved_12:4;
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/** vsync : R/W; bitpos: [27:16]; default: 2;
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* this field configures the length of vsync (by line) for dpi output
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*/
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uint32_t vsync:12;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} dsi_brg_dpi_v_cfg1_reg_t;
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/** Type of dpi_h_cfg0 register
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* dsi bridge dpi h config register 0
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*/
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typedef union {
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struct {
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/** htotal : R/W; bitpos: [11:0]; default: 800;
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* this field configures the total length of one line (by pixel num) for dpi output,
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* must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
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*/
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uint32_t htotal:12;
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uint32_t reserved_12:4;
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/** hdisp : R/W; bitpos: [27:16]; default: 640;
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* this field configures the length of valid pixel data (by pixel num) for dpi output
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*/
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uint32_t hdisp:12;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} dsi_brg_dpi_h_cfg0_reg_t;
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/** Type of dpi_h_cfg1 register
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* dsi bridge dpi h config register 1
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*/
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typedef union {
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struct {
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/** hbank : R/W; bitpos: [11:0]; default: 48;
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* this field configures the length between hsync and pixel data valid (by pixel num)
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* for dpi output
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*/
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uint32_t hbank:12;
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uint32_t reserved_12:4;
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/** hsync : R/W; bitpos: [27:16]; default: 96;
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* this field configures the length of hsync (by pixel num) for dpi output
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*/
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uint32_t hsync:12;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} dsi_brg_dpi_h_cfg1_reg_t;
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|
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/** Type of dpi_misc_config register
|
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* dsi_bridge dpi misc config register
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*/
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typedef union {
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struct {
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/** dpi_en : R/W; bitpos: [0]; default: 0;
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* this bit configures enable of dpi output, 0: disable, 1: enable
|
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*/
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uint32_t dpi_en:1;
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uint32_t reserved_1:3;
|
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/** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
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* this field configures the underrun interrupt musk, when underrun occurs and line
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* cnt is less then this field
|
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*/
|
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uint32_t fifo_underrun_discard_vcnt:12;
|
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uint32_t reserved_16:16;
|
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};
|
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uint32_t val;
|
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} dsi_brg_dpi_misc_config_reg_t;
|
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|
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/** Type of dpi_config_update register
|
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* dsi_bridge dpi config update register
|
||||
*/
|
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typedef union {
|
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struct {
|
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/** dpi_config_update : WT; bitpos: [0]; default: 0;
|
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* write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
|
||||
*/
|
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uint32_t dpi_config_update:1;
|
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uint32_t reserved_1:31;
|
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};
|
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uint32_t val;
|
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} dsi_brg_dpi_config_update_reg_t;
|
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|
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/** Type of host_trigger_rev register
|
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* dsi_bridge host trigger reverse control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
|
||||
* tx_trigger reverse. 0: disable, 1: enable
|
||||
*/
|
||||
uint32_t tx_trigger_rev_en:1;
|
||||
/** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
|
||||
* rx_trigger reverse. 0: disable, 1: enable
|
||||
*/
|
||||
uint32_t rx_trigger_rev_en:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_host_trigger_rev_reg_t;
|
||||
|
||||
/** Type of blk_raw_num_cfg register
|
||||
* dsi_bridge block raw number control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
|
||||
* this field configures number of total block pix bits/64
|
||||
*/
|
||||
uint32_t blk_raw_num_total:22;
|
||||
uint32_t reserved_22:9;
|
||||
/** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
|
||||
* write 1 to reload reg_blk_raw_num_total to internal cnt
|
||||
*/
|
||||
uint32_t blk_raw_num_total_set:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_blk_raw_num_cfg_reg_t;
|
||||
|
||||
/** Type of dma_frame_interval register
|
||||
* dsi_bridge dam frame interval control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
|
||||
* this field configures the max frame_slot_cnt
|
||||
*/
|
||||
uint32_t dma_frame_slot:10;
|
||||
/** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
|
||||
* this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
|
||||
* when frame_slot_cnt if full
|
||||
*/
|
||||
uint32_t dma_frame_interval:18;
|
||||
/** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
|
||||
* this bit configures enable multi-blk transfer, 0: disable, 1: enable
|
||||
*/
|
||||
uint32_t dma_multiblk_en:1;
|
||||
/** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
|
||||
* this bit configures enable interval between frame transfer, 0: disable, 1: enable
|
||||
*/
|
||||
uint32_t dma_frame_interval_en:1;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_dma_frame_interval_reg_t;
|
||||
|
||||
/** Type of mem_aux_ctrl register
|
||||
* dsi_bridge mem aux control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
|
||||
* this field configures dsi_bridge fifo memory aux ctrl
|
||||
*/
|
||||
uint32_t dsi_mem_aux_ctrl:14;
|
||||
uint32_t reserved_14:18;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_mem_aux_ctrl_reg_t;
|
||||
|
||||
/** Type of rdn_eco_low register
|
||||
* dsi_bridge rdn eco all low register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
|
||||
* rdn_eco_low
|
||||
*/
|
||||
uint32_t rdn_eco_low:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_rdn_eco_low_reg_t;
|
||||
|
||||
/** Type of rdn_eco_high register
|
||||
* dsi_bridge rdn eco all high register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* rdn_eco_high
|
||||
*/
|
||||
uint32_t rdn_eco_high:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_rdn_eco_high_reg_t;
|
||||
|
||||
/** Type of host_ctrl register
|
||||
* dsi_bridge host control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
|
||||
* enable
|
||||
*/
|
||||
uint32_t dsi_cfg_ref_clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_host_ctrl_reg_t;
|
||||
|
||||
/** Type of mem_clk_ctrl register
|
||||
* dsi_bridge mem force on control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
|
||||
* this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
|
||||
* force on
|
||||
*/
|
||||
uint32_t dsi_bridge_mem_clk_force_on:1;
|
||||
/** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
|
||||
* this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
|
||||
*/
|
||||
uint32_t dsi_mem_clk_force_on:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_mem_clk_ctrl_reg_t;
|
||||
|
||||
/** Type of dma_flow_ctrl register
|
||||
* dsi_bridge dma flow controller register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
|
||||
* this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
|
||||
* as flow controller
|
||||
*/
|
||||
uint32_t dsi_dma_flow_controller:1;
|
||||
uint32_t reserved_1:3;
|
||||
/** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
|
||||
* this field configures the num of blocks when multi-blk is enable and dmac as flow
|
||||
* controller
|
||||
*/
|
||||
uint32_t dma_flow_multiblk_num:4;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_dma_flow_ctrl_reg_t;
|
||||
|
||||
/** Type of raw_buf_almost_empty_thrd register
|
||||
* dsi_bridge buffer empty threshold register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
|
||||
* this field configures the fifo almost empty threshold, is valid only when dmac as
|
||||
* flow controller
|
||||
*/
|
||||
uint32_t dsi_raw_buf_almost_empty_thrd:11;
|
||||
uint32_t reserved_11:21;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
|
||||
|
||||
/** Type of yuv_cfg register
|
||||
* dsi_bridge yuv format config register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** protocol : R/W; bitpos: [0]; default: 0;
|
||||
* this bit configures yuv protoocl, 0: bt.601, 1: bt.709
|
||||
*/
|
||||
uint32_t protocol:1;
|
||||
/** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
|
||||
* this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
|
||||
*/
|
||||
uint32_t yuv_pix_endian:1;
|
||||
/** yuv422_format : R/W; bitpos: [3:2]; default: 0;
|
||||
* this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
|
||||
*/
|
||||
uint32_t yuv422_format:2;
|
||||
/** yuv_range : R/W; bitpos: [4]; default: 0;
|
||||
* Configures yuv pixel range, 0: limit range, 1: full range
|
||||
*/
|
||||
uint32_t yuv_range:1;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_yuv_cfg_reg_t;
|
||||
|
||||
/** Type of phy_lp_loopback_ctrl register
|
||||
* dsi phy lp_loopback test ctrl
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
|
||||
* txdataesc_1 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txdataesc_1:8;
|
||||
/** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
|
||||
* txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txrequestesc_1:1;
|
||||
/** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
|
||||
* txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txvalidesc_1:1;
|
||||
/** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
|
||||
* txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txlpdtesc_1:1;
|
||||
/** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
|
||||
* basedir_1 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_basedir_1:1;
|
||||
uint32_t reserved_12:4;
|
||||
/** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
|
||||
* txdataesc_0 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txdataesc_0:8;
|
||||
/** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
|
||||
* txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txrequestesc_0:1;
|
||||
/** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
|
||||
* txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txvalidesc_0:1;
|
||||
/** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
|
||||
* txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_txlpdtesc_0:1;
|
||||
/** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
|
||||
* basedir_0 ctrl when enable dsi phy lp_loopback_test
|
||||
*/
|
||||
uint32_t phy_lp_basedir_0:1;
|
||||
/** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
|
||||
* dsi phy lp_loopback test start check
|
||||
*/
|
||||
uint32_t phy_lp_loopback_check:1;
|
||||
/** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
|
||||
* dsi phy lp_loopback test check done
|
||||
*/
|
||||
uint32_t phy_lp_loopback_check_done:1;
|
||||
/** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
|
||||
* dsi phy lp_loopback ctrl en
|
||||
*/
|
||||
uint32_t phy_lp_loopback_en:1;
|
||||
/** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
|
||||
* result of dsi phy lp_loopback test
|
||||
*/
|
||||
uint32_t phy_lp_loopback_ok:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_phy_lp_loopback_ctrl_reg_t;
|
||||
|
||||
/** Type of phy_hs_loopback_ctrl register
|
||||
* dsi phy hp_loopback test ctrl
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
|
||||
* txdatahs_1 ctrl when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_txdatahs_1:8;
|
||||
/** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
|
||||
* txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_txrequestdatahs_1:1;
|
||||
/** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
|
||||
* basedir_1 ctrl when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_basedir_1:1;
|
||||
uint32_t reserved_10:6;
|
||||
/** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
|
||||
* txdatahs_0 ctrl when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_txdatahs_0:8;
|
||||
/** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
|
||||
* txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_txrequestdatahs_0:1;
|
||||
/** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
|
||||
* basedir_0 ctrl when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_basedir_0:1;
|
||||
uint32_t reserved_26:1;
|
||||
/** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
|
||||
* txrequesthsclk when enable dsi phy hs_loopback_test
|
||||
*/
|
||||
uint32_t phy_hs_txrequesthsclk:1;
|
||||
/** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
|
||||
* dsi phy hs_loopback test start check
|
||||
*/
|
||||
uint32_t phy_hs_loopback_check:1;
|
||||
/** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
|
||||
* dsi phy hs_loopback test check done
|
||||
*/
|
||||
uint32_t phy_hs_loopback_check_done:1;
|
||||
/** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
|
||||
* dsi phy hs_loopback ctrl en
|
||||
*/
|
||||
uint32_t phy_hs_loopback_en:1;
|
||||
/** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
|
||||
* result of dsi phy hs_loopback test
|
||||
*/
|
||||
uint32_t phy_hs_loopback_ok:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_phy_hs_loopback_ctrl_reg_t;
|
||||
|
||||
/** Type of phy_loopback_cnt register
|
||||
* loopback test cnt
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
|
||||
* hs_loopback test check cnt
|
||||
*/
|
||||
uint32_t phy_hs_check_cnt_th:8;
|
||||
uint32_t reserved_8:8;
|
||||
/** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
|
||||
* lp_loopback test check cnt
|
||||
*/
|
||||
uint32_t phy_lp_check_cnt_th:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_phy_loopback_cnt_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Registers */
|
||||
/** Type of fifo_flow_status register
|
||||
* dsi bridge raw buffer depth register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
|
||||
* this field configures the depth of dsi_bridge fifo depth
|
||||
*/
|
||||
uint32_t raw_buf_depth:14;
|
||||
uint32_t reserved_14:18;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_fifo_flow_status_reg_t;
|
||||
|
||||
/** Type of host_bist_ctl register
|
||||
* dsi_bridge host bist control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bistok : RO; bitpos: [0]; default: 0;
|
||||
* bistok
|
||||
*/
|
||||
uint32_t bistok:1;
|
||||
/** biston : R/W; bitpos: [1]; default: 0;
|
||||
* biston
|
||||
*/
|
||||
uint32_t biston:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_host_bist_ctl_reg_t;
|
||||
|
||||
/** Type of rdn_eco_cs register
|
||||
* dsi_bridge rdn eco cs register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rdn_eco_en : R/W; bitpos: [0]; default: 0;
|
||||
* rdn_eco_en
|
||||
*/
|
||||
uint32_t rdn_eco_en:1;
|
||||
/** rdn_eco_result : RO; bitpos: [1]; default: 0;
|
||||
* rdn_eco_result
|
||||
*/
|
||||
uint32_t rdn_eco_result:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_rdn_eco_cs_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Registers */
|
||||
/** Type of int_ena register
|
||||
* dsi_bridge interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** underrun_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
|
||||
* by dpi_underrun interrupt signal
|
||||
*/
|
||||
uint32_t underrun_int_ena:1;
|
||||
/** vsync_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
|
||||
* dpi_vsync interrupt signal
|
||||
*/
|
||||
uint32_t vsync_int_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* dsi_bridge interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** underrun_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
|
||||
*/
|
||||
uint32_t underrun_int_clr:1;
|
||||
/** vsync_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
|
||||
*/
|
||||
uint32_t vsync_int_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_clr_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* dsi_bridge raw interrupt register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* the raw interrupt status of dpi_underrun
|
||||
*/
|
||||
uint32_t underrun_int_raw:1;
|
||||
/** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* the raw interrupt status of dpi_vsync
|
||||
*/
|
||||
uint32_t vsync_int_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* dsi_bridge masked interrupt register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** underrun_int_st : RO; bitpos: [0]; default: 0;
|
||||
* the masked interrupt status of dpi_underrun
|
||||
*/
|
||||
uint32_t underrun_int_st:1;
|
||||
/** vsync_int_st : RO; bitpos: [1]; default: 0;
|
||||
* the masked interrupt status of dpi_vsync
|
||||
*/
|
||||
uint32_t vsync_int_st:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_st_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of ver_date register
|
||||
* version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ver_data : R/W; bitpos: [31:0]; default: 539296009;
|
||||
* Represents csv version
|
||||
*/
|
||||
uint32_t ver_data:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_ver_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile dsi_brg_clk_en_reg_t clk_en;
|
||||
volatile dsi_brg_en_reg_t en;
|
||||
volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
|
||||
volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
|
||||
volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
|
||||
volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
|
||||
volatile dsi_brg_pixel_type_reg_t pixel_type;
|
||||
volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
|
||||
volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
|
||||
volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
|
||||
volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
|
||||
uint32_t reserved_02c;
|
||||
volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
|
||||
volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
|
||||
volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
|
||||
volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
|
||||
volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
|
||||
volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
|
||||
uint32_t reserved_048[2];
|
||||
volatile dsi_brg_int_ena_reg_t int_ena;
|
||||
volatile dsi_brg_int_clr_reg_t int_clr;
|
||||
volatile dsi_brg_int_raw_reg_t int_raw;
|
||||
volatile dsi_brg_int_st_reg_t int_st;
|
||||
volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
|
||||
volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
|
||||
volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
|
||||
volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
|
||||
volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
|
||||
volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
|
||||
volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
|
||||
volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
|
||||
volatile dsi_brg_host_ctrl_reg_t host_ctrl;
|
||||
volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
|
||||
volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
|
||||
volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
|
||||
volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
|
||||
volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
|
||||
volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
|
||||
volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
|
||||
uint32_t reserved_0a0[24];
|
||||
volatile dsi_brg_ver_date_reg_t ver_date;
|
||||
} dsi_brg_dev_t;
|
||||
|
||||
extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -34,7 +34,11 @@ typedef union {
|
||||
* this bit configures module enable of dsi_bridge. 0: disable, 1: enable
|
||||
*/
|
||||
uint32_t dsi_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
/** dsi_brig_rst : R/W; bitpos: [1]; default: 0;
|
||||
* Configures software reset of dsi_bridge. 0: release reset, 1: reset
|
||||
*/
|
||||
uint32_t dsi_brig_rst:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_en_reg_t;
|
||||
@@ -109,7 +113,8 @@ typedef union {
|
||||
typedef union {
|
||||
struct {
|
||||
/** raw_type : R/W; bitpos: [3:0]; default: 0;
|
||||
* this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565
|
||||
* this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
|
||||
* 9:yuv422, 10:yuv420, 12:gray
|
||||
*/
|
||||
uint32_t raw_type:4;
|
||||
/** dpi_config : R/W; bitpos: [5:4]; default: 0;
|
||||
@@ -117,10 +122,14 @@ typedef union {
|
||||
*/
|
||||
uint32_t dpi_config:2;
|
||||
/** data_in_type : R/W; bitpos: [6]; default: 0;
|
||||
* input data type, 0: rgb, 1: yuv
|
||||
* input data type, 0: not yuv, 1: yuv
|
||||
*/
|
||||
uint32_t data_in_type:1;
|
||||
uint32_t reserved_7:25;
|
||||
/** dpi_type : R/W; bitpos: [10:7]; default: 0;
|
||||
* this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
|
||||
*/
|
||||
uint32_t dpi_type:4;
|
||||
uint32_t reserved_11:21;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_pixel_type_reg_t;
|
||||
@@ -198,7 +207,11 @@ typedef union {
|
||||
* this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
|
||||
*/
|
||||
uint32_t dpi_rsv_data:30;
|
||||
uint32_t reserved_30:2;
|
||||
/** dpi_dbg_en : R/W; bitpos: [30]; default: 0;
|
||||
* Configures data debug feature enable. 0: disable, 1: enable
|
||||
*/
|
||||
uint32_t dpi_dbg_en:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_dpi_rsv_dpi_data_reg_t;
|
||||
@@ -507,7 +520,11 @@ typedef union {
|
||||
* this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
|
||||
*/
|
||||
uint32_t yuv422_format:2;
|
||||
uint32_t reserved_4:28;
|
||||
/** yuv_range : R/W; bitpos: [4]; default: 0;
|
||||
* Configures yuv pixel range, 0: limit range, 1: full range
|
||||
*/
|
||||
uint32_t yuv_range:1;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_yuv_cfg_reg_t;
|
||||
@@ -716,7 +733,12 @@ typedef union {
|
||||
* by dpi_underrun interrupt signal
|
||||
*/
|
||||
uint32_t underrun_int_ena:1;
|
||||
uint32_t reserved_1:31;
|
||||
/** vsync_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
|
||||
* dpi_vsync interrupt signal
|
||||
*/
|
||||
uint32_t vsync_int_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_ena_reg_t;
|
||||
@@ -730,7 +752,11 @@ typedef union {
|
||||
* write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
|
||||
*/
|
||||
uint32_t underrun_int_clr:1;
|
||||
uint32_t reserved_1:31;
|
||||
/** vsync_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
|
||||
*/
|
||||
uint32_t vsync_int_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_clr_reg_t;
|
||||
@@ -744,7 +770,11 @@ typedef union {
|
||||
* the raw interrupt status of dpi_underrun
|
||||
*/
|
||||
uint32_t underrun_int_raw:1;
|
||||
uint32_t reserved_1:31;
|
||||
/** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* the raw interrupt status of dpi_vsync
|
||||
*/
|
||||
uint32_t vsync_int_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_raw_reg_t;
|
||||
@@ -758,11 +788,28 @@ typedef union {
|
||||
* the masked interrupt status of dpi_underrun
|
||||
*/
|
||||
uint32_t underrun_int_st:1;
|
||||
uint32_t reserved_1:31;
|
||||
/** vsync_int_st : RO; bitpos: [1]; default: 0;
|
||||
* the masked interrupt status of dpi_vsync
|
||||
*/
|
||||
uint32_t vsync_int_st:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_int_st_reg_t;
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of ver_date register
|
||||
* version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ver_data : R/W; bitpos: [31:0]; default: 539296009;
|
||||
* Represents csv version
|
||||
*/
|
||||
uint32_t ver_data:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} dsi_brg_ver_date_reg_t;
|
||||
|
||||
typedef struct dsi_brg_dev_t {
|
||||
volatile dsi_brg_clk_en_reg_t clk_en;
|
||||
@@ -804,15 +851,16 @@ typedef struct dsi_brg_dev_t {
|
||||
volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
|
||||
volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
|
||||
volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
|
||||
uint32_t reserved_0a0[24];
|
||||
volatile dsi_brg_ver_date_reg_t ver_date;
|
||||
} dsi_brg_dev_t;
|
||||
|
||||
extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure");
|
||||
_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure");
|
||||
#endif
|
||||
|
||||
extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -10,8 +10,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: IDF-13428
|
||||
|
||||
/** Group: Status register */
|
||||
/** Type of ch_ena_ad0 register
|
||||
* Channel enable status register
|
||||
|
||||
@@ -1,716 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
*/
|
||||
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
|
||||
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_EN (BIT(10))
|
||||
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
|
||||
#define TIMG_T0_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T0_ALARM_EN_S 10
|
||||
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer 0 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_T0_DIVCNT_RST (BIT(12))
|
||||
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
|
||||
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_T0_DIVCNT_RST_S 12
|
||||
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 0 clock (T0_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T0_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
|
||||
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_S 13
|
||||
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 0 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T0_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
|
||||
#define TIMG_T0_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T0_AUTORELOAD_S 29
|
||||
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 0 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 0 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T0_INCREASE (BIT(30))
|
||||
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
|
||||
#define TIMG_T0_INCREASE_V 0x00000001U
|
||||
#define TIMG_T0_INCREASE_S 30
|
||||
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer 0 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T0_EN (BIT(31))
|
||||
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
|
||||
#define TIMG_T0_EN_V 0x00000001U
|
||||
#define TIMG_T0_EN_S 31
|
||||
|
||||
/** TIMG_T0LO_REG register
|
||||
* Timer 0 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
|
||||
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
|
||||
#define TIMG_T0_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_S 0
|
||||
|
||||
/** TIMG_T0HI_REG register
|
||||
* Timer 0 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
|
||||
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_HI 0x003FFFFFU
|
||||
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
|
||||
#define TIMG_T0_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_HI_S 0
|
||||
|
||||
/** TIMG_T0UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
|
||||
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T0_UPDATE (BIT(31))
|
||||
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
|
||||
#define TIMG_T0_UPDATE_V 0x00000001U
|
||||
#define TIMG_T0_UPDATE_S 31
|
||||
|
||||
/** TIMG_T0ALARMLO_REG register
|
||||
* Timer 0 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
|
||||
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
|
||||
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T0ALARMHI_REG register
|
||||
* Timer 0 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
|
||||
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
|
||||
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T0LOADLO_REG register
|
||||
* Timer 0 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
|
||||
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 0 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
|
||||
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T0LOADHI_REG register
|
||||
* Timer 0 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
|
||||
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 0 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
|
||||
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T0LOAD_REG register
|
||||
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
|
||||
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 0 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T0_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
|
||||
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_S 0
|
||||
|
||||
/** TIMG_T1CONFIG_REG register
|
||||
* Timer 1 configuration register
|
||||
*/
|
||||
#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24)
|
||||
/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_EN (BIT(10))
|
||||
#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
|
||||
#define TIMG_T1_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T1_ALARM_EN_S 10
|
||||
/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer 1 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_T1_DIVCNT_RST (BIT(12))
|
||||
#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
|
||||
#define TIMG_T1_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_T1_DIVCNT_RST_S 12
|
||||
/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 1 clock (T1_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T1_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
|
||||
#define TIMG_T1_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T1_DIVIDER_S 13
|
||||
/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 1 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T1_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
|
||||
#define TIMG_T1_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T1_AUTORELOAD_S 29
|
||||
/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 1 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 1 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T1_INCREASE (BIT(30))
|
||||
#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
|
||||
#define TIMG_T1_INCREASE_V 0x00000001U
|
||||
#define TIMG_T1_INCREASE_S 30
|
||||
/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer 1 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T1_EN (BIT(31))
|
||||
#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S)
|
||||
#define TIMG_T1_EN_V 0x00000001U
|
||||
#define TIMG_T1_EN_S 31
|
||||
|
||||
/** TIMG_T1LO_REG register
|
||||
* Timer 1 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28)
|
||||
/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 1 can be read here.
|
||||
*/
|
||||
#define TIMG_T1_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S)
|
||||
#define TIMG_T1_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LO_S 0
|
||||
|
||||
/** TIMG_T1HI_REG register
|
||||
* Timer 1 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c)
|
||||
/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 1 can be read here.
|
||||
*/
|
||||
#define TIMG_T1_HI 0x003FFFFFU
|
||||
#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S)
|
||||
#define TIMG_T1_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_HI_S 0
|
||||
|
||||
/** TIMG_T1UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30)
|
||||
/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T1_UPDATE (BIT(31))
|
||||
#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
|
||||
#define TIMG_T1_UPDATE_V 0x00000001U
|
||||
#define TIMG_T1_UPDATE_S 31
|
||||
|
||||
/** TIMG_T1ALARMLO_REG register
|
||||
* Timer 1 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34)
|
||||
/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 1 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
|
||||
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T1ALARMHI_REG register
|
||||
* Timer 1 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38)
|
||||
/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 1 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
|
||||
#define TIMG_T1_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T1LOADLO_REG register
|
||||
* Timer 1 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c)
|
||||
/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 1 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T1_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
|
||||
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T1LOADHI_REG register
|
||||
* Timer 1 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40)
|
||||
/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 1 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T1_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
|
||||
#define TIMG_T1_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T1LOAD_REG register
|
||||
* Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44)
|
||||
/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 1 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T1_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
|
||||
#define TIMG_T1_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG0_REG register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
|
||||
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_S 12
|
||||
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_S 13
|
||||
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
|
||||
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
|
||||
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
|
||||
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_S 22
|
||||
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG3 0x00000003U
|
||||
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
|
||||
#define TIMG_WDT_STG3_V 0x00000003U
|
||||
#define TIMG_WDT_STG3_S 23
|
||||
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG2 0x00000003U
|
||||
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
|
||||
#define TIMG_WDT_STG2_V 0x00000003U
|
||||
#define TIMG_WDT_STG2_S 25
|
||||
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG1 0x00000003U
|
||||
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
|
||||
#define TIMG_WDT_STG1_V 0x00000003U
|
||||
#define TIMG_WDT_STG1_S 27
|
||||
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG0 0x00000003U
|
||||
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
|
||||
#define TIMG_WDT_STG0_V 0x00000003U
|
||||
#define TIMG_WDT_STG0_S 29
|
||||
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_EN (BIT(31))
|
||||
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
|
||||
#define TIMG_WDT_EN_V 0x00000001U
|
||||
#define TIMG_WDT_EN_S 31
|
||||
|
||||
/** TIMG_WDTCONFIG1_REG register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
|
||||
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_WDT_DIVCNT_RST (BIT(0))
|
||||
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
|
||||
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_WDT_DIVCNT_RST_S 0
|
||||
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
|
||||
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_S 16
|
||||
|
||||
/** TIMG_WDTCONFIG2_REG register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
|
||||
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
|
||||
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG3_REG register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
|
||||
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
|
||||
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG4_REG register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
|
||||
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
|
||||
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG5_REG register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
|
||||
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
|
||||
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTFEED_REG register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
|
||||
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
#define TIMG_WDT_FEED 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
|
||||
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_S 0
|
||||
|
||||
/** TIMG_WDTWPROTECT_REG register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
|
||||
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_WKEY 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
|
||||
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_S 0
|
||||
|
||||
/** TIMG_RTCCALICFG_REG register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
|
||||
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
|
||||
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
|
||||
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_CYCLING_S 12
|
||||
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
|
||||
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_S 13
|
||||
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
|
||||
* indicate one-shot frequency calculation is done.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_RDY (BIT(15))
|
||||
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
|
||||
#define TIMG_RTC_CALI_RDY_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_RDY_S 15
|
||||
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
|
||||
* Configure the time to calculate RTC slow clock's frequency.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_MAX 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
|
||||
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_S 16
|
||||
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start one-shot frequency calculation.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START (BIT(31))
|
||||
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
|
||||
#define TIMG_RTC_CALI_START_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_S 31
|
||||
|
||||
/** TIMG_RTCCALICFG1_REG register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
|
||||
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
|
||||
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
|
||||
* When one-shot or periodic frequency calculation is done, read this value to
|
||||
* calculate RTC slow clock's frequency.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
|
||||
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_S 7
|
||||
|
||||
/** TIMG_INT_ENA_TIMERS_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
|
||||
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ENA (BIT(0))
|
||||
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
|
||||
#define TIMG_T0_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T0_INT_ENA_S 0
|
||||
/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_ENA (BIT(1))
|
||||
#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
|
||||
#define TIMG_T1_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T1_INT_ENA_S 1
|
||||
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ENA (BIT(2))
|
||||
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
|
||||
#define TIMG_WDT_INT_ENA_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ENA_S 2
|
||||
|
||||
/** TIMG_INT_RAW_TIMERS_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
|
||||
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_RAW (BIT(0))
|
||||
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
|
||||
#define TIMG_T0_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T0_INT_RAW_S 0
|
||||
/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_RAW (BIT(1))
|
||||
#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
|
||||
#define TIMG_T1_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T1_INT_RAW_S 1
|
||||
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_RAW (BIT(2))
|
||||
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
|
||||
#define TIMG_WDT_INT_RAW_V 0x00000001U
|
||||
#define TIMG_WDT_INT_RAW_S 2
|
||||
|
||||
/** TIMG_INT_ST_TIMERS_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
|
||||
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ST (BIT(0))
|
||||
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
|
||||
#define TIMG_T0_INT_ST_V 0x00000001U
|
||||
#define TIMG_T0_INT_ST_S 0
|
||||
/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_ST (BIT(1))
|
||||
#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
|
||||
#define TIMG_T1_INT_ST_V 0x00000001U
|
||||
#define TIMG_T1_INT_ST_S 1
|
||||
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ST (BIT(2))
|
||||
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
|
||||
#define TIMG_WDT_INT_ST_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ST_S 2
|
||||
|
||||
/** TIMG_INT_CLR_TIMERS_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
|
||||
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_CLR (BIT(0))
|
||||
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
|
||||
#define TIMG_T0_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T0_INT_CLR_S 0
|
||||
/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_CLR (BIT(1))
|
||||
#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
|
||||
#define TIMG_T1_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T1_INT_CLR_S 1
|
||||
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_CLR (BIT(2))
|
||||
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
|
||||
#define TIMG_WDT_INT_CLR_V 0x00000001U
|
||||
#define TIMG_WDT_INT_CLR_S 2
|
||||
|
||||
/** TIMG_RTCCALICFG2_REG register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
|
||||
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
|
||||
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_TIMEOUT_S 0
|
||||
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
|
||||
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
|
||||
|
||||
/** TIMG_NTIMERS_DATE_REG register
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
|
||||
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
|
||||
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_S 0
|
||||
|
||||
/** TIMG_REGCLK_REG register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
|
||||
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
#define TIMG_ETM_EN (BIT(28))
|
||||
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
|
||||
#define TIMG_ETM_EN_V 0x00000001U
|
||||
#define TIMG_ETM_EN_S 28
|
||||
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
#define TIMG_CLK_EN (BIT(31))
|
||||
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
|
||||
#define TIMG_CLK_EN_V 0x00000001U
|
||||
#define TIMG_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,571 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: T0 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:10;
|
||||
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tx_alarm_en:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer x 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tx_divcnt_rst:1;
|
||||
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer x clock (Tx_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tx_divider:16;
|
||||
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer x auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tx_autoreload:1;
|
||||
/** tx_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer x time-base counter will increment every clock tick. When
|
||||
* cleared, the timer x time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tx_increase:1;
|
||||
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer x time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tx_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txconfig_reg_t;
|
||||
|
||||
/** Type of txlo register
|
||||
* Timer x current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txlo_reg_t;
|
||||
|
||||
/** Type of txhi register
|
||||
* Timer x current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txhi_reg_t;
|
||||
|
||||
/** Type of txupdate register
|
||||
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tx_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txupdate_reg_t;
|
||||
|
||||
/** Type of txalarmlo register
|
||||
* Timer x alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmlo_reg_t;
|
||||
|
||||
/** Type of txalarmhi register
|
||||
* Timer x alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmhi_reg_t;
|
||||
|
||||
/** Type of txloadlo register
|
||||
* Timer x reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer x time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tx_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadlo_reg_t;
|
||||
|
||||
/** Type of txloadhi register
|
||||
* Timer x reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer x time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tx_load_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadhi_reg_t;
|
||||
|
||||
/** Type of txload register
|
||||
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer x time-base counter reload.
|
||||
*/
|
||||
uint32_t tx_load:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txload_reg_t;
|
||||
|
||||
/** Group: WDT Control and configuration registers */
|
||||
/** Type of wdtconfig0 register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en:1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en:1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en:1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length:3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length:3;
|
||||
uint32_t reserved_21:1;
|
||||
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
uint32_t wdt_conf_update_en:1;
|
||||
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg3:2;
|
||||
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg2:2;
|
||||
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg1:2;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg0:2;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig0_reg_t;
|
||||
|
||||
/** Type of wdtconfig1 register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t wdt_divcnt_rst:1;
|
||||
uint32_t reserved_1:15;
|
||||
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
uint32_t wdt_clk_prescale:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig1_reg_t;
|
||||
|
||||
/** Type of wdtconfig2 register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig2_reg_t;
|
||||
|
||||
/** Type of wdtconfig3 register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig3_reg_t;
|
||||
|
||||
/** Type of wdtconfig4 register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig4_reg_t;
|
||||
|
||||
/** Type of wdtconfig5 register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig5_reg_t;
|
||||
|
||||
/** Type of wdtfeed register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
uint32_t wdt_feed:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtfeed_reg_t;
|
||||
|
||||
/** Type of wdtwprotect register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtwprotect_reg_t;
|
||||
|
||||
|
||||
/** Group: RTC CALI Control and configuration registers */
|
||||
/** Type of rtccalicfg register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
uint32_t rtc_cali_start_cycling:1;
|
||||
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
uint32_t rtc_cali_clk_sel:2;
|
||||
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
|
||||
* indicate one-shot frequency calculation is done.
|
||||
*/
|
||||
uint32_t rtc_cali_rdy:1;
|
||||
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
|
||||
* Configure the time to calculate RTC slow clock's frequency.
|
||||
*/
|
||||
uint32_t rtc_cali_max:15;
|
||||
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start one-shot frequency calculation.
|
||||
*/
|
||||
uint32_t rtc_cali_start:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg_reg_t;
|
||||
|
||||
/** Type of rtccalicfg1 register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
uint32_t rtc_cali_cycling_data_vld:1;
|
||||
uint32_t reserved_1:6;
|
||||
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
|
||||
* When one-shot or periodic frequency calculation is done, read this value to
|
||||
* calculate RTC slow clock's frequency.
|
||||
*/
|
||||
uint32_t rtc_cali_value:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg1_reg_t;
|
||||
|
||||
/** Type of rtccalicfg2 register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
uint32_t rtc_cali_timeout:1;
|
||||
uint32_t reserved_1:2;
|
||||
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_rst_cnt:4;
|
||||
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_thres:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg2_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_ena_timers register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_ena:1;
|
||||
/** t1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_ena:1;
|
||||
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_ena_timers_reg_t;
|
||||
|
||||
/** Type of int_raw_timers register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_raw:1;
|
||||
/** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_raw:1;
|
||||
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_raw_timers_reg_t;
|
||||
|
||||
/** Type of int_st_timers register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_st:1;
|
||||
/** t1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_st:1;
|
||||
/** wdt_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_st_timers_reg_t;
|
||||
|
||||
/** Type of int_clr_timers register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_clr:1;
|
||||
/** t1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_clr:1;
|
||||
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_clr_timers_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of ntimers_date register
|
||||
* Timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
uint32_t ntimgs_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_ntimers_date_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock configuration registers */
|
||||
/** Type of regclk register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:28;
|
||||
/** etm_en : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
uint32_t etm_en:1;
|
||||
uint32_t reserved_29:2;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_regclk_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile timg_txconfig_reg_t t0config;
|
||||
volatile timg_txlo_reg_t t0lo;
|
||||
volatile timg_txhi_reg_t t0hi;
|
||||
volatile timg_txupdate_reg_t t0update;
|
||||
volatile timg_txalarmlo_reg_t t0alarmlo;
|
||||
volatile timg_txalarmhi_reg_t t0alarmhi;
|
||||
volatile timg_txloadlo_reg_t t0loadlo;
|
||||
volatile timg_txloadhi_reg_t t0loadhi;
|
||||
volatile timg_txload_reg_t t0load;
|
||||
volatile timg_txconfig_reg_t t1config;
|
||||
volatile timg_txlo_reg_t t1lo;
|
||||
volatile timg_txhi_reg_t t1hi;
|
||||
volatile timg_txupdate_reg_t t1update;
|
||||
volatile timg_txalarmlo_reg_t t1alarmlo;
|
||||
volatile timg_txalarmhi_reg_t t1alarmhi;
|
||||
volatile timg_txloadlo_reg_t t1loadlo;
|
||||
volatile timg_txloadhi_reg_t t1loadhi;
|
||||
volatile timg_txload_reg_t t1load;
|
||||
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
||||
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
||||
volatile timg_wdtconfig2_reg_t wdtconfig2;
|
||||
volatile timg_wdtconfig3_reg_t wdtconfig3;
|
||||
volatile timg_wdtconfig4_reg_t wdtconfig4;
|
||||
volatile timg_wdtconfig5_reg_t wdtconfig5;
|
||||
volatile timg_wdtfeed_reg_t wdtfeed;
|
||||
volatile timg_wdtwprotect_reg_t wdtwprotect;
|
||||
volatile timg_rtccalicfg_reg_t rtccalicfg;
|
||||
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
|
||||
volatile timg_int_ena_timers_reg_t int_ena_timers;
|
||||
volatile timg_int_raw_timers_reg_t int_raw_timers;
|
||||
volatile timg_int_st_timers_reg_t int_st_timers;
|
||||
volatile timg_int_clr_timers_reg_t int_clr_timers;
|
||||
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
|
||||
uint32_t reserved_084[29];
|
||||
volatile timg_ntimers_date_reg_t ntimers_date;
|
||||
volatile timg_regclk_reg_t regclk;
|
||||
} timg_dev_t;
|
||||
|
||||
extern timg_dev_t TIMERG0;
|
||||
extern timg_dev_t TIMERG1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -11,7 +11,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: IDF-13422
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000)
|
||||
|
||||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
|
||||
@@ -10,8 +10,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: IDF-13422
|
||||
|
||||
/** Group: T0 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
|
||||
Reference in New Issue
Block a user