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Merge branch 'feat/c5_eco_spi_and_twai_support' into 'master'

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feat(driver_spi): c5 eco2 spi and twai support

Closes IDF-12636, IDF-12640, IDF-8699, IDF-10401, IDF-11269, IDF-12833, and IDF-12834

See merge request espressif/esp-idf!38380
This commit is contained in:
Wan Lei
2025-04-17 19:23:59 +08:00
parent 3c60a009f4 6bfdc0ce63
commit 3d83751dcc
10 changed files with 1020 additions and 1075 deletions
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14
components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c
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@ -121,7 +121,7 @@ TEST_CASE("twai transmit stop resume (loopback)", "[TWAI]")
twai_onchip_node_config_t node_config = {
.io_cfg.tx = TEST_TX_GPIO,
.io_cfg.rx = TEST_TX_GPIO, // Using same pin for test without transceiver
.bit_timing.bitrate = 1000000,
.bit_timing.bitrate = 20000,
.data_timing.bitrate = 4000000,
.data_timing.ssp_permill = 700, // ssp 70.0%
.tx_queue_depth = TEST_TWAI_QUEUE_DEPTH,
@ -130,14 +130,14 @@ TEST_CASE("twai transmit stop resume (loopback)", "[TWAI]")
};
TEST_ESP_OK(twai_new_node_onchip(&node_config, &node_hdl));
// reconfig fd timing to 48M/(12+5+6+1)=2MHz, ssp=20/(12+5+6+1)=83%
// reconfig fd timing to 80M/(4+3+2+1)=8MHz, ssp=8/(4+3+2+1)=80%
twai_timing_advanced_config_t timing_fd = {
.brp = 1,
.prop_seg = 12,
.tseg_1 = 5,
.tseg_2 = 6,
.sjw = 3,
.ssp_offset = 20,
.prop_seg = 4,
.tseg_1 = 3,
.tseg_2 = 2,
.sjw = 2,
.ssp_offset = 8,
};
TEST_ESP_OK(twai_node_reconfig_timing(node_hdl, NULL, &timing_fd));

7
components/hal/esp32c5/include/hal/spi_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -698,13 +698,14 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
*----------------------------------------------------------------------------*/
/**
* Set the standard clock mode for master.
* This config take effect only when SPI_CLK (pre-div before periph) div >=2
*
* @param hw Beginning address of the peripheral registers.
* @param enable_std True for std timing, False for half cycle delay sampling.
*/
static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point)
{
//This is not supported
hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1);
}
/**
@ -712,7 +713,7 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_
*/
static inline bool spi_ll_master_is_rx_std_sample_supported(void)
{
return false;
return true;
}
/**

2
components/hal/esp32c5/include/hal/twaifd_ll.h
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@ -92,7 +92,7 @@ static inline void twaifd_ll_reset_register(uint8_t twai_id)
*/
static inline void twaifd_ll_set_clock_source(uint8_t twai_id, twai_clock_source_t clk_src)
{
PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_RC_FAST) ? 1 : 0;
PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_XTAL) ? 0 : 1;
}
/**

8
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -422,15 +422,15 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of TWAI
*/
#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M}
/**
* @brief TWAI clock source
*/
typedef enum {
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TWAI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
TWAI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////

1
components/soc/esp32c5/include/soc/soc.h
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@ -21,7 +21,6 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C5
#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1

461
components/soc/esp32c5/register/soc/pcr_reg.h
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File diff suppressed because it is too large Load Diff

418
components/soc/esp32c5/register/soc/pcr_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -21,7 +21,7 @@ typedef union {
*/
uint32_t uart0_clk_en:1;
/** uart0_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart0 module
* Set 1 to reset uart0 module
*/
uint32_t uart0_rst_en:1;
/** uart0_ready : RO; bitpos: [2]; default: 1;
@ -51,10 +51,10 @@ typedef union {
*/
uint32_t uart0_sclk_div_num:8;
/** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t uart0_sclk_sel:2;
/** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
@ -95,7 +95,7 @@ typedef union {
*/
uint32_t uart1_clk_en:1;
/** uart1_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart1 module
* Set 1 to reset uart1 module
*/
uint32_t uart1_rst_en:1;
/** uart1_ready : RO; bitpos: [2]; default: 1;
@ -125,10 +125,10 @@ typedef union {
*/
uint32_t uart1_sclk_div_num:8;
/** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t uart1_sclk_sel:2;
/** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
@ -169,7 +169,7 @@ typedef union {
*/
uint32_t mspi_clk_en:1;
/** mspi_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset mspi module
* Set 1 to reset mspi module
*/
uint32_t mspi_rst_en:1;
/** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
@ -197,10 +197,10 @@ typedef union {
*/
uint32_t mspi_fast_div_num:8;
/** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0;
* Configures the clock source for MSPI.\\
* 0(default): XTAL_CLK\\
* 1 RC_FAST_CLK\\
* 2: PLL_F480M_CLK\\
* Configures the clock source for MSPI.
* 0(default): XTAL_CLK
* 1 RC_FAST_CLK
* 2: PLL_F480M_CLK
*/
uint32_t mspi_func_clk_sel:2;
/** mspi_func_clk_en : R/W; bitpos: [10]; default: 1;
@ -208,7 +208,7 @@ typedef union {
*/
uint32_t mspi_func_clk_en:1;
/** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0;
* Set 0 to reset axi_clock domain of mspi module
* Set 1 to reset axi_clock domain of mspi module
*/
uint32_t mspi_axi_rst_en:1;
uint32_t reserved_12:20;
@ -226,7 +226,7 @@ typedef union {
*/
uint32_t i2c_clk_en:1;
/** i2c_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2c module
* Set 1 to reset i2c module
*/
uint32_t i2c_rst_en:1;
uint32_t reserved_2:30;
@ -252,9 +252,9 @@ typedef union {
*/
uint32_t i2c_sclk_div_num:8;
/** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of I2C.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of I2C.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
uint32_t i2c_sclk_sel:1;
uint32_t reserved_21:1;
@ -277,7 +277,7 @@ typedef union {
*/
uint32_t twai_clk_en:1;
/** twai_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset twai module
* Set 1 to reset twai module
*/
uint32_t twai_rst_en:1;
/** twai_ready : RO; bitpos: [2]; default: 1;
@ -296,9 +296,9 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** twai_func_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of TWAI.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of TWAI.
* 0 (default): XTAL_CLK
* 1: PLL_F80M_CLK
*/
uint32_t twai_func_clk_sel:1;
uint32_t reserved_21:1;
@ -321,7 +321,7 @@ typedef union {
*/
uint32_t uhci_clk_en:1;
/** uhci_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uhci module
* Set 1 to reset uhci module
*/
uint32_t uhci_rst_en:1;
/** uhci_ready : RO; bitpos: [2]; default: 1;
@ -343,7 +343,7 @@ typedef union {
*/
uint32_t rmt_clk_en:1;
/** rmt_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset rmt module
* Set 1 to reset rmt module
*/
uint32_t rmt_rst_en:1;
uint32_t reserved_2:30;
@ -369,10 +369,10 @@ typedef union {
*/
uint32_t rmt_sclk_div_num:8;
/** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1;
* Configures the clock source of RMT.\\
* 0: XTAL_CLK\\
* 1 (default): RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of RMT.
* 0: XTAL_CLK
* 1 (default): RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t rmt_sclk_sel:2;
/** rmt_sclk_en : R/W; bitpos: [22]; default: 0;
@ -413,7 +413,7 @@ typedef union {
*/
uint32_t ledc_clk_en:1;
/** ledc_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ledc module
* Set 1 to reset ledc module
*/
uint32_t ledc_rst_en:1;
/** ledc_ready : RO; bitpos: [2]; default: 1;
@ -432,10 +432,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of LEDC.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of LEDC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t ledc_sclk_sel:2;
/** ledc_sclk_en : R/W; bitpos: [22]; default: 0;
@ -476,7 +476,7 @@ typedef union {
*/
uint32_t tg0_clk_en:1;
/** tg0_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group0 module
* Set 1 to reset timer_group0 module
*/
uint32_t tg0_rst_en:1;
/** tg0_wdt_ready : RO; bitpos: [2]; default: 1;
@ -503,10 +503,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of general-purpose timers in Timer Group 0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of general-purpose timers in Timer Group 0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg0_timer_clk_sel:2;
/** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
@ -525,10 +525,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of WDT in Timer Group 0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of WDT in Timer Group 0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg0_wdt_clk_sel:2;
/** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
@ -550,7 +550,7 @@ typedef union {
*/
uint32_t tg1_clk_en:1;
/** tg1_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 module
* Set 1 to reset timer_group1 module
*/
uint32_t tg1_rst_en:1;
/** tg1_wdt_ready : RO; bitpos: [2]; default: 1;
@ -577,10 +577,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of general-purpose timers in Timer Group 1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of general-purpose timers in Timer Group 1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg1_timer_clk_sel:2;
/** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
@ -599,10 +599,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of WDT in Timer Group 1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of WDT in Timer Group 1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg1_wdt_clk_sel:2;
/** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
@ -624,7 +624,7 @@ typedef union {
*/
uint32_t systimer_clk_en:1;
/** systimer_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset systimer module
* Set 1 to reset systimer module
*/
uint32_t systimer_rst_en:1;
/** systimer_ready : RO; bitpos: [2]; default: 1;
@ -643,9 +643,9 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of System Timer.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of System Timer.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
uint32_t systimer_func_clk_sel:1;
uint32_t reserved_21:1;
@ -668,7 +668,7 @@ typedef union {
*/
uint32_t i2s_clk_en:1;
/** i2s_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2s module
* Set 1 to reset i2s module
*/
uint32_t i2s_rst_en:1;
/** i2s_rx_ready : RO; bitpos: [2]; default: 1;
@ -698,11 +698,11 @@ typedef union {
*/
uint32_t i2s_tx_clkm_div_num:8;
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S TX.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F240M_CLK\\
* 2: PLL_F160M_CLK\\
* 3: I2S_MCLK_in\\
* Configures the clock source of I2S TX.
* 0 (default): XTAL_CLK
* 1: PLL_F240M_CLK
* 2: PLL_F160M_CLK
* 3: I2S_MCLK_in
*/
uint32_t i2s_tx_clkm_sel:2;
/** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 0;
@ -755,11 +755,11 @@ typedef union {
*/
uint32_t i2s_rx_clkm_div_num:8;
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S RX.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F240M_CLK\\
* 2: PLL_F160M_CLK\\
* 3: I2S_MCLK_in\\
* Configures the clock source of I2S RX.
* 0 (default): XTAL_CLK
* 1: PLL_F240M_CLK
* 2: PLL_F160M_CLK
* 3: I2S_MCLK_in
*/
uint32_t i2s_rx_clkm_sel:2;
/** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 0;
@ -767,9 +767,9 @@ typedef union {
*/
uint32_t i2s_rx_clkm_en:1;
/** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
* Configures to select master clock.\\
* 0 (default): I2S_TX_CLK\\
* 1: I2S_RX_CLK\\
* Configures to select master clock.
* 0 (default): I2S_TX_CLK
* 1: I2S_RX_CLK
*/
uint32_t i2s_mclk_sel:1;
uint32_t reserved_24:8;
@ -817,7 +817,7 @@ typedef union {
*/
uint32_t saradc_clk_en:1;
/** saradc_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset function_register of saradc module
* Set 1 to reset function_register of saradc module
*/
uint32_t saradc_rst_en:1;
/** saradc_reg_clk_en : R/W; bitpos: [2]; default: 0;
@ -825,7 +825,7 @@ typedef union {
*/
uint32_t saradc_reg_clk_en:1;
/** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
* Set 0 to reset apb_register of saradc module
* Set 1 to reset apb_register of saradc module
*/
uint32_t saradc_reg_rst_en:1;
uint32_t reserved_4:28;
@ -851,10 +851,10 @@ typedef union {
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of SAR ADC.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of SAR ADC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t saradc_clkm_sel:2;
/** saradc_clkm_en : R/W; bitpos: [22]; default: 0;
@ -873,9 +873,9 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of the temperature sensor.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of the temperature sensor.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
uint32_t tsens_clk_sel:1;
uint32_t reserved_21:1;
@ -884,7 +884,7 @@ typedef union {
*/
uint32_t tsens_clk_en:1;
/** tsens_rst_en : R/W; bitpos: [23]; default: 0;
* Set 0 to reset tsens module
* Set 1 to reset tsens module
*/
uint32_t tsens_rst_en:1;
uint32_t reserved_24:8;
@ -902,7 +902,7 @@ typedef union {
*/
uint32_t usb_device_clk_en:1;
/** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset usb_device module
* Set 1 to reset usb_device module
*/
uint32_t usb_device_rst_en:1;
/** usb_device_ready : RO; bitpos: [2]; default: 1;
@ -924,7 +924,7 @@ typedef union {
*/
uint32_t intmtx_clk_en:1;
/** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset intmtx module
* Set 1 to reset intmtx module
*/
uint32_t intmtx_rst_en:1;
/** intmtx_ready : RO; bitpos: [2]; default: 1;
@ -946,7 +946,7 @@ typedef union {
*/
uint32_t pcnt_clk_en:1;
/** pcnt_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset pcnt module
* Set 1 to reset pcnt module
*/
uint32_t pcnt_rst_en:1;
/** pcnt_ready : RO; bitpos: [2]; default: 1;
@ -968,7 +968,7 @@ typedef union {
*/
uint32_t etm_clk_en:1;
/** etm_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset etm module
* Set 1 to reset etm module
*/
uint32_t etm_rst_en:1;
/** etm_ready : RO; bitpos: [2]; default: 1;
@ -990,7 +990,7 @@ typedef union {
*/
uint32_t pwm_clk_en:1;
/** pwm_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset pwm module
* Set 1 to reset pwm module
*/
uint32_t pwm_rst_en:1;
/** pwm_ready : RO; bitpos: [2]; default: 1;
@ -1013,10 +1013,10 @@ typedef union {
*/
uint32_t pwm_div_num:8;
/** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of MCPWM.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F160M_CLK\\
* Configures the clock source of MCPWM.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F160M_CLK
*/
uint32_t pwm_clkm_sel:2;
/** pwm_clkm_en : R/W; bitpos: [22]; default: 0;
@ -1038,7 +1038,7 @@ typedef union {
*/
uint32_t parl_clk_en:1;
/** parl_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset parl apb reg
* Set 1 to reset parl apb reg
*/
uint32_t parl_rst_en:1;
/** parl_ready : RO; bitpos: [2]; default: 1;
@ -1060,11 +1060,11 @@ typedef union {
*/
uint32_t parl_clk_rx_div_num:16;
/** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0;
* Configures the clock source of Paraller IO RX\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F240M_CLK\\
* 3: Use the clock from chip pin\\
* Configures the clock source of Paraller IO RX
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F240M_CLK
* 3: Use the clock from chip pin
*/
uint32_t parl_clk_rx_sel:2;
/** parl_clk_rx_en : R/W; bitpos: [18]; default: 0;
@ -1072,7 +1072,7 @@ typedef union {
*/
uint32_t parl_clk_rx_en:1;
/** parl_rx_rst_en : R/W; bitpos: [19]; default: 0;
* Set 0 to reset parl rx module
* Set 1 to reset parl rx module
*/
uint32_t parl_rx_rst_en:1;
uint32_t reserved_20:12;
@ -1090,11 +1090,11 @@ typedef union {
*/
uint32_t parl_clk_tx_div_num:16;
/** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0;
* Configures the clock source of Paraller IO RX\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F240M_CLK\\
* 3: Use the clock from chip pin\\
* Configures the clock source of Paraller IO RX
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F240M_CLK
* 3: Use the clock from chip pin
*/
uint32_t parl_clk_tx_sel:2;
/** parl_clk_tx_en : R/W; bitpos: [18]; default: 0;
@ -1102,7 +1102,7 @@ typedef union {
*/
uint32_t parl_clk_tx_en:1;
/** parl_tx_rst_en : R/W; bitpos: [19]; default: 0;
* Set 0 to reset parl tx module
* Set 1 to reset parl tx module
*/
uint32_t parl_tx_rst_en:1;
uint32_t reserved_20:12;
@ -1120,7 +1120,7 @@ typedef union {
*/
uint32_t pvt_monitor_clk_en:1;
/** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset all pvt monitor module
* Set 1 to reset all pvt monitor module
*/
uint32_t pvt_monitor_rst_en:1;
/** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1;
@ -1151,9 +1151,9 @@ typedef union {
uint32_t pvt_monitor_func_clk_div_num:4;
uint32_t reserved_4:16;
/** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of PVT MONITOR.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F160M_CLK\\
* Configures the clock source of PVT MONITOR.
* 0 (default): XTAL_CLK
* 1: PLL_F160M_CLK
*/
uint32_t pvt_monitor_func_clk_sel:1;
uint32_t reserved_21:1;
@ -1176,7 +1176,7 @@ typedef union {
*/
uint32_t gdma_clk_en:1;
/** gdma_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset gdma module
* Set 1 to reset gdma module
*/
uint32_t gdma_rst_en:1;
uint32_t reserved_2:30;
@ -1194,7 +1194,7 @@ typedef union {
*/
uint32_t spi2_clk_en:1;
/** spi2_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset spi2 module
* Set 1 to reset spi2 module
*/
uint32_t spi2_rst_en:1;
/** spi2_ready : RO; bitpos: [2]; default: 1;
@ -1217,11 +1217,11 @@ typedef union {
*/
uint32_t spi2_clkm_div_num:8;
/** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of SPI2.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F160M_CLK\\
* 2: RC_FAST_CLK\\
* 3: PLL_F120M_CLK\\
* Configures the clock source of SPI2.
* 0 (default): XTAL_CLK
* 1: PLL_F160M_CLK
* 2: RC_FAST_CLK
* 3: PLL_F120M_CLK
*/
uint32_t spi2_clkm_sel:2;
/** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
@ -1243,7 +1243,7 @@ typedef union {
*/
uint32_t aes_clk_en:1;
/** aes_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset aes module
* Set 1 to reset aes module
*/
uint32_t aes_rst_en:1;
/** aes_ready : RO; bitpos: [2]; default: 1;
@ -1265,7 +1265,7 @@ typedef union {
*/
uint32_t sha_clk_en:1;
/** sha_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset sha module
* Set 1 to reset sha module
*/
uint32_t sha_rst_en:1;
/** sha_ready : RO; bitpos: [2]; default: 1;
@ -1287,7 +1287,7 @@ typedef union {
*/
uint32_t rsa_clk_en:1;
/** rsa_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset rsa module
* Set 1 to reset rsa module
*/
uint32_t rsa_rst_en:1;
/** rsa_ready : RO; bitpos: [2]; default: 1;
@ -1331,7 +1331,7 @@ typedef union {
*/
uint32_t ecc_clk_en:1;
/** ecc_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ecc module
* Set 1 to reset ecc module
*/
uint32_t ecc_rst_en:1;
/** ecc_ready : RO; bitpos: [2]; default: 1;
@ -1375,7 +1375,7 @@ typedef union {
*/
uint32_t ds_clk_en:1;
/** ds_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ds module
* Set 1 to reset ds module
*/
uint32_t ds_rst_en:1;
/** ds_ready : RO; bitpos: [2]; default: 1;
@ -1397,7 +1397,7 @@ typedef union {
*/
uint32_t hmac_clk_en:1;
/** hmac_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset hmac module
* Set 1 to reset hmac module
*/
uint32_t hmac_rst_en:1;
/** hmac_ready : RO; bitpos: [2]; default: 1;
@ -1419,7 +1419,7 @@ typedef union {
*/
uint32_t ecdsa_clk_en:1;
/** ecdsa_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ecdsa module
* Set 1 to reset ecdsa module
*/
uint32_t ecdsa_rst_en:1;
/** ecdsa_ready : RO; bitpos: [2]; default: 1;
@ -1441,7 +1441,7 @@ typedef union {
*/
uint32_t iomux_clk_en:1;
/** iomux_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset iomux module
* Set 1 to reset iomux module
*/
uint32_t iomux_rst_en:1;
uint32_t reserved_2:30;
@ -1456,10 +1456,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of IO MUX.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of IO MUX.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t iomux_func_clk_sel:2;
/** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
@ -1481,7 +1481,7 @@ typedef union {
*/
uint32_t regdma_clk_en:1;
/** regdma_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset regdma module
* Set 1 to reset regdma module
*/
uint32_t regdma_rst_en:1;
uint32_t reserved_2:30;
@ -1499,7 +1499,7 @@ typedef union {
*/
uint32_t trace_clk_en:1;
/** trace_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset trace module
* Set 1 to reset trace module
*/
uint32_t trace_rst_en:1;
uint32_t reserved_2:30;
@ -1517,7 +1517,7 @@ typedef union {
*/
uint32_t assist_clk_en:1;
/** assist_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset assist module
* Set 1 to reset assist module
*/
uint32_t assist_rst_en:1;
uint32_t reserved_2:30;
@ -1535,7 +1535,7 @@ typedef union {
*/
uint32_t cache_clk_en:1;
/** cache_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset cache module
* Set 1 to reset cache module
*/
uint32_t cache_rst_en:1;
/** cache_pu_en : R/W; bitpos: [2]; default: 1;
@ -1581,11 +1581,11 @@ typedef union {
struct {
uint32_t reserved_0:1;
/** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset cpu_peri timeout module
* Set 1 to reset cpu_peri timeout module
*/
uint32_t cpu_timeout_rst_en:1;
/** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
* Set 0 to reset hp_peri timeout module and hp_modem timeout module
* Set 1 to reset hp_peri timeout module and hp_modem timeout module
*/
uint32_t hp_timeout_rst_en:1;
uint32_t reserved_3:29;
@ -1598,13 +1598,21 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** ls_div_num : HRO; bitpos: [7:0]; default: 0;
* clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
* clock-source such as XTAL/FOSC.
*/
uint32_t ls_div_num:8;
/** hs_div_num : HRO; bitpos: [15:8]; default: 2;
* clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
*/
uint32_t hs_div_num:8;
/** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
* Configures to select the clock source of HP_ROOT_CLK.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F160M_CLK\\
* 2: PLL_F240M_CLK\\
* Configures to select the clock source of HP_ROOT_CLK.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F160M_CLK
* 2: PLL_F240M_CLK
*/
uint32_t soc_clk_sel:2;
uint32_t reserved_18:6;
@ -1626,14 +1634,7 @@ typedef union {
*/
typedef union {
struct {
/** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1;
* Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
*/
uint32_t cpuperiod_sel:2;
/** pll_freq_sel : HRO; bitpos: [2]; default: 1;
* Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
*/
uint32_t pll_freq_sel:1;
uint32_t reserved_0:3;
/** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
* Set 1 to force cpu_waiti_clk enable.
*/
@ -1821,12 +1822,12 @@ typedef union {
typedef union {
struct {
/** 32k_sel : R/W; bitpos: [2:0]; default: 0;
* Configures the 32KHz clock for TIMER_GROUP.\\
* 0 (default): RC32K_CLK\\
* 1: XTAL32K_CLK\\
* 2: OSC_SLOW_CLK\\
* 3: RC_SLOW_CLK\\
* 4: RC_FAST_CLK\\
* Configures the 32KHz clock for TIMER_GROUP.
* 0 (default): RC32K_CLK
* 1: XTAL32K_CLK
* 2: OSC_SLOW_CLK
* 3: RC_SLOW_CLK
* 4: RC_FAST_CLK
*/
uint32_t clk_32k_sel:3;
uint32_t reserved_3:5;
@ -1895,14 +1896,14 @@ typedef union {
struct {
/** sec_clk_sel : R/W; bitpos: [1:0]; default: 0;
* Configures the clock source for the External Memory Encryption and Decryption
* module.\\
* 0(default): XTAL_CLK\\
* 1 RC_FAST_CLK\\
* 2: PLL_F480M_CLK\\
* module.
* 0(default): XTAL_CLK
* 1 RC_FAST_CLK
* 2: PLL_F480M_CLK
*/
uint32_t sec_clk_sel:2;
/** sec_rst_en : R/W; bitpos: [2]; default: 0;
* Set 0 to reset sec module
* Set 1 to reset sec module
*/
uint32_t sec_rst_en:1;
uint32_t reserved_3:29;
@ -1910,28 +1911,6 @@ typedef union {
uint32_t val;
} pcr_sec_conf_reg_t;
/** Type of adc_dac_inv_phase_conf register
* xxxx
*/
typedef union {
struct {
/** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0;
* xxxx
*/
uint32_t clk_rx_adc_inv_phase_ena:1;
/** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0;
* xxxx
*/
uint32_t clk_tx_dac_inv_phase_ena:1;
/** clk_pwdet_adc_inv_phase_ena : R/W; bitpos: [2]; default: 0;
* xxxx
*/
uint32_t clk_pwdet_adc_inv_phase_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_adc_dac_inv_phase_conf_reg_t;
/** Type of bus_clk_update register
* Configuration register for applying updated high-performance system clock sources
*/
@ -1939,10 +1918,10 @@ typedef union {
struct {
/** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0;
* Configures whether or not to update configurations for CPU_CLK division, AHB_CLK
* division and HP_ROOT_CLK clock source selection.\\
* 0: Not update configurations\\
* 1: Update configurations\\
* This bit is automatically cleared when configurations have been updated.\\
* division and HP_ROOT_CLK clock source selection.
* 0: Not update configurations
* 1: Update configurations
* This bit is automatically cleared when configurations have been updated.
*/
uint32_t bus_clock_update:1;
uint32_t reserved_1:31;
@ -1956,13 +1935,11 @@ typedef union {
typedef union {
struct {
/** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4;
* Configures the divisor for SAR ADC 2 clock to generate ADC analog control
* signals.\\
* Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals.
*/
uint32_t sar2_clk_div_num:8;
/** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4;
* Configures the divisor for SAR ADC 1 clock to generate ADC analog control
* signals.\\
* Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals.
*/
uint32_t sar1_clk_div_num:8;
uint32_t reserved_16:16;
@ -1970,24 +1947,6 @@ typedef union {
uint32_t val;
} pcr_sar_clk_div_reg_t;
/** Type of pwdet_sar_clk_conf register
* xxxx
*/
typedef union {
struct {
/** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7;
* xxxx
*/
uint32_t pwdet_sar_clk_div_num:8;
/** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1;
* xxxx
*/
uint32_t pwdet_sar_clk_en:1;
uint32_t reserved_9:23;
};
uint32_t val;
} pcr_pwdet_sar_clk_conf_reg_t;
/** Type of bs_conf register
* BS configuration register
*/
@ -1998,7 +1957,7 @@ typedef union {
*/
uint32_t bs_clk_en:1;
/** bs_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset bs module
* Set 1 to reset bs module
*/
uint32_t bs_rst_en:1;
uint32_t reserved_2:30;
@ -2013,11 +1972,11 @@ typedef union {
struct {
uint32_t reserved_0:23;
/** bs_tx_rst_en : R/W; bitpos: [23]; default: 0;
* Set 0 to reset bs tx module
* Set 1 to reset bs tx module
*/
uint32_t bs_tx_rst_en:1;
/** bs_rx_rst_en : R/W; bitpos: [24]; default: 0;
* Set 0 to reset bs rx module
* Set 1 to reset bs rx module
*/
uint32_t bs_rx_rst_en:1;
uint32_t reserved_25:7;
@ -2050,11 +2009,11 @@ typedef union {
typedef union {
struct {
/** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0;
* Set 0 to reset timer_group0 wdt module
* Set 1 to reset timer_group0 wdt module
*/
uint32_t tg0_wdt_rst_en:1;
/** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 wdt module
* Set 1 to reset timer_group1 wdt module
*/
uint32_t tg1_wdt_rst_en:1;
uint32_t reserved_2:30;
@ -2068,11 +2027,11 @@ typedef union {
typedef union {
struct {
/** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0;
* Set 0 to reset timer_group0 xtal clock domain
* Set 1 to reset timer_group0 xtal clock domain
*/
uint32_t tg0_xtal_rst_en:1;
/** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 xtal clock domain
* Set 1 to reset timer_group1 xtal clock domain
*/
uint32_t tg1_xtal_rst_en:1;
/** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1;
@ -2094,7 +2053,7 @@ typedef union {
*/
uint32_t km_clk_en:1;
/** km_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset km module
* Set 1 to reset km module
*/
uint32_t km_rst_en:1;
/** km_ready : RO; bitpos: [2]; default: 1;
@ -2135,7 +2094,7 @@ typedef union {
*/
uint32_t tcm_mem_monitor_clk_en:1;
/** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset tcm_mem_monitor module
* Set 1 to reset tcm_mem_monitor module
*/
uint32_t tcm_mem_monitor_rst_en:1;
/** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1;
@ -2157,7 +2116,7 @@ typedef union {
*/
uint32_t psram_mem_monitor_clk_en:1;
/** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset psram_mem_monitor module
* Set 1 to reset psram_mem_monitor module
*/
uint32_t psram_mem_monitor_rst_en:1;
/** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1;
@ -2212,6 +2171,24 @@ typedef union {
uint32_t val;
} pcr_hpcore_0_pd_ctrl_reg_t;
/** Type of sdio_slave_conf register
* SDIO_SLAVE configuration register
*/
typedef union {
struct {
/** sdio_slave_clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to enable sdio_slave clock
*/
uint32_t sdio_slave_clk_en:1;
/** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0;
* Set 1 to reset sdio_slave module
*/
uint32_t sdio_slave_rst_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pcr_sdio_slave_conf_reg_t;
/** Type of clock_gate register
* PCR clock gating configure register
*/
@ -2268,7 +2245,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774528;
/** date : R/W; bitpos: [27:0]; default: 2363425;
* PCR version information.
*/
uint32_t date:28;
@ -2370,10 +2347,10 @@ typedef struct {
volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0;
volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1;
volatile pcr_sec_conf_reg_t sec_conf;
volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf;
uint32_t reserved_140;
volatile pcr_bus_clk_update_reg_t bus_clk_update;
volatile pcr_sar_clk_div_reg_t sar_clk_div;
volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf;
uint32_t reserved_14c;
volatile pcr_bs_conf_reg_t bs_conf;
volatile pcr_bs_func_conf_reg_t bs_func_conf;
volatile pcr_bs_pd_ctrl_reg_t bs_pd_ctrl;
@ -2385,7 +2362,8 @@ typedef struct {
volatile pcr_psram_mem_monitor_conf_reg_t psram_mem_monitor_conf;
volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
volatile pcr_hpcore_0_pd_ctrl_reg_t hpcore_0_pd_ctrl;
uint32_t reserved_17c[926];
volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf;
uint32_t reserved_180[925];
volatile pcr_fpga_debug_reg_t fpga_debug;
volatile pcr_clock_gate_reg_t clock_gate;
volatile pcr_date_reg_t date;

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components/soc/esp32c5/register/soc/spi_reg.h
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components/soc/esp32c5/register/soc/spi_struct.h
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docs/docs_not_updated/esp32c5.txt
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@ -23,7 +23,6 @@ api-reference/storage/fatfsgen.rst
api-reference/storage/index.rst
api-reference/storage/nvs_partition_parse.rst
api-reference/peripherals/twai.rst
api-reference/peripherals/spi_features.rst
api-reference/peripherals/touch_pad.rst
api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/index.rst