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Merge branch 'bugfix/rtcio_increase_size_v4.4' into 'release/v4.4'

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sleep: fixed ext1 cannot wakeup via RTCIO >= 18 issue (v4.4)

See merge request espressif/esp-idf!17201
This commit is contained in:
morris
2022-03-02 16:53:05 +08:00
parent ae2a6e40ab 21b80a969f
commit 5f56bbd2d0
3 changed files with 6 additions and 3 deletions
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5
components/esp_hw_support/sleep_modes.c
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@ -140,7 +140,7 @@ typedef struct {
uint64_t sleep_duration;
uint32_t wakeup_triggers : 15;
uint32_t ext1_trigger_mode : 1;
uint32_t ext1_rtc_gpio_mask : 18;
uint32_t ext1_rtc_gpio_mask : 22; //22 is the maximum RTCIO number in all chips
uint32_t ext0_trigger_level : 1;
uint32_t ext0_rtc_gpio_num : 5;
uint32_t gpio_wakeup_mask : 6;
@ -152,6 +152,9 @@ typedef struct {
uint64_t rtc_ticks_at_sleep_start;
} sleep_config_t;
_Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size");
static sleep_config_t s_config = {
.pd_options = {
ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO,

2
components/soc/esp32c3/include/soc/soc_caps.h
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@ -175,7 +175,7 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define SOC_RTCIO_PIN_COUNT (0U)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)

2
components/soc/esp32h2/include/soc/soc_caps.h
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@ -163,7 +163,7 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define SOC_RTCIO_PIN_COUNT (0U)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)