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https://github.com/espressif/esp-idf.git
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Merge branch 'test/parlio_rx_cache_safe_v5.4' into 'release/v5.4'
Reenable parlio rx cache safe test (v5.4) See merge request espressif/esp-idf!38683
This commit is contained in:
@ -321,15 +321,14 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
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ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
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#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
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// malloc unit memory
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uint32_t mem_caps = PARLIO_MEM_ALLOC_CAPS;
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unit = heap_caps_calloc(1, sizeof(parlio_tx_unit_t) + sizeof(parlio_tx_trans_desc_t) * config->trans_queue_depth, mem_caps);
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// allocate unit from internal memory because it contains atomic member
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unit = heap_caps_calloc(1, sizeof(parlio_tx_unit_t) + sizeof(parlio_tx_trans_desc_t) * config->trans_queue_depth, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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ESP_GOTO_ON_FALSE(unit, ESP_ERR_NO_MEM, err, TAG, "no memory for tx unit");
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unit->max_transfer_bits = config->max_transfer_size * 8;
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unit->base.dir = PARLIO_DIR_TX;
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unit->data_width = data_width;
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//create transaction queue
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// create transaction queue
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ESP_GOTO_ON_ERROR(parlio_tx_create_trans_queue(unit, config), err, TAG, "create transaction queue failed");
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// register the unit to a group
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@ -2,11 +2,6 @@ set(srcs "test_app_main.c"
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"test_parlio_rx.c"
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"test_parlio_tx.c")
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# TODO: IDF-7840, semaphore in 'spi_bus_lock.c' is not IRAM safe
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if(CONFIG_PARLIO_ISR_IRAM_SAFE)
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list(REMOVE_ITEM srcs "test_parlio_rx.c")
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endif()
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if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED AND CONFIG_PM_ENABLE)
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list(APPEND srcs "test_parlio_sleep.c")
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endif()
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@ -5,8 +5,8 @@
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*/
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#include <string.h>
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#include <stdatomic.h>
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#include "sdkconfig.h"
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#include "stdatomic.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_check.h"
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@ -29,6 +29,12 @@
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#include "soc/dport_reg.h"
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#endif
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#if CONFIG_SPI_MASTER_ISR_IN_IRAM || CONFIG_SPI_SLAVE_ISR_IN_IRAM
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#define SPI_COMMON_MALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define SPI_COMMON_MALLOC_CAPS (MALLOC_CAP_DEFAULT)
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#endif
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static const char *SPI_TAG = "spi";
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#define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, SPI_TAG, str)
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@ -270,7 +276,7 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma
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#endif
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esp_err_t ret = ESP_OK;
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spi_dma_ctx_t *dma_ctx = (spi_dma_ctx_t *)calloc(1, sizeof(spi_dma_ctx_t));
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spi_dma_ctx_t *dma_ctx = (spi_dma_ctx_t *)heap_caps_calloc(1, sizeof(spi_dma_ctx_t), SPI_COMMON_MALLOC_CAPS);
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if (!dma_ctx) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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@ -825,7 +831,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *
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SPI_CHECK(spi_chan_claimed, "host_id already in use", ESP_ERR_INVALID_STATE);
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//clean and initialize the context
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ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t));
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ctx = (spicommon_bus_context_t *)heap_caps_calloc(1, sizeof(spicommon_bus_context_t), SPI_COMMON_MALLOC_CAPS);
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if (!ctx) {
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err = ESP_ERR_NO_MEM;
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goto cleanup;
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@ -145,6 +145,12 @@ We have two bits to control the interrupt:
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#define SPI_MASTER_ATTR
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#endif
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#if CONFIG_SPI_MASTER_IN_IRAM || CONFIG_SPI_MASTER_ISR_IN_IRAM
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#define SPI_MASTER_MALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define SPI_MASTER_MALLOC_CAPS (MALLOC_CAP_DEFAULT)
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#endif
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#if SOC_PERIPH_CLK_CTRL_SHARED
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#define SPI_MASTER_PERI_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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@ -493,7 +499,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
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}
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//Allocate memory for device
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dev = malloc(sizeof(spi_device_t));
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dev = heap_caps_malloc(sizeof(spi_device_t), SPI_MASTER_MALLOC_CAPS);
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if (dev == NULL) {
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goto nomem;
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}
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@ -156,7 +156,8 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
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spi_chan_claimed = spicommon_periph_claim(host, "spi slave");
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SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
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spihost[host] = malloc(sizeof(spi_slave_t));
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// spi_slave_t contains atomic variable, memory must be allocated from internal memory
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spihost[host] = heap_caps_malloc(sizeof(spi_slave_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (spihost[host] == NULL) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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@ -585,7 +585,7 @@ SPI_BUS_LOCK_ISR_ATTR static inline esp_err_t dev_wait(spi_bus_lock_dev_t *dev_h
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******************************************************************************/
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esp_err_t spi_bus_init_lock(spi_bus_lock_handle_t *out_lock, const spi_bus_lock_config_t *config)
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{
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spi_bus_lock_t* lock = (spi_bus_lock_t*)calloc(1, sizeof(spi_bus_lock_t));
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spi_bus_lock_t* lock = (spi_bus_lock_t*)heap_caps_calloc(1, sizeof(spi_bus_lock_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (lock == NULL) {
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return ESP_ERR_NO_MEM;
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}
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@ -648,7 +648,7 @@ esp_err_t spi_bus_lock_register_dev(spi_bus_lock_handle_t lock, spi_bus_lock_dev
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if (dev_lock == NULL) {
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return ESP_ERR_NO_MEM;
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}
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dev_lock->semphr = xSemaphoreCreateBinary();
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dev_lock->semphr = xSemaphoreCreateBinaryWithCaps(MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (dev_lock->semphr == NULL) {
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free(dev_lock);
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atomic_store(&lock->dev[id], (intptr_t)NULL);
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@ -676,7 +676,7 @@ void spi_bus_lock_unregister_dev(spi_bus_lock_dev_handle_t dev_handle)
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atomic_store(&lock->dev[id], (intptr_t)NULL);
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if (dev_handle->semphr) {
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vSemaphoreDelete(dev_handle->semphr);
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vSemaphoreDeleteWithCaps(dev_handle->semphr);
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}
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free(dev_handle);
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@ -819,7 +819,7 @@ SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_clear_req(spi_bus_lock_dev_t *dev_han
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}
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SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_check_dev_acq(spi_bus_lock_t *lock,
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spi_bus_lock_dev_handle_t *out_dev_lock)
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spi_bus_lock_dev_handle_t *out_dev_lock)
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{
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BUS_LOCK_DEBUG_EXECUTE_CHECK(!lock->acquiring_dev);
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uint32_t status = lock_status_fetch(lock);
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@ -1,2 +1,2 @@
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
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@ -1,2 +1,2 @@
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| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
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| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
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