espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-07-29 18:27:20 +02:00
Code Issues Packages Projects Releases Wiki Activity

fix(esp_system): fix possible cache_error by another core accessing flash in esp_restart

Browse Source
This commit is contained in:
wuzhenghui
2025-03-06 21:02:37 +08:00
parent 72c031513a
commit 73d9cb3517
1 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
components/esp_system/port/soc/esp32s3/system_internal.c
View File

@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -102,10 +102,6 @@ void IRAM_ATTR esp_restart_noos(void)
}
#endif
// Disable cache
Cache_Disable_ICache();
Cache_Disable_DCache();
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
@ -117,6 +113,10 @@ void IRAM_ATTR esp_restart_noos(void)
esp_cpu_stall(other_core_id);
#endif
// Disable cache
Cache_Disable_ICache();
Cache_Disable_DCache();
// 2nd stage bootloader reconfigures SPI flash signals.
// Reset them to the defaults expected by ROM.
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);