espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-07-30 18:57:19 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/fix_esp32c61_eco2_ble_light_sleep_issue_v5.4' into 'release/v5.4'

Browse Source 
fix(ble): fix rtc freq div error on esp32c61 (v5.4)

See merge request espressif/esp-idf!36601
This commit is contained in:
Island
2025-01-26 14:26:02 +08:00
parent 649f9a72ae 4300c344ca
commit 998e365a61
1 changed files with 4 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/bt/controller/esp32c6/bt.c
View File

@ -522,12 +522,16 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
switch (slow_clk_src) { switch (slow_clk_src) {
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source"); ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
uint32_t chip_version = efuse_hal_chip_revision(); uint32_t chip_version = efuse_hal_chip_revision();
if (chip_version == 0) { if (chip_version == 0) {
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1)); modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
} else{ } else{
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1)); modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
} }
#else
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
#endif // SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
break; break;
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!"); ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");