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Merge branch 'feat/c61_eco3_soc_update' into 'master'

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feat(soc): c61 eco3 rom and soc header update

See merge request espressif/esp-idf!39166
This commit is contained in:
morris
2025-05-28 12:19:26 +08:00
parent e0c43e6e7c 6fde8cf8d2
commit bb9fbc040e
188 changed files with 29716 additions and 11319 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c
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@ -81,7 +81,9 @@ bool clock_domain_pd_allowed(void)
* necessary to check the state of CLOCK_MODEM to determine MODEM domain on
* or off. The clock and reset of digital peripherals are managed through
* PCR, with TOP domain similar to MODEM domain. */
#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED
sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } };
#endif
#if SOC_WIFI_SUPPORTED
modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32);
modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32);

14
components/esp_hw_support/port/esp32c61/Kconfig.hw_support
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@ -1,6 +1,6 @@
choice ESP32C61_REV_MIN
prompt "Minimum Supported ESP32-C61 Revision"
default ESP32C61_REV_MIN_0
default ESP32C61_REV_MIN_100
help
Required minimum chip revision. ESP-IDF will check for it and
reject to boot if the chip revision fails the check.
@ -9,13 +9,13 @@ choice ESP32C61_REV_MIN
The complied binary will only support chips above this revision,
this will also help to reduce binary size.
config ESP32C61_REV_MIN_0
bool "Rev v0.0"
config ESP32C61_REV_MIN_100
bool "Rev v1.0"
endchoice
config ESP32C61_REV_MIN_FULL
int
default 0 if ESP32C61_REV_MIN_0
default 100 if ESP32C61_REV_MIN_100
config ESP_REV_MIN_FULL
int
@ -25,7 +25,7 @@ config ESP_REV_MIN_FULL
# MAX Revision
#
comment "Maximum Supported ESP32-C61 Revision (Rev v0.99)"
comment "Maximum Supported ESP32-C61 Revision (Rev v1.99)"
# Maximum revision that IDF supports.
# It can not be changed by user.
# Only Espressif can change it when a new version will be supported in IDF.
@ -33,7 +33,7 @@ config ESP_REV_MIN_FULL
config ESP32C61_REV_MAX_FULL
int
default 99
default 199
# keep in sync the "Maximum Supported Revision" description with this value
config ESP_REV_MAX_FULL
@ -53,6 +53,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL
config ESP_EFUSE_BLOCK_REV_MAX_FULL
int
default 99
default 199
comment "Maximum Supported ESP32-C61 eFuse Block Revision (eFuse Block Rev v0.99)"
# The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL

4
components/esp_rom/CMakeLists.txt
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@ -67,10 +67,6 @@ if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBAC
list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c")
endif()
if(CONFIG_ESP_ROM_CACHE_WB_INVLD_LOW_RANGE)
list(APPEND sources "patches/esp_rom_cache_esp32c61.c")
endif()
if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG)
list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
endif()

4
components/esp_rom/esp32c61/Kconfig.soc_caps.in
View File

@ -107,10 +107,6 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
bool
default y
config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE
bool
default y
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y

1
components/esp_rom/esp32c61/esp_rom_caps.h
View File

@ -32,5 +32,4 @@
#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions
#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.

12
components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld
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@ -1,14 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c61.rom.coexist.ld for esp32c61
*
*
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
*
* Compatible with ROM where ECO version equal or greater to 0.
/* ROM function interface
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -35,7 +31,7 @@ coex_hw_timer_set = 0x40000a64;
coex_schm_interval_set = 0x40000a68;
coex_schm_lock = 0x40000a6c;
coex_schm_unlock = 0x40000a70;
/*coex_status_get = 0x40000a74;*/
coex_status_get = 0x40000a74;
coex_wifi_release = 0x40000a78;
esp_coex_ble_conn_dynamic_prio_get = 0x40000a7c;
/* Data (.data, .bss, .rodata) */

74
components/esp_rom/esp32c61/ld/esp32c61.rom.ld
View File

@ -1,14 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c61.rom.ld for esp32c61
*
*
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
*
* Compatible with ROM where ECO version equal or greater to 0.
/* ROM function interface
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -54,8 +50,6 @@ software_reset_cpu = 0x40000098;
ets_clk_assist_debug_clock_enable = 0x4000009c;
clear_super_wdt_reset_flag = 0x400000a0;
disable_default_watchdog = 0x400000a4;
esp_rom_set_rtc_wake_addr = 0x400000a8;
esp_rom_get_rtc_wake_addr = 0x400000ac;
send_packet = 0x400000b0;
recv_packet = 0x400000b4;
GetUartDevice = 0x400000b8;
@ -192,9 +186,9 @@ MMU_Set_Page_Mode = 0x40000624;
MMU_Get_Page_Mode = 0x40000628;
Cache_Sync_Items = 0x4000062c;
Cache_Op_Addr = 0x40000630;
/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */
Cache_Invalidate_Addr = 0x40000634;
Cache_Clean_Addr = 0x40000638;
/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */
Cache_WriteBack_Addr = 0x4000063c;
Cache_WriteBack_Invalidate_Addr = 0x40000640;
Cache_Invalidate_All = 0x40000644;
Cache_Clean_All = 0x40000648;
@ -369,7 +363,6 @@ ets_efuse_jtag_disabled = 0x400007fc;
ets_efuse_usb_print_is_disabled = 0x40000800;
ets_efuse_usb_download_mode_disabled = 0x40000804;
ets_efuse_usb_device_disabled = 0x40000808;
ets_efuse_secure_boot_fast_wake_enabled = 0x4000080c;
/***************************************
@ -393,3 +386,60 @@ usb_serial_device_rx_one_char = 0x40000a20;
usb_serial_device_rx_one_char_block = 0x40000a24;
usb_serial_device_tx_flush = 0x40000a28;
usb_serial_device_tx_one_char = 0x40000a2c;
/***************************************
Group lldesc
***************************************/
/* Functions */
lldesc_build_chain = 0x400014dc;
/***************************************
Group sip
***************************************/
/* Functions */
sip_after_tx_complete = 0x400014e0;
sip_alloc_to_host_evt = 0x400014e4;
sip_download_begin = 0x400014e8;
sip_get_ptr = 0x400014ec;
sip_get_state = 0x400014f0;
sip_init_attach = 0x400014f4;
sip_install_rx_ctrl_cb = 0x400014f8;
sip_install_rx_data_cb = 0x400014fc;
sip_is_active = 0x40001500;
sip_post_init = 0x40001504;
sip_reclaim_from_host_cmd = 0x40001508;
sip_reclaim_tx_data_pkt = 0x4000150c;
sip_send = 0x40001510;
sip_to_host_chain_append = 0x40001514;
sip_to_host_evt_send_done = 0x40001518;
/***************************************
Group slc
***************************************/
/* Functions */
slc_add_credits = 0x4000151c;
slc_enable = 0x40001520;
slc_from_host_chain_fetch = 0x40001524;
slc_from_host_chain_recycle = 0x40001528;
slc_has_pkt_to_host = 0x4000152c;
slc_init_attach = 0x40001530;
slc_init_credit = 0x40001534;
slc_reattach = 0x40001538;
slc_send_to_host_chain = 0x4000153c;
slc_set_host_io_max_window = 0x40001540;
slc_to_host_chain_recycle = 0x40001544;
/***************************************
Group recovery_bootloader
***************************************/
/* Functions */
ets_get_bootloader_offset = 0x40001548;
ets_set_bootloader_offset = 0x4000154c;

16
components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
View File

@ -1,14 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c61.rom.net80211.ld for esp32c61
*
*
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
*
* Compatible with ROM where ECO version equal or greater to 0.
/* ROM function interface
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -40,7 +36,7 @@ ieee80211_encap_esfbuf = 0x40000ac8;
ieee80211_is_tx_allowed = 0x40000acc;
ieee80211_output_pending_eb = 0x40000ad0;
ieee80211_output_process = 0x40000ad4;
/*ieee80211_set_tx_desc = 0x40000ad8;*/
ieee80211_set_tx_desc = 0x40000ad8;
ieee80211_classify = 0x40000adc;
ieee80211_copy_eb_header = 0x40000ae0;
ieee80211_recycle_cache_eb = 0x40000ae4;
@ -60,12 +56,12 @@ ieee80211_find_ext_elem = 0x40000b18;
ieee80211_find_ie = 0x40000b1c;
ieee80211_find_ext_ie = 0x40000b20;
ieee80211_merge_mbssid_profile = 0x40000b24;
/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/
ieee80211_encap_esfbuf_htc = 0x40000b28;
wifi_get_macaddr = 0x40000b2c;
wifi_rf_phy_disable = 0x40000b30;
wifi_rf_phy_enable = 0x40000b34;
wifi_is_started = 0x40000b38;
/*sta_input = 0x40000b3c;*/
sta_input = 0x40000b3c;
sta_rx_eapol = 0x40000b40;
sta_reset_beacon_timeout = 0x40000b44;
sta_get_beacon_timeout = 0x40000b48;

289
components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld
View File

@ -21,293 +21,8 @@
phy_param_addr = 0x4000104c;
chip762_phyrom_version = 0x40001050;
chip762_phyrom_version_num = 0x40001054;
phy_get_rc_dout = 0x40001058;
phy_rc_cal = 0x4000105c;
phy_abs_temp = 0x40001060;
phy_set_chan_cal_interp = 0x40001064;
phy_loopback_mode_en = 0x40001068;
phy_get_data_sat = 0x4000106c;
phy_byte_to_word = 0x40001070;
phy_bb_bss_cbw40 = 0x40001074;
phy_set_chan_reg = 0x40001078;
phy_i2c_master_reset = 0x4000107c;
phy_chan14_mic_enable = 0x40001080;
phy_chan14_mic_cfg = 0x40001084;
phy_freq_module_resetn = 0x40001088;
phy_freq_chan_en_sw = 0x4000108c;
phy_write_chan_freq = 0x40001090;
phy_get_freq_mem_param = 0x40001094;
phy_get_freq_mem_addr = 0x40001098;
phy_wr_rf_freq_mem = 0x4000109c;
phy_read_rf_freq_mem = 0x400010a0;
phy_freq_i2c_mem_write = 0x400010a4;
phy_freq_reg_init = 0x400010a8;
phy_freq_num_get_data = 0x400010ac;
phy_freq_i2c_num_addr = 0x400010b0;
phy_freq_i2c_write_set = 0x400010b4;
phy_pll_dac_mem_update = 0x400010b8;
phy_pll_cap_mem_update = 0x400010bc;
phy_get_rf_freq_cap = 0x400010c0;
phy_get_rf_freq_init = 0x400010c4;
phy_freq_get_i2c_data = 0x400010c8;
phy_freq_i2c_data_write = 0x400010cc;
phy_set_chan_freq_hw_init = 0x400010d0;
phy_en_hw_set_freq = 0x400010d4;
phy_dis_hw_set_freq = 0x400010d8;
phy_wait_freq_set_busy = 0x400010dc;
phy_set_chan_freq_sw_start = 0x400010e0;
phy_wait_i2c_sdm_stable = 0x400010e4;
phy_reg_init = 0x400010e8;
phy_xpd_rf = 0x400010ec;
phy_close_rf = 0x400010f0;
phy_get_mac_addr = 0x400010f4;
phy_set_mac_data = 0x400010f8;
phy_rfcal_data_sub = 0x400010fc;
phy_rf_cal_data_recovery = 0x40001100;
phy_rf_cal_data_backup = 0x40001104;
phy_rfcal_data_check = 0x40001108;
phy_pwdet_reg_init = 0x4000110c;
phy_pwdet_sar2_init = 0x40001110;
phy_en_pwdet = 0x40001114;
phy_get_sar_sig_ref = 0x40001118;
phy_pwdet_tone_start = 0x4000111c;
phy_get_tone_sar_dout = 0x40001120;
phy_get_fm_sar_dout = 0x40001124;
phy_txtone_linear_pwr = 0x40001128;
phy_linear_to_db = 0x4000112c;
phy_get_power_db = 0x40001130;
phy_meas_tone_pwr_db = 0x40001134;
phy_pwdet_wait_idle = 0x40001138;
phy_pkdet_vol_start = 0x4000113c;
phy_read_sar_dout = 0x40001140;
phy_read_sar2_code = 0x40001144;
phy_get_sar2_vol = 0x40001148;
phy_get_pll_vol = 0x4000114c;
phy_tx_pwctrl_bg_init = 0x40001150;
phy_set_most_tpw = 0x40001154;
phy_get_most_tpw = 0x40001158;
phy_tx_state_out = 0x4000115c;
phy_ant_dft_cfg = 0x40001160;
phy_ant_wifitx_cfg = 0x40001164;
phy_ant_wifirx_cfg = 0x40001168;
phy_ant_bttx_cfg = 0x4000116c;
phy_ant_btrx_cfg = 0x40001170;
phy_chan_dump_cfg = 0x40001174;
phy_enable_low_rate = 0x40001178;
phy_disable_low_rate = 0x4000117c;
phy_is_low_rate_enabled = 0x40001180;
phy_dig_reg_backup = 0x40001184;
phy_chan_filt_set = 0x40001188;
phy_rx11blr_cfg = 0x4000118c;
phy_set_cca = 0x40001190;
phy_set_rx_sense = 0x40001194;
phy_rx_gain_force = 0x40001198;
phy_mhz2ieee = 0x4000119c;
phy_chan_to_freq = 0x400011a0;
phy_restart_cal = 0x400011a4;
phy_write_rfpll_sdm = 0x400011a8;
phy_wait_rfpll_cal_end = 0x400011ac;
phy_rfpll_set_freq = 0x400011b0;
phy_set_rf_freq_offset = 0x400011b4;
phy_set_rfpll_freq = 0x400011b8;
phy_set_channel_rfpll_freq = 0x400011bc;
phy_rfpll_cap_correct = 0x400011c0;
phy_rfpll_cap_init_cal = 0x400011c4;
phy_set_freq = 0x400011c8;
phy_write_pll_cap = 0x400011cc;
phy_read_pll_cap = 0x400011d0;
phy_chip_set_chan_misc = 0x400011d4;
phy_freq_set_reg = 0x400011d8;
phy_rfpll_chgp_cal = 0x400011dc;
phy_gen_rx_gain_table = 0x400011e0;
phy_get_rxbb_dc = 0x400011e4;
phy_wr_rx_gain_mem = 0x400011e8;
phy_rfpll_cap_track = 0x400011ec;
phy_param_track = 0x400011f0;
phy_txpwr_correct = 0x400011f4;
phy_txpwr_cal_track = 0x400011f8;
phy_bt_track_tx_power = 0x400011fc;
phy_wifi_track_tx_power = 0x40001200;
phy_bt_txdc_cal = 0x40001204;
phy_bt_txiq_cal = 0x40001208;
phy_txdc_cal_pwdet = 0x4000120c;
phy_txdc_cal = 0x40001210;
phy_txiq_get_mis_pwr = 0x40001214;
phy_txiq_cover = 0x40001218;
phy_rfcal_txiq = 0x4000121c;
phy_get_power_atten = 0x40001220;
phy_pwdet_ref_code = 0x40001224;
phy_pwdet_code_cal = 0x40001228;
phy_rfcal_txcap = 0x4000122c;
phy_tx_cap_init = 0x40001230;
phy_rfcal_pwrctrl = 0x40001234;
phy_tx_pwctrl_init_cal = 0x40001238;
phy_tx_pwctrl_init = 0x4000123c;
phy_bt_tx_pwctrl_init = 0x40001240;
phy_i2c_enter_critical_ = 0x40001244;
phy_i2c_exit_critical_ = 0x40001248;
phy_i2c_clk_sel = 0x4000124c;
phy_get_i2c_read_mask_ = 0x40001250;
phy_get_i2c_mst0_mask = 0x40001254;
phy_get_i2c_hostid_ = 0x40001258;
phy_chip_i2c_readReg_org = 0x4000125c;
phy_chip_i2c_readReg = 0x40001260;
phy_i2c_paral_set_mst0 = 0x40001264;
phy_i2c_paral_set_read = 0x40001268;
phy_i2c_paral_read = 0x4000126c;
phy_i2c_paral_write = 0x40001270;
phy_i2c_paral_write_num = 0x40001274;
phy_i2c_paral_write_mask = 0x40001278;
phy_i2c_readReg = 0x4000127c;
phy_chip_i2c_writeReg = 0x40001280;
phy_i2c_writeReg = 0x40001284;
phy_i2c_readReg_Mask = 0x40001288;
phy_i2c_writeReg_Mask = 0x4000128c;
phy_set_txcap_reg = 0x40001290;
phy_i2c_sar2_init_code = 0x40001294;
phy_test_filter_band_set = 0x40001298;
phy_filter_dcap_set = 0x4000129c;
phy_i2c_init1 = 0x400012a0;
phy_i2c_init2 = 0x400012a4;
phy_bias_reg_set = 0x400012a8;
phy_i2c_rc_cal_set = 0x400012ac;
phy_i2c_bbpll_set = 0x400012b0;
phy_adc_rate_set = 0x400012b4;
phy_dac_rate_set = 0x400012b8;
phy_encode_i2c_master = 0x400012bc;
phy_i2c_master_fill = 0x400012c0;
phy_i2c_master_mem_txcap = 0x400012c4;
/* phy_i2c_master_cmd_mem_init = 0x400012c8; */
/* phy_i2c_master_mem_cfg = 0x400012cc; */
phy_pbus_force_mode = 0x400012d0;
phy_pbus_rd_addr = 0x400012d4;
phy_pbus_rd_shift = 0x400012d8;
phy_pbus_force_test = 0x400012dc;
phy_pbus_rd = 0x400012e0;
phy_pbus_debugmode = 0x400012e4;
phy_pbus_workmode = 0x400012e8;
phy_pbus_set_rxgain = 0x400012ec;
phy_pbus_xpd_rx_off = 0x400012f0;
phy_pbus_xpd_rx_on = 0x400012f4;
phy_pbus_xpd_tx_off = 0x400012f8;
phy_pbus_xpd_tx_on = 0x400012fc;
phy_pbus_set_dco = 0x40001300;
phy_set_loopback_gain = 0x40001304;
phy_txcal_debuge_mode_ = 0x40001308;
phy_txcal_work_mode = 0x4000130c;
phy_pbus_clear_reg = 0x40001310;
phy_save_pbus_reg = 0x40001314;
phy_write_pbus_mem = 0x40001318;
phy_set_pbus_mem = 0x4000131c;
phy_disable_agc = 0x40001320;
phy_enable_agc = 0x40001324;
phy_disable_cca = 0x40001328;
phy_enable_cca = 0x4000132c;
phy_write_gain_mem = 0x40001330;
phy_bb_bss_cbw40_dig = 0x40001334;
phy_mac_tx_chan_offset = 0x40001338;
phy_rx_11b_opt = 0x4000133c;
phy_tx_paon_set = 0x40001340;
phy_i2cmst_reg_init = 0x40001344;
phy_bt_gain_offset = 0x40001348;
phy_fe_reg_init = 0x4000134c;
phy_mac_enable_bb = 0x40001350;
phy_bb_wdg_cfg = 0x40001354;
phy_fe_txrx_reset = 0x40001358;
phy_set_rx_comp_ = 0x4000135c;
phy_agc_reg_init = 0x40001360;
phy_btbb_wifi_bb_cfg2 = 0x40001364;
phy_bb_reg_init = 0x40001368;
phy_open_i2c_xpd = 0x4000136c;
phy_force_txrx_off = 0x40001370;
phy_txiq_set_reg = 0x40001374;
phy_rxiq_set_reg = 0x40001378;
phy_set_txclk_en = 0x4000137c;
phy_set_rxclk_en = 0x40001380;
phy_start_tx_tone_step = 0x40001384;
phy_stop_tx_tone = 0x40001388;
phy_bb_wdg_test_en = 0x4000138c;
phy_noise_floor_auto_set = 0x40001390;
phy_read_hw_noisefloor = 0x40001394;
phy_iq_corr_enable = 0x40001398;
phy_wifi_agc_sat_gain = 0x4000139c;
phy_bbpll_cal = 0x400013a0;
phy_ant_init = 0x400013a4;
phy_wifi_fbw_sel = 0x400013a8;
phy_bt_filter_reg = 0x400013ac;
phy_rx_sense_set = 0x400013b0;
phy_tx_state_set = 0x400013b4;
phy_close_pa = 0x400013b8;
phy_freq_correct = 0x400013bc;
phy_set_pbus_reg = 0x400013c0;
phy_wifi_rifs_mode_en = 0x400013c4;
phy_nrx_freq_set = 0x400013c8;
phy_fe_adc_on = 0x400013cc;
phy_force_pwr_index = 0x400013d0;
phy_fft_scale_force = 0x400013d4;
phy_force_rx_gain = 0x400013d8;
phy_wifi_enable_set = 0x400013dc;
phy_bb_wdt_rst_enable = 0x400013e0;
phy_bb_wdt_int_enable = 0x400013e4;
phy_bb_wdt_timeout_clear = 0x400013e8;
phy_bb_wdt_get_status = 0x400013ec;
phy_iq_est_enable = 0x400013f0;
phy_iq_est_disable = 0x400013f4;
phy_dc_iq_est = 0x400013f8;
phy_set_cal_rxdc = 0x400013fc;
phy_rxiq_get_mis = 0x40001400;
phy_rxiq_cover_mg_mp = 0x40001404;
phy_rfcal_rxiq = 0x40001408;
phy_get_rfcal_rxiq_data = 0x4000140c;
phy_get_dco_comp = 0x40001410;
phy_pbus_rx_dco_cal = 0x40001414;
phy_rxdc_est_min = 0x40001418;
phy_pbus_rx_dco_cal_1step = 0x4000141c;
phy_get_iq_value = 0x40001420;
phy_set_lb_txiq = 0x40001424;
phy_set_rx_gain_cal_iq = 0x40001428;
phy_set_rx_gain_cal_dc = 0x4000142c;
phy_spur_reg_write_one_tone = 0x40001430;
phy_spur_cal = 0x40001434;
phy_spur_coef_cfg = 0x40001438;
phy_bb_gain_index = 0x4000143c;
phy_rfrx_gain_index = 0x40001440;
phy_set_tsens_power_ = 0x40001444;
phy_set_tsens_range_ = 0x40001448;
phy_get_tsens_value_ = 0x4000144c;
phy_tsens_read_init = 0x40001450;
phy_code_to_temp = 0x40001454;
phy_tsens_dac_to_index = 0x40001458;
phy_tsens_dac_cal = 0x4000145c;
phy_tsens_code_read = 0x40001460;
phy_tsens_temp_read = 0x40001464;
phy_tsens_temp_read_local = 0x40001468;
phy_temp_to_power = 0x4000146c;
phy_txbbgain_to_index = 0x40001470;
phy_index_to_txbbgain = 0x40001474;
phy_bt_index_to_bb = 0x40001478;
phy_bt_bb_to_index = 0x4000147c;
phy_bt_get_tx_gain = 0x40001480;
phy_dig_gain_check = 0x40001484;
phy_wifi_get_tx_gain = 0x40001488;
phy_wifi_11g_rate_chg = 0x4000148c;
phy_set_tx_gain_mem = 0x40001490;
phy_get_rate_fcc_index = 0x40001494;
phy_get_chan_target_power = 0x40001498;
phy_get_tx_gain_value = 0x4000149c;
phy_wifi_get_target_power = 0x400014a0;
phy_wifi_get_tx_tab_ = 0x400014a4;
phy_wifi_set_tx_gain = 0x400014a8;
phy_bt_get_tx_tab_ = 0x400014ac;
phy_bt_set_tx_gain = 0x400014b0;
phy_bt_tx_gain_init = 0x400014b4;
phy_rate_to_index = 0x400014b8;
phy_get_target_pwr = 0x400014bc;
phy_get_max_pwr = 0x400014c0;
phy_get_pwr_index = 0x400014c4;
phy_chip_set_chan_ana = 0x400014d4;
phy_get_romfuncs = 0x400014d8;
/* Data (.data, .bss, .rodata) */
phy_param_rom = 0x4084fc6c;
rom_phyFuns = 0x4084fb84;
rom_phyFuns = 0x4084fc68;
rom_phyFuns_eco2 = 0x4084fc68;

99
components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
View File

@ -1,14 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c61.rom.pp.ld for esp32c61
*
*
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
*
* Compatible with ROM where ECO version equal or greater to 0.
/* ROM function interface
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -27,14 +23,14 @@ esf_buf_recycle = 0x40000b64;
GetAccess = 0x40000b68;
hal_mac_is_low_rate_enabled = 0x40000b6c;
hal_mac_tx_get_blockack = 0x40000b70;
/*hal_mac_tx_set_ppdu = 0x40000b74;*/
hal_mac_tx_set_ppdu = 0x40000b74;
hal_mac_tx_clr_mplen = 0x40000b78;
hal_mac_get_txq_state = 0x40000b7c;
hal_mac_clr_txq_state = 0x40000b80;
hal_mac_get_txq_complete = 0x40000b84;
hal_mac_deinit_twt_tx = 0x40000b88;
hal_mac_is_dma_enable = 0x40000b8c;
/*hal_he_get_bss_color = 0x40000b90;*/
hal_he_get_bss_color = 0x40000b90;
hal_he_set_ersu = 0x40000b94;
hal_he_get_mplen_addr_start = 0x40000b98;
hal_he_get_mplen_addr_end = 0x40000b9c;
@ -53,11 +49,6 @@ hal_tsf_get_tbttstart = 0x40000bcc;
hal_get_tsf_time = 0x40000bd0;
hal_get_sta_tsf = 0x40000bd4;
tsf_hal_get_tbtt_interval = 0x40000bd8;
tsf_hal_get_time = 0x400014cc;
/*pm_get_tbtt_count = 0x400014c8;*/
tsf_hal_get_counter_value = 0x400014d0;
dbg_hal_check_clr_mplen_bitmap = 0x40000bdc;
dbg_hal_check_set_mplen_bitmap = 0x40000be0;
ic_get_trc = 0x40000be4;
ic_mac_deinit = 0x40000be8;
ic_mac_init = 0x40000bec;
@ -81,7 +72,7 @@ lmacRecycleMPDU = 0x40000c30;
lmacRxDone = 0x40000c34;
lmacSetTxFrame = 0x40000c38;
lmacTxDone = 0x40000c3c;
/*lmacTxFrame = 0x40000c40;*/
lmacTxFrame = 0x40000c40;
lmacDisableTransmit = 0x40000c44;
lmacDiscardFrameExchangeSequence = 0x40000c48;
lmacProcessCollision = 0x40000c4c;
@ -105,7 +96,7 @@ mac_tx_set_plcp1 = 0x40000c90;
mac_tx_set_plcp2 = 0x40000c94;
mac_tx_set_len = 0x40000c98;
mac_tx_set_htsig = 0x40000c9c;
/*mac_tx_set_hesig = 0x40000ca0;*/
mac_tx_set_hesig = 0x40000ca0;
mac_tx_set_tb = 0x40000ca4;
mac_tx_set_mplen = 0x40000ca8;
mac_tx_set_txop_q = 0x40000cac;
@ -116,14 +107,14 @@ pm_disable_sleep_delay_timer = 0x40000cbc;
pm_dream = 0x40000cc0;
pm_mac_wakeup = 0x40000cc4;
pm_mac_sleep = 0x40000cc8;
/*pm_enable_active_timer = 0x40000ccc;*/
pm_enable_active_timer = 0x40000ccc;
pm_enable_sleep_delay_timer = 0x40000cd0;
pm_local_tsf_process = 0x40000cd4;
//pm_set_beacon_filter = 0x40000cd8;
/*pm_is_in_wifi_slice_threshold = 0x40000cdc;*/
pm_set_beacon_filter = 0x40000cd8;
pm_is_in_wifi_slice_threshold = 0x40000cdc;
pm_is_waked = 0x40000ce0;
//pm_keep_alive = 0x40000ce4;
/*pm_on_beacon_rx = 0x40000ce8;*/
pm_keep_alive = 0x40000ce4;
pm_on_beacon_rx = 0x40000ce8;
pm_on_data_rx = 0x40000cec;
pm_on_data_tx = 0x40000cf0;
pm_on_tbtt = 0x40000cf4;
@ -133,38 +124,38 @@ pm_on_isr_set_twt_target = 0x40000d00;
pm_on_isr_twt_wake = 0x40000d04;
pm_on_tsf_timer = 0x40000d08;
pm_on_twt_force_tx = 0x40000d0c;
/*pm_parse_beacon = 0x40000d10;*/
/*pm_process_tim = 0x40000d14;*/
pm_parse_beacon = 0x40000d10;
pm_process_tim = 0x40000d14;
pm_rx_beacon_process = 0x40000d18;
pm_rx_data_process = 0x40000d1c;
pm_sleep = 0x40000d20;
pm_sleep_for = 0x40000d24;
/*pm_tbtt_process = 0x40000d28;*/
pm_tbtt_process = 0x40000d28;
pm_tx_data_done_process = 0x40000d2c;
pm_allow_tx = 0x40000d30;
pm_extend_tbtt_adaptive_servo = 0x40000d34;
pm_scale_listen_interval = 0x40000d38;
pm_parse_mbssid_element = 0x40000d3c;
pm_disconnected_wake = 0x40000d40;
/*pm_tx_data_process = 0x40000d44;*/
pm_tx_data_process = 0x40000d44;
pm_is_twt_awake = 0x40000d48;
pm_enable_twt_keep_alive = 0x40000d4c;
pm_twt_on_tsf_timer = 0x40000d50;
/*pm_twt_process = 0x40000d54;*/
pm_twt_process = 0x40000d54;
pm_is_twt_start = 0x40000d58;
pm_twt_set_target_wdev_time = 0x40000d5c;
pm_twt_set_target_tsf = 0x40000d60;
pm_enable_twt_keep_alive_timer = 0x40000d64;
/*pm_mac_try_enable_modem_state = 0x40000d68;*/
pm_mac_try_enable_modem_state = 0x40000d68;
pm_beacon_monitor_tbtt_timeout_process = 0x40000d6c;
pm_update_next_tbtt = 0x40000d70;
pm_twt_disallow_tx = 0x40000d74;
pm_clear_wakeup_signal = 0x40000d78;
/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;
//pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
//pm_mac_modem_params_rt_update = 0x40000d8c;*/
pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
pm_mac_modem_params_rt_update = 0x40000d8c;
pm_update_at_next_beacon = 0x40000d90;
pm_get_null_max_tx_time = 0x40000d94;
pm_coex_schm_overall_period_get = 0x40000d98;
@ -184,17 +175,17 @@ ppEmptyDelimiterLength = 0x40000dcc;
ppEnqueueRxq = 0x40000dd0;
ppEnqueueTxDone = 0x40000dd4;
ppGetTxframe = 0x40000dd8;
/*ppMapTxQueue = 0x40000ddc;*/
ppMapTxQueue = 0x40000ddc;
ppProcTxSecFrame = 0x40000de0;
ppProcessRxPktHdr = 0x40000de4;
/*ppProcessTxQ = 0x40000de8;*/
ppProcessTxQ = 0x40000de8;
ppRecordBarRRC = 0x40000dec;
ppRecycleAmpdu = 0x40000df0;
ppRecycleRxPkt = 0x40000df4;
ppResortTxAMPDU = 0x40000df8;
ppResumeTxAMPDU = 0x40000dfc;
ppRxFragmentProc = 0x40000e00;
/*ppRxPkt = 0x40000e04;*/
ppRxPkt = 0x40000e04;
ppRxProtoProc = 0x40000e08;
ppSearchTxQueue = 0x40000e0c;
ppSearchTxframe = 0x40000e10;
@ -214,7 +205,7 @@ ppMapWaitTxq = 0x40000e44;
ppProcessWaitingQueue = 0x40000e48;
ppDisableQueue = 0x40000e4c;
ppCheckTxRTS = 0x40000e50;
/*ppProcessLifeTime = 0x40000e54;*/
ppProcessLifeTime = 0x40000e54;
ppProcTxCallback = 0x40000e58;
ppCalPreFecPaddingFactor = 0x40000e5c;
ppCalDeliNum = 0x40000e60;
@ -228,7 +219,7 @@ pp_coex_tx_release = 0x40000e7c;
ppAdd2AMPDUTail = 0x40000e80;
ppDirectRecycleAmpdu = 0x40000e84;
ppRegressAmpdu = 0x40000e88;
/*pp_timer_do_process = 0x40000e8c;*/
pp_timer_do_process = 0x40000e8c;
rcGetAmpduSched = 0x40000e90;
rcUpdateRxDone = 0x40000e94;
rc_get_trc = 0x40000e98;
@ -238,7 +229,7 @@ rcampduuprate = 0x40000ea4;
rcClearCurAMPDUSched = 0x40000ea8;
rcClearCurSched = 0x40000eac;
rcClearCurStat = 0x40000eb0;
/* rcGetSched = 0x40000eb4;*/
rcGetSched = 0x40000eb4;
rcLowerSched = 0x40000eb8;
rcSetTxAmpduLimit = 0x40000ebc;
rcTxUpdatePer = 0x40000ec0;
@ -278,7 +269,7 @@ wdev_mac_special_reg_store = 0x40000f44;
wdev_mac_wakeup = 0x40000f48;
wdev_mac_sleep = 0x40000f4c;
wDev_ProcessFiq = 0x40000f50;
/*wDev_ProcessRxSucData = 0x40000f54;*/
wDev_ProcessRxSucData = 0x40000f54;
wdevProcessRxSucDataAll = 0x40000f58;
wdev_csi_len_align = 0x40000f5c;
wDev_IndicateBeaconMemoryFrame = 0x40000f60;
@ -290,8 +281,6 @@ wdev_process_tsf_timer = 0x40000f74;
wdev_process_beacon_filter = 0x40000f78;
wdev_process_mac_modem_beacon_miss = 0x40000f7c;
config_is_cache_tx_buf_enabled = 0x40000f80;
config_get_wifi_feature_capabilities = 0x40000f84;
config_get_wifi_ampdu_tx_hetb_tid_limit = 0x40000f88;
esp_test_disable_tx_statistics = 0x40000f8c;
esp_test_enable_tx_statistics = 0x40000f90;
esp_test_clr_tx_statistics = 0x40000f94;
@ -451,3 +440,33 @@ g_pp_timer_info_ptr = 0x4084fc98;
g_rts_threshold_bytes_ptr = 0x4084fc94;
g_he_max_apep_length_tab_ptr = 0x4084fc90;
s_tbttstart = 0x4084fc88;
/***************************************
Group rom_pp
***************************************/
/* Functions */
pm_get_tbtt_count = 0x400014c8;
tsf_hal_get_time = 0x400014cc;
tsf_hal_get_counter_value = 0x400014d0;
/***************************************
Group rom_pp
***************************************/
/* Functions */
pm_save_tbtt_info = 0x40001550;
pm_beacon_offset_is_enabled = 0x40001554;
pm_beacon_offset_is_sampling = 0x40001558;
pm_beacon_offset_add_total_counter = 0x4000155c;
pm_beacon_offset_add_loss_counter = 0x40001560;
pm_beacon_offset_check = 0x40001564;
pm_beacon_offset_get_average = 0x40001568;
pm_beacon_offset_get_expect = 0x4000156c;
pm_beacon_offset_get_params = 0x40001570;
pm_beacon_monitor_tbtt_stop = 0x40001574;
pm_enable_max_idle_timer = 0x40001578;
/* Data (.data, .bss, .rodata) */
s_pm_beacon_offset_ptr = 0x4084fc64;
s_pm_beacon_offset_config_ptr = 0x4084fc60;

13
components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld
View File

@ -1,14 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c61.rom.rvfp.ld for esp32c61
*
*
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
*
* Compatible with ROM where ECO version equal or greater to 0.
/* ROM function interface
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -61,9 +57,10 @@ __muldf3 = 0x40000a14;
__nedf2 = 0x40000a18;
__subdf3 = 0x40000a1c;
/***************************************
Group libgcc
***************************************/
***************************************/
/* Functions */
__divsf3 = 0x40000828;

7
components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,9 +9,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
/* systimer_hal_init = 0x400003d0; */
/* systimer_hal_deinit = 0x400003d4; */
systimer_hal_init = 0x400003d0;
systimer_hal_deinit = 0x400003d4;
systimer_hal_set_tick_rate_ops = 0x400003d8;
systimer_hal_get_counter_value = 0x400003dc;
systimer_hal_get_time = 0x400003e0;

2
components/esp_rom/linker.lf
View File

@ -9,8 +9,6 @@ entries:
esp_rom_cache_esp32s2_esp32s3 (noflash)
if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y:
esp_rom_cache_writeback_esp32s3 (noflash)
if ESP_ROM_CACHE_WB_INVLD_LOW_RANGE = y:
esp_rom_cache_esp32c61 (noflash)
if HEAP_TLSF_USE_ROM_IMPL = y && (ESP_ROM_TLSF_CHECK_PATCH = y || HEAP_TLSF_CHECK_PATCH = y):
esp_rom_tlsf (noflash)
if SOC_SYSTIMER_SUPPORTED = y:

97
components/esp_rom/patches/esp_rom_cache_esp32c61.c
View File

@ -1,97 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_rom_caps.h"
#include "soc/soc_caps.h"
#include "soc/cache_reg.h"
#include "soc/cache_struct.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "esp32c61/rom/cache.h"
#include "esp_rom_sys.h"
#define CACHE_MAX_SYNC_NUM ((CACHE_SYNC_SIZE + 1) >> 1)
/**
* @brief Sync Cache items
*
* @param type sync type
* @param addr address
* @param bytes bytes to be synced
*/
__attribute__((always_inline))
static inline void s_cache_sync_items(uint32_t type, uint32_t addr, uint32_t bytes)
{
REG_WRITE(CACHE_SYNC_ADDR_REG, addr);
REG_SET_FIELD(CACHE_SYNC_SIZE_REG, CACHE_SYNC_SIZE, bytes);
REG_SET_BIT(CACHE_SYNC_CTRL_REG, type);
while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE))
;
}
int Cache_Invalidate_Addr(uint32_t vaddr, uint32_t size)
{
uint32_t plus = 0;
uint32_t cache_line_size = 32;
uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM;
if (size == 0) {
HAL_ASSERT(false);
}
//aligned start address to cache line size
plus = vaddr & (cache_line_size - 1);
vaddr -= plus;
//make the length fit the start address
size += plus;
//aligned the length to cache line size(0->0)
size = (size + cache_line_size - 1) & ~(cache_line_size - 1);
while (size > 0) {
//aligned to cache_max_sync_size, (0->cache_max_sync_size)
uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr;
if (this_size > size) {
this_size = size;
}
s_cache_sync_items(CACHE_SYNC_INVALIDATE, vaddr, this_size);
vaddr += this_size;
size -= this_size;
}
return 0;
}
int Cache_WriteBack_Addr(uint32_t vaddr, uint32_t size)
{
uint32_t plus = 0;
uint32_t cache_line_size = 32;
uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM;
if (size == 0) {
HAL_ASSERT(false);
}
//aligned start address to cache line size
plus = vaddr & (cache_line_size - 1);
vaddr -= plus;
//make the length fit the start address
size += plus;
//aligned the length to cache line size(0->0)
size = (size + cache_line_size - 1) & ~(cache_line_size - 1);
while (size > 0) {
//aligned to cache_max_sync_size, (0->cache_max_sync_size)
uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr;
if (this_size > size) {
this_size = size;
}
s_cache_sync_items(CACHE_SYNC_WRITEBACK, vaddr, this_size);
vaddr += this_size;
size -= this_size;
}
return 0;
}

4
components/esp_rom/patches/esp_rom_systimer.c
View File

@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
}
#endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
void systimer_hal_init(systimer_hal_context_t *hal)
{
hal->dev = &SYSTIMER;
@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
systimer_ll_enable_clock(hal->dev, false);
hal->dev = NULL;
}
#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
#endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL

4
components/esp_wifi/test_apps/bin_size_apsta/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

4
components/esp_wifi/test_apps/wifi_connect/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

4
components/esp_wifi/test_apps/wifi_function/README.md
View File

@ -1,3 +1,3 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

4
components/esp_wifi/test_apps/wifi_nvs_config/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

2
components/hal/esp32c61/include/hal/gpio_ll.h
View File

@ -38,7 +38,7 @@ extern "C" {
#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0))
#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE
#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE
/**
* @brief Get the configuration for an IO

4
components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h
View File

@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i;
for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
buf[i] = USB_SERIAL_JTAG.ep1.val;
}
return i;
}
@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i;
for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
USB_SERIAL_JTAG.ep1.val = buf[i];
}
return i;
}

14
components/soc/esp32c61/gdma_periph.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -30,8 +30,8 @@ const gdma_signal_conn_t gdma_periph_signals = {
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
@ -40,7 +40,7 @@ const gdma_signal_conn_t gdma_periph_signals = {
#define G0P0_RETENTION_REGS_CNT_0 13
#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG
#define G0P0_RETENTION_REGS_CNT_1 12
#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG
#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
@ -68,8 +68,8 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
@ -78,7 +78,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
#define G0P1_RETENTION_REGS_CNT_0 13
#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG
#define G0P1_RETENTION_REGS_CNT_1 12
#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG
#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {

92
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -31,10 +31,6 @@ config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_USB_SERIAL_JTAG_SUPPORTED
bool
default y
@ -47,14 +43,6 @@ config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
config SOC_PHY_SUPPORTED
bool
default y
config SOC_WIFI_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
@ -1214,83 +1202,3 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
config SOC_WIFI_FTM_SUPPORT
bool
default n
config SOC_WIFI_GCMP_SUPPORT
bool
default y
config SOC_WIFI_WAPI_SUPPORT
bool
default y
config SOC_WIFI_CSI_SUPPORT
bool
default y
config SOC_WIFI_MESH_SUPPORT
bool
default y
config SOC_WIFI_HE_SUPPORT
bool
default y
config SOC_WIFI_MAC_VERSION_NUM
int
default 3
config SOC_WIFI_NAN_SUPPORT
bool
default y
config SOC_BLE_SUPPORTED
bool
default y
config SOC_BLE_MESH_SUPPORTED
bool
default y
config SOC_ESP_NIMBLE_CONTROLLER
bool
default y
config SOC_BLE_50_SUPPORTED
bool
default y
config SOC_BLE_DEVICE_PRIVACY_SUPPORTED
bool
default y
config SOC_BLE_POWER_CONTROL_SUPPORTED
bool
default y
config SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED
bool
default y
config SOC_BLUFI_SUPPORTED
bool
default y
config SOC_BLE_MULTI_CONN_OPTIMIZATION
bool
default y
config SOC_BLE_CTE_SUPPORTED
bool
default y
config SOC_PHY_COMBO_MODULE
bool
default y

6
components/soc/esp32c61/include/soc/gpio_sig_map.h
View File

@ -1,12 +1,11 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// version date 2310090
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
@ -141,6 +140,7 @@
#define GPIO_TASK_MATRIX_OUT2_IDX 120
#define GPIO_EVENT_MATRIX_IN3_IDX 121
#define GPIO_TASK_MATRIX_OUT3_IDX 121
#define SDIO_TOHOST_INT_OUT_IDX 124
#define CLK_OUT_OUT1_IDX 126
#define CLK_OUT_OUT2_IDX 127
#define CLK_OUT_OUT3_IDX 128
@ -176,5 +176,5 @@
#define MODEM_DIAG29_IDX 158
#define MODEM_DIAG30_IDX 159
#define MODEM_DIAG31_IDX 160
// version date 2310090
#define SIG_GPIO_OUT_IDX 256

2
components/soc/esp32c61/include/soc/interrupt_reg.h
View File

@ -14,5 +14,3 @@
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE

24
components/soc/esp32c61/include/soc/interrupts.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -35,15 +35,15 @@ typedef enum {
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
ETS_LP_APM_M0_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE,
ETS_FROM_CPU_INTR1_SOURCE,
ETS_FROM_CPU_INTR2_SOURCE,
ETS_FROM_CPU_INTR3_SOURCE,
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
ETS_ASSIST_DEBUG_INTR_SOURCE,
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE,
ETS_GPIO_INTERRUPT_PRO_SOURCE,
ETS_GPIO_INTERRUPT_EXT_SOURCE,
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
@ -52,6 +52,8 @@ typedef enum {
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_CPU_APM_M0_INTR_SOURCE,
ETS_CPU_APM_M1_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
@ -62,16 +64,18 @@ typedef enum {
ETS_I2C_EXT0_INTR_SOURCE,
ETS_TG0_T0_INTR_SOURCE,
ETS_TG0_T1_INTR_SOURCE,
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
ETS_TG0_WDT_INTR_SOURCE,
ETS_TG1_T0_INTR_SOURCE,
ETS_TG1_T1_INTR_SOURCE,
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
ETS_TG1_WDT_INTR_SOURCE,
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
ETS_APB_ADC_INTR_SOURCE = 53,
ETS_APB_ADC_INTR_SOURCE,
ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE = 54,
ETS_SLC0_INTR_SOURCE,
ETS_SLC1_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE,
ETS_DMA_IN_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,

4
components/soc/esp32c61/include/soc/pmu_icg_mapping.h
View File

@ -1,10 +1,11 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
@ -35,6 +36,7 @@
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TG0 14

2
components/soc/esp32c61/include/soc/soc.h
View File

@ -22,9 +22,7 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)

50
components/soc/esp32c61/include/soc/soc_caps.h
View File

@ -24,13 +24,13 @@
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
// #define SOC_BT_SUPPORTED 1 // TODO: IDF-13139, re-enable for c61 eco3
// \#define SOC_IEEE802154_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_PHY_SUPPORTED 1
#define SOC_WIFI_SUPPORTED 1
// #define SOC_PHY_SUPPORTED 1 //TODO: IDF-13141, re-open for c61 eco3
// #define SOC_WIFI_SUPPORTED 1 //TODO: IDF-13138, re-open on c61 eco3
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1
@ -498,30 +498,32 @@
#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN (1)
/*------------------------------------ WI-FI CAPS ------------------------------------*/
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */
#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
#define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */
#define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */
#define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */
//TODO: IDF-13138, re-open on c61 eco3
// #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
// #define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */
// #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
// #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
// #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
// #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
// #define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */
// #define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */
// #define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
#define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
#define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
#define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
#define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
#define SOC_BLE_CTE_SUPPORTED (1) /*!< Support Bluetooth LE Constant Tone Extension (CTE) */
// /*---------------------------------- Bluetooth CAPS ----------------------------------*/
// TODO: IDF-13139, re-enable for c61 eco3
// #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
// #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
// #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
// #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
// #define SOC_BLE_CTE_SUPPORTED (1) /*!< Support Bluetooth LE Constant Tone Extension (CTE) */
/*------------------------------------- PHY CAPS -------------------------------------*/
#define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/
// #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/
/*------------------------------------- No Reset CAPS -------------------------------------*/
// \#define SOC_CAPS_NO_RESET_BY_ANA_BOD (1) //TODO: [ESP32C61] IDF-9254

12
components/soc/esp32c61/include/soc/system_intr.h
View File

@ -8,10 +8,10 @@
#include "soc/interrupts.h"
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_FROM_CPU_INTR2_SOURCE
#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_FROM_CPU_INTR3_SOURCE
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_CPU_INTR_FROM_CPU_1_SOURCE
#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_CPU_INTR_FROM_CPU_2_SOURCE
#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_CPU_INTR_FROM_CPU_3_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE

58
components/soc/esp32c61/interrupts.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -43,30 +43,34 @@ const char *const esp_isr_names[] = {
[33] = "HP_APM_M1",
[34] = "HP_APM_M2",
[35] = "HP_APM_M3",
[36] = "MSPI",
[37] = "I2S1",
[38] = "UART0",
[39] = "UART1",
[40] = "UART2",
[41] = "LEDC",
[42] = "USB",
[43] = "I2C_EXT0",
[44] = "TG0_T0",
[45] = "TG0_T1",
[46] = "TG0_WDT",
[47] = "TG1_T0",
[48] = "TG1_T1",
[49] = "TG1_WDT",
[50] = "SYSTIMER_TARGET0",
[51] = "SYSTIMER_TARGET1",
[52] = "SYSTIMER_TARGET2",
[53] = "APB_ADC",
[54] = "DMA_IN_CH0",
[55] = "DMA_IN_CH1",
[56] = "DMA_OUT_CH0",
[57] = "DMA_OUT_CH1",
[58] = "GPSPI2",
[59] = "SHA",
[60] = "ECC",
[61] = "ECDSA",
[36] = "CPU_APM_M0",
[37] = "CPU_APM_M1",
[38] = "MSPI",
[39] = "I2S0",
[40] = "UART0",
[41] = "UART1",
[42] = "UART2",
[43] = "LEDC",
[44] = "USB",
[45] = "I2C_EXT0",
[46] = "TG0_T0",
[47] = "TG0_T1",
[48] = "TG0_WDT",
[49] = "TG1_T0",
[50] = "TG1_T1",
[51] = "TG1_WDT",
[52] = "SYSTIMER_TARGET0",
[53] = "SYSTIMER_TARGET1",
[54] = "SYSTIMER_TARGET2",
[55] = "APB_ADC",
[56] = "SLC0",
[57] = "SLC1",
[58] = "DMA_IN_CH0",
[59] = "DMA_IN_CH1",
[60] = "DMA_OUT_CH0",
[61] = "DMA_OUT_CH1",
[62] = "GPSPI2",
[63] = "SHA",
[64] = "ECC",
[65] = "ECDSA",
};

18
components/soc/esp32c61/ld/esp32c61.peripherals.ld
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,8 +20,10 @@ PROVIDE ( ADC = 0x6000E000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( PVT_MONITOR = 0x60019000 );
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );
PROVIDE ( HINF = 0x60016000 );
PROVIDE ( SLC = 0x60017000 );
PROVIDE ( HOST = 0x60018000 );
PROVIDE ( PVT = 0x60019000 );
PROVIDE ( AHB_DMA = 0x60080000 );
PROVIDE ( GPSPI2 = 0x60081000 );
PROVIDE ( SHA = 0x60089000 );
@ -31,19 +33,15 @@ PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091e00 );
PROVIDE ( GPIO_ETM = 0x60091f18 );
PROVIDE ( TCM_MEM_MONITOR = 0x60092000 );
PROVIDE ( MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );
PROVIDE ( HP_SYSTEM = 0x60095000 );
PROVIDE ( PCR = 0x60096000 );
PROVIDE ( TEE = 0x60098000 );
PROVIDE ( HP_APM = 0x60099000 );
PROVIDE ( MISC = 0x6009F000 );
PROVIDE ( MODEM_SYSCON = 0x600A9C00 );
PROVIDE ( MODEM_LPCON = 0x600AF000 );
PROVIDE ( MODEM0 = 0x600A0000 );
PROVIDE ( MODEM1 = 0x600AC000 );
PROVIDE ( MODEM_PWR0 = 0x600AD000 );
PROVIDE ( MODEM_PWR1 = 0x600AF000 );
PROVIDE ( CPU_APM_REG = 0x6009A000 );
PROVIDE ( PMU = 0x600B0000 );
PROVIDE ( LP_CLKRST = 0x600B0400 );
PROVIDE ( LP_TIMER = 0x600B0C00 );
@ -56,7 +54,7 @@ PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( LP_IO_MUX = 0x600B4000 );
PROVIDE ( LP_GPIO = 0x600B4400 );
PROVIDE ( EFUSE0 = 0x600B4800 );
PROVIDE ( EFUSE1 = 0x600B4C00 );
PROVIDE ( OTP_DEBUG = 0x600B4C00 );
PROVIDE ( TRACE = 0x600C0000 );
PROVIDE ( BUS_MONITOR = 0x600C2000 );
PROVIDE ( INTPRI = 0x600C5000 );

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components/soc/esp32c61/register/soc/ahb_dma_reg.h
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components/soc/esp32c61/register/soc/ahb_dma_struct.h
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components/soc/esp32c61/register/soc/cpu_apm_reg.h Normal file
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components/soc/esp32c61/register/soc/cpu_apm_struct.h Normal file
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@ -0,0 +1,403 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of apm_region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** apm_region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t apm_region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} cpu_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of apm_regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** apm_regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t apm_regionn_addr_start_l:12;
/** apm_regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
* Configures start address of region n.
*/
uint32_t apm_regionn_addr_start:7;
/** apm_regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, start address of region n.
*/
uint32_t apm_regionn_addr_start_h:13;
};
uint32_t val;
} cpu_apm_regionn_addr_start_reg_t;
/** Type of apm_regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** apm_regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region n.
*/
uint32_t apm_regionn_addr_end_l:12;
/** apm_regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
* Configures end address of region n.
*/
uint32_t apm_regionn_addr_end:7;
/** apm_regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, end address of region n.
*/
uint32_t apm_regionn_addr_end_h:13;
};
uint32_t val;
} cpu_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of apm_regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_x:1;
/** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_w:1;
/** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_r:1;
uint32_t reserved_3:1;
/** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_x:1;
/** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_w:1;
/** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_r:1;
uint32_t reserved_7:1;
/** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_x:1;
/** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_w:1;
/** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_r:1;
/** apm_regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t apm_regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} cpu_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of apm_func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** apm_m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t apm_m0_func_en:1;
/** apm_m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t apm_m1_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of apm_m0_status register
* M0 status register
*/
typedef union {
struct {
/** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of apm_m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of apm_m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m0_exception_region:16;
/** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m0_exception_mode:2;
/** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of apm_m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m0_exception_addr:32;
};
uint32_t val;
} cpu_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of apm_m1_status register
* M1 status register
*/
typedef union {
struct {
/** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of apm_m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of apm_m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m1_exception_region:16;
/** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m1_exception_mode:2;
/** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of apm_m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m1_exception_addr:32;
};
uint32_t val;
} cpu_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of apm_int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m0_apm_int_en:1;
/** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of apm_clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** apm_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t apm_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of apm_date register
* Version control register
*/
typedef union {
struct {
/** apm_date : R/W; bitpos: [27:0]; default: 37823248;
* Version control register.
*/
uint32_t apm_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} cpu_apm_date_reg_t;
typedef struct {
volatile cpu_apm_region_filter_en_reg_t apm_region_filter_en;
volatile cpu_apm_regionn_addr_start_reg_t apm_region0_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region0_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region0_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region1_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region1_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region1_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region2_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region2_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region2_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region3_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region3_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region3_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region4_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region4_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region4_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region5_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region5_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region5_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region6_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region6_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region6_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region7_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region7_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region7_attr;
uint32_t reserved_064[24];
volatile cpu_apm_func_ctrl_reg_t apm_func_ctrl;
volatile cpu_apm_m0_status_reg_t apm_m0_status;
volatile cpu_apm_m0_status_clr_reg_t apm_m0_status_clr;
volatile cpu_apm_m0_exception_info0_reg_t apm_m0_exception_info0;
volatile cpu_apm_m0_exception_info1_reg_t apm_m0_exception_info1;
volatile cpu_apm_m1_status_reg_t apm_m1_status;
volatile cpu_apm_m1_status_clr_reg_t apm_m1_status_clr;
volatile cpu_apm_m1_exception_info0_reg_t apm_m1_exception_info0;
volatile cpu_apm_m1_exception_info1_reg_t apm_m1_exception_info1;
uint32_t reserved_0e8[12];
volatile cpu_apm_int_en_reg_t apm_int_en;
uint32_t reserved_11c[439];
volatile cpu_apm_clock_gate_reg_t apm_clock_gate;
volatile cpu_apm_date_reg_t apm_date;
} cpu_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c61/register/soc/gpio_ext_reg.h
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components/soc/esp32c61/register/soc/gpio_ext_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,48 +10,23 @@
extern "C" {
#endif
/** Group: Clock gate Register */
/** Type of clock_gate register
* Clock Gating Configure Register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Clock enable bit of configuration registers for sigma delta modulation.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_ext_clock_gate_reg_t;
/** Group: Configure Registers */
/** Type of pad_comp_config_0 register
* Configuration register for zero-crossing detection
* PAD Compare configure Register
*/
typedef union {
struct {
/** xpd_comp_0 : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the function of analog PAD voltage comparator.\\
* 0: Disable\\
* 1: Enable\\
* Pad compare enable bit.
*/
uint32_t xpd_comp_0:1;
/** mode_comp_0 : R/W; bitpos: [1]; default: 0;
* Configures the reference voltage for analog PAD voltage comparator.. \\
* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
* used as a regular GPIO\\
* 1: Reference voltage is the voltage on the GPIO8 PAD\\
* 1 to enable external reference from PAD[x]. 0 to enable internal reference,
* meanwhile PAD[x] can be used as a regular GPIO.
*/
uint32_t mode_comp_0:1;
/** dref_comp_0 : R/W; bitpos: [4:2]; default: 0;
* Configures the internal reference voltage for analog PAD voltage coparator. \\
* 0: Internal reference voltage is 0 * VDDPST1\\
* 1: Internal reference voltage is 0.1 * VDDPST1\\
* ......\\
* 6: Internal reference voltage is 0.6 * VDDPST1\\
* 7: Internal reference voltage is 0.7 * VDDPST1\\
* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
*/
uint32_t dref_comp_0:3;
uint32_t reserved_5:27;
@ -60,14 +35,12 @@ typedef union {
} gpio_ext_pad_comp_config_0_reg_t;
/** Type of pad_comp_filter_0 register
* Configuration register for interrupt source mask period of zero-crossing detection
* Zero Detect filter Register
*/
typedef union {
struct {
/** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0;
* Configures the period of masking new interrupt source foe analog PAD voltage
* comparator.\\
* Measurement unit: IO MUX operating clock cycle\\
* Zero Detect filter cycle length
*/
uint32_t zero_det_filter_cnt_0:32;
};
@ -100,27 +73,19 @@ typedef union {
} gpio_ext_pin_ctrl_reg_t;
/** Group: ETM Configuration Registers */
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* ETM configuration register for channel 0
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0;
* Configures to select GPIO for ETM event channel.\\
* 0: Select GPIO0\\
* 1: Select GPIO1\\
* ......\\
* 23: Select GPIO23\\
* 24: Select GPIO24\\
* 25 ~ 31: Reserved\\
/** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_chn_event_sel:5;
uint32_t reserved_5:2;
uint32_t etm_chn_event_sel:6;
uint32_t reserved_6:1;
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable ETM event send.\\
* 0: Not enable\\
* 1: Enable\\
* Etm event send enable bit.
*/
uint32_t etm_chn_event_en:1;
uint32_t reserved_8:24;
@ -129,177 +94,108 @@ typedef union {
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of etm_task_pn_cfg register
* GPIO selection register for ETM.
* This register is an abstraction of the following registers:
* gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t
*/
typedef union {
uint32_t val;
} gpio_ext_etm_task_pn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* GPIO selection register 0 for ETM
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO0.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO0 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO1.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO1 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO2.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO2 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO3.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO3 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO4.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO4 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio4_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p0_cfg_reg_t;
} gpio_ext_etm_task_pn_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* GPIO selection register 1 for ETM
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO5.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO5 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO6.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO6 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO7.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO7 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO8.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO8 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO9.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO9 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio9_en:1;
uint32_t reserved_30:2;
@ -308,83 +204,53 @@ typedef union {
} gpio_ext_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* GPIO selection register 2 for ETM
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO10.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO10 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO11.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO11 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO12.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO12 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO13.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO13 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO14.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO14 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio14_en:1;
uint32_t reserved_30:2;
@ -393,83 +259,53 @@ typedef union {
} gpio_ext_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* GPIO selection register 3 for ETM
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO15.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO15 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO16.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO16 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO17.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO17 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO18.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO18 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO19.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO19 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio19_en:1;
uint32_t reserved_30:2;
@ -478,83 +314,53 @@ typedef union {
} gpio_ext_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* GPIO selection register 4 for ETM
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO20.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO20 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO21.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO21 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO22.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO22 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO23.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO23 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO24.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO24 to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio24_en:1;
uint32_t reserved_30:2;
@ -562,6 +368,61 @@ typedef union {
uint32_t val;
} gpio_ext_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio28_en:1;
/** etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio29_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio29_en : R/W; bitpos: [29]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio29_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p5_cfg_reg_t;
/** Group: Interrupt Registers */
/** Type of int_raw register
@ -655,11 +516,11 @@ typedef union {
/** Group: Version Register */
/** Type of version register
* Version control register
* Version Control Register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37753392;
/** date : R/W; bitpos: [27:0]; default: 37823120;
* Version control register.
*/
uint32_t date:28;
@ -670,18 +531,17 @@ typedef union {
typedef struct gpio_etm_dev_t {
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_138[8];
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5];
uint32_t reserved_080[8];
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6];
} gpio_etm_dev_t;
typedef struct {
volatile gpio_ext_clock_gate_reg_t clock_gate;
uint32_t reserved_004[21];
uint32_t reserved_000[22];
volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
uint32_t reserved_060[46];
volatile gpio_etm_dev_t etm;
uint32_t reserved_16c[25];
uint32_t reserved_170[24];
volatile gpio_ext_int_raw_reg_t int_raw;
volatile gpio_ext_int_st_reg_t int_st;
volatile gpio_ext_int_ena_reg_t int_ena;

5092
components/soc/esp32c61/register/soc/gpio_reg.h
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557
components/soc/esp32c61/register/soc/gpio_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,20 +10,14 @@
extern "C" {
#endif
/** Group: Configuration Registers */
/** Group: configuration register */
/** Type of strap register
* Strapping pin register
* pad strapping register
*/
typedef union {
struct {
/** strapping : RO; bitpos: [15:0]; default: 0;
* Represents the values of GPIO strapping pins.
*
* - bit0 ~ bit1: invalid
* - bit2: GPIO8
* - bit3: GPIO9
* - bit4: GPIO7
* - bit5 ~ bit15: invalid
* pad strapping register
*/
uint32_t strapping:16;
uint32_t reserved_16:16;
@ -32,297 +26,389 @@ typedef union {
} gpio_strap_reg_t;
/** Type of out register
* GPIO output register
* GPIO output register for GPIO0-31
*/
typedef union {
struct {
/** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0;
* Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
* 0: Low level\\
* 1: High level\\
* The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
* respectively. Bit25 ~ bit31 are invalid.\\
/** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
* GPIO output register for GPIO0-31
*/
uint32_t out_data_orig:29;
uint32_t reserved_29:3;
uint32_t out_data_orig:32;
};
uint32_t val;
} gpio_out_reg_t;
/** Type of out_w1ts register
* GPIO output set register
* GPIO output set register for GPIO0-31
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [28:0]; default: 0;
* Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
* GPIO24.\\
* 0: Not set\\
* 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
* Recommended operation: use this register to set GPIO_OUT_REG. \\
/** out_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO output set register for GPIO0-31
*/
uint32_t out_w1ts:29;
uint32_t reserved_29:3;
uint32_t out_w1ts:32;
};
uint32_t val;
} gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* GPIO output clear register
* GPIO output clear register for GPIO0-31
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [28:0]; default: 0;
* Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
* GPIO24 output.\\
* 0: Not clear\\
* 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
* Recommended operation: use this register to clear GPIO_OUT_REG. \\
/** out_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO output clear register for GPIO0-31
*/
uint32_t out_w1tc:29;
uint32_t reserved_29:3;
uint32_t out_w1tc:32;
};
uint32_t val;
} gpio_out_w1tc_reg_t;
/** Type of enable register
* GPIO output enable register
/** Type of out1 register
* GPIO output register for GPIO32-33
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [28:0]; default: 0;
* Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
* 0: Not enable\\
* 1: Enable\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
/** out1_data_orig : R/W/SC/WTC; bitpos: [1:0]; default: 0;
* GPIO output register for GPIO32-33
*/
uint32_t enable_data:29;
uint32_t reserved_29:3;
uint32_t out1_data_orig:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_out1_reg_t;
/** Type of out1_w1ts register
* GPIO output set register for GPIO32-33
*/
typedef union {
struct {
/** out1_w1ts : WT; bitpos: [1:0]; default: 0;
* GPIO output set register for GPIO32-33
*/
uint32_t out1_w1ts:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_out1_w1ts_reg_t;
/** Type of out1_w1tc register
* GPIO output clear register for GPIO32-33
*/
typedef union {
struct {
/** out1_w1tc : WT; bitpos: [1:0]; default: 0;
* GPIO output clear register for GPIO32-33
*/
uint32_t out1_w1tc:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_out1_w1tc_reg_t;
/** Type of enable register
* GPIO output enable register for GPIO0-31
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
* GPIO output enable register for GPIO0-31
*/
uint32_t enable_data:32;
};
uint32_t val;
} gpio_enable_reg_t;
/** Type of enable_w1ts register
* GPIO output enable set register
* GPIO output enable set register for GPIO0-31
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [28:0]; default: 0;
* Configures whether or not to set the output enable register GPIO_ENABLE_REG of
* GPIO0 ~ GPIO24.\\
* 0: Not set\\
* 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
* Recommended operation: use this register to set GPIO_ENABLE_REG.\\
/** enable_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO output enable set register for GPIO0-31
*/
uint32_t enable_w1ts:29;
uint32_t reserved_29:3;
uint32_t enable_w1ts:32;
};
uint32_t val;
} gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* GPIO output enable clear register
* GPIO output enable clear register for GPIO0-31
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [28:0]; default: 0;
* Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
* GPIO0 ~ GPIO24. \\
* 0: Not clear\\
* 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
* Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
/** enable_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO output enable clear register for GPIO0-31
*/
uint32_t enable_w1tc:29;
uint32_t reserved_29:3;
uint32_t enable_w1tc:32;
};
uint32_t val;
} gpio_enable_w1tc_reg_t;
/** Type of in register
* GPIO input register
/** Type of enable1 register
* GPIO output enable register for GPIO32-33
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [28:0]; default: 0;
* Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
* value:\\
* 0: Low level\\
* 1: High level\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
/** enable1_data : R/W/WTC; bitpos: [1:0]; default: 0;
* GPIO output enable register for GPIO32-33
*/
uint32_t in_data_next:29;
uint32_t reserved_29:3;
uint32_t enable1_data:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_enable1_reg_t;
/** Type of enable1_w1ts register
* GPIO output enable set register for GPIO32-33
*/
typedef union {
struct {
/** enable1_w1ts : WT; bitpos: [1:0]; default: 0;
* GPIO output enable set register for GPIO32-33
*/
uint32_t enable1_w1ts:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_enable1_w1ts_reg_t;
/** Type of enable1_w1tc register
* GPIO output enable clear register for GPIO32-33
*/
typedef union {
struct {
/** enable1_w1tc : WT; bitpos: [1:0]; default: 0;
* GPIO output enable clear register for GPIO32-33
*/
uint32_t enable1_w1tc:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_enable1_w1tc_reg_t;
/** Type of in register
* GPIO input register for GPIO0-31
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [31:0]; default: 0;
* GPIO input register for GPIO0-31
*/
uint32_t in_data_next:32;
};
uint32_t val;
} gpio_in_reg_t;
/** Group: Interrupt Status Registers */
/** Type of status register
* GPIO interrupt status register
/** Type of in1 register
* GPIO input register for GPIO32-33
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0;
* The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
*
* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
* - Each bit represents the status of its corresponding GPIO:
*
* - 0: Represents the GPIO does not generate the interrupt configured by
* GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
* - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
* or this bit is configured to 1 by the software.
*
/** in1_data_next : RO; bitpos: [1:0]; default: 0;
* GPIO input register for GPIO32-33
*/
uint32_t status_interrupt:29;
uint32_t reserved_29:3;
uint32_t in1_data_next:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_in1_reg_t;
/** Type of status register
* GPIO interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
* GPIO interrupt status register for GPIO0-31
*/
uint32_t status_interrupt:32;
};
uint32_t val;
} gpio_status_reg_t;
/** Type of status_w1ts register
* GPIO interrupt status set register
* GPIO interrupt status set register for GPIO0-31
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [28:0]; default: 0;
* Configures whether or not to set the interrupt status register
* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
*
* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
* register to set GPIO_STATUS_INTERRUPT.
/** status_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO interrupt status set register for GPIO0-31
*/
uint32_t status_w1ts:29;
uint32_t reserved_29:3;
uint32_t status_w1ts:32;
};
uint32_t val;
} gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* GPIO interrupt status clear register
* GPIO interrupt status clear register for GPIO0-31
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [28:0]; default: 0;
* Configures whether or not to clear the interrupt status register
* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
*
* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
* register to clear GPIO_STATUS_INTERRUPT.
/** status_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO interrupt status clear register for GPIO0-31
*/
uint32_t status_w1tc:29;
uint32_t reserved_29:3;
uint32_t status_w1tc:32;
};
uint32_t val;
} gpio_status_w1tc_reg_t;
/** Type of procpu_int register
* CPU interrupt status register
/** Type of status1 register
* GPIO interrupt status register for GPIO32-33
*/
typedef union {
struct {
/** procpu_int : RO; bitpos: [28:0]; default: 0;
* Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
* 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
* interrupt configured by GPIO_PIN$n_INT_TYPE.\\
* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
* after the CPU interrupt is enabled.\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
* interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
* enable signal (bit13 of GPIO_PIN$n_REG). \\
/** status1_interrupt : R/W/WTC; bitpos: [1:0]; default: 0;
* GPIO interrupt status register for GPIO32-33
*/
uint32_t procpu_int:29;
uint32_t reserved_29:3;
uint32_t status1_interrupt:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_status1_reg_t;
/** Type of status1_w1ts register
* GPIO interrupt status set register for GPIO32-33
*/
typedef union {
struct {
/** status1_w1ts : WT; bitpos: [1:0]; default: 0;
* GPIO interrupt status set register for GPIO32-33
*/
uint32_t status1_w1ts:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_status1_w1ts_reg_t;
/** Type of status1_w1tc register
* GPIO interrupt status clear register for GPIO32-33
*/
typedef union {
struct {
/** status1_w1tc : WT; bitpos: [1:0]; default: 0;
* GPIO interrupt status clear register for GPIO32-33
*/
uint32_t status1_w1tc:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_status1_w1tc_reg_t;
/** Type of procpu_int register
* GPIO_PROCPU_INT interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** procpu_int : RO; bitpos: [31:0]; default: 0;
* GPIO_PROCPU_INT interrupt status register for GPIO0-31
*/
uint32_t procpu_int:32;
};
uint32_t val;
} gpio_procpu_int_reg_t;
/** Type of status_next register
* GPIO interrupt source register
/** Type of sdio_int register
* GPIO_SDIO_INT interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [28:0]; default: 0;
* Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
* bit represents:\\
* 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
* 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
* The interrupt could be rising edge interrupt, falling edge interrupt, level
* sensitive interrupt and any edge interrupt.\\
/** sdio_int : RO; bitpos: [31:0]; default: 0;
* GPIO_SDIO_INT interrupt status register for GPIO0-31
*/
uint32_t status_interrupt_next:29;
uint32_t reserved_29:3;
uint32_t sdio_int:32;
};
uint32_t val;
} gpio_sdio_int_reg_t;
/** Type of procpu_int1 register
* GPIO_PROCPU_INT interrupt status register for GPIO32-33
*/
typedef union {
struct {
/** procpu_int1 : RO; bitpos: [1:0]; default: 0;
* GPIO_PROCPU_INT interrupt status register for GPIO32-33
*/
uint32_t procpu_int1:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_procpu_int1_reg_t;
/** Type of sdio_int1 register
* GPIO_SDIO_INT interrupt status register for GPIO32-33
*/
typedef union {
struct {
/** sdio_int1 : RO; bitpos: [1:0]; default: 0;
* GPIO_SDIO_INT interrupt status register for GPIO32-33
*/
uint32_t sdio_int1:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_sdio_int1_reg_t;
/** Type of status_next register
* GPIO interrupt source register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt source register for GPIO0-31
*/
uint32_t status_interrupt_next:32;
};
uint32_t val;
} gpio_status_next_reg_t;
/** Type of status_next1 register
* GPIO interrupt source register for GPIO32-33
*/
typedef union {
struct {
/** status_interrupt_next1 : RO; bitpos: [1:0]; default: 0;
* GPIO interrupt source register for GPIO32-33
*/
uint32_t status_interrupt_next1:2;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_status_next1_reg_t;
/** Group: Pin Configuration Registers */
/** Type of pinn register
* GPIOn configuration register
* GPIO pin configuration register
*/
typedef union {
struct {
/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t pinn_sync2_bypass:2;
/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
* set this bit to select pad driver. 1:open-drain. 0:normal.
*/
uint32_t pinn_pad_driver:1;
/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t pinn_sync1_bypass:2;
uint32_t reserved_5:2;
/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
* at high level
*/
uint32_t pinn_int_type:3;
/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
*/
uint32_t pinn_wakeup_enable:1;
uint32_t reserved_11:2;
/** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
* set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int.
*/
uint32_t pinn_int_ena:5;
uint32_t reserved_18:14;
@ -330,82 +416,51 @@ typedef union {
uint32_t val;
} gpio_pinn_reg_t;
/** Group: Input Configuration Registers */
/** Type of func0_in_sel_cfg register
* Configuration register for input signal 0
/** Type of func_in_sel_cfg register
* GPIO input function configuration register
*/
typedef union {
struct {
/** func_in_sel : R/W; bitpos: [5:0]; default: 48;
* Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
* 0: Select GPIO0\\
* 1: Select GPIO1\\
* ......\\
* 23: Select GPIO23\\
* 24: Select GPIO24\\
* Or\\
* 0x20: A constantly high input\\
* 0x30: A constantly low input\\
/** func_in_sel : R/W; bitpos: [6:0]; default: 96;
* set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always
* high level. s=0x60: set this port always low level.
*/
uint32_t func_in_sel:6;
/** func_in_inv_sel : R/W; bitpos: [6]; default: 0;
* Configures whether or not to invert the input value.\\
* 0: Not invert\\
* 1: Invert\\
uint32_t func_in_sel:7;
/** func_in_inv_sel : R/W; bitpos: [7]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
uint32_t func_in_inv_sel:1;
/** sig_in_sel : R/W; bitpos: [7]; default: 0;
* Configures whether or not to route signals via GPIO matrix.\\
* 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
* IO MUX.\\
* 1: Route signals via GPIO matrix.\\
/** sig0_in_sel : R/W; bitpos: [8]; default: 0;
* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
*/
uint32_t sig_in_sel:1;
uint32_t reserved_8:24;
uint32_t reserved_9:23;
};
uint32_t val;
} gpio_func_in_sel_cfg_reg_t;
/** Group: Output Configuration Registers */
/** Type of funcn_out_sel_cfg register
* Configuration register for GPIOn output
* GPIO output function select register
*/
typedef union {
struct {
/** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIOn.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
* output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
* The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
* output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
* GPIO_OUT_REG[n].
*/
uint32_t funcn_out_sel:9;
/** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
* set this bit to invert output signal.1:invert.0:not invert.
*/
uint32_t funcn_out_inv_sel:1;
/** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\
* set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
* enable signal.0:use peripheral output enable signal.
*/
uint32_t funcn_oe_sel:1;
/** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
* set this bit to invert output enable signal.1:invert.0:not invert.
*/
uint32_t funcn_oe_inv_sel:1;
uint32_t reserved_12:20;
@ -413,17 +468,13 @@ typedef union {
uint32_t val;
} gpio_funcn_out_sel_cfg_reg_t;
/** Group: Clock Gate Register */
/** Type of clock_gate register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable clock gate.\\
* 0: Not enable\\
* 1: Enable, the clock is free running. \\
* set this bit to enable GPIO clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@ -431,15 +482,13 @@ typedef union {
uint32_t val;
} gpio_clock_gate_reg_t;
/** Group: Version Register */
/** Type of date register
* GPIO version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37753392;
* Version control register. \\
/** date : R/W; bitpos: [27:0]; default: 37823120;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
@ -453,27 +502,41 @@ typedef struct {
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;
volatile gpio_out_w1tc_reg_t out_w1tc;
uint32_t reserved_010[9];
volatile gpio_out1_reg_t out1;
volatile gpio_out1_w1ts_reg_t out1_w1ts;
volatile gpio_out1_w1tc_reg_t out1_w1tc;
uint32_t reserved_01c[6];
volatile gpio_enable_reg_t enable;
volatile gpio_enable_w1ts_reg_t enable_w1ts;
volatile gpio_enable_w1tc_reg_t enable_w1tc;
uint32_t reserved_040[9];
volatile gpio_enable1_reg_t enable1;
volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
uint32_t reserved_04c[6];
volatile gpio_in_reg_t in;
uint32_t reserved_068[3];
volatile gpio_in1_reg_t in1;
uint32_t reserved_06c[2];
volatile gpio_status_reg_t status;
volatile gpio_status_w1ts_reg_t status_w1ts;
volatile gpio_status_w1tc_reg_t status_w1tc;
uint32_t reserved_080[9];
volatile gpio_status1_reg_t status1;
volatile gpio_status1_w1ts_reg_t status1_w1ts;
volatile gpio_status1_w1tc_reg_t status1_w1tc;
uint32_t reserved_08c[6];
volatile gpio_procpu_int_reg_t procpu_int;
uint32_t reserved_0a8[3];
volatile gpio_sdio_int_reg_t sdio_int;
volatile gpio_procpu_int1_reg_t procpu_int1;
volatile gpio_sdio_int1_reg_t sdio_int1;
uint32_t reserved_0b4[4];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_0b8[3];
volatile gpio_pinn_reg_t pinn[25]; // 0-24 are fanned out, 25-28 are not padded out. Only 0-24 are available.
uint32_t reserved_128[103];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
uint32_t reserved_4ac[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
uint32_t reserved_b28[180];
volatile gpio_status_next1_reg_t status_next1;
uint32_t reserved_0cc[2];
volatile gpio_pinn_reg_t pinn[34]; // 0~29 available, 30~34 not fan out, N/A
uint32_t reserved_15c[94];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; // 0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255
uint32_t reserved_542[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[34]; // 0~29 available, 30~34 not fan out, N/A
uint32_t reserved_b5c[167];
volatile gpio_clock_gate_reg_t clock_gate;
volatile gpio_date_reg_t date;
} gpio_dev_t;

216
components/soc/esp32c61/register/soc/hp_system_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,9 +16,9 @@ extern "C" {
*/
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
@ -32,10 +32,9 @@ extern "C" {
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot
* mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
@ -43,9 +42,9 @@ extern "C" {
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode. \\
* 0: Disable\\
* 1: Enable\\
* mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
@ -56,13 +55,6 @@ extern "C" {
* HP memory usage configuration register
*/
#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYSTEM_CACHE_USAGE (BIT(0))
#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U
#define HP_SYSTEM_CACHE_USAGE_S 0
/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [12:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
@ -84,11 +76,11 @@ extern "C" {
#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to enable anti-DPA attack. Valid only when
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
* 0: Disable\\
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
* 0: Disable
* 1-3: Enable. The larger the number, the higher the security level, which represents
* the ability to resist DPA attacks, with increased computational overhead of the
* hardware crypto-accelerators at the same time. \\
* hardware crypto-accelerators at the same time.
*/
#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
@ -96,9 +88,9 @@ extern "C" {
#define HP_SYSTEM_SEC_DPA_LEVEL_S 0
/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
* eFuse) to control DPA level. \\
* 0: Select EFUSE_SEC_DPA_LEVEL\\
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
* eFuse) to control DPA level.
* 0: Select EFUSE_SEC_DPA_LEVEL
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL
*/
#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
@ -126,9 +118,9 @@ extern "C" {
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
@ -173,9 +165,9 @@ extern "C" {
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.\\
* 0: No effect\\
* 1: Clear timeout interrupt\\
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
@ -183,9 +175,9 @@ extern "C" {
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
@ -217,66 +209,14 @@ extern "C" {
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
* MODEM_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
* MODEM_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
* MODEM_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
* ROM-Table lock register
*/
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
* 0: Unlock \\
* 1: Lock \\
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
@ -357,78 +297,66 @@ extern "C" {
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_RND_ECO_REG register
* redcy eco register.
*/
#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x4c)
/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_ENA (BIT(0))
#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
#define HP_SYSTEM_REDCY_ENA_V 0x00000001U
#define HP_SYSTEM_REDCY_ENA_S 0
/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_RESULT (BIT(1))
#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U
#define HP_SYSTEM_REDCY_RESULT_S 1
/** HP_SYSTEM_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x50)
/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_S 0
/** HP_SYSTEM_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x54)
/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_S 0
/** HP_SYSTEM_DEBUG_REG register
* HP-SYSTEM debug register
*/
#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x58)
/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
* Reserved
*/
#define HP_SYSTEM_FPGA_DEBUG (BIT(0))
#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S)
#define HP_SYSTEM_FPGA_DEBUG_V 0x00000001U
#define HP_SYSTEM_FPGA_DEBUG_S 0
/** HP_SYSTEM_CLOCK_GATE_REG register
* HP-SYSTEM clock gating configure register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x5c)
/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_CLK_EN (BIT(0))
#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
#define HP_SYSTEM_CLK_EN_V 0x00000001U
#define HP_SYSTEM_CLK_EN_S 0
/** HP_SYSTEM_AXI_MST_PRI_REG register
* AXI mst priority configuration register
*/
#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_SYSTEM_BASE + 0x60)
/** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
#define HP_SYSTEM_DMA_PRIORITY (BIT(0))
#define HP_SYSTEM_DMA_PRIORITY_M (HP_SYSTEM_DMA_PRIORITY_V << HP_SYSTEM_DMA_PRIORITY_S)
#define HP_SYSTEM_DMA_PRIORITY_V 0x00000001U
#define HP_SYSTEM_DMA_PRIORITY_S 0
/** HP_SYSTEM_CACHE_PRIORITY : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
#define HP_SYSTEM_CACHE_PRIORITY (BIT(1))
#define HP_SYSTEM_CACHE_PRIORITY_M (HP_SYSTEM_CACHE_PRIORITY_V << HP_SYSTEM_CACHE_PRIORITY_S)
#define HP_SYSTEM_CACHE_PRIORITY_V 0x00000001U
#define HP_SYSTEM_CACHE_PRIORITY_S 1
/** HP_SYSTEM_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x64)
/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0))
#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S)
#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U
#define HP_SYSTEM_DIS_SDIO_PROB_S 0
/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1))
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S)
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1
/** HP_SYSTEM_DATE_REG register
* Date control and version control register
*/
#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 36769824;
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823088;
* Version control register.
*/
#define HP_SYSTEM_DATE 0x0FFFFFFFU

400
components/soc/esp32c61/register/soc/hp_system_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,438 +11,344 @@ extern "C" {
#endif
/** Group: Configuration Register */
/** Type of external_device_encrypt_decrypt_control register
/** Type of system_external_device_encrypt_decrypt_control register
* External device encryption/decryption configuration register
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
* 0: Disable\\
* 1: Enable\\
/** system_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
uint32_t system_enable_spi_manual_encrypt:1;
/** system_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot
* mode.\\
* 0: Disable\\
* 1: Enable\\
uint32_t system_enable_download_db_encrypt:1;
/** system_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
uint32_t system_enable_download_g0cb_decrypt:1;
/** system_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode. \\
* 0: Disable\\
* 1: Enable\\
* mode.
* 0: Disable
* 1: Enable
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t system_enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_system_external_device_encrypt_decrypt_control_reg_t;
/** Type of sram_usage_conf register
/** Type of system_sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
/** cache_usage : HRO; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cache_usage:1;
uint32_t reserved_1:7;
/** sram_usage : R/W; bitpos: [12:8]; default: 0;
uint32_t reserved_0:8;
/** system_sram_usage : R/W; bitpos: [12:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
uint32_t sram_usage:5;
uint32_t system_sram_usage:5;
uint32_t reserved_13:3;
/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
/** system_mac_dump_alloc : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
uint32_t mac_dump_alloc:1;
uint32_t system_mac_dump_alloc:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_system_sram_usage_conf_reg_t;
/** Type of sec_dpa_conf register
/** Type of system_sec_dpa_conf register
* HP anti-DPA security configuration register
*/
typedef union {
struct {
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
/** system_sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to enable anti-DPA attack. Valid only when
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
* 0: Disable\\
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
* 0: Disable
* 1-3: Enable. The larger the number, the higher the security level, which represents
* the ability to resist DPA attacks, with increased computational overhead of the
* hardware crypto-accelerators at the same time. \\
* hardware crypto-accelerators at the same time.
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
uint32_t system_sec_dpa_level:2;
/** system_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
* eFuse) to control DPA level. \\
* 0: Select EFUSE_SEC_DPA_LEVEL\\
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
* eFuse) to control DPA level.
* 0: Select EFUSE_SEC_DPA_LEVEL
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL
*/
uint32_t sec_dpa_cfg_sel:1;
uint32_t system_sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_system_sec_dpa_conf_reg_t;
/** Type of rom_table_lock register
/** Type of system_rom_table_lock register
* ROM-Table lock register
*/
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
* 0: Unlock \\
* 1: Lock \\
/** system_rom_table_lock : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
uint32_t rom_table_lock:1;
uint32_t system_rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_rom_table_lock_reg_t;
/** Type of rom_table register
/** Type of system_rom_table register
* ROM-Table register
*/
typedef union {
struct {
/** rom_table : R/W; bitpos: [31:0]; default: 0;
/** system_rom_table : R/W; bitpos: [31:0]; default: 0;
* Software ROM-Table register, whose content can be modified only when
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
*/
uint32_t rom_table:32;
uint32_t system_rom_table:32;
};
uint32_t val;
} hp_system_rom_table_reg_t;
/** Type of core_debug_runstall_conf register
/** Type of system_core_debug_runstall_conf register
* Core Debug RunStall configurion register
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** core_runstalled : RO; bitpos: [1]; default: 0;
/** system_core_runstalled : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
uint32_t core_runstalled:1;
uint32_t system_core_runstalled:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_core_debug_runstall_conf_reg_t;
/** Type of sprom_ctrl register
/** Type of system_sprom_ctrl register
* reserved
*/
typedef union {
struct {
/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
/** system_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
uint32_t sprom_mem_aux_ctrl:32;
uint32_t system_sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprom_ctrl_reg_t;
/** Type of spram_ctrl register
/** Type of system_spram_ctrl register
* reserved
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
/** system_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t spram_mem_aux_ctrl:32;
uint32_t system_spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
/** Type of system_sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
/** system_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t sprf_mem_aux_ctrl:32;
uint32_t system_sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprf_ctrl_reg_t;
/** Type of sdprf_ctrl register
/** Type of system_sdprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
/** system_sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t sdprf_mem_aux_ctrl:32;
uint32_t system_sdprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sdprf_ctrl_reg_t;
/** Type of clock_gate register
* HP-SYSTEM clock gating configure register
/** Type of system_axi_mst_pri register
* AXI mst priority configuration register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
/** system_dma_priority : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
uint32_t system_dma_priority:1;
/** system_cache_priority : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t system_cache_priority:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_clock_gate_reg_t;
} hp_system_axi_mst_pri_reg_t;
/** Type of system_sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** system_dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t system_dis_sdio_prob:1;
/** system_sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t system_sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_sdio_ctrl_reg_t;
/** Group: Timeout Register */
/** Type of cpu_peri_timeout_conf register
/** Type of system_cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
/** system_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing CPU peripheral
* register in the number of clock cycles of the clock domain.
*/
uint32_t cpu_peri_timeout_thres:16;
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
uint32_t system_cpu_peri_timeout_thres:16;
/** system_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Write 1 to clear timeout interrupt.
*/
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
uint32_t system_cpu_peri_timeout_int_clear:1;
/** system_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t system_cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_cpu_peri_timeout_conf_reg_t;
/** Type of cpu_peri_timeout_addr register
/** Type of system_cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
/** system_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t cpu_peri_timeout_addr:32;
uint32_t system_cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_cpu_peri_timeout_addr_reg_t;
/** Type of cpu_peri_timeout_uid register
/** Type of system_cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
/** system_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t cpu_peri_timeout_uid:7;
uint32_t system_cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_cpu_peri_timeout_uid_reg_t;
/** Type of hp_peri_timeout_conf register
/** Type of system_hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
/** system_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing HP peripheral
* register, corresponding to the number of clock cycles of the clock domain.
*/
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.\\
* 0: No effect\\
* 1: Clear timeout interrupt\\
uint32_t system_hp_peri_timeout_thres:16;
/** system_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
uint32_t system_hp_peri_timeout_int_clear:1;
/** system_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t hp_peri_timeout_protect_en:1;
uint32_t system_hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_hp_peri_timeout_conf_reg_t;
/** Type of hp_peri_timeout_addr register
/** Type of system_hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
/** system_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t hp_peri_timeout_addr:32;
uint32_t system_hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_hp_peri_timeout_addr_reg_t;
/** Type of hp_peri_timeout_uid register
/** Type of system_hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
/** system_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t hp_peri_timeout_uid:7;
uint32_t system_hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_hp_peri_timeout_uid_reg_t;
/** Type of modem_peri_timeout_conf register
* MODEM_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t modem_peri_timeout_thres:16;
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t modem_peri_timeout_int_clear:1;
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
uint32_t modem_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_modem_peri_timeout_conf_reg_t;
/** Type of modem_peri_timeout_addr register
* MODEM_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t modem_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_modem_peri_timeout_addr_reg_t;
/** Type of modem_peri_timeout_uid register
* MODEM_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t modem_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_modem_peri_timeout_uid_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} hp_system_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} hp_system_rnd_eco_high_reg_t;
/** Group: Debug Register */
/** Type of debug register
* HP-SYSTEM debug register
*/
typedef union {
struct {
/** fpga_debug : R/W; bitpos: [0]; default: 1;
* Reserved
*/
uint32_t fpga_debug:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_debug_reg_t;
/** Group: Version Register */
/** Type of date register
/** Type of system_date register
* Date control and version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36769824;
/** system_date : R/W; bitpos: [27:0]; default: 37823088;
* Version control register.
*/
uint32_t date:28;
uint32_t system_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
@ -450,32 +356,28 @@ typedef union {
typedef struct {
volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
volatile hp_system_rom_table_lock_reg_t rom_table_lock;
volatile hp_system_rom_table_reg_t rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
volatile hp_system_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t sprf_ctrl;
volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl;
volatile hp_system_rnd_eco_reg_t rnd_eco;
volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
volatile hp_system_debug_reg_t debug;
volatile hp_system_clock_gate_reg_t clock_gate;
uint32_t reserved_060[231];
volatile hp_system_date_reg_t date;
volatile hp_system_external_device_encrypt_decrypt_control_reg_t system_external_device_encrypt_decrypt_control;
volatile hp_system_sram_usage_conf_reg_t system_sram_usage_conf;
volatile hp_system_sec_dpa_conf_reg_t system_sec_dpa_conf;
volatile hp_system_cpu_peri_timeout_conf_reg_t system_cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t system_cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t system_cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t system_hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t system_hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t system_hp_peri_timeout_uid;
uint32_t reserved_024[3];
volatile hp_system_rom_table_lock_reg_t system_rom_table_lock;
volatile hp_system_rom_table_reg_t system_rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t system_core_debug_runstall_conf;
volatile hp_system_sprom_ctrl_reg_t system_sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t system_spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t system_sprf_ctrl;
volatile hp_system_sdprf_ctrl_reg_t system_sdprf_ctrl;
uint32_t reserved_04c[5];
volatile hp_system_axi_mst_pri_reg_t system_axi_mst_pri;
volatile hp_system_sdio_ctrl_reg_t system_sdio_ctrl;
uint32_t reserved_068[229];
volatile hp_system_date_reg_t system_date;
} hp_system_dev_t;
extern hp_system_dev_t HP_SYSTEM;

396
components/soc/esp32c61/register/soc/i2c_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,8 +17,8 @@ extern "C" {
*/
#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
* Configures the low level width of the SCL Clock in master mode. \\
* Measurement unit: i2c_sclk \\
* Configures the low level width of the SCL Clock in master mode.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_LOW_PERIOD 0x000001FFU
#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
@ -30,27 +30,27 @@ extern "C" {
*/
#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
* Configures the SDA output mode.\\
* 0: Open drain output \\
* 1: Direct output \\
* Configures the SDA output mode.
* 0: Open drain output
* 1: Direct output
*/
#define I2C_SDA_FORCE_OUT (BIT(0))
#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
#define I2C_SDA_FORCE_OUT_V 0x00000001U
#define I2C_SDA_FORCE_OUT_S 0
/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
* Configures the SCL output mode.\\
* 0: Open drain output \\
* 1: Direct output \\
* Configures the SCL output mode.
* 0: Open drain output
* 1: Direct output
*/
#define I2C_SCL_FORCE_OUT (BIT(1))
#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
#define I2C_SCL_FORCE_OUT_V 0x00000001U
#define I2C_SCL_FORCE_OUT_S 1
/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
* Configures the sample mode for SDA.\\
* 0: Sample SDA data on the SCL high level \\
* 1: Sample SDA data on the SCL low level \\
* Configures the sample mode for SDA.
* 0: Sample SDA data on the SCL high level
* 1: Sample SDA data on the SCL low level
*/
#define I2C_SAMPLE_SCL_LEVEL (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
@ -58,24 +58,24 @@ extern "C" {
#define I2C_SAMPLE_SCL_LEVEL_S 2
/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
* Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
* reached the threshold.\\
* reached the threshold.
*/
#define I2C_RX_FULL_ACK_LEVEL (BIT(3))
#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U
#define I2C_RX_FULL_ACK_LEVEL_S 3
/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
* Configures the module as an I2C Master or Slave.\\
* 0: Slave \\
* 1: Master \\
* Configures the module as an I2C Master or Slave.
* 0: Slave
* 1: Master
*/
#define I2C_MS_MODE (BIT(4))
#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S)
#define I2C_MS_MODE_V 0x00000001U
#define I2C_MS_MODE_S 4
/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
* Configures whether the slave starts sending the data in txfifo.\\
* 0: No effect \\
* Configures whether the slave starts sending the data in txfifo.
* 0: No effect
* 1: Start
*/
#define I2C_TRANS_START (BIT(5))
@ -83,44 +83,44 @@ extern "C" {
#define I2C_TRANS_START_V 0x00000001U
#define I2C_TRANS_START_S 5
/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
* Configures to control the sending order for data needing to be sent.\\
* 0: send data from the most significant bit \\
* 1: send data from the least significant bit \\
* Configures to control the sending order for data needing to be sent.
* 0: send data from the most significant bit
* 1: send data from the least significant bit
*/
#define I2C_TX_LSB_FIRST (BIT(6))
#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
#define I2C_TX_LSB_FIRST_V 0x00000001U
#define I2C_TX_LSB_FIRST_S 6
/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
* Configures to control the storage order for received data.\\
* 0: receive data from the most significant bit \\
* 1: receive data from the least significant bit \\
* Configures to control the storage order for received data.
* 0: receive data from the most significant bit
* 1: receive data from the least significant bit
*/
#define I2C_RX_LSB_FIRST (BIT(7))
#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
#define I2C_RX_LSB_FIRST_V 0x00000001U
#define I2C_RX_LSB_FIRST_S 7
/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
* Configures whether to gate clock signal for registers.\\
* 0: Support clock only when registers are read or written to by software \\
* 1: Force clock on for registers \\
* Configures whether to gate clock signal for registers.
* 0: Support clock only when registers are read or written to by software
* 1: Force clock on for registers
*/
#define I2C_CLK_EN (BIT(8))
#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S)
#define I2C_CLK_EN_V 0x00000001U
#define I2C_CLK_EN_S 8
/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
* Configures to enable I2C bus arbitration detection.\\
* 0: No effect \\
* 1: Enable \\
* Configures to enable I2C bus arbitration detection.
* 0: No effect
* 1: Enable
*/
#define I2C_ARBITRATION_EN (BIT(9))
#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
#define I2C_ARBITRATION_EN_V 0x00000001U
#define I2C_ARBITRATION_EN_S 9
/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
* Configures to reset the SCL_FSM.\\
* 0: No effect \\
* Configures to reset the SCL_FSM.
* 0: No effect
* 1: Reset
*/
#define I2C_FSM_RST (BIT(10))
@ -128,8 +128,8 @@ extern "C" {
#define I2C_FSM_RST_V 0x00000001U
#define I2C_FSM_RST_S 10
/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
* Configures this bit for synchronization.\\
* 0: No effect \\
* Configures this bit for synchronization.
* 0: No effect
* 1: Synchronize
*/
#define I2C_CONF_UPGATE (BIT(11))
@ -137,17 +137,17 @@ extern "C" {
#define I2C_CONF_UPGATE_V 0x00000001U
#define I2C_CONF_UPGATE_S 11
/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
* Configures to enable slave to send data automatically\\
* 0: Disable\\
* 1: Enable \\
* Configures to enable slave to send data automatically
* 0: Disable
* 1: Enable
*/
#define I2C_SLV_TX_AUTO_START_EN (BIT(12))
#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U
#define I2C_SLV_TX_AUTO_START_EN_S 12
/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
* Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\
* 0: Not check\\
* Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
* 0: Not check
* 1: Check
*/
#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13))
@ -155,9 +155,9 @@ extern "C" {
#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U
#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13
/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
* Configures to support the 7 bit general call function.\\
* 0: Not support \\
* 1: Support \\
* Configures to support the 7 bit general call function.
* 0: Not support
* 1: Support
*/
#define I2C_ADDR_BROADCASTING_EN (BIT(14))
#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
@ -169,8 +169,8 @@ extern "C" {
*/
#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
* Represents the received ACK value in master mode or slave mode.\\
* 0: ACK\\
* Represents the received ACK value in master mode or slave mode.
* 0: ACK
* 1: NACK.
*/
#define I2C_RESP_REC (BIT(0))
@ -178,8 +178,8 @@ extern "C" {
#define I2C_RESP_REC_V 0x00000001U
#define I2C_RESP_REC_S 0
/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
* Represents the transfer direction in slave mode.\\
* 1: Master reads from slave\\
* Represents the transfer direction in slave mode.
* 1: Master reads from slave
* 0: Master writes to slave.
*/
#define I2C_SLAVE_RW (BIT(1))
@ -187,18 +187,18 @@ extern "C" {
#define I2C_SLAVE_RW_V 0x00000001U
#define I2C_SLAVE_RW_S 1
/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
* Represents whether the I2C controller loses control of SCL line.\\
* 0: No arbitration lost\\
* 1: Arbitration lost\\
* Represents whether the I2C controller loses control of SCL line.
* 0: No arbitration lost
* 1: Arbitration lost
*/
#define I2C_ARB_LOST (BIT(3))
#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
#define I2C_ARB_LOST_V 0x00000001U
#define I2C_ARB_LOST_S 3
/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
* Represents the I2C bus state.\\
* 1: The I2C bus is busy transferring data\\
* 0: The I2C bus is in idle state.\\
* Represents the I2C bus state.
* 1: The I2C bus is busy transferring data
* 0: The I2C bus is in idle state.
*/
#define I2C_BUS_BUSY (BIT(4))
#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
@ -206,10 +206,10 @@ extern "C" {
#define I2C_BUS_BUSY_S 4
/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
* Represents whether the address sent by the master is equal to the address of the
* slave.\\
* Valid only when the module is configured as an I2C Slave.\\
* 0: Not equal\\
* 1: Equal\\
* slave.
* Valid only when the module is configured as an I2C Slave.
* 0: Not equal
* 1: Equal
*/
#define I2C_SLAVE_ADDRESSED (BIT(5))
#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
@ -223,9 +223,9 @@ extern "C" {
#define I2C_RXFIFO_CNT_V 0x0000003FU
#define I2C_RXFIFO_CNT_S 8
/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
* Represents the cause of SCL clocking stretching in slave mode.\\
* 0: Stretching SCL low when the master starts to read data.\\
* 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\
* Represents the cause of SCL clocking stretching in slave mode.
* 0: Stretching SCL low when the master starts to read data.
* 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
* 2: Stretching SCL low when I2C RX FIFO is full in slave mode.
*/
#define I2C_STRETCH_CAUSE 0x00000003U
@ -240,13 +240,13 @@ extern "C" {
#define I2C_TXFIFO_CNT_V 0x0000003FU
#define I2C_TXFIFO_CNT_S 18
/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
* Represents the states of the I2C module state machine.\\
* 0: Idle\\
* 1: Address shift\\
* 2: ACK address\\
* 3: Rx data\\
* 4: Tx data\\
* 5: Send ACK\\
* Represents the states of the I2C module state machine.
* 0: Idle
* 1: Address shift
* 2: ACK address
* 3: Rx data
* 4: Tx data
* 5: Send ACK
* 6: Wait ACK
*/
#define I2C_SCL_MAIN_STATE_LAST 0x00000007U
@ -254,13 +254,13 @@ extern "C" {
#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U
#define I2C_SCL_MAIN_STATE_LAST_S 24
/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
* Represents the states of the state machine used to produce SCL.\\
* 0: Idle\\
* 1: Start\\
* 2: Negative edge\\
* 3: Low\\
* 4: Positive edge\\
* 5: High\\
* Represents the states of the state machine used to produce SCL.
* 0: Idle
* 1: Start
* 2: Negative edge
* 3: Low
* 4: Positive edge
* 5: High
* 6: Stop
*/
#define I2C_SCL_STATE_LAST 0x00000007U
@ -274,17 +274,17 @@ extern "C" {
#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
* Configures the timeout threshold period for SCL stucking at high or low level. The
* actual period is 2\^{}(reg_time_out_value).\\
* Measurement unit: i2c_sclk \\
* actual period is 2\^{}(reg_time_out_value).
* Measurement unit: i2c_sclk
*/
#define I2C_TIME_OUT_VALUE 0x0000001FU
#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
#define I2C_TIME_OUT_VALUE_V 0x0000001FU
#define I2C_TIME_OUT_VALUE_S 0
/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
* Configures to enable time out control.\\
* 0: No effect \\
* 1: Enable \\
* Configures to enable time out control.
* 0: No effect
* 1: Enable
*/
#define I2C_TIME_OUT_EN (BIT(5))
#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
@ -296,16 +296,16 @@ extern "C" {
*/
#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
* Configure the slave address of I2C Slave.\\
* Configure the slave address of I2C Slave.
*/
#define I2C_SLAVE_ADDR 0x00007FFFU
#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
#define I2C_SLAVE_ADDR_V 0x00007FFFU
#define I2C_SLAVE_ADDR_S 0
/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
* Configures to enable the slave 10-bit addressing mode in master mode.\\
* 0: No effect \\
* 1: Enable \\
* Configures to enable the slave 10-bit addressing mode in master mode.
* 0: No effect
* 1: Enable
*/
#define I2C_ADDR_10BIT_EN (BIT(31))
#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
@ -387,17 +387,17 @@ extern "C" {
/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
* Configures the slave to enable dual address mode. When this mode is enabled, the
* byte received after the I2C address byte represents the offset address in the I2C
* Slave RAM. \\
* 0: Disable\\
* 1: Enable \\
* Slave RAM.
* 0: Disable
* 1: Enable
*/
#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U
#define I2C_FIFO_ADDR_CFG_EN_S 11
/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
* Configures to reset RXFIFO.\\
* 0: No effect \\
* Configures to reset RXFIFO.
* 0: No effect
* 1: Reset
*/
#define I2C_RX_FIFO_RST (BIT(12))
@ -405,8 +405,8 @@ extern "C" {
#define I2C_RX_FIFO_RST_V 0x00000001U
#define I2C_RX_FIFO_RST_S 12
/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
* Configures to reset TXFIFO.\\
* 0: No effect \\
* Configures to reset TXFIFO.
* 0: No effect
* 1: Reset
*/
#define I2C_TX_FIFO_RST (BIT(13))
@ -415,9 +415,9 @@ extern "C" {
#define I2C_TX_FIFO_RST_S 13
/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
* Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
* valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\
* 0: No effect \\
* 1: Enable \\
* valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
* 0: No effect
* 1: Enable
*/
#define I2C_FIFO_PRT_EN (BIT(14))
#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
@ -993,8 +993,8 @@ extern "C" {
*/
#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
* Configures the time to hold the data after the falling edge of SCL.\\
* Measurement unit: i2c_sclk \\
* Configures the time to hold the data after the falling edge of SCL.
* Measurement unit: i2c_sclk
*/
#define I2C_SDA_HOLD_TIME 0x000001FFU
#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
@ -1006,8 +1006,8 @@ extern "C" {
*/
#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
* Configures the time for sampling SDA.\\
* Measurement unit: i2c_sclk \\
* Configures the time for sampling SDA.
* Measurement unit: i2c_sclk
*/
#define I2C_SDA_SAMPLE_TIME 0x000001FFU
#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
@ -1019,16 +1019,16 @@ extern "C" {
*/
#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
* Configures for how long SCL remains high in master mode.\\
* Measurement unit: i2c_sclk \\
* Configures for how long SCL remains high in master mode.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_HIGH_PERIOD 0x000001FFU
#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU
#define I2C_SCL_HIGH_PERIOD_S 0
/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
* Configures the SCL_FSM's waiting period for SCL high level in master mode.\\
* Measurement unit: i2c_sclk \\
* Configures the SCL_FSM's waiting period for SCL high level in master mode.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU
#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
@ -1041,8 +1041,8 @@ extern "C" {
#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the falling edge of SDA and the falling edge of SCL for
* a START condition.\\
* Measurement unit: i2c_sclk \\
* a START condition.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_START_HOLD_TIME 0x000001FFU
#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
@ -1056,8 +1056,8 @@ extern "C" {
#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the positive edge of SCL and the negative edge of SDA
* for a RESTART condition.\\
* Measurement unit: i2c_sclk \\
* for a RESTART condition.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU
#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
@ -1070,8 +1070,8 @@ extern "C" {
*/
#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the delay after the STOP condition.\\
* Measurement unit: i2c_sclk \\
* Configures the delay after the STOP condition.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU
#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
@ -1100,7 +1100,7 @@ extern "C" {
* Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
* input has smaller width than this register value, the I2C controller will ignore
* that pulse.
* Measurement unit: i2c_sclk \\
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_FILTER_THRES 0x0000000FU
#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
@ -1110,97 +1110,57 @@ extern "C" {
* Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
* input has smaller width than this register value, the I2C controller will ignore
* that pulse.
* Measurement unit: i2c_sclk \\
* Measurement unit: i2c_sclk
*/
#define I2C_SDA_FILTER_THRES 0x0000000FU
#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
#define I2C_SDA_FILTER_THRES_V 0x0000000FU
#define I2C_SDA_FILTER_THRES_S 4
/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
* Configures to enable the filter function for SCL. \\
* 0: No effect \\
* 1: Enable \\
* Configures to enable the filter function for SCL.
* 0: No effect
* 1: Enable
*/
#define I2C_SCL_FILTER_EN (BIT(8))
#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
#define I2C_SCL_FILTER_EN_V 0x00000001U
#define I2C_SCL_FILTER_EN_S 8
/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
* Configures to enable the filter function for SDA. \\
* 0: No effect \\
* 1: Enable \\
* Configures to enable the filter function for SDA.
* 0: No effect
* 1: Enable
*/
#define I2C_SDA_FILTER_EN (BIT(9))
#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
#define I2C_SDA_FILTER_EN_V 0x00000001U
#define I2C_SDA_FILTER_EN_S 9
/** I2C_CLK_CONF_REG register
* I2C CLK configuration register
*/
#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54)
/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* the integral part of the fractional divisor for i2c module
*/
#define I2C_SCLK_DIV_NUM 0x000000FFU
#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S)
#define I2C_SCLK_DIV_NUM_V 0x000000FFU
#define I2C_SCLK_DIV_NUM_S 0
/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0;
* the numerator of the fractional part of the fractional divisor for i2c module
*/
#define I2C_SCLK_DIV_A 0x0000003FU
#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S)
#define I2C_SCLK_DIV_A_V 0x0000003FU
#define I2C_SCLK_DIV_A_S 8
/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0;
* the denominator of the fractional part of the fractional divisor for i2c module
*/
#define I2C_SCLK_DIV_B 0x0000003FU
#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S)
#define I2C_SCLK_DIV_B_V 0x0000003FU
#define I2C_SCLK_DIV_B_S 14
/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
* The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
*/
#define I2C_SCLK_SEL (BIT(20))
#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S)
#define I2C_SCLK_SEL_V 0x00000001U
#define I2C_SCLK_SEL_S 20
/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1;
* The clock switch for i2c module
*/
#define I2C_SCLK_ACTIVE (BIT(21))
#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S)
#define I2C_SCLK_ACTIVE_V 0x00000001U
#define I2C_SCLK_ACTIVE_S 21
/** I2C_COMD0_REG register
* I2C command register 0
*/
#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. \\
* It consists of three parts:\\
* op_code is the command\\
* 1: WRITE\\
* 2: STOP\\
* 3: READ\\
* 4: END\\
* 6: RSTART\\
* Byte_num represents the number of bytes that need to be sent or received.\\
* Configures command 0.
* It consists of three parts:
* op_code is the command
* 1: WRITE
* 2: STOP
* 3: READ
* 4: END
* 6: RSTART
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure <a href=fig:i2c-cmd-structure">link</a> for more information.
* \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
* structure for more information.
* \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
*/
#define I2C_COMMAND0 0x00003FFFU
#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S)
#define I2C_COMMAND0_V 0x00003FFFU
#define I2C_COMMAND0_S 0
/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 0 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND0_DONE (BIT(31))
#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
@ -1212,7 +1172,7 @@ extern "C" {
*/
#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1.\\
* Configures command 1.
* See details in I2C_CMD0_REG[13:0].
*/
#define I2C_COMMAND1 0x00003FFFU
@ -1220,9 +1180,9 @@ extern "C" {
#define I2C_COMMAND1_V 0x00003FFFU
#define I2C_COMMAND1_S 0
/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 1 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 1 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND1_DONE (BIT(31))
#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
@ -1241,9 +1201,9 @@ extern "C" {
#define I2C_COMMAND2_V 0x00003FFFU
#define I2C_COMMAND2_S 0
/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 2 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 2 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND2_DONE (BIT(31))
#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
@ -1262,9 +1222,9 @@ extern "C" {
#define I2C_COMMAND3_V 0x00003FFFU
#define I2C_COMMAND3_S 0
/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 3 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 3 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND3_DONE (BIT(31))
#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
@ -1283,9 +1243,9 @@ extern "C" {
#define I2C_COMMAND4_V 0x00003FFFU
#define I2C_COMMAND4_S 0
/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 4 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 4 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND4_DONE (BIT(31))
#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
@ -1304,9 +1264,9 @@ extern "C" {
#define I2C_COMMAND5_V 0x00003FFFU
#define I2C_COMMAND5_S 0
/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 5 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 5 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND5_DONE (BIT(31))
#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
@ -1325,9 +1285,9 @@ extern "C" {
#define I2C_COMMAND6_V 0x00003FFFU
#define I2C_COMMAND6_S 0
/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 6 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 6 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND6_DONE (BIT(31))
#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
@ -1346,9 +1306,9 @@ extern "C" {
#define I2C_COMMAND7_V 0x00003FFFU
#define I2C_COMMAND7_S 0
/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 7 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
* Represents whether command 7 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
#define I2C_COMMAND7_DONE (BIT(31))
#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
@ -1361,8 +1321,8 @@ extern "C" {
#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_FSM state unchanged period. It should be no
* more than 23.\\
* Measurement unit: i2c_sclk \\
* more than 23.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_ST_TO_I2C 0x0000001FU
#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
@ -1375,8 +1335,8 @@ extern "C" {
#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
* no more than 23.\\
* Measurement unit: i2c_sclk \\
* no more than 23.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU
#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
@ -1396,18 +1356,18 @@ extern "C" {
#define I2C_SCL_RST_SLV_EN_V 0x00000001U
#define I2C_SCL_RST_SLV_EN_S 0
/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
* Configure the pulses of SCL generated in I2C master mode. \\
* Valid when I2C_SCL_RST_SLV_EN is 1.\\
* Measurement unit: i2c_sclk \\
* Configure the pulses of SCL generated in I2C master mode.
* Valid when I2C_SCL_RST_SLV_EN is 1.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_RST_SLV_NUM 0x0000001FU
#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU
#define I2C_SCL_RST_SLV_NUM_S 1
/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
* Configures to power down the I2C output SCL line. \\
* 0: Not power down.\\
* 1: Not work and power down.\\
* Configures to power down the I2C output SCL line.
* 0: Not power down.
* 1: Not work and power down.
* Valid only when I2C_SCL_FORCE_OUT is 1.
*/
#define I2C_SCL_PD_EN (BIT(6))
@ -1415,9 +1375,9 @@ extern "C" {
#define I2C_SCL_PD_EN_V 0x00000001U
#define I2C_SCL_PD_EN_S 6
/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
* Configures to power down the I2C output SDA line. \\
* 0: Not power down.\\
* 1: Not work and power down.\\
* Configures to power down the I2C output SDA line.
* 0: Not power down.
* 1: Not work and power down.
* Valid only when I2C_SDA_FORCE_OUT is 1.
*/
#define I2C_SDA_PD_EN (BIT(7))
@ -1431,8 +1391,8 @@ extern "C" {
#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
* Configures the time period to release the SCL line from stretching to avoid timing
* violation. Usually it should be larger than the SDA setup time.\\
* Measurement unit: i2c_sclk \\
* violation. Usually it should be larger than the SDA setup time.
* Measurement unit: i2c_sclk
*/
#define I2C_STRETCH_PROTECT_NUM 0x000003FFU
#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
@ -1441,36 +1401,36 @@ extern "C" {
/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
* Configures to enable slave SCL stretch function. The SCL output line will be
* stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
* stretch cause can be seen in I2C_STRETCH_CAUSE.\\
* 0: Disable \\
* 1: Enable \\
* stretch cause can be seen in I2C_STRETCH_CAUSE.
* 0: Disable
* 1: Enable
*/
#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10))
#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U
#define I2C_SLAVE_SCL_STRETCH_EN_S 10
/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
* Configures to clear the I2C slave SCL stretch function.\\
* 0: No effect \\
* 1: Clear\\
* Configures to clear the I2C slave SCL stretch function.
* 0: No effect
* 1: Clear
*/
#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11))
#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U
#define I2C_SLAVE_SCL_STRETCH_CLR_S 11
/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
* Configures to enable the function for slave to control ACK level.\\
* 0: Disable \\
* 1: Enable \\
* Configures to enable the function for slave to control ACK level.
* 0: Disable
* 1: Enable
*/
#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12))
#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U
#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12
/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
* Set the ACK level when slave controlling ACK level function enables.\\
* 0: Low level\\
* 1: High level \\
* Set the ACK level when slave controlling ACK level function enables.
* 0: Low level
* 1: High level
*/
#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13))
#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
@ -1481,7 +1441,7 @@ extern "C" {
* Version register
*/
#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
/** I2C_DATE : R/W; bitpos: [31:0]; default: 37752896;
/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765248;
* Version control register.
*/
#define I2C_DATE 0xFFFFFFFFU

375
components/soc/esp32c61/register/soc/i2c_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,8 +18,8 @@ extern "C" {
typedef union {
struct {
/** scl_low_period : R/W; bitpos: [8:0]; default: 0;
* Configures the low level width of the SCL Clock in master mode. \\
* Measurement unit: i2c_sclk \\
* Configures the low level width of the SCL Clock in master mode.
* Measurement unit: i2c_sclk
*/
uint32_t scl_low_period:9;
uint32_t reserved_9:23;
@ -33,8 +33,8 @@ typedef union {
typedef union {
struct {
/** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
* Configures the time to hold the data after the falling edge of SCL.\\
* Measurement unit: i2c_sclk \\
* Configures the time to hold the data after the falling edge of SCL.
* Measurement unit: i2c_sclk
*/
uint32_t sda_hold_time:9;
uint32_t reserved_9:23;
@ -48,8 +48,8 @@ typedef union {
typedef union {
struct {
/** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
* Configures the time for sampling SDA.\\
* Measurement unit: i2c_sclk \\
* Configures the time for sampling SDA.
* Measurement unit: i2c_sclk
*/
uint32_t sda_sample_time:9;
uint32_t reserved_9:23;
@ -63,13 +63,13 @@ typedef union {
typedef union {
struct {
/** scl_high_period : R/W; bitpos: [8:0]; default: 0;
* Configures for how long SCL remains high in master mode.\\
* Measurement unit: i2c_sclk \\
* Configures for how long SCL remains high in master mode.
* Measurement unit: i2c_sclk
*/
uint32_t scl_high_period:9;
/** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
* Configures the SCL_FSM's waiting period for SCL high level in master mode.\\
* Measurement unit: i2c_sclk \\
* Configures the SCL_FSM's waiting period for SCL high level in master mode.
* Measurement unit: i2c_sclk
*/
uint32_t scl_wait_high_period:7;
uint32_t reserved_16:16;
@ -84,8 +84,8 @@ typedef union {
struct {
/** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the falling edge of SDA and the falling edge of SCL for
* a START condition.\\
* Measurement unit: i2c_sclk \\
* a START condition.
* Measurement unit: i2c_sclk
*/
uint32_t scl_start_hold_time:9;
uint32_t reserved_9:23;
@ -101,8 +101,8 @@ typedef union {
struct {
/** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the positive edge of SCL and the negative edge of SDA
* for a RESTART condition.\\
* Measurement unit: i2c_sclk \\
* for a RESTART condition.
* Measurement unit: i2c_sclk
*/
uint32_t scl_rstart_setup_time:9;
uint32_t reserved_9:23;
@ -117,8 +117,8 @@ typedef union {
typedef union {
struct {
/** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
* Configures the delay after the STOP condition.\\
* Measurement unit: i2c_sclk \\
* Configures the delay after the STOP condition.
* Measurement unit: i2c_sclk
*/
uint32_t scl_stop_hold_time:9;
uint32_t reserved_9:23;
@ -149,8 +149,8 @@ typedef union {
struct {
/** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_FSM state unchanged period. It should be no
* more than 23.\\
* Measurement unit: i2c_sclk \\
* more than 23.
* Measurement unit: i2c_sclk
*/
uint32_t scl_st_to_i2c:5;
uint32_t reserved_5:27;
@ -165,8 +165,8 @@ typedef union {
struct {
/** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
* no more than 23.\\
* Measurement unit: i2c_sclk \\
* no more than 23.
* Measurement unit: i2c_sclk
*/
uint32_t scl_main_st_to_i2c:5;
uint32_t reserved_5:27;
@ -182,92 +182,92 @@ typedef union {
typedef union {
struct {
/** sda_force_out : R/W; bitpos: [0]; default: 0;
* Configures the SDA output mode.\\
* 0: Open drain output \\
* 1: Direct output \\
* Configures the SDA output mode.
* 0: Open drain output
* 1: Direct output
*/
uint32_t sda_force_out:1;
/** scl_force_out : R/W; bitpos: [1]; default: 0;
* Configures the SCL output mode.\\
* 0: Open drain output \\
* 1: Direct output \\
* Configures the SCL output mode.
* 0: Open drain output
* 1: Direct output
*/
uint32_t scl_force_out:1;
/** sample_scl_level : R/W; bitpos: [2]; default: 0;
* Configures the sample mode for SDA.\\
* 0: Sample SDA data on the SCL high level \\
* 1: Sample SDA data on the SCL low level \\
* Configures the sample mode for SDA.
* 0: Sample SDA data on the SCL high level
* 1: Sample SDA data on the SCL low level
*/
uint32_t sample_scl_level:1;
/** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
* Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
* reached the threshold.\\
* reached the threshold.
*/
uint32_t rx_full_ack_level:1;
/** ms_mode : R/W; bitpos: [4]; default: 0;
* Configures the module as an I2C Master or Slave.\\
* 0: Slave \\
* 1: Master \\
* Configures the module as an I2C Master or Slave.
* 0: Slave
* 1: Master
*/
uint32_t ms_mode:1;
/** trans_start : WT; bitpos: [5]; default: 0;
* Configures whether the slave starts sending the data in txfifo.\\
* 0: No effect \\
* Configures whether the slave starts sending the data in txfifo.
* 0: No effect
* 1: Start
*/
uint32_t trans_start:1;
/** tx_lsb_first : R/W; bitpos: [6]; default: 0;
* Configures to control the sending order for data needing to be sent.\\
* 0: send data from the most significant bit \\
* 1: send data from the least significant bit \\
* Configures to control the sending order for data needing to be sent.
* 0: send data from the most significant bit
* 1: send data from the least significant bit
*/
uint32_t tx_lsb_first:1;
/** rx_lsb_first : R/W; bitpos: [7]; default: 0;
* Configures to control the storage order for received data.\\
* 0: receive data from the most significant bit \\
* 1: receive data from the least significant bit \\
* Configures to control the storage order for received data.
* 0: receive data from the most significant bit
* 1: receive data from the least significant bit
*/
uint32_t rx_lsb_first:1;
/** clk_en : R/W; bitpos: [8]; default: 0;
* Configures whether to gate clock signal for registers.\\
* 0: Support clock only when registers are read or written to by software \\
* 1: Force clock on for registers \\
* Configures whether to gate clock signal for registers.
* 0: Support clock only when registers are read or written to by software
* 1: Force clock on for registers
*/
uint32_t clk_en:1;
/** arbitration_en : R/W; bitpos: [9]; default: 1;
* Configures to enable I2C bus arbitration detection.\\
* 0: No effect \\
* 1: Enable \\
* Configures to enable I2C bus arbitration detection.
* 0: No effect
* 1: Enable
*/
uint32_t arbitration_en:1;
/** fsm_rst : WT; bitpos: [10]; default: 0;
* Configures to reset the SCL_FSM.\\
* 0: No effect \\
* Configures to reset the SCL_FSM.
* 0: No effect
* 1: Reset
*/
uint32_t fsm_rst:1;
/** conf_upgate : WT; bitpos: [11]; default: 0;
* Configures this bit for synchronization.\\
* 0: No effect \\
* Configures this bit for synchronization.
* 0: No effect
* 1: Synchronize
*/
uint32_t conf_upgate:1;
/** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
* Configures to enable slave to send data automatically\\
* 0: Disable\\
* 1: Enable \\
* Configures to enable slave to send data automatically
* 0: Disable
* 1: Enable
*/
uint32_t slv_tx_auto_start_en:1;
/** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
* Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\
* 0: Not check\\
* Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
* 0: Not check
* 1: Check
*/
uint32_t addr_10bit_rw_check_en:1;
/** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
* Configures to support the 7 bit general call function.\\
* 0: Not support \\
* 1: Support \\
* Configures to support the 7 bit general call function.
* 0: Not support
* 1: Support
*/
uint32_t addr_broadcasting_en:1;
uint32_t reserved_15:17;
@ -282,14 +282,14 @@ typedef union {
struct {
/** time_out_value : R/W; bitpos: [4:0]; default: 16;
* Configures the timeout threshold period for SCL stucking at high or low level. The
* actual period is 2\^{}(reg_time_out_value).\\
* Measurement unit: i2c_sclk \\
* actual period is 2\^{}(reg_time_out_value).
* Measurement unit: i2c_sclk
*/
uint32_t time_out_value:5;
/** time_out_en : R/W; bitpos: [5]; default: 0;
* Configures to enable time out control.\\
* 0: No effect \\
* 1: Enable \\
* Configures to enable time out control.
* 0: No effect
* 1: Enable
*/
uint32_t time_out_en:1;
uint32_t reserved_6:26;
@ -303,14 +303,14 @@ typedef union {
typedef union {
struct {
/** slave_addr : R/W; bitpos: [14:0]; default: 0;
* Configure the slave address of I2C Slave.\\
* Configure the slave address of I2C Slave.
*/
uint32_t slave_addr:15;
uint32_t reserved_15:16;
/** addr_10bit_en : R/W; bitpos: [31]; default: 0;
* Configures to enable the slave 10-bit addressing mode in master mode.\\
* 0: No effect \\
* 1: Enable \\
* Configures to enable the slave 10-bit addressing mode in master mode.
* 0: No effect
* 1: Enable
*/
uint32_t addr_10bit_en:1;
};
@ -343,28 +343,28 @@ typedef union {
/** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
* Configures the slave to enable dual address mode. When this mode is enabled, the
* byte received after the I2C address byte represents the offset address in the I2C
* Slave RAM. \\
* 0: Disable\\
* 1: Enable \\
* Slave RAM.
* 0: Disable
* 1: Enable
*/
uint32_t fifo_addr_cfg_en:1;
/** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
* Configures to reset RXFIFO.\\
* 0: No effect \\
* Configures to reset RXFIFO.
* 0: No effect
* 1: Reset
*/
uint32_t rx_fifo_rst:1;
/** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
* Configures to reset TXFIFO.\\
* 0: No effect \\
* Configures to reset TXFIFO.
* 0: No effect
* 1: Reset
*/
uint32_t tx_fifo_rst:1;
/** fifo_prt_en : R/W; bitpos: [14]; default: 1;
* Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
* valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\
* 0: No effect \\
* 1: Enable \\
* valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
* 0: No effect
* 1: Enable
*/
uint32_t fifo_prt_en:1;
uint32_t reserved_15:17;
@ -381,26 +381,26 @@ typedef union {
* Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
* input has smaller width than this register value, the I2C controller will ignore
* that pulse.
* Measurement unit: i2c_sclk \\
* Measurement unit: i2c_sclk
*/
uint32_t scl_filter_thres:4;
/** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
* Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
* input has smaller width than this register value, the I2C controller will ignore
* that pulse.
* Measurement unit: i2c_sclk \\
* Measurement unit: i2c_sclk
*/
uint32_t sda_filter_thres:4;
/** scl_filter_en : R/W; bitpos: [8]; default: 1;
* Configures to enable the filter function for SCL. \\
* 0: No effect \\
* 1: Enable \\
* Configures to enable the filter function for SCL.
* 0: No effect
* 1: Enable
*/
uint32_t scl_filter_en:1;
/** sda_filter_en : R/W; bitpos: [9]; default: 1;
* Configures to enable the filter function for SDA. \\
* 0: No effect \\
* 1: Enable \\
* Configures to enable the filter function for SDA.
* 0: No effect
* 1: Enable
*/
uint32_t sda_filter_en:1;
uint32_t reserved_10:22;
@ -408,36 +408,6 @@ typedef union {
uint32_t val;
} i2c_filter_cfg_reg_t;
/** Type of clk_conf register
* I2C CLK configuration register
*/
typedef union {
struct {
/** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
* the integral part of the fractional divisor for i2c module
*/
uint32_t sclk_div_num:8;
/** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
* the numerator of the fractional part of the fractional divisor for i2c module
*/
uint32_t sclk_div_a:6;
/** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
* the denominator of the fractional part of the fractional divisor for i2c module
*/
uint32_t sclk_div_b:6;
/** sclk_sel : R/W; bitpos: [20]; default: 0;
* The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
*/
uint32_t sclk_sel:1;
/** sclk_active : R/W; bitpos: [21]; default: 1;
* The clock switch for i2c module
*/
uint32_t sclk_active:1;
uint32_t reserved_22:10;
};
uint32_t val;
} i2c_clk_conf_reg_t;
/** Type of scl_sp_conf register
* Power configuration register
*/
@ -449,22 +419,22 @@ typedef union {
*/
uint32_t scl_rst_slv_en:1;
/** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
* Configure the pulses of SCL generated in I2C master mode. \\
* Valid when I2C_SCL_RST_SLV_EN is 1.\\
* Measurement unit: i2c_sclk \\
* Configure the pulses of SCL generated in I2C master mode.
* Valid when I2C_SCL_RST_SLV_EN is 1.
* Measurement unit: i2c_sclk
*/
uint32_t scl_rst_slv_num:5;
/** scl_pd_en : R/W; bitpos: [6]; default: 0;
* Configures to power down the I2C output SCL line. \\
* 0: Not power down.\\
* 1: Not work and power down.\\
* Configures to power down the I2C output SCL line.
* 0: Not power down.
* 1: Not work and power down.
* Valid only when I2C_SCL_FORCE_OUT is 1.
*/
uint32_t scl_pd_en:1;
/** sda_pd_en : R/W; bitpos: [7]; default: 0;
* Configures to power down the I2C output SDA line. \\
* 0: Not power down.\\
* 1: Not work and power down.\\
* Configures to power down the I2C output SDA line.
* 0: Not power down.
* 1: Not work and power down.
* Valid only when I2C_SDA_FORCE_OUT is 1.
*/
uint32_t sda_pd_en:1;
@ -480,34 +450,34 @@ typedef union {
struct {
/** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
* Configures the time period to release the SCL line from stretching to avoid timing
* violation. Usually it should be larger than the SDA setup time.\\
* Measurement unit: i2c_sclk \\
* violation. Usually it should be larger than the SDA setup time.
* Measurement unit: i2c_sclk
*/
uint32_t stretch_protect_num:10;
/** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
* Configures to enable slave SCL stretch function. The SCL output line will be
* stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
* stretch cause can be seen in I2C_STRETCH_CAUSE.\\
* 0: Disable \\
* 1: Enable \\
* stretch cause can be seen in I2C_STRETCH_CAUSE.
* 0: Disable
* 1: Enable
*/
uint32_t slave_scl_stretch_en:1;
/** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
* Configures to clear the I2C slave SCL stretch function.\\
* 0: No effect \\
* 1: Clear\\
* Configures to clear the I2C slave SCL stretch function.
* 0: No effect
* 1: Clear
*/
uint32_t slave_scl_stretch_clr:1;
/** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
* Configures to enable the function for slave to control ACK level.\\
* 0: Disable \\
* 1: Enable \\
* Configures to enable the function for slave to control ACK level.
* 0: Disable
* 1: Enable
*/
uint32_t slave_byte_ack_ctl_en:1;
/** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
* Set the ACK level when slave controlling ACK level function enables.\\
* 0: Low level\\
* 1: High level \\
* Set the ACK level when slave controlling ACK level function enables.
* 0: Low level
* 1: High level
*/
uint32_t slave_byte_ack_lvl:1;
uint32_t reserved_14:18;
@ -523,36 +493,36 @@ typedef union {
typedef union {
struct {
/** resp_rec : RO; bitpos: [0]; default: 0;
* Represents the received ACK value in master mode or slave mode.\\
* 0: ACK\\
* Represents the received ACK value in master mode or slave mode.
* 0: ACK
* 1: NACK.
*/
uint32_t resp_rec:1;
/** slave_rw : RO; bitpos: [1]; default: 0;
* Represents the transfer direction in slave mode.\\
* 1: Master reads from slave\\
* Represents the transfer direction in slave mode.
* 1: Master reads from slave
* 0: Master writes to slave.
*/
uint32_t slave_rw:1;
uint32_t reserved_2:1;
/** arb_lost : RO; bitpos: [3]; default: 0;
* Represents whether the I2C controller loses control of SCL line.\\
* 0: No arbitration lost\\
* 1: Arbitration lost\\
* Represents whether the I2C controller loses control of SCL line.
* 0: No arbitration lost
* 1: Arbitration lost
*/
uint32_t arb_lost:1;
/** bus_busy : RO; bitpos: [4]; default: 0;
* Represents the I2C bus state.\\
* 1: The I2C bus is busy transferring data\\
* 0: The I2C bus is in idle state.\\
* Represents the I2C bus state.
* 1: The I2C bus is busy transferring data
* 0: The I2C bus is in idle state.
*/
uint32_t bus_busy:1;
/** slave_addressed : RO; bitpos: [5]; default: 0;
* Represents whether the address sent by the master is equal to the address of the
* slave.\\
* Valid only when the module is configured as an I2C Slave.\\
* 0: Not equal\\
* 1: Equal\\
* slave.
* Valid only when the module is configured as an I2C Slave.
* 0: Not equal
* 1: Equal
*/
uint32_t slave_addressed:1;
uint32_t reserved_6:2;
@ -561,9 +531,9 @@ typedef union {
*/
uint32_t rxfifo_cnt:6;
/** stretch_cause : RO; bitpos: [15:14]; default: 3;
* Represents the cause of SCL clocking stretching in slave mode.\\
* 0: Stretching SCL low when the master starts to read data.\\
* 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\
* Represents the cause of SCL clocking stretching in slave mode.
* 0: Stretching SCL low when the master starts to read data.
* 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
* 2: Stretching SCL low when I2C RX FIFO is full in slave mode.
*/
uint32_t stretch_cause:2;
@ -573,25 +543,25 @@ typedef union {
*/
uint32_t txfifo_cnt:6;
/** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
* Represents the states of the I2C module state machine.\\
* 0: Idle\\
* 1: Address shift\\
* 2: ACK address\\
* 3: Rx data\\
* 4: Tx data\\
* 5: Send ACK\\
* Represents the states of the I2C module state machine.
* 0: Idle
* 1: Address shift
* 2: ACK address
* 3: Rx data
* 4: Tx data
* 5: Send ACK
* 6: Wait ACK
*/
uint32_t scl_main_state_last:3;
uint32_t reserved_27:1;
/** scl_state_last : RO; bitpos: [30:28]; default: 0;
* Represents the states of the state machine used to produce SCL.\\
* 0: Idle\\
* 1: Start\\
* 2: Negative edge\\
* 3: Low\\
* 4: Positive edge\\
* 5: High\\
* Represents the states of the state machine used to produce SCL.
* 0: Idle
* 1: Start
* 2: Negative edge
* 3: Low
* 4: Positive edge
* 5: High
* 6: Stop
*/
uint32_t scl_state_last:3;
@ -1000,38 +970,39 @@ typedef union {
typedef union {
struct {
/** command : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. \\
* It consists of three parts:\\
* op_code is the command\\
* 1: WRITE\\
* 2: STOP\\
* 3: READ\\
* 4: END\\
* 6: RSTART\\
* Byte_num represents the number of bytes that need to be sent or received.\\
* Configures command 0.
* It consists of three parts:
* op_code is the command
* 1: WRITE
* 2: STOP
* 3: READ
* 4: END
* 6: RSTART
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure <a href=fig:i2c-cmd-structure">link</a> for more information.
* \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
* structure for more information.
* \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
*/
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.
* 0: Not done
* 1: Done
*/
uint32_t command_done:1;
};
uint32_t val;
} i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 37752896;
/** date : R/W; bitpos: [31:0]; default: 37765248;
* Version control register.
*/
uint32_t date:32;
@ -1040,6 +1011,34 @@ typedef union {
} i2c_date_reg_t;
/** Group: Address register */
/** Type of txfifo_start_addr register
* I2C TXFIFO base address register
*/
typedef union {
struct {
/** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C txfifo first address.
*/
uint32_t txfifo_start_addr:32;
};
uint32_t val;
} i2c_txfifo_start_addr_reg_t;
/** Type of rxfifo_start_addr register
* I2C RXFIFO base address register
*/
typedef union {
struct {
/** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C rxfifo first address.
*/
uint32_t rxfifo_start_addr:32;
};
uint32_t val;
} i2c_rxfifo_start_addr_reg_t;
typedef struct {
volatile i2c_scl_low_period_reg_t scl_low_period;
volatile i2c_ctr_reg_t ctr;
@ -1062,7 +1061,7 @@ typedef struct {
volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
volatile i2c_clk_conf_reg_t clk_conf;
uint32_t reserved_054;
volatile i2c_comd_reg_t command[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;

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components/soc/esp32c61/register/soc/interrupt_matrix_reg.h
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components/soc/esp32c61/register/soc/interrupt_matrix_struct.h
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components/soc/esp32c61/register/soc/io_mux_reg.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -73,59 +73,38 @@ extern "C" {
#define FILTER_EN_V 1
#define FILTER_EN_S 15
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS1_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_VDD_SPI_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_SDIO_DATA2_U
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_SDIO_DATA3_U
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_SDIO_CMD_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SDIO_CLK_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SDIO_DATA0_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SDIO_DATA1_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTMS
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTDI
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTCK
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_MTDO
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0RXD
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0TXD
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SPICS1
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SPICS0
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SPIQ
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SPIWP
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define PIN_FUNC_GPIO 1
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
@ -141,111 +120,136 @@ extern "C" {
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0)
#define FUNC_XTAL_32K_P_GPIO0 1
#define FUNC_XTAL_32K_P_GPIO0_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_XTAL_32K_P_GPIO0_0 0
#define FUNC_XTAL_32K_P_GPIO0 1
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4)
#define FUNC_XTAL_32K_N_GPIO1 1
#define FUNC_XTAL_32K_N_GPIO1_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_XTAL_32K_N_GPIO1_0 0
#define FUNC_XTAL_32K_N_GPIO1 1
#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8)
#define FUNC_GPIO2_FSPIQ 2
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO2_GPIO2_0 0
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_FSPIQ 2
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC)
#define FUNC_MTMS_FSPIHD 2
#define FUNC_MTMS_GPIO3 1
#define FUNC_MTMS_MTMS 0
// Strapping: Boot Mode select 0/SDIO input strapping
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_MTMS_MTMS 0
#define FUNC_MTMS_GPIO3 1
#define FUNC_MTMS_FSPIHD 2
#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10)
#define FUNC_MTDI_FSPIWP 2
#define FUNC_MTDI_GPIO4 1
#define FUNC_MTDI_MTDI 0
// Strapping: Boot Mode select 1/SDIO output strapping
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_MTDI_MTDI 0
#define FUNC_MTDI_GPIO4 1
#define FUNC_MTDI_FSPIWP 2
#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14)
#define FUNC_MTCK_GPIO5 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_MTCK_MTCK 0
#define FUNC_MTCK_GPIO5 1
#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18)
#define FUNC_MTDO_FSPICLK 2
#define FUNC_MTDO_GPIO6 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_MTDO_MTDO 0
#define FUNC_MTDO_GPIO6 1
#define FUNC_MTDO_FSPICLK 2
#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO7_FSPID 2
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
// Strapping: JTAG select
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO7_GPIO7_0 0
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_FSPID 2
#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO8_FSPICS0 2
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
// Strapping: Boot Mode select 2
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO8_GPIO8_0 0
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_FSPICS0 2
#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
// Strapping: Boot Mode select 3
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO9_GPIO9_0 0
#define FUNC_GPIO9_GPIO9 1
#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x28)
#define FUNC_U0RXD_GPIO10 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_U0RXD_U0RXD 0
#define FUNC_U0RXD_GPIO10 1
#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C)
#define FUNC_U0TXD_GPIO11 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_U0TXD_U0TXD 0
#define FUNC_U0TXD_GPIO11 1
#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30)
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO12_GPIO12_0 0
#define FUNC_GPIO12_GPIO12 1
#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO13_GPIO13_0 0
#define FUNC_GPIO13_GPIO13 1
#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x38)
#define FUNC_SPICS1_GPIO14 1
#define FUNC_SPICS1_SPICS1 0
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPICS1_SPICS1 0
#define FUNC_SPICS1_GPIO14 1
#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x3C)
#define FUNC_SPICS0_GPIO15 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPICS0_SPICS0 0
#define FUNC_SPICS0_GPIO15 1
#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x40)
#define FUNC_SPIQ_GPIO16 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPIQ_SPIQ 0
#define FUNC_SPIQ_GPIO16 1
#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x44)
#define FUNC_SPIWP_GPIO17 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPIWP_SPIWP 0
#define FUNC_SPIWP_GPIO17 1
#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x48)
#define FUNC_VDD_SPI_GPIO18 1
#define FUNC_VDD_SPI_GPIO18_0 0
#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_VDD_SPI_GPIO18_0 0
#define FUNC_VDD_SPI_GPIO18 1
#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x4C)
#define FUNC_SPIHD_GPIO19 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPIHD_SPIHD 0
#define FUNC_SPIHD_GPIO19 1
#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x50)
#define FUNC_SPICLK_GPIO20 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPICLK_SPICLK 0
#define FUNC_SPICLK_GPIO20 1
#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x54)
#define FUNC_SPID_GPIO21 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SPID_SPID 0
#define FUNC_SPID_GPIO21 1
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SDIO_DATA2_SDIO_DATA2 0
#define FUNC_SDIO_DATA2_GPIO22 1
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SDIO_DATA3_SDIO_DATA3 0
#define FUNC_SDIO_DATA3_GPIO23 1
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO24_GPIO24_0 0
#define FUNC_GPIO24_GPIO24 1
#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SDIO_CMD_SDIO_CMD 0
#define FUNC_SDIO_CMD_GPIO25 1
#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SDIO_CLK_SDIO_CLK 0
#define FUNC_SDIO_CLK_GPIO26 1
#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SDIO_DATA0_SDIO_DATA0 0
#define FUNC_SDIO_DATA0_GPIO27 1
#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_SDIO_DATA1_SDIO_DATA1 0
#define FUNC_SDIO_DATA1_GPIO28 1
#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO29_GPIO29_0 0
#define FUNC_GPIO29_GPIO29 1
/** IO_MUX_DATE_REG register
* Version control register

85
components/soc/esp32c61/register/soc/io_mux_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,100 +10,73 @@
extern "C" {
#endif
/** Group: Configuration Registers */
/** Group: Configure Registers */
/** Type of gpion register
* IO MUX configuration register for GPIOn
* IO_MUX Configure Register
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn in sleep mode.
* 0: Disable\\
* 1: Enable\\
* Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for GPIOn.\\
* 0: Not enter\\
* 1: Enter\\
* Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
*/
uint32_t gpion_slp_sel:1;
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.\\
* 0: Disable\\
* 1: Enable\\
* Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0:
* internal pull-down disabled.
*/
uint32_t gpion_mcu_wpd:1;
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. \\
* 0: Disable\\
* 1: Enable\\
* Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0:
* internal pull-up disabled.
*/
uint32_t gpion_mcu_wpu:1;
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.\\
* 0: Disable\\
* 1: Enable\\
* Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_mcu_ie:1;
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode. \\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
* Select the drive strength of the pad during sleep mode.
*/
uint32_t gpion_mcu_drv:2;
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of GPIOn.\\
* 0: Disable\\
* 1: Enable\\
* Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down
* disabled.
*/
uint32_t gpion_fun_wpd:1;
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of GPIOn.\\
* 0: Disable\\
* 1: Enable\\
* Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up
* disabled.
*/
uint32_t gpion_fun_wpu:1;
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of GPIOn.\\
* 0: Disable\\
* 1: Enable\\
* Input enable of the pad. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_fun_ie:1;
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn. \\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
* Select the drive strength of the pad.
*/
uint32_t gpion_fun_drv:2;
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select IO MUX function for this signal. \\
* 0: Select Function 0\\
* 1: Select Function 1\\
* ......\\
* Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2.
* etc.
*/
uint32_t gpion_mcu_sel:3;
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.\\
* 0: Disable\\
* 1: Enable\\
* Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.
*/
uint32_t gpion_filter_en:1;
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.\\
* 0: Disable\\
* 1: Enable\\
* Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0:
* Hysteresis disabled.
*/
uint32_t gpion_hys_en:1;
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn. \\
* 0: Choose the output enable signal of eFuse, there is no efuse bit for it, should never set to 0\\
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN, always set to 1\\
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling signal from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t gpion_hys_sel:1;
uint32_t reserved_18:14;
@ -111,14 +84,12 @@ typedef union {
uint32_t val;
} io_mux_gpion_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
* IO_MUX Version Control Register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 36774288;
/** reg_date : R/W; bitpos: [27:0]; default: 37823072;
* Version control register
*/
uint32_t reg_date:28;
@ -129,8 +100,8 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t gpion[25];
uint32_t reserved_064[102];
volatile io_mux_gpion_reg_t gpion[30];
uint32_t reserved_078[97];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;

34
components/soc/esp32c61/register/soc/lp_aon_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -290,31 +290,17 @@ extern "C" {
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
/** LP_AON_SDIO_ACTIVE_REG register
* need_des
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0;
* This field controls fast memory WPULSE parameter.
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
#define LP_AON_FAST_MEM_WPULSE 0x00000007U
#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S)
#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U
#define LP_AON_FAST_MEM_WPULSE_S 16
/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4;
* This field controls fast memory WA parameter.
*/
#define LP_AON_FAST_MEM_WA 0x00000007U
#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S)
#define LP_AON_FAST_MEM_WA_V 0x00000007U
#define LP_AON_FAST_MEM_WA_S 19
/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0;
* This field controls fast memory RA parameter.
*/
#define LP_AON_FAST_MEM_RA 0x00000003U
#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S)
#define LP_AON_FAST_MEM_RA_V 0x00000003U
#define LP_AON_FAST_MEM_RA_S 22
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_S 22
/** LP_AON_LPCORE_REG register
* need_des
@ -439,7 +425,7 @@ extern "C" {
* need_des
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36766272;
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823232;
* need_des
*/
#define LP_AON_DATE 0x7FFFFFFFU

29
components/soc/esp32c61/register/soc/lp_aon_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -287,28 +287,19 @@ typedef union {
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of lpbus register
/** Type of sdio_active register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0;
* This field controls fast memory WPULSE parameter.
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
uint32_t fast_mem_wpulse:3;
/** fast_mem_wa : R/W; bitpos: [21:19]; default: 4;
* This field controls fast memory WA parameter.
*/
uint32_t fast_mem_wa:3;
/** fast_mem_ra : R/W; bitpos: [23:22]; default: 0;
* This field controls fast memory RA parameter.
*/
uint32_t fast_mem_ra:2;
uint32_t reserved_24:8;
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
} lp_aon_sdio_active_reg_t;
/** Type of lpcore register
* need_des
@ -405,7 +396,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36766272;
/** date : R/W; bitpos: [30:0]; default: 37823232;
* need_des
*/
uint32_t date:31;
@ -465,8 +456,8 @@ typedef struct {
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
uint32_t reserved_04c;
uint32_t reserved_048;
volatile lp_aon_sdio_active_reg_t sdio_active;
volatile lp_aon_lpcore_reg_t lpcore;
volatile lp_aon_sar_cct_reg_t sar_cct;
volatile lp_aon_modem_bus_reg_t modem_bus;

417
components/soc/esp32c61/register/soc/pcr_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,7 +23,7 @@ extern "C" {
#define PCR_UART0_CLK_EN_V 0x00000001U
#define PCR_UART0_CLK_EN_S 0
/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart0 module
* Set 1 to reset uart0 module
*/
#define PCR_UART0_RST_EN (BIT(1))
#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
@ -63,10 +63,10 @@ extern "C" {
#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU
#define PCR_UART0_SCLK_DIV_NUM_S 12
/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_UART0_SCLK_SEL 0x00000003U
#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
@ -111,7 +111,7 @@ extern "C" {
#define PCR_UART1_CLK_EN_V 0x00000001U
#define PCR_UART1_CLK_EN_S 0
/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart1 module
* Set 1 to reset uart1 module
*/
#define PCR_UART1_RST_EN (BIT(1))
#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
@ -151,10 +151,10 @@ extern "C" {
#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU
#define PCR_UART1_SCLK_DIV_NUM_S 12
/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_UART1_SCLK_SEL 0x00000003U
#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
@ -199,7 +199,7 @@ extern "C" {
#define PCR_UART2_CLK_EN_V 0x00000001U
#define PCR_UART2_CLK_EN_S 0
/** PCR_UART2_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart2 module
* Set 1 to reset uart2 module
*/
#define PCR_UART2_RST_EN (BIT(1))
#define PCR_UART2_RST_EN_M (PCR_UART2_RST_EN_V << PCR_UART2_RST_EN_S)
@ -239,10 +239,10 @@ extern "C" {
#define PCR_UART2_SCLK_DIV_NUM_V 0x000000FFU
#define PCR_UART2_SCLK_DIV_NUM_S 12
/** PCR_UART2_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART2.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART2.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_UART2_SCLK_SEL 0x00000003U
#define PCR_UART2_SCLK_SEL_M (PCR_UART2_SCLK_SEL_V << PCR_UART2_SCLK_SEL_S)
@ -287,7 +287,7 @@ extern "C" {
#define PCR_MSPI_CLK_EN_V 0x00000001U
#define PCR_MSPI_CLK_EN_S 0
/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset mspi module
* Set 1 to reset mspi module
*/
#define PCR_MSPI_RST_EN (BIT(1))
#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
@ -322,10 +322,10 @@ extern "C" {
#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU
#define PCR_MSPI_FAST_DIV_NUM_S 0
/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0;
* Configures the clock source for MSPI.\\
* 0(default): XTAL_CLK\\
* 1 RC_FAST_CLK\\
* 2: PLL_F480M_CLK\\
* Configures the clock source for MSPI.
* 0(default): XTAL_CLK
* 1 RC_FAST_CLK
* 2: PLL_F480M_CLK
*/
#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U
#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S)
@ -339,7 +339,7 @@ extern "C" {
#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U
#define PCR_MSPI_FUNC_CLK_EN_S 10
/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0;
* Set 0 to reset axi_clock domain of mspi module
* Set 1 to reset axi_clock domain of mspi module
*/
#define PCR_MSPI_AXI_RST_EN (BIT(11))
#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S)
@ -358,7 +358,7 @@ extern "C" {
#define PCR_I2C_CLK_EN_V 0x00000001U
#define PCR_I2C_CLK_EN_S 0
/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2c module
* Set 1 to reset i2c module
*/
#define PCR_I2C_RST_EN (BIT(1))
#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S)
@ -391,9 +391,9 @@ extern "C" {
#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU
#define PCR_I2C_SCLK_DIV_NUM_S 12
/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
* Configures the clock source of I2C.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of I2C.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
#define PCR_I2C_SCLK_SEL (BIT(20))
#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S)
@ -419,7 +419,7 @@ extern "C" {
#define PCR_LEDC_CLK_EN_V 0x00000001U
#define PCR_LEDC_CLK_EN_S 0
/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ledc module
* Set 1 to reset ledc module
*/
#define PCR_LEDC_RST_EN (BIT(1))
#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
@ -438,10 +438,10 @@ extern "C" {
*/
#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of LEDC.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of LEDC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_LEDC_SCLK_SEL 0x00000003U
#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
@ -486,7 +486,7 @@ extern "C" {
#define PCR_TG0_CLK_EN_V 0x00000001U
#define PCR_TG0_CLK_EN_S 0
/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group0 module
* Set 1 to reset timer_group0 module
*/
#define PCR_TG0_RST_EN (BIT(1))
#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
@ -519,10 +519,10 @@ extern "C" {
*/
#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44)
/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of general-purpose timers in Timer Group 0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of general-purpose timers in Timer Group 0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_TG0_TIMER_CLK_SEL 0x00000003U
#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
@ -541,10 +541,10 @@ extern "C" {
*/
#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48)
/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of WDT in Timer Group 0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of WDT in Timer Group 0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_TG0_WDT_CLK_SEL 0x00000003U
#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
@ -570,7 +570,7 @@ extern "C" {
#define PCR_TG1_CLK_EN_V 0x00000001U
#define PCR_TG1_CLK_EN_S 0
/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 module
* Set 1 to reset timer_group1 module
*/
#define PCR_TG1_RST_EN (BIT(1))
#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
@ -603,10 +603,10 @@ extern "C" {
*/
#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50)
/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of general-purpose timers in Timer Group 1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of general-purpose timers in Timer Group 1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_TG1_TIMER_CLK_SEL 0x00000003U
#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
@ -625,10 +625,10 @@ extern "C" {
*/
#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54)
/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of WDT in Timer Group 1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of WDT in Timer Group 1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_TG1_WDT_CLK_SEL 0x00000003U
#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
@ -654,7 +654,7 @@ extern "C" {
#define PCR_SYSTIMER_CLK_EN_V 0x00000001U
#define PCR_SYSTIMER_CLK_EN_S 0
/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset systimer module
* Set 1 to reset systimer module
*/
#define PCR_SYSTIMER_RST_EN (BIT(1))
#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
@ -673,9 +673,9 @@ extern "C" {
*/
#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c)
/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
* Configures the clock source of System Timer.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of System Timer.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20))
#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
@ -701,7 +701,7 @@ extern "C" {
#define PCR_I2S_CLK_EN_V 0x00000001U
#define PCR_I2S_CLK_EN_S 0
/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2s module
* Set 1 to reset i2s module
*/
#define PCR_I2S_RST_EN (BIT(1))
#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
@ -737,11 +737,11 @@ extern "C" {
#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU
#define PCR_I2S_TX_CLKM_DIV_NUM_S 12
/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S TX.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F120M_CLK\\
* 2: PLL_F160M_CLK\\
* 3: I2S_MCLK_in\\
* Configures the clock source of I2S TX.
* 0 (default): XTAL_CLK
* 1: PLL_F120M_CLK
* 2: PLL_F160M_CLK
* 3: I2S_MCLK_in
*/
#define PCR_I2S_TX_CLKM_SEL 0x00000003U
#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
@ -804,11 +804,11 @@ extern "C" {
#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU
#define PCR_I2S_RX_CLKM_DIV_NUM_S 12
/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S RX.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F120M_CLK\\
* 2: PLL_F160M_CLK\\
* 3: I2S_MCLK_in\\
* Configures the clock source of I2S RX.
* 0 (default): XTAL_CLK
* 1: PLL_F120M_CLK
* 2: PLL_F160M_CLK
* 3: I2S_MCLK_in
*/
#define PCR_I2S_RX_CLKM_SEL 0x00000003U
#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
@ -822,9 +822,9 @@ extern "C" {
#define PCR_I2S_RX_CLKM_EN_V 0x00000001U
#define PCR_I2S_RX_CLKM_EN_S 22
/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
* Configures to select master clock.\\
* 0 (default): I2S_TX_CLK\\
* 1: I2S_RX_CLK\\
* Configures to select master clock.
* 0 (default): I2S_TX_CLK
* 1: I2S_RX_CLK
*/
#define PCR_I2S_MCLK_SEL (BIT(23))
#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
@ -880,7 +880,7 @@ extern "C" {
#define PCR_SARADC_CLK_EN_V 0x00000001U
#define PCR_SARADC_CLK_EN_S 0
/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset function_register of saradc module
* Set 1 to reset function_register of saradc module
*/
#define PCR_SARADC_RST_EN (BIT(1))
#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
@ -894,7 +894,7 @@ extern "C" {
#define PCR_SARADC_REG_CLK_EN_V 0x00000001U
#define PCR_SARADC_REG_CLK_EN_S 2
/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
* Set 0 to reset apb_register of saradc module
* Set 1 to reset apb_register of saradc module
*/
#define PCR_SARADC_REG_RST_EN (BIT(3))
#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
@ -927,10 +927,10 @@ extern "C" {
#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define PCR_SARADC_CLKM_DIV_NUM_S 12
/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of SAR ADC.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of SAR ADC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_SARADC_CLKM_SEL 0x00000003U
#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
@ -949,9 +949,9 @@ extern "C" {
*/
#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x7c)
/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
* Configures the clock source of the temperature sensor.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of the temperature sensor.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
#define PCR_TSENS_CLK_SEL (BIT(20))
#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
@ -965,7 +965,7 @@ extern "C" {
#define PCR_TSENS_CLK_EN_V 0x00000001U
#define PCR_TSENS_CLK_EN_S 22
/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
* Set 0 to reset tsens module
* Set 1 to reset tsens module
*/
#define PCR_TSENS_RST_EN (BIT(23))
#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
@ -984,7 +984,7 @@ extern "C" {
#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U
#define PCR_USB_DEVICE_CLK_EN_S 0
/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset usb_device module
* Set 1 to reset usb_device module
*/
#define PCR_USB_DEVICE_RST_EN (BIT(1))
#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
@ -1010,7 +1010,7 @@ extern "C" {
#define PCR_INTMTX_CLK_EN_V 0x00000001U
#define PCR_INTMTX_CLK_EN_S 0
/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset intmtx module
* Set 1 to reset intmtx module
*/
#define PCR_INTMTX_RST_EN (BIT(1))
#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
@ -1076,9 +1076,9 @@ extern "C" {
#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU
#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0
/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
* Configures the clock source of PVT MONITOR.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F160M_CLK\\
* Configures the clock source of PVT MONITOR.
* 0 (default): XTAL_CLK
* 1: PLL_F160M_CLK
*/
#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20))
#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
@ -1104,7 +1104,7 @@ extern "C" {
#define PCR_GDMA_CLK_EN_V 0x00000001U
#define PCR_GDMA_CLK_EN_S 0
/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset gdma module
* Set 1 to reset gdma module
*/
#define PCR_GDMA_RST_EN (BIT(1))
#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
@ -1123,7 +1123,7 @@ extern "C" {
#define PCR_SPI2_CLK_EN_V 0x00000001U
#define PCR_SPI2_CLK_EN_S 0
/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset spi2 module
* Set 1 to reset spi2 module
*/
#define PCR_SPI2_RST_EN (BIT(1))
#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
@ -1149,10 +1149,10 @@ extern "C" {
#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU
#define PCR_SPI2_CLKM_DIV_NUM_S 12
/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of SPI2.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F160M_CLK\\
* 2: RC_FAST_CLK\\
* Configures the clock source of SPI2.
* 0 (default): XTAL_CLK
* 1: PLL_F160M_CLK
* 2: RC_FAST_CLK
*/
#define PCR_SPI2_CLKM_SEL 0x00000003U
#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
@ -1178,7 +1178,7 @@ extern "C" {
#define PCR_AES_CLK_EN_V 0x00000001U
#define PCR_AES_CLK_EN_S 0
/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset aes module
* Set 1 to reset aes module
*/
#define PCR_AES_RST_EN (BIT(1))
#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
@ -1204,7 +1204,7 @@ extern "C" {
#define PCR_SHA_CLK_EN_V 0x00000001U
#define PCR_SHA_CLK_EN_S 0
/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset sha module
* Set 1 to reset sha module
*/
#define PCR_SHA_RST_EN (BIT(1))
#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
@ -1230,7 +1230,7 @@ extern "C" {
#define PCR_RSA_CLK_EN_V 0x00000001U
#define PCR_RSA_CLK_EN_S 0
/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset rsa module
* Set 1 to reset rsa module
*/
#define PCR_RSA_RST_EN (BIT(1))
#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
@ -1282,7 +1282,7 @@ extern "C" {
#define PCR_ECC_CLK_EN_V 0x00000001U
#define PCR_ECC_CLK_EN_S 0
/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ecc module
* Set 1 to reset ecc module
*/
#define PCR_ECC_RST_EN (BIT(1))
#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
@ -1334,7 +1334,7 @@ extern "C" {
#define PCR_DS_CLK_EN_V 0x00000001U
#define PCR_DS_CLK_EN_S 0
/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ds module
* Set 1 to reset ds module
*/
#define PCR_DS_RST_EN (BIT(1))
#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
@ -1360,7 +1360,7 @@ extern "C" {
#define PCR_HMAC_CLK_EN_V 0x00000001U
#define PCR_HMAC_CLK_EN_S 0
/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset hmac module
* Set 1 to reset hmac module
*/
#define PCR_HMAC_RST_EN (BIT(1))
#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
@ -1386,7 +1386,7 @@ extern "C" {
#define PCR_ECDSA_CLK_EN_V 0x00000001U
#define PCR_ECDSA_CLK_EN_S 0
/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ecdsa module
* Set 1 to reset ecdsa module
*/
#define PCR_ECDSA_RST_EN (BIT(1))
#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S)
@ -1412,7 +1412,7 @@ extern "C" {
#define PCR_IOMUX_CLK_EN_V 0x00000001U
#define PCR_IOMUX_CLK_EN_S 0
/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset iomux module
* Set 1 to reset iomux module
*/
#define PCR_IOMUX_RST_EN (BIT(1))
#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
@ -1424,10 +1424,10 @@ extern "C" {
*/
#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xc4)
/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of IO MUX.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of IO MUX.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U
#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
@ -1453,7 +1453,7 @@ extern "C" {
#define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U
#define PCR_TCM_MEM_MONITOR_CLK_EN_S 0
/** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset tcm_mem_monitor module
* Set 1 to reset tcm_mem_monitor module
*/
#define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1))
#define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S)
@ -1479,7 +1479,7 @@ extern "C" {
#define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U
#define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0
/** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset psram_mem_monitor module
* Set 1 to reset psram_mem_monitor module
*/
#define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1))
#define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S)
@ -1505,7 +1505,7 @@ extern "C" {
#define PCR_TRACE_CLK_EN_V 0x00000001U
#define PCR_TRACE_CLK_EN_S 0
/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset trace module
* Set 1 to reset trace module
*/
#define PCR_TRACE_RST_EN (BIT(1))
#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
@ -1524,7 +1524,7 @@ extern "C" {
#define PCR_ASSIST_CLK_EN_V 0x00000001U
#define PCR_ASSIST_CLK_EN_S 0
/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset assist module
* Set 1 to reset assist module
*/
#define PCR_ASSIST_RST_EN (BIT(1))
#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
@ -1543,7 +1543,7 @@ extern "C" {
#define PCR_CACHE_CLK_EN_V 0x00000001U
#define PCR_CACHE_CLK_EN_S 0
/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset cache module
* Set 1 to reset cache module
*/
#define PCR_CACHE_RST_EN (BIT(1))
#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
@ -1601,14 +1601,14 @@ extern "C" {
*/
#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0xe4)
/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset cpu_peri timeout module
* Set 1 to reset cpu_peri timeout module
*/
#define PCR_CPU_TIMEOUT_RST_EN (BIT(1))
#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U
#define PCR_CPU_TIMEOUT_RST_EN_S 1
/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
* Set 0 to reset hp_peri timeout module and hp_modem timeout module
* Set 1 to reset hp_peri timeout module and hp_modem timeout module
*/
#define PCR_HP_TIMEOUT_RST_EN (BIT(2))
#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
@ -1619,11 +1619,26 @@ extern "C" {
* SYSCLK configuration register
*/
#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0xe8)
/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
* clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
* clock-source such as XTAL/FOSC.
*/
#define PCR_LS_DIV_NUM 0x000000FFU
#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
#define PCR_LS_DIV_NUM_V 0x000000FFU
#define PCR_LS_DIV_NUM_S 0
/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
* clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
*/
#define PCR_HS_DIV_NUM 0x000000FFU
#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
#define PCR_HS_DIV_NUM_V 0x000000FFU
#define PCR_HS_DIV_NUM_S 8
/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
* Configures to select the clock source of HP_ROOT_CLK.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F160M_CLK\\
* Configures to select the clock source of HP_ROOT_CLK.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F160M_CLK
*/
#define PCR_SOC_CLK_SEL 0x00000003U
#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
@ -1649,20 +1664,6 @@ extern "C" {
* CPU_WAITI configuration register
*/
#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0xec)
/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
* Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
*/
#define PCR_CPUPERIOD_SEL 0x00000003U
#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
#define PCR_CPUPERIOD_SEL_V 0x00000003U
#define PCR_CPUPERIOD_SEL_S 0
/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
* Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
*/
#define PCR_PLL_FREQ_SEL (BIT(2))
#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
#define PCR_PLL_FREQ_SEL_V 0x00000001U
#define PCR_PLL_FREQ_SEL_S 2
/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
* Set 1 to force cpu_waiti_clk enable.
*/
@ -1684,7 +1685,7 @@ extern "C" {
*/
#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf0)
/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is
* Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
* div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
* clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
*/
@ -1698,7 +1699,7 @@ extern "C" {
*/
#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf4)
/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is
* Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
* div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
* low-speed clock-source such as XTAL/FOSC, and should be used together with
* PCR_CPU_DIV_NUM.
@ -1726,7 +1727,7 @@ extern "C" {
#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU
#define PCR_APB_DECREASE_DIV_NUM_S 0
/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
* Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is
* Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
* div1(default)/div2/div4 of clk_ahb.
*/
#define PCR_APB_DIV_NUM 0x000000FFU
@ -1758,7 +1759,7 @@ extern "C" {
*/
#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x100)
/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
* This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close,
* This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_160M_CLK_EN (BIT(1))
@ -1766,7 +1767,7 @@ extern "C" {
#define PCR_PLL_160M_CLK_EN_V 0x00000001U
#define PCR_PLL_160M_CLK_EN_S 1
/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
* This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close,
* This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_120M_CLK_EN (BIT(2))
@ -1774,7 +1775,7 @@ extern "C" {
#define PCR_PLL_120M_CLK_EN_V 0x00000001U
#define PCR_PLL_120M_CLK_EN_S 2
/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
* This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close,
* This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_80M_CLK_EN (BIT(3))
@ -1782,7 +1783,7 @@ extern "C" {
#define PCR_PLL_80M_CLK_EN_V 0x00000001U
#define PCR_PLL_80M_CLK_EN_S 3
/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1;
* This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close,
* This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_60M_CLK_EN (BIT(4))
@ -1790,7 +1791,7 @@ extern "C" {
#define PCR_PLL_60M_CLK_EN_V 0x00000001U
#define PCR_PLL_60M_CLK_EN_S 4
/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
* This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close,
* This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_48M_CLK_EN (BIT(5))
@ -1798,7 +1799,7 @@ extern "C" {
#define PCR_PLL_48M_CLK_EN_V 0x00000001U
#define PCR_PLL_48M_CLK_EN_S 5
/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1;
* This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close,
* This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_40M_CLK_EN (BIT(6))
@ -1806,21 +1807,13 @@ extern "C" {
#define PCR_PLL_40M_CLK_EN_V 0x00000001U
#define PCR_PLL_40M_CLK_EN_S 6
/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1;
* This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close,
* This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_20M_CLK_EN (BIT(7))
#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
#define PCR_PLL_20M_CLK_EN_V 0x00000001U
#define PCR_PLL_20M_CLK_EN_S 7
/** PCR_PLL_12M_CLK_EN : HRO; bitpos: [8]; default: 1;
* This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
#define PCR_PLL_12M_CLK_EN (BIT(8))
#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S)
#define PCR_PLL_12M_CLK_EN_V 0x00000001U
#define PCR_PLL_12M_CLK_EN_S 8
/** PCR_CTRL_CLK_OUT_EN_REG register
* CLK_OUT_EN configuration register
@ -1902,12 +1895,12 @@ extern "C" {
*/
#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x10c)
/** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0;
* Configures the 32KHz clock for TIMER_GROUP.\\
* 0 (default): RC32K_CLK\\
* 1: XTAL32K_CLK\\
* 2: OSC_SLOW_CLK\\
* 3: RC_SLOW_CLK\\
* 4: RC_FAST_CLK\\
* Configures the 32KHz clock for TIMER_GROUP.
* 0 (default): RC32K_CLK
* 1: XTAL32K_CLK
* 2: OSC_SLOW_CLK
* 3: RC_SLOW_CLK
* 4: RC_FAST_CLK
*/
#define PCR_32K_SEL 0x00000007U
#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S)
@ -1982,52 +1975,33 @@ extern "C" {
#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x118)
/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* Configures the clock source for the External Memory Encryption and Decryption
* module.\\
* 0(default): XTAL_CLK\\
* 1 RC_FAST_CLK\\
* 2: PLL_F480M_CLK\\
* module.
* 0(default): XTAL_CLK
* 1 RC_FAST_CLK
* 2: PLL_F480M_CLK
*/
#define PCR_SEC_CLK_SEL 0x00000003U
#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S)
#define PCR_SEC_CLK_SEL_V 0x00000003U
#define PCR_SEC_CLK_SEL_S 0
/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0;
* Set 0 to reset sec module
* Set 1 to reset sec module
*/
#define PCR_SEC_RST_EN (BIT(2))
#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S)
#define PCR_SEC_RST_EN_V 0x00000001U
#define PCR_SEC_RST_EN_S 2
/** PCR_ADC_DAC_INV_PHASE_CONF_REG register
* xxxx
*/
#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x11c)
/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
* xxxx
*/
#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0))
#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S)
#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U
#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0
/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0;
* xxxx
*/
#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1))
#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S)
#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U
#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1
/** PCR_BUS_CLK_UPDATE_REG register
* Configuration register for applying updated high-performance system clock sources
*/
#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x120)
/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0;
* Configures whether or not to update configurations for CPU_CLK division, AHB_CLK
* division and HP_ROOT_CLK clock source selection.\\
* 0: Not update configurations\\
* 1: Update configurations\\
* This bit is automatically cleared when configurations have been updated.\\
* division and HP_ROOT_CLK clock source selection.
* 0: Not update configurations
* 1: Update configurations
* This bit is automatically cleared when configurations have been updated.
*/
#define PCR_BUS_CLOCK_UPDATE (BIT(0))
#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S)
@ -2039,54 +2013,33 @@ extern "C" {
*/
#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x124)
/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Configures the divisor for SAR ADC 2 clock to generate ADC analog control
* signals.\\
* Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals.
*/
#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU
#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S)
#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU
#define PCR_SAR2_CLK_DIV_NUM_S 0
/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
* Configures the divisor for SAR ADC 1 clock to generate ADC analog control
* signals.\\
* Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals.
*/
#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU
#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S)
#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU
#define PCR_SAR1_CLK_DIV_NUM_S 8
/** PCR_PWDET_SAR_CLK_CONF_REG register
* xxxx
*/
#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x128)
/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7;
* xxxx
*/
#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU
#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S)
#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU
#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0
/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1;
* xxxx
*/
#define PCR_PWDET_SAR_CLK_EN (BIT(8))
#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S)
#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U
#define PCR_PWDET_SAR_CLK_EN_S 8
/** PCR_TIMERGROUP_WDT_CONF_REG register
* TIMERGROUP_WDT configuration register
*/
#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x12c)
/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0;
* Set 0 to reset timer_group0 wdt module
* Set 1 to reset timer_group0 wdt module
*/
#define PCR_TG0_WDT_RST_EN (BIT(0))
#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S)
#define PCR_TG0_WDT_RST_EN_V 0x00000001U
#define PCR_TG0_WDT_RST_EN_S 0
/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 wdt module
* Set 1 to reset timer_group1 wdt module
*/
#define PCR_TG1_WDT_RST_EN (BIT(1))
#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S)
@ -2098,14 +2051,14 @@ extern "C" {
*/
#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x130)
/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0;
* Set 0 to reset timer_group0 xtal clock domain
* Set 1 to reset timer_group0 xtal clock domain
*/
#define PCR_TG0_XTAL_RST_EN (BIT(0))
#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S)
#define PCR_TG0_XTAL_RST_EN_V 0x00000001U
#define PCR_TG0_XTAL_RST_EN_S 0
/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 xtal clock domain
* Set 1 to reset timer_group1 xtal clock domain
*/
#define PCR_TG1_XTAL_RST_EN (BIT(1))
#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S)
@ -2156,7 +2109,7 @@ extern "C" {
#define PCR_REGDMA_CLK_EN_V 0x00000001U
#define PCR_REGDMA_CLK_EN_S 0
/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset regdma module
* Set 1 to reset regdma module
*/
#define PCR_REGDMA_RST_EN (BIT(1))
#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
@ -2175,7 +2128,7 @@ extern "C" {
#define PCR_ETM_CLK_EN_V 0x00000001U
#define PCR_ETM_CLK_EN_S 0
/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 0 to reset etm module
* Set 1 to reset etm module
*/
#define PCR_ETM_RST_EN (BIT(1))
#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
@ -2189,35 +2142,49 @@ extern "C" {
#define PCR_ETM_READY_V 0x00000001U
#define PCR_ETM_READY_S 2
/** PCR_FPGA_DEBUG_REG register
* fpga debug register
/** PCR_SDIO_SLAVE_CONF_REG register
* SDIO_SLAVE configuration register
*/
#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
* Only used in fpga debug.
#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x158)
/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 to enable sdio_slave clock
*/
#define PCR_FPGA_DEBUG 0xFFFFFFFFU
#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU
#define PCR_FPGA_DEBUG_S 0
#define PCR_SDIO_SLAVE_CLK_EN (BIT(0))
#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S)
#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U
#define PCR_SDIO_SLAVE_CLK_EN_S 0
/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 1 to reset sdio_slave module
*/
#define PCR_SDIO_SLAVE_RST_EN (BIT(1))
#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S)
#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U
#define PCR_SDIO_SLAVE_RST_EN_S 1
/** PCR_CLOCK_GATE_REG register
* PCR clock gating configure register
/** PCR_SDIO_SLAVE_PD_CTRL_REG register
* LEDC power control register
*/
#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
#define PCR_SDIO_SLAVE_PD_CTRL_REG (DR_REG_PCR_BASE + 0x15c)
/** PCR_SDIO_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
* Set this bit to force power down SDIO memory.
*/
#define PCR_CLK_EN (BIT(0))
#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S)
#define PCR_CLK_EN_V 0x00000001U
#define PCR_CLK_EN_S 0
#define PCR_SDIO_MEM_FORCE_PU (BIT(1))
#define PCR_SDIO_MEM_FORCE_PU_M (PCR_SDIO_MEM_FORCE_PU_V << PCR_SDIO_MEM_FORCE_PU_S)
#define PCR_SDIO_MEM_FORCE_PU_V 0x00000001U
#define PCR_SDIO_MEM_FORCE_PU_S 1
/** PCR_SDIO_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
* Set this bit to force power up SDIO memory.
*/
#define PCR_SDIO_MEM_FORCE_PD (BIT(2))
#define PCR_SDIO_MEM_FORCE_PD_M (PCR_SDIO_MEM_FORCE_PD_V << PCR_SDIO_MEM_FORCE_PD_S)
#define PCR_SDIO_MEM_FORCE_PD_V 0x00000001U
#define PCR_SDIO_MEM_FORCE_PD_S 2
/** PCR_DATE_REG register
* Date register.
*/
#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
/** PCR_DATE : R/W; bitpos: [27:0]; default: 37753376;
/** PCR_DATE : R/W; bitpos: [27:0]; default: 37823120;
* PCR version information.
*/
#define PCR_DATE 0x0FFFFFFFU

445
components/soc/esp32c61/register/soc/pcr_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -21,7 +21,7 @@ typedef union {
*/
uint32_t uart0_clk_en:1;
/** uart0_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart0 module
* Set 1 to reset uart0 module
*/
uint32_t uart0_rst_en:1;
/** uart0_ready : RO; bitpos: [2]; default: 1;
@ -51,10 +51,10 @@ typedef union {
*/
uint32_t uart0_sclk_div_num:8;
/** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t uart0_sclk_sel:2;
/** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
@ -95,7 +95,7 @@ typedef union {
*/
uint32_t uart1_clk_en:1;
/** uart1_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart1 module
* Set 1 to reset uart1 module
*/
uint32_t uart1_rst_en:1;
/** uart1_ready : RO; bitpos: [2]; default: 1;
@ -125,10 +125,10 @@ typedef union {
*/
uint32_t uart1_sclk_div_num:8;
/** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t uart1_sclk_sel:2;
/** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
@ -169,7 +169,7 @@ typedef union {
*/
uint32_t uart2_clk_en:1;
/** uart2_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset uart2 module
* Set 1 to reset uart2 module
*/
uint32_t uart2_rst_en:1;
/** uart2_ready : RO; bitpos: [2]; default: 1;
@ -199,10 +199,10 @@ typedef union {
*/
uint32_t uart2_sclk_div_num:8;
/** uart2_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of UART2.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of UART2.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t uart2_sclk_sel:2;
/** uart2_sclk_en : R/W; bitpos: [22]; default: 1;
@ -243,7 +243,7 @@ typedef union {
*/
uint32_t mspi_clk_en:1;
/** mspi_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset mspi module
* Set 1 to reset mspi module
*/
uint32_t mspi_rst_en:1;
/** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
@ -271,10 +271,10 @@ typedef union {
*/
uint32_t mspi_fast_div_num:8;
/** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0;
* Configures the clock source for MSPI.\\
* 0(default): XTAL_CLK\\
* 1 RC_FAST_CLK\\
* 2: PLL_F480M_CLK\\
* Configures the clock source for MSPI.
* 0(default): XTAL_CLK
* 1 RC_FAST_CLK
* 2: PLL_F480M_CLK
*/
uint32_t mspi_func_clk_sel:2;
/** mspi_func_clk_en : R/W; bitpos: [10]; default: 1;
@ -282,7 +282,7 @@ typedef union {
*/
uint32_t mspi_func_clk_en:1;
/** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0;
* Set 0 to reset axi_clock domain of mspi module
* Set 1 to reset axi_clock domain of mspi module
*/
uint32_t mspi_axi_rst_en:1;
uint32_t reserved_12:20;
@ -300,7 +300,7 @@ typedef union {
*/
uint32_t i2c_clk_en:1;
/** i2c_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2c module
* Set 1 to reset i2c module
*/
uint32_t i2c_rst_en:1;
uint32_t reserved_2:30;
@ -326,9 +326,9 @@ typedef union {
*/
uint32_t i2c_sclk_div_num:8;
/** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of I2C.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of I2C.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
uint32_t i2c_sclk_sel:1;
uint32_t reserved_21:1;
@ -351,7 +351,7 @@ typedef union {
*/
uint32_t ledc_clk_en:1;
/** ledc_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ledc module
* Set 1 to reset ledc module
*/
uint32_t ledc_rst_en:1;
/** ledc_ready : RO; bitpos: [2]; default: 1;
@ -370,10 +370,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of LEDC.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of LEDC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t ledc_sclk_sel:2;
/** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
@ -414,7 +414,7 @@ typedef union {
*/
uint32_t tg0_clk_en:1;
/** tg0_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group0 module
* Set 1 to reset timer_group0 module
*/
uint32_t tg0_rst_en:1;
/** tg0_wdt_ready : RO; bitpos: [2]; default: 1;
@ -441,10 +441,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of general-purpose timers in Timer Group 0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of general-purpose timers in Timer Group 0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg0_timer_clk_sel:2;
/** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
@ -463,10 +463,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of WDT in Timer Group 0.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of WDT in Timer Group 0.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg0_wdt_clk_sel:2;
/** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
@ -488,7 +488,7 @@ typedef union {
*/
uint32_t tg1_clk_en:1;
/** tg1_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 module
* Set 1 to reset timer_group1 module
*/
uint32_t tg1_rst_en:1;
/** tg1_wdt_ready : RO; bitpos: [2]; default: 1;
@ -515,10 +515,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of general-purpose timers in Timer Group 1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of general-purpose timers in Timer Group 1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg1_timer_clk_sel:2;
/** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
@ -537,10 +537,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of WDT in Timer Group 1.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of WDT in Timer Group 1.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t tg1_wdt_clk_sel:2;
/** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
@ -562,7 +562,7 @@ typedef union {
*/
uint32_t systimer_clk_en:1;
/** systimer_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset systimer module
* Set 1 to reset systimer module
*/
uint32_t systimer_rst_en:1;
/** systimer_ready : RO; bitpos: [2]; default: 1;
@ -581,9 +581,9 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of System Timer.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of System Timer.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
uint32_t systimer_func_clk_sel:1;
uint32_t reserved_21:1;
@ -606,7 +606,7 @@ typedef union {
*/
uint32_t i2s_clk_en:1;
/** i2s_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset i2s module
* Set 1 to reset i2s module
*/
uint32_t i2s_rst_en:1;
/** i2s_rx_ready : RO; bitpos: [2]; default: 1;
@ -636,11 +636,11 @@ typedef union {
*/
uint32_t i2s_tx_clkm_div_num:8;
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S TX.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F120M_CLK\\
* 2: PLL_F160M_CLK\\
* 3: I2S_MCLK_in\\
* Configures the clock source of I2S TX.
* 0 (default): XTAL_CLK
* 1: PLL_F120M_CLK
* 2: PLL_F160M_CLK
* 3: I2S_MCLK_in
*/
uint32_t i2s_tx_clkm_sel:2;
/** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1;
@ -693,11 +693,11 @@ typedef union {
*/
uint32_t i2s_rx_clkm_div_num:8;
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S RX.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F120M_CLK\\
* 2: PLL_F160M_CLK\\
* 3: I2S_MCLK_in\\
* Configures the clock source of I2S RX.
* 0 (default): XTAL_CLK
* 1: PLL_F120M_CLK
* 2: PLL_F160M_CLK
* 3: I2S_MCLK_in
*/
uint32_t i2s_rx_clkm_sel:2;
/** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
@ -705,9 +705,9 @@ typedef union {
*/
uint32_t i2s_rx_clkm_en:1;
/** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
* Configures to select master clock.\\
* 0 (default): I2S_TX_CLK\\
* 1: I2S_RX_CLK\\
* Configures to select master clock.
* 0 (default): I2S_TX_CLK
* 1: I2S_RX_CLK
*/
uint32_t i2s_mclk_sel:1;
uint32_t reserved_24:8;
@ -755,7 +755,7 @@ typedef union {
*/
uint32_t saradc_clk_en:1;
/** saradc_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset function_register of saradc module
* Set 1 to reset function_register of saradc module
*/
uint32_t saradc_rst_en:1;
/** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1;
@ -763,7 +763,7 @@ typedef union {
*/
uint32_t saradc_reg_clk_en:1;
/** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
* Set 0 to reset apb_register of saradc module
* Set 1 to reset apb_register of saradc module
*/
uint32_t saradc_reg_rst_en:1;
uint32_t reserved_4:28;
@ -789,10 +789,10 @@ typedef union {
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of SAR ADC.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of SAR ADC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t saradc_clkm_sel:2;
/** saradc_clkm_en : R/W; bitpos: [22]; default: 1;
@ -811,9 +811,9 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of the temperature sensor.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* Configures the clock source of the temperature sensor.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
*/
uint32_t tsens_clk_sel:1;
uint32_t reserved_21:1;
@ -822,7 +822,7 @@ typedef union {
*/
uint32_t tsens_clk_en:1;
/** tsens_rst_en : R/W; bitpos: [23]; default: 0;
* Set 0 to reset tsens module
* Set 1 to reset tsens module
*/
uint32_t tsens_rst_en:1;
uint32_t reserved_24:8;
@ -840,7 +840,7 @@ typedef union {
*/
uint32_t usb_device_clk_en:1;
/** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset usb_device module
* Set 1 to reset usb_device module
*/
uint32_t usb_device_rst_en:1;
/** usb_device_ready : RO; bitpos: [2]; default: 1;
@ -862,7 +862,7 @@ typedef union {
*/
uint32_t intmtx_clk_en:1;
/** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset intmtx module
* Set 1 to reset intmtx module
*/
uint32_t intmtx_rst_en:1;
/** intmtx_ready : RO; bitpos: [2]; default: 1;
@ -916,9 +916,9 @@ typedef union {
uint32_t pvt_monitor_func_clk_div_num:4;
uint32_t reserved_4:16;
/** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
* Configures the clock source of PVT MONITOR.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F160M_CLK\\
* Configures the clock source of PVT MONITOR.
* 0 (default): XTAL_CLK
* 1: PLL_F160M_CLK
*/
uint32_t pvt_monitor_func_clk_sel:1;
uint32_t reserved_21:1;
@ -941,7 +941,7 @@ typedef union {
*/
uint32_t gdma_clk_en:1;
/** gdma_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset gdma module
* Set 1 to reset gdma module
*/
uint32_t gdma_rst_en:1;
uint32_t reserved_2:30;
@ -959,7 +959,7 @@ typedef union {
*/
uint32_t spi2_clk_en:1;
/** spi2_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset spi2 module
* Set 1 to reset spi2 module
*/
uint32_t spi2_rst_en:1;
/** spi2_ready : RO; bitpos: [2]; default: 1;
@ -982,10 +982,10 @@ typedef union {
*/
uint32_t spi2_clkm_div_num:8;
/** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of SPI2.\\
* 0 (default): XTAL_CLK\\
* 1: PLL_F160M_CLK\\
* 2: RC_FAST_CLK\\
* Configures the clock source of SPI2.
* 0 (default): XTAL_CLK
* 1: PLL_F160M_CLK
* 2: RC_FAST_CLK
*/
uint32_t spi2_clkm_sel:2;
/** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
@ -1007,7 +1007,7 @@ typedef union {
*/
uint32_t aes_clk_en:1;
/** aes_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset aes module
* Set 1 to reset aes module
*/
uint32_t aes_rst_en:1;
/** aes_ready : RO; bitpos: [2]; default: 1;
@ -1029,7 +1029,7 @@ typedef union {
*/
uint32_t sha_clk_en:1;
/** sha_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset sha module
* Set 1 to reset sha module
*/
uint32_t sha_rst_en:1;
/** sha_ready : RO; bitpos: [2]; default: 1;
@ -1051,7 +1051,7 @@ typedef union {
*/
uint32_t rsa_clk_en:1;
/** rsa_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset rsa module
* Set 1 to reset rsa module
*/
uint32_t rsa_rst_en:1;
/** rsa_ready : RO; bitpos: [2]; default: 1;
@ -1095,7 +1095,7 @@ typedef union {
*/
uint32_t ecc_clk_en:1;
/** ecc_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ecc module
* Set 1 to reset ecc module
*/
uint32_t ecc_rst_en:1;
/** ecc_ready : RO; bitpos: [2]; default: 1;
@ -1139,7 +1139,7 @@ typedef union {
*/
uint32_t ds_clk_en:1;
/** ds_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ds module
* Set 1 to reset ds module
*/
uint32_t ds_rst_en:1;
/** ds_ready : RO; bitpos: [2]; default: 1;
@ -1161,7 +1161,7 @@ typedef union {
*/
uint32_t hmac_clk_en:1;
/** hmac_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset hmac module
* Set 1 to reset hmac module
*/
uint32_t hmac_rst_en:1;
/** hmac_ready : RO; bitpos: [2]; default: 1;
@ -1183,7 +1183,7 @@ typedef union {
*/
uint32_t ecdsa_clk_en:1;
/** ecdsa_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset ecdsa module
* Set 1 to reset ecdsa module
*/
uint32_t ecdsa_rst_en:1;
/** ecdsa_ready : RO; bitpos: [2]; default: 1;
@ -1205,7 +1205,7 @@ typedef union {
*/
uint32_t iomux_clk_en:1;
/** iomux_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset iomux module
* Set 1 to reset iomux module
*/
uint32_t iomux_rst_en:1;
uint32_t reserved_2:30;
@ -1220,10 +1220,10 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of IO MUX.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F80M_CLK\\
* Configures the clock source of IO MUX.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
*/
uint32_t iomux_func_clk_sel:2;
/** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
@ -1245,7 +1245,7 @@ typedef union {
*/
uint32_t tcm_mem_monitor_clk_en:1;
/** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset tcm_mem_monitor module
* Set 1 to reset tcm_mem_monitor module
*/
uint32_t tcm_mem_monitor_rst_en:1;
/** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1;
@ -1267,7 +1267,7 @@ typedef union {
*/
uint32_t psram_mem_monitor_clk_en:1;
/** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset psram_mem_monitor module
* Set 1 to reset psram_mem_monitor module
*/
uint32_t psram_mem_monitor_rst_en:1;
/** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1;
@ -1289,7 +1289,7 @@ typedef union {
*/
uint32_t trace_clk_en:1;
/** trace_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset trace module
* Set 1 to reset trace module
*/
uint32_t trace_rst_en:1;
uint32_t reserved_2:30;
@ -1307,7 +1307,7 @@ typedef union {
*/
uint32_t assist_clk_en:1;
/** assist_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset assist module
* Set 1 to reset assist module
*/
uint32_t assist_rst_en:1;
uint32_t reserved_2:30;
@ -1325,7 +1325,7 @@ typedef union {
*/
uint32_t cache_clk_en:1;
/** cache_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset cache module
* Set 1 to reset cache module
*/
uint32_t cache_rst_en:1;
uint32_t reserved_2:30;
@ -1382,11 +1382,11 @@ typedef union {
struct {
uint32_t reserved_0:1;
/** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset cpu_peri timeout module
* Set 1 to reset cpu_peri timeout module
*/
uint32_t cpu_timeout_rst_en:1;
/** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
* Set 0 to reset hp_peri timeout module and hp_modem timeout module
* Set 1 to reset hp_peri timeout module and hp_modem timeout module
*/
uint32_t hp_timeout_rst_en:1;
uint32_t reserved_3:29;
@ -1399,12 +1399,20 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** ls_div_num : HRO; bitpos: [7:0]; default: 0;
* clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
* clock-source such as XTAL/FOSC.
*/
uint32_t ls_div_num:8;
/** hs_div_num : HRO; bitpos: [15:8]; default: 2;
* clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
*/
uint32_t hs_div_num:8;
/** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
* Configures to select the clock source of HP_ROOT_CLK.\\
* 0 (default): XTAL_CLK\\
* 1: RC_FAST_CLK\\
* 2: PLL_F160M_CLK\\
* Configures to select the clock source of HP_ROOT_CLK.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F160M_CLK
*/
uint32_t soc_clk_sel:2;
uint32_t reserved_18:6;
@ -1426,14 +1434,7 @@ typedef union {
*/
typedef union {
struct {
/** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1;
* Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
*/
uint32_t cpuperiod_sel:2;
/** pll_freq_sel : HRO; bitpos: [2]; default: 1;
* Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
*/
uint32_t pll_freq_sel:1;
uint32_t reserved_0:3;
/** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
* Set 1 to force cpu_waiti_clk enable.
*/
@ -1454,7 +1455,7 @@ typedef union {
typedef union {
struct {
/** cpu_div_num : R/W; bitpos: [7:0]; default: 0;
* Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is
* Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
* div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
* clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
*/
@ -1470,7 +1471,7 @@ typedef union {
typedef union {
struct {
/** ahb_div_num : R/W; bitpos: [7:0]; default: 0;
* Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is
* Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
* div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
* low-speed clock-source such as XTAL/FOSC, and should be used together with
* PCR_CPU_DIV_NUM.
@ -1497,7 +1498,7 @@ typedef union {
*/
uint32_t apb_decrease_div_num:8;
/** apb_div_num : R/W; bitpos: [15:8]; default: 0;
* Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is
* Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
* div1(default)/div2/div4 of clk_ahb.
*/
uint32_t apb_div_num:8;
@ -1513,46 +1514,41 @@ typedef union {
struct {
uint32_t reserved_0:1;
/** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
* This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close,
* This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_160m_clk_en:1;
/** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
* This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close,
* This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_120m_clk_en:1;
/** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
* This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close,
* This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_80m_clk_en:1;
/** pll_60m_clk_en : R/W; bitpos: [4]; default: 1;
* This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close,
* This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_60m_clk_en:1;
/** pll_48m_clk_en : R/W; bitpos: [5]; default: 1;
* This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close,
* This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_48m_clk_en:1;
/** pll_40m_clk_en : R/W; bitpos: [6]; default: 1;
* This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close,
* This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_40m_clk_en:1;
/** pll_20m_clk_en : R/W; bitpos: [7]; default: 1;
* This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close,
* This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_20m_clk_en:1;
/** pll_12m_clk_en : HRO; bitpos: [8]; default: 1;
* This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close,
* 1: open(default). Only available when high-speed clock-source SPLL is active.
*/
uint32_t pll_12m_clk_en:1;
uint32_t reserved_9:23;
uint32_t reserved_8:24;
};
uint32_t val;
} pcr_pll_div_clk_en_reg_t;
@ -1612,13 +1608,13 @@ typedef union {
*/
typedef union {
struct {
/** 32k_sel : R/W; bitpos: [2:0]; default: 0;
* Configures the 32KHz clock for TIMER_GROUP.\\
* 0 (default): RC32K_CLK\\
* 1: XTAL32K_CLK\\
* 2: OSC_SLOW_CLK\\
* 3: RC_SLOW_CLK\\
* 4: RC_FAST_CLK\\
/** clk_32k_sel : R/W; bitpos: [2:0]; default: 0;
* Configures the 32KHz clock for TIMER_GROUP.
* 0 (default): RC32K_CLK
* 1: XTAL32K_CLK
* 2: OSC_SLOW_CLK
* 3: RC_SLOW_CLK
* 4: RC_FAST_CLK
*/
uint32_t clk_32k_sel:3;
uint32_t reserved_3:5;
@ -1687,14 +1683,14 @@ typedef union {
struct {
/** sec_clk_sel : R/W; bitpos: [1:0]; default: 0;
* Configures the clock source for the External Memory Encryption and Decryption
* module.\\
* 0(default): XTAL_CLK\\
* 1 RC_FAST_CLK\\
* 2: PLL_F480M_CLK\\
* module.
* 0(default): XTAL_CLK
* 1 RC_FAST_CLK
* 2: PLL_F480M_CLK
*/
uint32_t sec_clk_sel:2;
/** sec_rst_en : R/W; bitpos: [2]; default: 0;
* Set 0 to reset sec module
* Set 1 to reset sec module
*/
uint32_t sec_rst_en:1;
uint32_t reserved_3:29;
@ -1702,24 +1698,6 @@ typedef union {
uint32_t val;
} pcr_sec_conf_reg_t;
/** Type of adc_dac_inv_phase_conf register
* xxxx
*/
typedef union {
struct {
/** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0;
* xxxx
*/
uint32_t clk_rx_adc_inv_phase_ena:1;
/** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0;
* xxxx
*/
uint32_t clk_tx_dac_inv_phase_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pcr_adc_dac_inv_phase_conf_reg_t;
/** Type of bus_clk_update register
* Configuration register for applying updated high-performance system clock sources
*/
@ -1727,10 +1705,10 @@ typedef union {
struct {
/** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0;
* Configures whether or not to update configurations for CPU_CLK division, AHB_CLK
* division and HP_ROOT_CLK clock source selection.\\
* 0: Not update configurations\\
* 1: Update configurations\\
* This bit is automatically cleared when configurations have been updated.\\
* division and HP_ROOT_CLK clock source selection.
* 0: Not update configurations
* 1: Update configurations
* This bit is automatically cleared when configurations have been updated.
*/
uint32_t bus_clock_update:1;
uint32_t reserved_1:31;
@ -1744,13 +1722,11 @@ typedef union {
typedef union {
struct {
/** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4;
* Configures the divisor for SAR ADC 2 clock to generate ADC analog control
* signals.\\
* Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals.
*/
uint32_t sar2_clk_div_num:8;
/** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4;
* Configures the divisor for SAR ADC 1 clock to generate ADC analog control
* signals.\\
* Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals.
*/
uint32_t sar1_clk_div_num:8;
uint32_t reserved_16:16;
@ -1758,35 +1734,17 @@ typedef union {
uint32_t val;
} pcr_sar_clk_div_reg_t;
/** Type of pwdet_sar_clk_conf register
* xxxx
*/
typedef union {
struct {
/** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7;
* xxxx
*/
uint32_t pwdet_sar_clk_div_num:8;
/** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1;
* xxxx
*/
uint32_t pwdet_sar_clk_en:1;
uint32_t reserved_9:23;
};
uint32_t val;
} pcr_pwdet_sar_clk_conf_reg_t;
/** Type of timergroup_wdt_conf register
* TIMERGROUP_WDT configuration register
*/
typedef union {
struct {
/** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0;
* Set 0 to reset timer_group0 wdt module
* Set 1 to reset timer_group0 wdt module
*/
uint32_t tg0_wdt_rst_en:1;
/** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 wdt module
* Set 1 to reset timer_group1 wdt module
*/
uint32_t tg1_wdt_rst_en:1;
uint32_t reserved_2:30;
@ -1800,11 +1758,11 @@ typedef union {
typedef union {
struct {
/** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0;
* Set 0 to reset timer_group0 xtal clock domain
* Set 1 to reset timer_group0 xtal clock domain
*/
uint32_t tg0_xtal_rst_en:1;
/** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset timer_group1 xtal clock domain
* Set 1 to reset timer_group1 xtal clock domain
*/
uint32_t tg1_xtal_rst_en:1;
/** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1;
@ -1816,30 +1774,6 @@ typedef union {
uint32_t val;
} pcr_timergroup_xtal_conf_reg_t;
/** Type of reset_event_bypass register
* reset event bypass backdoor configuration register
*/
typedef union {
struct {
/** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0;
* This field is used to control reset event relationship for
* tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
* by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
* will not only be reset by power-reset, but also some reset event.
*/
uint32_t reset_event_bypass_apm:1;
/** reset_event_bypass : R/W; bitpos: [1]; default: 1;
* This field is used to control reset event relationship for system-bus. 1: system
* bus (including arbiter/router) will only be reset by power-reset. some reset event
* will be bypass. 0: system bus (including arbiter/router) will not only be reset by
* power-reset, but also some reset event.
*/
uint32_t reset_event_bypass:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pcr_reset_event_bypass_reg_t;
/** Type of regdma_conf register
* REGDMA configuration register
*/
@ -1850,7 +1784,7 @@ typedef union {
*/
uint32_t regdma_clk_en:1;
/** regdma_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset regdma module
* Set 1 to reset regdma module
*/
uint32_t regdma_rst_en:1;
uint32_t reserved_2:30;
@ -1868,7 +1802,7 @@ typedef union {
*/
uint32_t etm_clk_en:1;
/** etm_rst_en : R/W; bitpos: [1]; default: 0;
* Set 0 to reset etm module
* Set 1 to reset etm module
*/
uint32_t etm_rst_en:1;
/** etm_ready : RO; bitpos: [2]; default: 1;
@ -1880,19 +1814,42 @@ typedef union {
uint32_t val;
} pcr_etm_conf_reg_t;
/** Type of clock_gate register
* PCR clock gating configure register
/** Type of sdio_slave_conf register
* SDIO_SLAVE configuration register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
/** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable sdio_slave clock
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
uint32_t sdio_slave_clk_en:1;
/** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0;
* Set 1 to reset sdio_slave module
*/
uint32_t sdio_slave_rst_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pcr_clock_gate_reg_t;
} pcr_sdio_slave_conf_reg_t;
/** Type of sdio_slave_pd_ctrl register
* LEDC power control register
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** sdio_mem_force_pu : R/W; bitpos: [1]; default: 1;
* Set this bit to force power down SDIO memory.
*/
uint32_t sdio_mem_force_pu:1;
/** sdio_mem_force_pd : R/W; bitpos: [2]; default: 0;
* Set this bit to force power up SDIO memory.
*/
uint32_t sdio_mem_force_pd:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_sdio_slave_pd_ctrl_reg_t;
/** Group: Frequency Statistics Register */
@ -1915,28 +1872,13 @@ typedef union {
} pcr_sysclk_freq_query_0_reg_t;
/** Group: FPGA Debug Register */
/** Type of fpga_debug register
* fpga debug register
*/
typedef union {
struct {
/** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295;
* Only used in fpga debug.
*/
uint32_t fpga_debug:32;
};
uint32_t val;
} pcr_fpga_debug_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37753376;
/** date : R/W; bitpos: [27:0]; default: 37823120;
* PCR version information.
*/
uint32_t date:28;
@ -2018,18 +1960,19 @@ typedef struct {
volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0;
volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1;
volatile pcr_sec_conf_reg_t sec_conf;
volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf;
uint32_t reserved_11c;
volatile pcr_bus_clk_update_reg_t bus_clk_update;
volatile pcr_sar_clk_div_reg_t sar_clk_div;
volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf;
uint32_t reserved_128;
volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf;
volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf;
volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
uint32_t reserved_134;
volatile pcr_regdma_conf_reg_t regdma_conf;
volatile pcr_etm_conf_reg_t etm_conf;
uint32_t reserved_140[941];
volatile pcr_fpga_debug_reg_t fpga_debug;
volatile pcr_clock_gate_reg_t clock_gate;
uint32_t reserved_140[6];
volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf;
volatile pcr_sdio_slave_pd_ctrl_reg_t sdio_slave_pd_ctrl;
uint32_t reserved_160[935];
volatile pcr_date_reg_t date;
} pcr_dev_t;

23
components/soc/esp32c61/register/soc/reg_base.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,9 +20,12 @@
#define DR_REG_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTMTX_BASE 0x60010000
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_PVT_MONITOR_BASE 0x60019000
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
#define DR_REG_HINF_BASE 0x60016000
#define DR_REG_SLC_BASE 0x60017000
#define DR_REG_HOST_BASE 0x60018000
#define DR_REG_PVT_BASE 0x60019000
#define DR_REG_AHB_DMA_BASE 0x60080000
#define DR_REG_SPI2_BASE 0x60081000
#define DR_REG_SHA_BASE 0x60089000
@ -31,18 +34,13 @@
#define DR_REG_IO_MUX_BASE 0x60090000
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_GPIO_EXT_BASE 0x60091E00
#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000
#define DR_REG_MEM_MONITOR_BASE 0x60092000
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000
#define DR_REG_PCR_BASE 0x60096000
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_MISC_BASE 0x6009F000
#define DR_REG_MODEM0_BASE 0x600A0000
#define DR_REG_MODEM1_BASE 0x600AC000
#define DR_REG_MODEM_PWR0_BASE 0x600AD000
#define DR_REG_MODEM_PWR1_BASE 0x600AF000
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800
#define DR_REG_CPU_APM_REG_BASE 0x6009A000
#define DR_REG_PMU_BASE 0x600B0000
#define DR_REG_LP_CLKRST_BASE 0x600B0400
#define DR_REG_LP_TIMER_BASE 0x600B0C00
@ -55,10 +53,13 @@
#define DR_REG_LP_IO_MUX_BASE 0x600B4000
#define DR_REG_LP_GPIO_BASE 0x600B4400
#define DR_REG_EFUSE0_BASE 0x600B4800
#define DR_REG_EFUSE1_BASE 0x600B4C00
#define DR_REG_OTP_DEBUG_BASE 0x600B4C00
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_BUS_MONITOR_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000
// below are not generated but pick from old file
#define DR_REG_CLINT_M_BASE 0x20000000
#define PWDET_CONF_REG 0x600A0808
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800

576
components/soc/esp32c61/register/soc/sdio_hinf_reg.h Normal file
View File

@ -0,0 +1,576 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HINF_CFG_DATA0_REG register
* Configure sdio cis content
*/
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
#define HINF_DEVICE_ID_FN1 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_S 0
/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
#define HINF_USER_ID_FN1 0x0000FFFFU
#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
#define HINF_USER_ID_FN1_V 0x0000FFFFU
#define HINF_USER_ID_FN1_S 16
/** HINF_CFG_DATA1_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
#define HINF_SDIO_ENABLE_V 0x00000001U
#define HINF_SDIO_ENABLE_S 0
/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
#define HINF_SDIO_IOREADY1_V 0x00000001U
#define HINF_SDIO_IOREADY1_S 1
/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
#define HINF_HIGHSPEED_ENABLE_V 0x00000001U
#define HINF_HIGHSPEED_ENABLE_S 2
/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
#define HINF_HIGHSPEED_MODE_V 0x00000001U
#define HINF_HIGHSPEED_MODE_S 3
/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
#define HINF_SDIO_CD_ENABLE_V 0x00000001U
#define HINF_SDIO_CD_ENABLE_S 4
/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
#define HINF_SDIO_IOREADY2_V 0x00000001U
#define HINF_SDIO_IOREADY2_S 5
/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
#define HINF_SDIO_INT_MASK_V 0x00000001U
#define HINF_SDIO_INT_MASK_S 6
/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
#define HINF_IOENABLE2_V 0x00000001U
#define HINF_IOENABLE2_S 7
/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
#define HINF_CD_DISABLE_V 0x00000001U
#define HINF_CD_DISABLE_S 8
/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
#define HINF_FUNC1_EPS_V 0x00000001U
#define HINF_FUNC1_EPS_S 9
/** HINF_EMP : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S)
#define HINF_EMP_V 0x00000001U
#define HINF_EMP_S 10
/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
#define HINF_IOENABLE1_V 0x00000001U
#define HINF_IOENABLE1_S 11
/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
#define HINF_SDIO_VER 0x00000FFFU
#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
#define HINF_SDIO_VER_V 0x00000FFFU
#define HINF_SDIO_VER_S 12
/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
#define HINF_FUNC2_EPS (BIT(24))
#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
#define HINF_FUNC2_EPS_V 0x00000001U
#define HINF_FUNC2_EPS_S 24
/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
#define HINF_SDIO20_CONF 0x0000007FU
#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
#define HINF_SDIO20_CONF_V 0x0000007FU
#define HINF_SDIO20_CONF_S 25
/** HINF_CFG_TIMING_REG register
* Timing configuration registers
*/
#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
#define HINF_NCRC 0x00000007U
#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S)
#define HINF_NCRC_V 0x00000007U
#define HINF_NCRC_S 0
/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_S 3
/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_S 10
/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
#define HINF_SDCLK_STOP_THRES 0x000007FFU
#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
#define HINF_SDCLK_STOP_THRES_V 0x000007FFU
#define HINF_SDCLK_STOP_THRES_S 16
/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_S 28
/** HINF_CFG_UPDATE_REG register
* update sdio configurations
*/
#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
#define HINF_CONF_UPDATE (BIT(0))
#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
#define HINF_CONF_UPDATE_V 0x00000001U
#define HINF_CONF_UPDATE_S 0
/** HINF_CFG_DATA7_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
#define HINF_PIN_STATE 0x000000FFU
#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
#define HINF_PIN_STATE_V 0x000000FFU
#define HINF_PIN_STATE_S 0
/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
#define HINF_CHIP_STATE 0x000000FFU
#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
#define HINF_CHIP_STATE_V 0x000000FFU
#define HINF_CHIP_STATE_S 8
/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
#define HINF_SDIO_RST_V 0x00000001U
#define HINF_SDIO_RST_S 16
/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
#define HINF_SDIO_IOREADY0_V 0x00000001U
#define HINF_SDIO_IOREADY0_S 17
/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
#define HINF_SDIO_MEM_PD (BIT(18))
#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
#define HINF_SDIO_MEM_PD_V 0x00000001U
#define HINF_SDIO_MEM_PD_S 18
/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
#define HINF_ESDIO_DATA1_INT_EN (BIT(19))
#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U
#define HINF_ESDIO_DATA1_INT_EN_S 19
/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20))
#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_SW_S 20
/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21))
#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U
#define HINF_DDR50_BLK_LEN_FIX_EN_S 21
/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
#define HINF_CLK_EN (BIT(22))
#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S)
#define HINF_CLK_EN_V 0x00000001U
#define HINF_CLK_EN_S 22
/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
#define HINF_SDDR50 (BIT(23))
#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S)
#define HINF_SDDR50_V 0x00000001U
#define HINF_SDDR50_S 23
/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
#define HINF_SSDR104 (BIT(24))
#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S)
#define HINF_SSDR104_V 0x00000001U
#define HINF_SSDR104_S 24
/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
#define HINF_SSDR50 (BIT(25))
#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S)
#define HINF_SSDR50_V 0x00000001U
#define HINF_SSDR50_S 25
/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
#define HINF_SDTD (BIT(26))
#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S)
#define HINF_SDTD_V 0x00000001U
#define HINF_SDTD_S 26
/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
#define HINF_SDTA (BIT(27))
#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S)
#define HINF_SDTA_V 0x00000001U
#define HINF_SDTA_S 27
/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
#define HINF_SDTC (BIT(28))
#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S)
#define HINF_SDTC_V 0x00000001U
#define HINF_SDTC_S 28
/** HINF_SAI : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
#define HINF_SAI (BIT(29))
#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S)
#define HINF_SAI_V 0x00000001U
#define HINF_SAI_S 29
/** HINF_SDIO_WAKEUP_CLR : R/W; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
#define HINF_SDIO_WAKEUP_CLR (BIT(30))
#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U
#define HINF_SDIO_WAKEUP_CLR_S 30
/** HINF_CIS_CONF_W0_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
#define HINF_CIS_CONF_W0 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_S 0
/** HINF_CIS_CONF_W1_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
#define HINF_CIS_CONF_W1 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_S 0
/** HINF_CIS_CONF_W2_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
#define HINF_CIS_CONF_W2 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_S 0
/** HINF_CIS_CONF_W3_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
#define HINF_CIS_CONF_W3 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_S 0
/** HINF_CIS_CONF_W4_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
#define HINF_CIS_CONF_W4 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_S 0
/** HINF_CIS_CONF_W5_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
#define HINF_CIS_CONF_W5 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_S 0
/** HINF_CIS_CONF_W6_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
#define HINF_CIS_CONF_W6 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_S 0
/** HINF_CIS_CONF_W7_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
#define HINF_CIS_CONF_W7 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_S 0
/** HINF_CFG_DATA16_REG register
* SDIO cis configuration register
*/
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
#define HINF_DEVICE_ID_FN2 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_S 0
/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
#define HINF_USER_ID_FN2 0x0000FFFFU
#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
#define HINF_USER_ID_FN2_V 0x0000FFFFU
#define HINF_USER_ID_FN2_S 16
/** HINF_CFG_UHS1_INT_MODE_REG register
* configure int to start and end ahead of time in uhs1 mode
*/
#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_END_AHEAD_MODE 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_S 0
/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_END_AHEAD_MODE 0x00000003U
#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
#define HINF_INT_END_AHEAD_MODE_V 0x00000003U
#define HINF_INT_END_AHEAD_MODE_S 2
/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_S 4
/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_ST_AHEAD_MODE 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_S 6
/** HINF_CONF_STATUS_REG register
* func0 config0 status
*/
#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
#define HINF_FUNC0_CONFIG0 0x000000FFU
#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
#define HINF_FUNC0_CONFIG0_V 0x000000FFU
#define HINF_FUNC0_CONFIG0_S 0
/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
#define HINF_SDR25_ST (BIT(8))
#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
#define HINF_SDR25_ST_V 0x00000001U
#define HINF_SDR25_ST_S 8
/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
#define HINF_SDR50_ST (BIT(9))
#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
#define HINF_SDR50_ST_V 0x00000001U
#define HINF_SDR50_ST_S 9
/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
#define HINF_SDR104_ST (BIT(10))
#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
#define HINF_SDR104_ST_V 0x00000001U
#define HINF_SDR104_ST_S 10
/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
#define HINF_DDR50_ST (BIT(11))
#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
#define HINF_DDR50_ST_V 0x00000001U
#define HINF_DDR50_ST_S 11
/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
#define HINF_TUNE_ST 0x00000007U
#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
#define HINF_TUNE_ST_V 0x00000007U
#define HINF_TUNE_ST_S 12
/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15))
#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_ST_S 15
/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
#define HINF_SDIO_SWITCH_END (BIT(16))
#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
#define HINF_SDIO_SWITCH_END_V 0x00000001U
#define HINF_SDIO_SWITCH_END_S 16
/** HINF_SDIO_SLAVE_LDO_CONF_REG register
* sdio slave ldo control register
*/
#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
#define HINF_LDO_READY_CTL_IN_EN (BIT(0))
#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U
#define HINF_LDO_READY_CTL_IN_EN_S 0
/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
#define HINF_LDO_READY_THRES 0x0000001FU
#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
#define HINF_LDO_READY_THRES_V 0x0000001FU
#define HINF_LDO_READY_THRES_S 1
/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
#define HINF_LDO_READY_IGNORE_EN (BIT(6))
#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U
#define HINF_LDO_READY_IGNORE_EN_S 6
/** HINF_SDIO_DATE_REG register
* ******* Description ***********
*/
#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 37822544;
* sdio version date.
*/
#define HINF_SDIO_DATE 0xFFFFFFFFU
#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
#define HINF_SDIO_DATE_V 0xFFFFFFFFU
#define HINF_SDIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration registers */
/** Type of cfg_data0 register
* Configure sdio cis content
*/
typedef union {
struct {
/** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
uint32_t device_id_fn1:16;
/** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
uint32_t user_id_fn1:16;
};
uint32_t val;
} hinf_cfg_data0_reg_t;
/** Type of cfg_data1 register
* SDIO configuration register
*/
typedef union {
struct {
/** sdio_enable : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
uint32_t sdio_enable:1;
/** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready1:1;
/** highspeed_enable : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
uint32_t highspeed_enable:1;
/** highspeed_mode : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
uint32_t highspeed_mode:1;
/** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
uint32_t sdio_cd_enable:1;
/** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready2:1;
/** sdio_int_mask : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
uint32_t sdio_int_mask:1;
/** ioenable2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
uint32_t ioenable2:1;
/** cd_disable : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
uint32_t cd_disable:1;
/** func1_eps : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
uint32_t func1_eps:1;
/** emp : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
uint32_t emp:1;
/** ioenable1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
uint32_t ioenable1:1;
/** sdio_ver : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
uint32_t sdio_ver:12;
/** func2_eps : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
uint32_t func2_eps:1;
/** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
uint32_t sdio20_conf:7;
};
uint32_t val;
} hinf_cfg_data1_reg_t;
/** Type of cfg_timing register
* Timing configuration registers
*/
typedef union {
struct {
/** ncrc : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
uint32_t ncrc:3;
/** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
uint32_t pst_end_cmd_low_value:7;
/** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
uint32_t pst_end_data_low_value:6;
/** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
uint32_t sdclk_stop_thres:11;
uint32_t reserved_27:1;
/** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
uint32_t sample_clk_divider:4;
};
uint32_t val;
} hinf_cfg_timing_reg_t;
/** Type of cfg_update register
* update sdio configurations
*/
typedef union {
struct {
/** conf_update : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
uint32_t conf_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hinf_cfg_update_reg_t;
/** Type of cfg_data7 register
* SDIO configuration register
*/
typedef union {
struct {
/** pin_state : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
uint32_t pin_state:8;
/** chip_state : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
uint32_t chip_state:8;
/** sdio_rst : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
uint32_t sdio_rst:1;
/** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
uint32_t sdio_ioready0:1;
/** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
uint32_t sdio_mem_pd:1;
/** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
uint32_t esdio_data1_int_en:1;
/** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
uint32_t sdio_switch_volt_sw:1;
/** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
uint32_t ddr50_blk_len_fix_en:1;
/** clk_en : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
uint32_t clk_en:1;
/** sddr50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
uint32_t sddr50:1;
/** ssdr104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
uint32_t ssdr104:1;
/** ssdr50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
uint32_t ssdr50:1;
/** sdtd : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
uint32_t sdtd:1;
/** sdta : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
uint32_t sdta:1;
/** sdtc : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
uint32_t sdtc:1;
/** sai : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
uint32_t sai:1;
/** sdio_wakeup_clr : R/W; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
uint32_t sdio_wakeup_clr:1;
uint32_t reserved_31:1;
};
uint32_t val;
} hinf_cfg_data7_reg_t;
/** Type of cis_conf_w0 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
uint32_t cis_conf_w0:32;
};
uint32_t val;
} hinf_cis_conf_w0_reg_t;
/** Type of cis_conf_w1 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
uint32_t cis_conf_w1:32;
};
uint32_t val;
} hinf_cis_conf_w1_reg_t;
/** Type of cis_conf_w2 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
uint32_t cis_conf_w2:32;
};
uint32_t val;
} hinf_cis_conf_w2_reg_t;
/** Type of cis_conf_w3 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
uint32_t cis_conf_w3:32;
};
uint32_t val;
} hinf_cis_conf_w3_reg_t;
/** Type of cis_conf_w4 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
uint32_t cis_conf_w4:32;
};
uint32_t val;
} hinf_cis_conf_w4_reg_t;
/** Type of cis_conf_w5 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
uint32_t cis_conf_w5:32;
};
uint32_t val;
} hinf_cis_conf_w5_reg_t;
/** Type of cis_conf_w6 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
uint32_t cis_conf_w6:32;
};
uint32_t val;
} hinf_cis_conf_w6_reg_t;
/** Type of cis_conf_w7 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
uint32_t cis_conf_w7:32;
};
uint32_t val;
} hinf_cis_conf_w7_reg_t;
/** Type of cfg_data16 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
uint32_t device_id_fn2:16;
/** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
uint32_t user_id_fn2:16;
};
uint32_t val;
} hinf_cfg_data16_reg_t;
/** Type of cfg_uhs1_int_mode register
* configure int to start and end ahead of time in uhs1 mode
*/
typedef union {
struct {
/** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_end_ahead_mode:2;
/** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_end_ahead_mode:2;
/** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_st_ahead_mode:2;
/** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_st_ahead_mode:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hinf_cfg_uhs1_int_mode_reg_t;
/** Type of sdio_slave_ldo_conf register
* sdio slave ldo control register
*/
typedef union {
struct {
/** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
uint32_t ldo_ready_ctl_in_en:1;
/** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
uint32_t ldo_ready_thres:5;
/** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
uint32_t ldo_ready_ignore_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hinf_sdio_slave_ldo_conf_reg_t;
/** Group: Status registers */
/** Type of conf_status register
* func0 config0 status
*/
typedef union {
struct {
/** func0_config0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
uint32_t func0_config0:8;
/** sdr25_st : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
uint32_t sdr25_st:1;
/** sdr50_st : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
uint32_t sdr50_st:1;
/** sdr104_st : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
uint32_t sdr104_st:1;
/** ddr50_st : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
uint32_t ddr50_st:1;
/** tune_st : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
uint32_t tune_st:3;
/** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
uint32_t sdio_switch_volt_st:1;
/** sdio_switch_end : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
uint32_t sdio_switch_end:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hinf_conf_status_reg_t;
/** Group: Version register */
/** Type of sdio_date register
* ******* Description ***********
*/
typedef union {
struct {
/** sdio_date : R/W; bitpos: [31:0]; default: 37822544;
* sdio version date.
*/
uint32_t sdio_date:32;
};
uint32_t val;
} hinf_sdio_date_reg_t;
typedef struct {
volatile hinf_cfg_data0_reg_t cfg_data0;
volatile hinf_cfg_data1_reg_t cfg_data1;
volatile hinf_cfg_timing_reg_t cfg_timing;
volatile hinf_cfg_update_reg_t cfg_update;
uint32_t reserved_010[3];
volatile hinf_cfg_data7_reg_t cfg_data7;
volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
volatile hinf_cfg_data16_reg_t cfg_data16;
volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
uint32_t reserved_048[3];
volatile hinf_conf_status_reg_t conf_status;
uint32_t reserved_058[22];
volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
uint32_t reserved_0b4[18];
volatile hinf_sdio_date_reg_t sdio_date;
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifndef __cplusplus
_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c61/register/soc/spi1_mem_reg.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -35,6 +35,7 @@ extern "C" {
* In user mode, it is set to indicate that program/erase operation will be triggered.
* The bit is combined with spi_mem_usr bit. The bit will be cleared once the
* operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_PE (BIT(17))
#define SPI_MEM_FLASH_PE_M (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S)
@ -51,6 +52,7 @@ extern "C" {
/** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
* Drive Flash into high performance mode. The bit will be cleared once the operation
* done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_HPM (BIT(19))
#define SPI_MEM_FLASH_HPM_M (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S)
@ -60,6 +62,7 @@ extern "C" {
* This bit combined with reg_resandres bit releases Flash from the power-down state
* or high performance mode and obtains the devices ID. The bit will be cleared once
* the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_RES (BIT(20))
#define SPI_MEM_FLASH_RES_M (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S)
@ -68,6 +71,7 @@ extern "C" {
/** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
* Drive Flash into power down. An operation will be triggered when the bit is set.
* The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_DP (BIT(21))
#define SPI_MEM_FLASH_DP_M (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S)
@ -76,6 +80,7 @@ extern "C" {
/** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
* Chip erase enable. Chip erase operation will be triggered when the bit is set. The
* bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_CE (BIT(22))
#define SPI_MEM_FLASH_CE_M (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S)
@ -84,6 +89,7 @@ extern "C" {
/** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
* Block erase enable(32KB) . Block erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_BE (BIT(23))
#define SPI_MEM_FLASH_BE_M (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S)
@ -92,6 +98,7 @@ extern "C" {
/** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
* Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_SE (BIT(24))
#define SPI_MEM_FLASH_SE_M (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S)
@ -101,6 +108,7 @@ extern "C" {
* Page program enable(1 byte ~256 bytes data to be programmed). Page program
* operation will be triggered when the bit is set. The bit will be cleared once the
* operation done .1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_PP (BIT(25))
#define SPI_MEM_FLASH_PP_M (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S)
@ -109,6 +117,7 @@ extern "C" {
/** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
* Write status register enable. Write status operation will be triggered when the
* bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_WRSR (BIT(26))
#define SPI_MEM_FLASH_WRSR_M (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S)
@ -117,6 +126,7 @@ extern "C" {
/** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
* Read status register-1. Read status operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_RDSR (BIT(27))
#define SPI_MEM_FLASH_RDSR_M (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S)
@ -125,6 +135,7 @@ extern "C" {
/** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
* Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
* cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_RDID (BIT(28))
#define SPI_MEM_FLASH_RDID_M (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S)
@ -133,6 +144,7 @@ extern "C" {
/** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
* Write flash disable. Write disable command will be sent when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_WRDI (BIT(29))
#define SPI_MEM_FLASH_WRDI_M (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S)
@ -141,6 +153,7 @@ extern "C" {
/** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
* Write flash enable. Write enable command will be sent when the bit is set. The bit
* will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_WREN (BIT(30))
#define SPI_MEM_FLASH_WREN_M (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S)
@ -149,6 +162,7 @@ extern "C" {
/** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
* Read flash enable. Read flash operation will be triggered when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FLASH_READ (BIT(31))
#define SPI_MEM_FLASH_READ_M (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S)
@ -226,6 +240,7 @@ extern "C" {
/** SPI_MEM_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
* For SPI1, initialize crc32 module before writing encrypted data to flash. Active
* low.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FCS_CRC_EN (BIT(10))
#define SPI_MEM_FCS_CRC_EN_M (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S)
@ -233,6 +248,7 @@ extern "C" {
#define SPI_MEM_FCS_CRC_EN_S 10
/** SPI_MEM_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
* For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_TX_CRC_EN (BIT(11))
#define SPI_MEM_TX_CRC_EN_M (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S)
@ -256,6 +272,7 @@ extern "C" {
/** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1;
* The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
* spi_mem_flash_res bit. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_RESANDRES (BIT(15))
#define SPI_MEM_RESANDRES_M (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S)
@ -292,6 +309,7 @@ extern "C" {
/** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0;
* two bytes data will be written to status register when it is set. 1: enable 0:
* disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WRSR_2B (BIT(22))
#define SPI_MEM_WRSR_2B_M (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S)
@ -328,13 +346,21 @@ extern "C" {
#define SPI_MEM_CLK_MODE_V 0x00000003U
#define SPI_MEM_CLK_MODE_S 0
/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
* SPI_CLK cycles.
* After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
* 128) SPI_CLK cycles.
*/
#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S)
#define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_RES_S 2
/** SPI_MEM_CS_HOLD_DLY_PER : R/W; bitpos: [21:12]; default: 1023;
* After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK
* cycles.
*/
#define SPI_MEM_CS_HOLD_DLY_PER 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_PER_M (SPI_MEM_CS_HOLD_DLY_PER_V << SPI_MEM_CS_HOLD_DLY_PER_S)
#define SPI_MEM_CS_HOLD_DLY_PER_V 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_PER_S 12
/** SPI_MEM_CTRL2_REG register
* SPI1 control2 register.
@ -353,14 +379,14 @@ extern "C" {
*/
#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)
/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
* In the master mode it must be equal to SPI_MEM_CLKCNT_N.
*/
#define SPI_MEM_CLKCNT_L 0x000000FFU
#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
#define SPI_MEM_CLKCNT_L_V 0x000000FFU
#define SPI_MEM_CLKCNT_L_S 0
/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
* In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1).
*/
#define SPI_MEM_CLKCNT_H 0x000000FFU
#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
@ -368,7 +394,7 @@ extern "C" {
#define SPI_MEM_CLKCNT_H_S 8
/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi_mem_clkcnt_N+1)
* system/(SPI_MEM_CLKCNT_N+1)
*/
#define SPI_MEM_CLKCNT_N 0x000000FFU
#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
@ -556,6 +582,7 @@ extern "C" {
#define SPI_MEM_STATUS_S 0
/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE 0x000000FFU
#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
@ -563,6 +590,7 @@ extern "C" {
#define SPI_MEM_WB_MODE_S 16
/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0;
* Mode bits length for flash fast read mode.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE_BITLEN 0x00000007U
#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S)
@ -570,6 +598,7 @@ extern "C" {
#define SPI_MEM_WB_MODE_BITLEN_S 24
/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0;
* Mode bits is valid while this bit is enable. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE_EN (BIT(27))
#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S)
@ -625,10 +654,13 @@ extern "C" {
/** SPI_MEM_CACHE_FCTRL_REG register
* SPI1 bit mode control register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c)
/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1))
#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S)
@ -637,6 +669,7 @@ extern "C" {
/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
* For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
* spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FDIN_DUAL (BIT(3))
#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S)
@ -645,6 +678,7 @@ extern "C" {
/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
* For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FDOUT_DUAL (BIT(4))
#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S)
@ -653,6 +687,7 @@ extern "C" {
/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
* For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FADDR_DUAL (BIT(5))
#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S)
@ -661,6 +696,7 @@ extern "C" {
/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
* For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FDIN_QUAD (BIT(6))
#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S)
@ -669,6 +705,7 @@ extern "C" {
/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
* For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FDOUT_QUAD (BIT(7))
#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S)
@ -677,6 +714,7 @@ extern "C" {
/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
* For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_FADDR_QUAD (BIT(8))
#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S)
@ -999,14 +1037,14 @@ extern "C" {
#define SPI_MEM_PESR_END_MSK_M (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S)
#define SPI_MEM_PESR_END_MSK_V 0x0000FFFFU
#define SPI_MEM_PESR_END_MSK_S 6
/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
/** SPI_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
* 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when
* check flash SUS/SUS1/SUS2 status bit
*/
#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22))
#define SPI_MEM_FMEM_RD_SUS_2B_M (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S)
#define SPI_MEM_FMEM_RD_SUS_2B_V 0x00000001U
#define SPI_MEM_FMEM_RD_SUS_2B_S 22
#define SPI_FMEM_RD_SUS_2B (BIT(22))
#define SPI_FMEM_RD_SUS_2B_M (SPI_FMEM_RD_SUS_2B_V << SPI_FMEM_RD_SUS_2B_S)
#define SPI_FMEM_RD_SUS_2B_V 0x00000001U
#define SPI_FMEM_RD_SUS_2B_S 22
/** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0;
* 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
* flash. 0: Only need to check WIP is 0.
@ -1361,110 +1399,110 @@ extern "C" {
* SPI1 DDR control register
*/
#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4)
/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
* 1: in ddr mode, 0 in sdr mode
*/
#define SPI_MEM_FMEM_DDR_EN (BIT(0))
#define SPI_MEM_FMEM_DDR_EN_M (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S)
#define SPI_MEM_FMEM_DDR_EN_V 0x00000001U
#define SPI_MEM_FMEM_DDR_EN_S 0
/** SPI_MEM_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
#define SPI_FMEM_DDR_EN (BIT(0))
#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S)
#define SPI_FMEM_DDR_EN_V 0x00000001U
#define SPI_FMEM_DDR_EN_S 0
/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
* Set the bit to enable variable dummy cycle in spi ddr mode.
*/
#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1))
#define SPI_MEM_FMEM_VAR_DUMMY_M (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S)
#define SPI_MEM_FMEM_VAR_DUMMY_V 0x00000001U
#define SPI_MEM_FMEM_VAR_DUMMY_S 1
/** SPI_MEM_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
#define SPI_FMEM_VAR_DUMMY (BIT(1))
#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S)
#define SPI_FMEM_VAR_DUMMY_V 0x00000001U
#define SPI_FMEM_VAR_DUMMY_S 1
/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
* Set the bit to reorder rx data of the word in spi ddr mode.
*/
#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2))
#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S)
#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x00000001U
#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2
/** SPI_MEM_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
#define SPI_FMEM_DDR_RDAT_SWP (BIT(2))
#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S)
#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U
#define SPI_FMEM_DDR_RDAT_SWP_S 2
/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
* Set the bit to reorder tx data of the word in spi ddr mode.
*/
#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3))
#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S)
#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x00000001U
#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3
/** SPI_MEM_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
#define SPI_FMEM_DDR_WDAT_SWP (BIT(3))
#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S)
#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U
#define SPI_FMEM_DDR_WDAT_SWP_S 3
/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
* the bit is used to disable dual edge in command phase when ddr mode.
*/
#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4))
#define SPI_MEM_FMEM_DDR_CMD_DIS_M (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S)
#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x00000001U
#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4
/** SPI_MEM_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
#define SPI_FMEM_DDR_CMD_DIS (BIT(4))
#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S)
#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U
#define SPI_FMEM_DDR_CMD_DIS_S 4
/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
* It is the minimum output data length in the panda device.
*/
#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007FU
#define SPI_MEM_FMEM_OUTMINBYTELEN_M (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S)
#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x0000007FU
#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5
/** SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU
#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S)
#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU
#define SPI_FMEM_OUTMINBYTELEN_S 5
/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
* The delay number of data strobe which from memory based on SPI clock.
*/
#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007FU
#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S)
#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x0000007FU
#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14
/** SPI_MEM_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU
#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S)
#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU
#define SPI_FMEM_USR_DDR_DQS_THD_S 14
/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS.
*/
#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21))
#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S)
#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x00000001U
#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21
/** SPI_MEM_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
#define SPI_FMEM_DDR_DQS_LOOP (BIT(21))
#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S)
#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U
#define SPI_FMEM_DDR_DQS_LOOP_S 21
/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
* Set this bit to enable the differential SPI_CLK#.
*/
#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24))
#define SPI_MEM_FMEM_CLK_DIFF_EN_M (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S)
#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x00000001U
#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24
/** SPI_MEM_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
#define SPI_FMEM_CLK_DIFF_EN (BIT(24))
#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S)
#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U
#define SPI_FMEM_CLK_DIFF_EN_S 24
/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
* Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
*/
#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26))
#define SPI_MEM_FMEM_DQS_CA_IN_M (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S)
#define SPI_MEM_FMEM_DQS_CA_IN_V 0x00000001U
#define SPI_MEM_FMEM_DQS_CA_IN_S 26
/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
#define SPI_FMEM_DQS_CA_IN (BIT(26))
#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S)
#define SPI_FMEM_DQS_CA_IN_V 0x00000001U
#define SPI_FMEM_DQS_CA_IN_S 26
/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
* Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
* accesses flash or SPI1 accesses flash or sram.
*/
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27))
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S)
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U
#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27
/** SPI_MEM_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27))
#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S)
#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U
#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27
/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
* Set this bit to invert SPI_DIFF when accesses to flash. .
*/
#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28))
#define SPI_MEM_FMEM_CLK_DIFF_INV_M (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S)
#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x00000001U
#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28
/** SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
#define SPI_FMEM_CLK_DIFF_INV (BIT(28))
#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S)
#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U
#define SPI_FMEM_CLK_DIFF_INV_S 28
/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
* Set this bit to enable octa_ram address out when accesses to flash, which means
* ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
*/
#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29))
#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S)
#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x00000001U
#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29
/** SPI_MEM_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29))
#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S)
#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U
#define SPI_FMEM_OCTA_RAM_ADDR_S 29
/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
* Set this bit to enable HyperRAM address out when accesses to flash, which means
* ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
*/
#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30))
#define SPI_MEM_FMEM_HYPERBUS_CA_M (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S)
#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x00000001U
#define SPI_MEM_FMEM_HYPERBUS_CA_S 30
#define SPI_FMEM_HYPERBUS_CA (BIT(30))
#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S)
#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U
#define SPI_FMEM_HYPERBUS_CA_S 30
/** SPI_MEM_TIMING_CALI_REG register
* SPI1 timing control register
@ -1501,7 +1539,7 @@ extern "C" {
* Version control register
*/
#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400;
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37823232;
* Version control register
*/
#define SPI_MEM_DATE 0x0FFFFFFFU

259
components/soc/esp32c61/register/soc/spi1_mem_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -31,6 +31,7 @@ typedef union {
* In user mode, it is set to indicate that program/erase operation will be triggered.
* The bit is combined with spi_mem_usr bit. The bit will be cleared once the
* operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_pe:1;
/** usr : R/W/SC; bitpos: [18]; default: 0;
@ -41,68 +42,81 @@ typedef union {
/** flash_hpm : R/W/SC; bitpos: [19]; default: 0;
* Drive Flash into high performance mode. The bit will be cleared once the operation
* done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_hpm:1;
/** flash_res : R/W/SC; bitpos: [20]; default: 0;
* This bit combined with reg_resandres bit releases Flash from the power-down state
* or high performance mode and obtains the devices ID. The bit will be cleared once
* the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_res:1;
/** flash_dp : R/W/SC; bitpos: [21]; default: 0;
* Drive Flash into power down. An operation will be triggered when the bit is set.
* The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_dp:1;
/** flash_ce : R/W/SC; bitpos: [22]; default: 0;
* Chip erase enable. Chip erase operation will be triggered when the bit is set. The
* bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_ce:1;
/** flash_be : R/W/SC; bitpos: [23]; default: 0;
* Block erase enable(32KB) . Block erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_be:1;
/** flash_se : R/W/SC; bitpos: [24]; default: 0;
* Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_se:1;
/** flash_pp : R/W/SC; bitpos: [25]; default: 0;
* Page program enable(1 byte ~256 bytes data to be programmed). Page program
* operation will be triggered when the bit is set. The bit will be cleared once the
* operation done .1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_pp:1;
/** flash_wrsr : R/W/SC; bitpos: [26]; default: 0;
* Write status register enable. Write status operation will be triggered when the
* bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_wrsr:1;
/** flash_rdsr : R/W/SC; bitpos: [27]; default: 0;
* Read status register-1. Read status operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_rdsr:1;
/** flash_rdid : R/W/SC; bitpos: [28]; default: 0;
* Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
* cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_rdid:1;
/** flash_wrdi : R/W/SC; bitpos: [29]; default: 0;
* Write flash disable. Write disable command will be sent when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_wrdi:1;
/** flash_wren : R/W/SC; bitpos: [30]; default: 0;
* Write flash enable. Write enable command will be sent when the bit is set. The bit
* will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_wren:1;
/** flash_read : R/W/SC; bitpos: [31]; default: 0;
* Read flash enable. Read flash operation will be triggered when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t flash_read:1;
};
@ -268,10 +282,12 @@ typedef union {
/** fcs_crc_en : R/W; bitpos: [10]; default: 0;
* For SPI1, initialize crc32 module before writing encrypted data to flash. Active
* low.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t fcs_crc_en:1;
/** tx_crc_en : R/W; bitpos: [11]; default: 0;
* For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t tx_crc_en:1;
uint32_t reserved_12:1;
@ -287,6 +303,7 @@ typedef union {
/** resandres : R/W; bitpos: [15]; default: 1;
* The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
* spi_mem_flash_res bit. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t resandres:1;
uint32_t reserved_16:2;
@ -309,6 +326,7 @@ typedef union {
/** wrsr_2b : R/W; bitpos: [22]; default: 0;
* two bytes data will be written to status register when it is set. 1: enable 0:
* disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wrsr_2b:1;
/** fread_dio : R/W; bitpos: [23]; default: 0;
@ -338,11 +356,16 @@ typedef union {
*/
uint32_t clk_mode:2;
/** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
* SPI_CLK cycles.
* After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
* 128) SPI_CLK cycles.
*/
uint32_t cs_hold_dly_res:10;
uint32_t reserved_12:20;
/** cs_hold_dly_per : R/W; bitpos: [21:12]; default: 1023;
* After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK
* cycles.
*/
uint32_t cs_hold_dly_per:10;
uint32_t reserved_22:10;
};
uint32_t val;
} spi_mem_ctrl1_reg_t;
@ -367,16 +390,16 @@ typedef union {
typedef union {
struct {
/** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
* In the master mode it must be equal to SPI_MEM_CLKCNT_N.
*/
uint32_t clkcnt_l:8;
/** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
* In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1).
*/
uint32_t clkcnt_h:8;
/** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi_mem_clkcnt_N+1)
* system/(SPI_MEM_CLKCNT_N+1)
*/
uint32_t clkcnt_n:8;
uint32_t reserved_24:7;
@ -427,14 +450,17 @@ typedef union {
uint32_t status:16;
/** wb_mode : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode:8;
/** wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0;
* Mode bits length for flash fast read mode.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode_bitlen:3;
/** wb_mode_en : R/W; bitpos: [27]; default: 0;
* Mode bits is valid while this bit is enable. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wb_mode_en:1;
uint32_t reserved_28:4;
@ -479,37 +505,44 @@ typedef union {
uint32_t reserved_0:1;
/** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t cache_usr_addr_4byte:1;
uint32_t reserved_2:1;
/** fdin_dual : R/W; bitpos: [3]; default: 0;
* For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
* spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t fdin_dual:1;
/** fdout_dual : R/W; bitpos: [4]; default: 0;
* For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t fdout_dual:1;
/** faddr_dual : R/W; bitpos: [5]; default: 0;
* For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t faddr_dual:1;
/** fdin_quad : R/W; bitpos: [6]; default: 0;
* For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t fdin_quad:1;
/** fdout_quad : R/W; bitpos: [7]; default: 0;
* For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t fdout_quad:1;
/** faddr_quad : R/W; bitpos: [8]; default: 0;
* For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t faddr_quad:1;
uint32_t reserved_9:23;
@ -834,216 +867,6 @@ typedef union {
} spi_mem_tx_crc_reg_t;
/** Group: Memory data buffer register */
/** Type of word buffer register
* SPI1 memory data buffer_n
*/
typedef union {
struct {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf0:32;
};
uint32_t val;
} spi_mem_buffer_reg_t;
/** Type of w1 register
* SPI1 memory data buffer1
*/
typedef union {
struct {
/** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf1:32;
};
uint32_t val;
} spi_mem_w1_reg_t;
/** Type of w2 register
* SPI1 memory data buffer2
*/
typedef union {
struct {
/** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf2:32;
};
uint32_t val;
} spi_mem_w2_reg_t;
/** Type of w3 register
* SPI1 memory data buffer3
*/
typedef union {
struct {
/** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf3:32;
};
uint32_t val;
} spi_mem_w3_reg_t;
/** Type of w4 register
* SPI1 memory data buffer4
*/
typedef union {
struct {
/** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf4:32;
};
uint32_t val;
} spi_mem_w4_reg_t;
/** Type of w5 register
* SPI1 memory data buffer5
*/
typedef union {
struct {
/** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf5:32;
};
uint32_t val;
} spi_mem_w5_reg_t;
/** Type of w6 register
* SPI1 memory data buffer6
*/
typedef union {
struct {
/** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf6:32;
};
uint32_t val;
} spi_mem_w6_reg_t;
/** Type of w7 register
* SPI1 memory data buffer7
*/
typedef union {
struct {
/** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf7:32;
};
uint32_t val;
} spi_mem_w7_reg_t;
/** Type of w8 register
* SPI1 memory data buffer8
*/
typedef union {
struct {
/** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf8:32;
};
uint32_t val;
} spi_mem_w8_reg_t;
/** Type of w9 register
* SPI1 memory data buffer9
*/
typedef union {
struct {
/** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf9:32;
};
uint32_t val;
} spi_mem_w9_reg_t;
/** Type of w10 register
* SPI1 memory data buffer10
*/
typedef union {
struct {
/** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf10:32;
};
uint32_t val;
} spi_mem_w10_reg_t;
/** Type of w11 register
* SPI1 memory data buffer11
*/
typedef union {
struct {
/** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf11:32;
};
uint32_t val;
} spi_mem_w11_reg_t;
/** Type of w12 register
* SPI1 memory data buffer12
*/
typedef union {
struct {
/** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf12:32;
};
uint32_t val;
} spi_mem_w12_reg_t;
/** Type of w13 register
* SPI1 memory data buffer13
*/
typedef union {
struct {
/** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf13:32;
};
uint32_t val;
} spi_mem_w13_reg_t;
/** Type of w14 register
* SPI1 memory data buffer14
*/
typedef union {
struct {
/** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf14:32;
};
uint32_t val;
} spi_mem_w14_reg_t;
/** Type of w15 register
* SPI1 memory data buffer15
*/
typedef union {
struct {
/** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf15:32;
};
uint32_t val;
} spi_mem_w15_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena register
* SPI1 interrupt enable register
@ -1222,7 +1045,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774400;
/** date : R/W; bitpos: [27:0]; default: 37823232;
* Version control register
*/
uint32_t date:28;

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components/soc/esp32c61/register/soc/spi_mem_c_struct.h
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components/soc/esp32c61/register/soc/spi_reg.h
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components/soc/esp32c61/register/soc/spi_struct.h
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19
components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -540,13 +540,6 @@ extern "C" {
* PHY hardware configuration.
*/
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY
*/
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U
#define USB_SERIAL_JTAG_PHY_SEL_S 0
/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D- exchange
*/
@ -640,6 +633,14 @@ extern "C" {
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15
/** USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL : R/W; bitpos: [16]; default: 0;
* Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at
* clock negative edge. 1: tx output at clock positive edge.
*/
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL (BIT(16))
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S)
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V 0x00000001U
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S 16
/** USB_SERIAL_JTAG_TEST_REG register
* Registers used for debugging the PHY.
@ -1215,7 +1216,7 @@ extern "C" {
* Date register
*/
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368;
/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 37822848;
* register version.
*/
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU

17
components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,7 +23,8 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:32;
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
@ -59,6 +60,7 @@ typedef union {
struct {
/** phy_sel : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t phy_sel:1;
/** exchg_pins_override : R/W; bitpos: [1]; default: 0;
@ -115,7 +117,12 @@ typedef union {
* through GPIO Matrix.
*/
uint32_t usb_jtag_bridge_en:1;
uint32_t reserved_16:16;
/** usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0;
* Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at
* clock negative edge. 1: tx output at clock positive edge.
*/
uint32_t usb_phy_tx_edge_sel:1;
uint32_t reserved_17:15;
};
uint32_t val;
} usb_serial_jtag_conf0_reg_t;
@ -130,7 +137,7 @@ typedef union {
*/
uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad output enable in test
* USB pad oen in test
*/
uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
@ -925,7 +932,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36770368;
/** date : R/W; bitpos: [31:0]; default: 37822848;
* register version.
*/
uint32_t date:32;

4
components/wpa_supplicant/test_apps/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# wpa_supplicant unit test

2
docs/conf_common.py
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@ -287,7 +287,7 @@ ESP32C2_DOCS = ['api-guides/RF_calibration.rst', 'api-guides/phy.rst']
ESP32C5_DOCS = ['api-guides/phy.rst', 'api-reference/peripherals/sd_pullup_requirements.rst']
ESP32C61_DOCS = ['api-guides/phy.rst']
ESP32C61_DOCS = [] # TODO: IDF-13141, re-open for c61 eco3
ESP32C6_DOCS = [
'api-guides/RF_calibration.rst',

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docs/doxygen/Doxyfile_esp32c61
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@ -1,5 +1,6 @@
INPUT += \
$(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_he_types.h \
$(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_he.h \
$(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt.h \
$(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt_vs.h \
# //TODO: IDF-13141, re-open for c61 eco3
# $(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt.h \
# $(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt_vs.h \

4
examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# Bluedroid Beacon Example

4
examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# Bluedroid Connection Example

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examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# Bluedroid GATT Server Example

4
examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# NimBLE Beacon Example

4
examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# NimBLE Connection Example

4
examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# NimBLE GATT Server Example

4
examples/bluetooth/ble_get_started/nimble/NimBLE_Security/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# NimBLE Security Example

4
examples/bluetooth/bluedroid/ble/ble_ancs/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE ANCS Example

4
examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE Compatibility Test Example

4
examples/bluetooth/bluedroid/ble/ble_eddystone_receiver/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Eddystone Example

4
examples/bluetooth/bluedroid/ble/ble_eddystone_sender/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Eddystone Example

4
examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE HID Example

4
examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF iBeacon demo

4
examples/bluetooth/bluedroid/ble/ble_spp_client/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF SPP GATT CLIENT demo

4
examples/bluetooth/bluedroid/ble/ble_spp_server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
## ESP-IDF GATT SERVER SPP Example

4
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE throughput GATT CLIENT Test

4
examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE throughput GATT SERVER Test

4
examples/bluetooth/bluedroid/ble/gatt_client/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Client Example

4
examples/bluetooth/bluedroid/ble/gatt_security_client/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Security Client Example

4
examples/bluetooth/bluedroid/ble/gatt_security_server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Security Server Example

4
examples/bluetooth/bluedroid/ble/gatt_server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Server Example

4
examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Server Service Table Example

4
examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Client Multi Connection Example

4
examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF Gatt Security Client Example

4
examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE50 Security Server Example

4
examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_client/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE 50 throughput GATT CLIENT Test

4
examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_server/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP-IDF BLE 50 throughput GATT SERVER Test

4
examples/bluetooth/bluedroid/ble_50/multi-adv/README.md
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
#ESP-IDF Multi Adv Example

Some files were not shown because too many files have changed in this diff Show More