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fix(uart): correct C3/S3 module enable porcedure to avoid undesired line noise

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This commit is contained in:
Song Ruo Jing
2025-03-19 22:00:09 +08:00
parent 3b3ae85bbe
commit ec373b51b8
2 changed files with 5 additions and 0 deletions
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2
components/hal/esp32c3/include/hal/uart_ll.h
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@ -107,12 +107,14 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// ESP32C3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value
switch (uart_num) {
case 0:
SYSTEM.perip_rst_en0.reg_uart_rst = 0;
UART0.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.reg_uart_rst = 1;
SYSTEM.perip_rst_en0.reg_uart_rst = 0;
UART0.clk_conf.rst_core = 0;
break;
case 1:
SYSTEM.perip_rst_en0.reg_uart1_rst = 0;
UART1.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.reg_uart1_rst = 1;
SYSTEM.perip_rst_en0.reg_uart1_rst = 0;

3
components/hal/esp32s3/include/hal/uart_ll.h
View File

@ -112,18 +112,21 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// ESP32S3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value
switch (uart_num) {
case 0:
SYSTEM.perip_rst_en0.uart_rst = 0;
UART0.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.uart_rst = 1;
SYSTEM.perip_rst_en0.uart_rst = 0;
UART0.clk_conf.rst_core = 0;
break;
case 1:
SYSTEM.perip_rst_en0.uart1_rst = 0;
UART1.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.uart1_rst = 1;
SYSTEM.perip_rst_en0.uart1_rst = 0;
UART1.clk_conf.rst_core = 0;
break;
case 2:
SYSTEM.perip_rst_en1.uart2_rst = 0;
UART2.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en1.uart2_rst = 1;
SYSTEM.perip_rst_en1.uart2_rst = 0;