forked from Makuna/NeoPixelBus
362 lines
12 KiB
C++
362 lines
12 KiB
C++
/*-------------------------------------------------------------------------
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NeoPixel library helper functions for Esp8266.
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Written by Michael C. Miller.
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I invest time and resources providing this open source code,
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please support me by dontating (see https://github.com/Makuna/NeoPixelBus)
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-------------------------------------------------------------------------
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This file is part of the Makuna/NeoPixelBus library.
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NeoPixelBus is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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NeoPixelBus is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with NeoPixel. If not, see
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<http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------*/
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#pragma once
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#ifdef ARDUINO_ARCH_ESP8266
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#include "Arduino.h"
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extern "C"
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{
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#include "osapi.h"
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#include "ets_sys.h"
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#include "i2s_reg.h"
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#ifdef ARDUINO_ESP8266_MAJOR //this define was added in ESP8266 Arduino Core version v3.0.1
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#include "core_esp8266_i2s.h" //for Arduino core >= 3.0.1
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#else
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#include "i2s.h" //for Arduino core <= 3.0.0
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#endif
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#include "eagle_soc.h"
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#include "esp8266_peri.h"
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#include "slc_register.h"
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#include "osapi.h"
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#include "ets_sys.h"
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#include "user_interface.h"
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#if !defined(__CORE_ESP8266_VERSION_H) || defined(ARDUINO_ESP8266_RELEASE_2_5_0)
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void rom_i2c_writeReg_Mask(uint32_t block, uint32_t host_id, uint32_t reg_add, uint32_t Msb, uint32_t Lsb, uint32_t indata);
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#endif
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}
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struct slc_queue_item
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{
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uint32 blocksize : 12;
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uint32 datalen : 12;
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uint32 unused : 5;
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uint32 sub_sof : 1;
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uint32 eof : 1;
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uint32 owner : 1;
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uint8* buf_ptr;
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struct slc_queue_item* next_link_ptr;
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};
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enum NeoDmaState
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{
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NeoDmaState_Idle,
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NeoDmaState_Pending,
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NeoDmaState_Sending
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};
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const uint16_t c_maxDmaBlockSize = 4095;
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const uint8_t c_I2sPin = 3; // due to I2S hardware, the pin used is restricted to this
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class NeoEsp8266I2sMethodCore
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{
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private:
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static const uint8_t c_StateBlockCount = 2;
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static const size_t c_StateDataSize = 4; // mulitples of c_I2sByteBoundarySize
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// i2s sends 4 byte elements,
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static const uint16_t c_I2sByteBoundarySize = 4;
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protected:
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static NeoEsp8266I2sMethodCore* s_this; // for the ISR
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volatile NeoDmaState _dmaState;
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slc_queue_item* _i2sBufDesc; // dma block descriptors
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uint16_t _i2sBufDescCount; // count of block descriptors in _i2sBufDesc
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size_t _i2sBufferSize; // total size of _i2sBuffer
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uint8_t* _i2sBuffer; // holds the DMA buffer that is referenced by _i2sBufDesc
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size_t _i2sIdleDataTotalSize; // total size of represented zeroes, mulitple uses of _i2sIdleData
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size_t _i2sIdleDataSize; // size of _i2sIdleData
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uint8_t* _i2sIdleData;
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uint16_t _is2BufMaxBlockSize; // max size based on size of a pixel of a single block
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size_t GetSendSize() const
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{
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return _i2sBufferSize + _i2sIdleDataTotalSize;
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}
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// This routine is called as soon as the DMA routine has something to tell us. All we
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// handle here is the RX_EOF_INT status, which indicate the DMA has sent a buffer whose
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// descriptor has the 'EOF' field set to 1.
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// in the case of this code, the second to last state descriptor
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static void IRAM_ATTR i2s_slc_isr(void)
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{
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ETS_SLC_INTR_DISABLE();
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uint32_t slc_intr_status = SLCIS;
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SLCIC = 0xFFFFFFFF;
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if ((slc_intr_status & SLCIRXEOF) && s_this)
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{
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if (s_this->_dmaState != NeoDmaState_Idle)
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{
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// first two items are the state blocks
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slc_queue_item* itemLoop = s_this->_i2sBufDesc;
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slc_queue_item* itemLoopBreaker = itemLoop + 1;
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// set to loop on idle items
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itemLoopBreaker->next_link_ptr = itemLoop;
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s_this->_dmaState = NeoDmaState_Idle;
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}
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}
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ETS_SLC_INTR_ENABLE();
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}
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NeoEsp8266I2sMethodCore()
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{ };
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void AllocateI2s(const size_t i2sBufferSize, // expected multiples of c_I2sByteBoundarySize
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const size_t i2sZeroesSize, // expected multiples of c_I2sByteBoundarySize
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const size_t is2BufMaxBlockSize,
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const uint8_t idleLevel)
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{
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_i2sBufferSize = i2sBufferSize;
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_i2sIdleDataTotalSize = i2sZeroesSize;
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_i2sIdleDataSize = _i2sIdleDataTotalSize;
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size_t countIdleQueueItems = 1;
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if (_i2sIdleDataSize > 256)
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{
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// reuse a single idle data buffer of 256 with multiple dma slc_queue_items
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countIdleQueueItems = _i2sIdleDataSize / 256 + 1;
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_i2sIdleDataSize = 256;
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}
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else
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{
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_i2sIdleDataSize = NeoUtil::RoundUp(_i2sIdleDataSize, c_I2sByteBoundarySize);
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}
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_is2BufMaxBlockSize = is2BufMaxBlockSize;
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_i2sBuffer = static_cast<uint8_t*>(malloc(_i2sBufferSize));
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// no need to initialize it, it gets overwritten on every send
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_i2sIdleData = static_cast<uint8_t*>(malloc(_i2sIdleDataSize));
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memset(_i2sIdleData, idleLevel * 0xff, _i2sIdleDataSize);
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_i2sBufDescCount = (_i2sBufferSize / _is2BufMaxBlockSize) + 1 +
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countIdleQueueItems +
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c_StateBlockCount; // need more for state/latch blocks
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_i2sBufDesc = (slc_queue_item*)malloc(_i2sBufDescCount * sizeof(slc_queue_item));
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s_this = this; // store this for the ISR
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}
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void FreeI2s()
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{
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StopI2s();
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s_this = nullptr;
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pinMode(c_I2sPin, INPUT);
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free(_i2sBuffer);
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free(_i2sBufDesc);
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free(_i2sIdleData);
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}
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bool IsIdle() const
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{
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return (_dmaState == NeoDmaState_Idle);
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}
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void DmaItemInit(slc_queue_item* item, uint8_t* data, size_t sizeData, slc_queue_item* itemNext)
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{
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item->owner = 1;
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item->eof = 0; // no need to trigger interrupt generally
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item->sub_sof = 0;
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item->datalen = sizeData;
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item->blocksize = sizeData;
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item->buf_ptr = data;
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item->unused = 0;
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item->next_link_ptr = itemNext;
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}
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void InitializeI2s(const uint32_t i2sClockDivisor, const uint32_t i2sBaseClockDivisor)
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{
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StopI2s();
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pinMode(c_I2sPin, FUNCTION_1); // I2S0_DATA
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uint8_t* is2Buffer = _i2sBuffer;
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uint8_t* is2BufferEnd = _i2sBuffer + _i2sBufferSize;
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uint32_t is2BufferSize;
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uint16_t indexDesc = 0;
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// prepare the two state/latch descriptors
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uint16_t stateDataSize = min(c_StateDataSize, _i2sIdleDataSize);
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while (indexDesc < c_StateBlockCount)
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{
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DmaItemInit(&_i2sBufDesc[indexDesc], _i2sIdleData, stateDataSize, &(_i2sBufDesc[indexDesc + 1]));
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indexDesc++;
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}
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// prepare main data block decriptors that point into our one static dma buffer
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is2BufferSize = _i2sBufferSize;
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while (is2Buffer < is2BufferEnd)
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{
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uint32_t blockSize = (is2BufferSize > _is2BufMaxBlockSize) ? _is2BufMaxBlockSize : is2BufferSize;
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DmaItemInit(&_i2sBufDesc[indexDesc], is2Buffer, blockSize, &(_i2sBufDesc[indexDesc + 1]));
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is2Buffer += blockSize;
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is2BufferSize -= blockSize;
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indexDesc++;
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}
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// last data item triggers EOF ISR
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_i2sBufDesc[indexDesc - 1].eof = 1;
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// prepare idle block decriptors that point into our one idle dma buffer
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is2BufferSize = _i2sIdleDataTotalSize;
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while (indexDesc < _i2sBufDescCount)
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{
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uint32_t blockSize = (is2BufferSize > _i2sIdleDataSize) ? _i2sIdleDataSize : is2BufferSize;
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DmaItemInit(&_i2sBufDesc[indexDesc], _i2sIdleData, blockSize, &(_i2sBufDesc[indexDesc + 1]));
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is2Buffer += blockSize;
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is2BufferSize -= blockSize;
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indexDesc++;
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}
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// the last item will loop to the first item
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_i2sBufDesc[indexDesc - 1].next_link_ptr = reinterpret_cast<struct slc_queue_item*>(&(_i2sBufDesc[0]));
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// the last state block will loop to the first state block by defualt
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_i2sBufDesc[c_StateBlockCount - 1].next_link_ptr = reinterpret_cast<struct slc_queue_item*>(&(_i2sBufDesc[0]));
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// setup the rest of i2s DMA
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//
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ETS_SLC_INTR_DISABLE();
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// start off in idel state as that is what it will be all setup to be
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// for the interrupt
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_dmaState = NeoDmaState_Idle;
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SLCC0 |= SLCRXLR | SLCTXLR;
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SLCC0 &= ~(SLCRXLR | SLCTXLR);
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SLCIC = 0xFFFFFFFF;
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// Configure DMA
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SLCC0 &= ~(SLCMM << SLCM); // clear DMA MODE
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SLCC0 |= (1 << SLCM); // set DMA MODE to 1
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SLCRXDC |= SLCBINR | SLCBTNR; // enable INFOR_NO_REPLACE and TOKEN_NO_REPLACE
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SLCRXDC &= ~(SLCBRXFE | SLCBRXEM | SLCBRXFM); // disable RX_FILL, RX_EOF_MODE and RX_FILL_MODE
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// Feed DMA the 1st buffer desc addr
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// To send data to the I2S subsystem, counter-intuitively we use the RXLINK part, not the TXLINK as you might
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// expect. The TXLINK part still needs a valid DMA descriptor, even if it's unused: the DMA engine will throw
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// an error at us otherwise. Just feed it any random descriptor.
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SLCTXL &= ~(SLCTXLAM << SLCTXLA); // clear TX descriptor address
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// set TX descriptor address. any random desc is OK, we don't use TX but it needs to be valid
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SLCTXL |= (uint32) & (_i2sBufDesc[_i2sBufDescCount - 1]) << SLCTXLA;
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SLCRXL &= ~(SLCRXLAM << SLCRXLA); // clear RX descriptor address
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// set RX descriptor address. use first of the data addresses
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SLCRXL |= (uint32) & (_i2sBufDesc[0]) << SLCRXLA;
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ETS_SLC_INTR_ATTACH(i2s_slc_isr, NULL);
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SLCIE = SLCIRXEOF; // Enable only for RX EOF interrupt
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ETS_SLC_INTR_ENABLE();
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//Start transmission
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SLCTXL |= SLCTXLS;
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SLCRXL |= SLCRXLS;
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I2S_CLK_ENABLE();
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I2SIC = 0x3F;
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I2SIE = 0;
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//Reset I2S
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I2SC &= ~(I2SRST);
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I2SC |= I2SRST;
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I2SC &= ~(I2SRST);
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// Set RX/TX FIFO_MOD=0 and disable DMA (FIFO only)
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I2SFC &= ~(I2SDE | (I2STXFMM << I2STXFM) | (I2SRXFMM << I2SRXFM));
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I2SFC |= I2SDE; //Enable DMA
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// Set RX/TX CHAN_MOD=0
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I2SCC &= ~((I2STXCMM << I2STXCM) | (I2SRXCMM << I2SRXCM));
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// set the rate
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uint32_t i2s_clock_div = i2sClockDivisor & I2SCDM;
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uint8_t i2s_bck_div = i2sBaseClockDivisor & I2SBDM;
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//!trans master, !bits mod, rece slave mod, rece msb shift, right first, msb right
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I2SC &= ~(I2STSM | I2SRSM | (I2SBMM << I2SBM) | (I2SBDM << I2SBD) | (I2SCDM << I2SCD));
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I2SC |= I2SRF | I2SMR | I2SRSM | I2SRMS | (i2s_bck_div << I2SBD) | (i2s_clock_div << I2SCD);
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I2SC |= I2STXS; // Start transmission
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}
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void WriteI2s()
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{
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// first two items are the state blocks
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slc_queue_item* itemLoopBreaker = &(_i2sBufDesc[1]);
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slc_queue_item* itemData = itemLoopBreaker + 1;
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// set to NOT loop on idle items
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itemLoopBreaker->next_link_ptr = itemData;
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_dmaState = NeoDmaState_Sending;
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}
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void StopI2s()
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{
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ETS_SLC_INTR_DISABLE();
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// Disable any I2S send or receive
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I2SC &= ~(I2STXS | I2SRXS);
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// Reset I2S
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I2SC &= ~(I2SRST);
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I2SC |= I2SRST;
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I2SC &= ~(I2SRST);
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SLCIC = 0xFFFFFFFF;
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SLCIE = 0;
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SLCTXL &= ~(SLCTXLAM << SLCTXLA); // clear TX descriptor address
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SLCRXL &= ~(SLCRXLAM << SLCRXLA); // clear RX descriptor address
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pinMode(c_I2sPin, INPUT);
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}
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};
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#endif // ARDUINO_ARCH_ESP8266
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