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Merge branch 'feature/support_c5_eco2_soc' into 'master'

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feat(soc): support esp32c5 eco2 soc

See merge request espressif/esp-idf!38425
This commit is contained in:
Kevin (Lao Kaiyao)
2025-04-18 18:09:58 +08:00
parent eb0d3677ba 849ff888b1
commit 0f1fd5a20c
75 changed files with 57646 additions and 3387 deletions
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29
components/hal/esp32c5/include/hal/assist_debug_ll.h
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@@ -9,8 +9,11 @@
#pragma once
#include "soc/assist_debug_reg.h"
#define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
#define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_MONTR_ENA_REG
#define BUS_MONITOR_SP_SPILL_BITS (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA | BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA)
#define BUS_MONITOR_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONTR_ENA_REG
// Compatible alias
#define ASSIST_DEBUG_SP_SPILL_BITS BUS_MONITOR_SP_SPILL_BITS
#define ASSIST_DEBUG_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONITOR_REG
#ifndef __ASSEMBLER__
@@ -60,57 +63,57 @@ extern "C" {
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id)
{
REG_SET_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
REG_SET_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
}
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id)
{
REG_CLR_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
REG_CLR_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
}
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id)
{
REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
REG_SET_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
}
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id)
{
REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
REG_CLR_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
}
FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id)
{
return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS;
return REG_READ(BUS_MONITOR_CORE_0_INTR_RAW_REG) & BUS_MONITOR_SP_SPILL_BITS;
}
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id)
{
REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS);
REG_WRITE(BUS_MONITOR_CORE_0_INTR_CLR_REG, BUS_MONITOR_SP_SPILL_BITS);
}
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min)
{
REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min);
REG_WRITE(BUS_MONITOR_CORE_0_SP_MIN_REG, min);
}
FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id)
{
return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG);
return REG_READ(BUS_MONITOR_CORE_0_SP_MIN_REG);
}
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max)
{
REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max);
REG_WRITE(BUS_MONITOR_CORE_0_SP_MAX_REG, max);
}
FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id)
{
return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG);
return REG_READ(BUS_MONITOR_CORE_0_SP_MAX_REG);
}
FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id)
{
return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG);
}
FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)

2
components/hal/esp32c5/include/hal/uart_ll.h
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@@ -561,7 +561,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{
for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte;
buf[i] = hw->fifo.val;
}
}

4
components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h
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@@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i;
for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
buf[i] = USB_SERIAL_JTAG.ep1.val;
}
return i;
}
@@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i;
for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
USB_SERIAL_JTAG.ep1.val = buf[i];
}
return i;
}

21
components/soc/esp32c5/include/soc/assist_debug_reg.h Normal file
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@@ -0,0 +1,21 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/bus_monitor_reg.h"
// Compatible alias
#define DR_REG_ASSIST_DEBUG_BASE DR_REG_BUS_MONITOR_BASE
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG BUS_MONITOR_CORE_0_DEBUG_MODE_REG
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG BUS_MONITOR_CORE_0_SP_MIN_REG
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG BUS_MONITOR_CORE_0_SP_MAX_REG
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG BUS_MONITOR_CORE_0_RCD_EN_REG
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN BUS_MONITOR_CORE_0_RCD_PDEBUGEN
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN BUS_MONITOR_CORE_0_RCD_RECORDEN

6
components/soc/esp32c5/include/soc/gpio_sig_map.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -152,6 +152,7 @@
#define PWM0_F2_IN_IDX 85
#define PWM0_OUT2B_IDX 85
#define PWM0_CAP0_IN_IDX 86
#define PARL_TX_CS_O_IDX 86
#define PWM0_CAP1_IN_IDX 87
#define PWM0_CAP2_IN_IDX 88
#define GPIO_EVENT_MATRIX_IN0_IDX 89
@@ -165,6 +166,7 @@
#define CLK_OUT_OUT1_IDX 93
#define CLK_OUT_OUT2_IDX 94
#define CLK_OUT_OUT3_IDX 95
#define SDIO_TOHOST_INT_OUT_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
@@ -242,5 +244,5 @@
#define ANT_SEL13_IDX 151
#define ANT_SEL14_IDX 152
#define ANT_SEL15_IDX 153
#define SIG_GPIO_OUT_IDX 256
// version date 2311280
#define SIG_GPIO_OUT_IDX 256

120
components/soc/esp32c5/include/soc/pmu_icg_mapping.h
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@@ -1,67 +1,67 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_LEDC 14
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_SOC_ETM 22
#define PMU_ICG_APB_ENA_SPI2 2
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_FUNC_ENA_CAN0 31
#define PMU_ICG_FUNC_ENA_CAN1 30
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
#define PMU_ICG_FUNC_ENA_TG0 14
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_HPBUS 15
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_LEDC 14
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_APB_ENA_TWAI0 18
#define PMU_ICG_APB_ENA_TWAI1 19
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_SOC_ETM 22
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TG0 14
#define PMU_ICG_FUNC_ENA_HPBUS 15
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_TWAI1 30
#define PMU_ICG_FUNC_ENA_TWAI0 31

8
components/soc/esp32c5/ld/esp32c5.peripherals.ld
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -27,6 +27,9 @@ PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM0 = 0x60014000 );
PROVIDE ( PARL_IO = 0x60015000 );
PROVIDE ( HINF = 0x60016000 );
PROVIDE ( SLC = 0x60017000 );
PROVIDE ( HOST = 0x60018000 );
PROVIDE ( PVT_MONITOR = 0x60019000 );
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );
PROVIDE ( AHB_DMA = 0x60080000 );
@@ -53,6 +56,7 @@ PROVIDE ( PCR = 0x60096000 );
PROVIDE ( TEE = 0x60098000 );
PROVIDE ( HP_APM = 0x60099000 );
PROVIDE ( LP_APM0 = 0x60099800 );
PROVIDE ( CPU_APM = 0x6009A000 );
PROVIDE ( MISC = 0x6009F000 );
PROVIDE ( IEEE802154 = 0x600A3000 ); /* TODO: [ESP32C5] IDF-9140 Check the address */
@@ -82,6 +86,6 @@ PROVIDE ( LP_GPIO = 0x600B4400 );
PROVIDE ( EFUSE = 0x600B4800 );
PROVIDE ( OTP_DEBUG = 0x600B4D00 );
PROVIDE ( TRACE = 0x600C0000 );
PROVIDE ( ASSIST_DEBUG = 0x600C2000 );
PROVIDE ( BUS_MONITOR = 0x600C2000 );
PROVIDE ( INTPRI = 0x600C5000 );
PROVIDE ( CACHE = 0x600C8000 );

3977
components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h Normal file
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File diff suppressed because it is too large Load Diff

3574
components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h Normal file
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File diff suppressed because it is too large Load Diff

823
components/soc/esp32c5/register/soc/assist_debug_reg.h
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@@ -1,823 +0,0 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether to monitor read operations in region 0 by the Data bus. \\
* 0: Not monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Configures whether to monitor write operations in region 0 by the Data bus.\\
* 0: Not monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Configures whether to monitor read operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Configures whether to monitor write operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Configures whether to monitor SP exceeding the lower bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Configures whether to monitor SP exceeding the upper bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor enable
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor enable
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* The raw interrupt status of read operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* The raw interrupt status of write operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* The raw interrupt status of read operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* The raw interrupt status of write operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* The raw interrupt status of read operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* The raw interrupt status of write operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* The raw interrupt status of read operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* The raw interrupt status of write operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* The raw interrupt status of SP exceeding the lower bound address of SP monitored
* region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* The raw interrupt status of SP exceeding the upper bound address of SP monitored
* region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
* DBUS busy monitor initerrupt status
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S 11
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clear register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
* monitored region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
* monitored region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* Configures lower boundary address of region 0 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* Configures upper boundary address of region 0 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* Configures lower boundary address of region 1 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* Configures upper boundary address of region 1 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* Configures lower boundary address of region 0 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* Configures upper boundary address of region 0 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* Configures lower boundary address of region 1 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* Configures upper boundary address of region 1 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* Region monitoring HP CPU PC status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value when an interrupt is triggered during region monitoring.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* Region monitoring HP CPU SP status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* Represents the SP value when an interrupt is triggered during region monitoring.
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* Configures stack monitoring lower boundary address
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of SP.
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* Configures stack monitoring upper boundary address
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the upper bound address of SP.
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* Stack monitoring HP CPU PC status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value during stack monitoring.
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* HP CPU PC logging enable register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Configures whether to enable PC logging.\\
* 0: Disable\\
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Configures whether to enable HP CPU debugging.\\
* 0: Disable\\
* 1: HP CPU outputs PC\\
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* PC logging register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value at HP CPU reset.
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* PC logging register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* Represents SP.
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(30))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 30
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(31))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 31
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(30))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 30
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(31))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 31
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register2
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(0))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 1
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register3
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
* exception monitor status register4
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
* exception monitor status register5
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(0))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 1
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
* exception monitor status register6
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
* exception monitor status register7
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* Represents the PC of the last command before the HP CPU enters exception.
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
* 1: In debugging mode\\
* 0: Not in debugging mode\\
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* Represents the status of the RISC-V CPU (HP CPU) debug module.\\
* 1: Active status\\
* Other: Inactive status\\
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register8
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register9
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* Register clock control
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to enable the register clock gating. \\
* 0: Disable\\
* 1: Enable\\
*/
#define ASSIST_DEBUG_CLK_EN (BIT(0))
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
#define ASSIST_DEBUG_CLK_EN_S 0
/** ASSIST_DEBUG_DATE_REG register
* Version control register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
* version register
*/
#define ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/register/soc/bus_monitor_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** BUS_MONITOR_CORE_0_MONTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define BUS_MONITOR_CORE_0_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x0)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether to monitor read operations in region 0 by the Data bus.
* 0: Not monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Configures whether to monitor write operations in region 0 by the Data bus.
* 0: Not monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Configures whether to monitor read operations in region 1 by the Data bus.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Configures whether to monitor write operations in region 1 by the Data bus.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Configures whether to monitor read operations in region 0 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Configures whether to monitor write operations in region 0 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Configures whether to monitor read operations in region 1 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Configures whether to monitor write operations in region 1 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Configures whether to monitor SP exceeding the lower bound address of SP monitored
* region.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S 8
/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Configures whether to monitor SP exceeding the upper bound address of SP monitored
* region.
* 0: Not Monitor
* 1: Monitor
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S 9
/** BUS_MONITOR_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define BUS_MONITOR_CORE_0_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x4)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* The raw interrupt status of read operations in region 0 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* The raw interrupt status of write operations in region 0 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* The raw interrupt status of read operations in region 1 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* The raw interrupt status of write operations in region 1 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* The raw interrupt status of read operations in region 0 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* The raw interrupt status of write operations in region 0 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* The raw interrupt status of read operations in region 1 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* The raw interrupt status of write operations in region 1 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* The raw interrupt status of SP exceeding the lower bound address of SP monitored
* region.
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S 8
/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* The raw interrupt status of SP exceeding the upper bound address of SP monitored
* region.
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S 9
/** BUS_MONITOR_CORE_0_INTR_ENA_REG register
* core0 monitor interrupt enable register
*/
#define BUS_MONITOR_CORE_0_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x8)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3
/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4
/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5
/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6
/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7
/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8))
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8
/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9))
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9
/** BUS_MONITOR_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clear register
*/
#define BUS_MONITOR_CORE_0_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0xc)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Data bus.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_M (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
* monitored region.
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_M (BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S 8
/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
* monitored region.
*/
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_M (BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S)
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S 9
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG register
* Configures lower boundary address of region 0 monitored on Data bus
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x10)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 0.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG register
* Configures upper boundary address of region 0 monitored on Data bus
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x14)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 0.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_M (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG register
* Configures lower boundary address of region 1 monitored on Data bus
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x18)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 1.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S 0
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG register
* Configures upper boundary address of region 1 monitored on Data bus
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x1c)
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 1.
*/
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_M (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S)
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S 0
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG register
* Configures lower boundary address of region 0 monitored on Peripheral bus
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x20)
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 0.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_M (BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S 0
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG register
* Configures upper boundary address of region 0 monitored on Peripheral bus
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x24)
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 0.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_M (BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S 0
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG register
* Configures lower boundary address of region 1 monitored on Peripheral bus
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x28)
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 1.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_M (BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S 0
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG register
* Configures upper boundary address of region 1 monitored on Peripheral bus
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x2c)
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 1.
*/
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_M (BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S)
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S 0
/** BUS_MONITOR_CORE_0_AREA_PC_REG register
* Region monitoring HP CPU PC status register
*/
#define BUS_MONITOR_CORE_0_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x30)
/** BUS_MONITOR_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value when an interrupt is triggered during region monitoring.
*/
#define BUS_MONITOR_CORE_0_AREA_PC 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PC_M (BUS_MONITOR_CORE_0_AREA_PC_V << BUS_MONITOR_CORE_0_AREA_PC_S)
#define BUS_MONITOR_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_PC_S 0
/** BUS_MONITOR_CORE_0_AREA_SP_REG register
* Region monitoring HP CPU SP status register
*/
#define BUS_MONITOR_CORE_0_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0x34)
/** BUS_MONITOR_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* Represents the SP value when an interrupt is triggered during region monitoring.
*/
#define BUS_MONITOR_CORE_0_AREA_SP 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_SP_M (BUS_MONITOR_CORE_0_AREA_SP_V << BUS_MONITOR_CORE_0_AREA_SP_S)
#define BUS_MONITOR_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_AREA_SP_S 0
/** BUS_MONITOR_CORE_0_SP_MIN_REG register
* Configures stack monitoring lower boundary address
*/
#define BUS_MONITOR_CORE_0_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x38)
/** BUS_MONITOR_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of SP.
*/
#define BUS_MONITOR_CORE_0_SP_MIN 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_SP_MIN_M (BUS_MONITOR_CORE_0_SP_MIN_V << BUS_MONITOR_CORE_0_SP_MIN_S)
#define BUS_MONITOR_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_SP_MIN_S 0
/** BUS_MONITOR_CORE_0_SP_MAX_REG register
* Configures stack monitoring upper boundary address
*/
#define BUS_MONITOR_CORE_0_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x3c)
/** BUS_MONITOR_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the upper bound address of SP.
*/
#define BUS_MONITOR_CORE_0_SP_MAX 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_SP_MAX_M (BUS_MONITOR_CORE_0_SP_MAX_V << BUS_MONITOR_CORE_0_SP_MAX_S)
#define BUS_MONITOR_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_SP_MAX_S 0
/** BUS_MONITOR_CORE_0_SP_PC_REG register
* Stack monitoring HP CPU PC status register
*/
#define BUS_MONITOR_CORE_0_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x40)
/** BUS_MONITOR_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value during stack monitoring.
*/
#define BUS_MONITOR_CORE_0_SP_PC 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_SP_PC_M (BUS_MONITOR_CORE_0_SP_PC_V << BUS_MONITOR_CORE_0_SP_PC_S)
#define BUS_MONITOR_CORE_0_SP_PC_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_SP_PC_S 0
/** BUS_MONITOR_CORE_0_RCD_EN_REG register
* HP CPU PC logging enable register
*/
#define BUS_MONITOR_CORE_0_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0x44)
/** BUS_MONITOR_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Configures whether to enable PC logging.
* 0: Disable
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time
*/
#define BUS_MONITOR_CORE_0_RCD_RECORDEN (BIT(0))
#define BUS_MONITOR_CORE_0_RCD_RECORDEN_M (BUS_MONITOR_CORE_0_RCD_RECORDEN_V << BUS_MONITOR_CORE_0_RCD_RECORDEN_S)
#define BUS_MONITOR_CORE_0_RCD_RECORDEN_V 0x00000001U
#define BUS_MONITOR_CORE_0_RCD_RECORDEN_S 0
/** BUS_MONITOR_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Configures whether to enable HP CPU debugging.
* 0: Disable
* 1: HP CPU outputs PC
*/
#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN (BIT(1))
#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_M (BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V << BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S)
#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S 1
/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG register
* PC logging register
*/
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0x48)
/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value at HP CPU reset.
*/
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_M (BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V << BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S)
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S 0
/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG register
* PC logging register
*/
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0x4c)
/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* Represents SP.
*/
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_M (BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V << BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S)
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S 0
/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0x70)
/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* Represents the PC of the last command before the HP CPU enters exception.
*/
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_M (BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V << BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S)
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S 0
/** BUS_MONITOR_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define BUS_MONITOR_CORE_0_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0x74)
/** BUS_MONITOR_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.
* 1: In debugging mode
* 0: Not in debugging mode
*/
#define BUS_MONITOR_CORE_0_DEBUG_MODE (BIT(0))
#define BUS_MONITOR_CORE_0_DEBUG_MODE_M (BUS_MONITOR_CORE_0_DEBUG_MODE_V << BUS_MONITOR_CORE_0_DEBUG_MODE_S)
#define BUS_MONITOR_CORE_0_DEBUG_MODE_V 0x00000001U
#define BUS_MONITOR_CORE_0_DEBUG_MODE_S 0
/** BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* Represents the status of the RISC-V CPU (HP CPU) debug module.
* 1: Active status
* Other: Inactive status
*/
#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_M (BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V << BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register8
*/
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_BUS_MONITOR_BASE + 0x100)
/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register9
*/
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_BUS_MONITOR_BASE + 0x104)
/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
/** BUS_MONITOR_CLOCK_GATE_REG register
* Register clock control
*/
#define BUS_MONITOR_CLOCK_GATE_REG (DR_REG_BUS_MONITOR_BASE + 0x108)
/** BUS_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to enable the register clock gating.
* 0: Disable
* 1: Enable
*/
#define BUS_MONITOR_CLK_EN (BIT(0))
#define BUS_MONITOR_CLK_EN_M (BUS_MONITOR_CLK_EN_V << BUS_MONITOR_CLK_EN_S)
#define BUS_MONITOR_CLK_EN_V 0x00000001U
#define BUS_MONITOR_CLK_EN_S 0
/** BUS_MONITOR_DATE_REG register
* Version control register
*/
#define BUS_MONITOR_DATE_REG (DR_REG_BUS_MONITOR_BASE + 0x3fc)
/** BUS_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34640176;
* version register
*/
#define BUS_MONITOR_DATE 0x0FFFFFFFU
#define BUS_MONITOR_DATE_M (BUS_MONITOR_DATE_V << BUS_MONITOR_DATE_S)
#define BUS_MONITOR_DATE_V 0x0FFFFFFFU
#define BUS_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

383
components/soc/esp32c5/register/soc/assist_debug_struct.h → components/soc/esp32c5/register/soc/bus_monitor_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,79 +17,71 @@ extern "C" {
typedef union {
struct {
/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
* Configures whether to monitor read operations in region 0 by the Data bus. \\
* 0: Not monitor\\
* 1: Monitor\\
* Configures whether to monitor read operations in region 0 by the Data bus.
* 0: Not monitor
* 1: Monitor
*/
uint32_t core_0_area_dram0_0_rd_ena:1;
/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
* Configures whether to monitor write operations in region 0 by the Data bus.\\
* 0: Not monitor\\
* 1: Monitor\\
* Configures whether to monitor write operations in region 0 by the Data bus.
* 0: Not monitor
* 1: Monitor
*/
uint32_t core_0_area_dram0_0_wr_ena:1;
/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
* Configures whether to monitor read operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
* Configures whether to monitor read operations in region 1 by the Data bus.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_area_dram0_1_rd_ena:1;
/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
* Configures whether to monitor write operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
* Configures whether to monitor write operations in region 1 by the Data bus.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_area_dram0_1_wr_ena:1;
/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
* Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
* Configures whether to monitor read operations in region 0 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_area_pif_0_rd_ena:1;
/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
* Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
* Configures whether to monitor write operations in region 0 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_area_pif_0_wr_ena:1;
/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
* Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
* Configures whether to monitor read operations in region 1 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_area_pif_1_rd_ena:1;
/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
* Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
* Configures whether to monitor write operations in region 1 by the Peripheral bus.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_area_pif_1_wr_ena:1;
/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
* Configures whether to monitor SP exceeding the lower bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
* region.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_sp_spill_min_ena:1;
/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
* Configures whether to monitor SP exceeding the upper bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
* region.
* 0: Not Monitor
* 1: Monitor
*/
uint32_t core_0_sp_spill_max_ena:1;
/** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor enable
*/
uint32_t core_0_iram0_exception_monitor_ena:1;
/** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor enable
*/
uint32_t core_0_dram0_exception_monitor_ena:1;
uint32_t reserved_12:20;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_montr_ena_reg_t;
} bus_monitor_core_0_montr_ena_reg_t;
/** Type of core_0_area_dram0_0_min register
* Configures lower boundary address of region 0 monitored on Data bus
@@ -102,7 +94,7 @@ typedef union {
uint32_t core_0_area_dram0_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_min_reg_t;
} bus_monitor_core_0_area_dram0_0_min_reg_t;
/** Type of core_0_area_dram0_0_max register
* Configures upper boundary address of region 0 monitored on Data bus
@@ -115,7 +107,7 @@ typedef union {
uint32_t core_0_area_dram0_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_max_reg_t;
} bus_monitor_core_0_area_dram0_0_max_reg_t;
/** Type of core_0_area_dram0_1_min register
* Configures lower boundary address of region 1 monitored on Data bus
@@ -128,7 +120,7 @@ typedef union {
uint32_t core_0_area_dram0_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_min_reg_t;
} bus_monitor_core_0_area_dram0_1_min_reg_t;
/** Type of core_0_area_dram0_1_max register
* Configures upper boundary address of region 1 monitored on Data bus
@@ -141,7 +133,7 @@ typedef union {
uint32_t core_0_area_dram0_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_max_reg_t;
} bus_monitor_core_0_area_dram0_1_max_reg_t;
/** Type of core_0_area_pif_0_min register
* Configures lower boundary address of region 0 monitored on Peripheral bus
@@ -154,7 +146,7 @@ typedef union {
uint32_t core_0_area_pif_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_min_reg_t;
} bus_monitor_core_0_area_pif_0_min_reg_t;
/** Type of core_0_area_pif_0_max register
* Configures upper boundary address of region 0 monitored on Peripheral bus
@@ -167,7 +159,7 @@ typedef union {
uint32_t core_0_area_pif_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_max_reg_t;
} bus_monitor_core_0_area_pif_0_max_reg_t;
/** Type of core_0_area_pif_1_min register
* Configures lower boundary address of region 1 monitored on Peripheral bus
@@ -180,7 +172,7 @@ typedef union {
uint32_t core_0_area_pif_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_min_reg_t;
} bus_monitor_core_0_area_pif_1_min_reg_t;
/** Type of core_0_area_pif_1_max register
* Configures upper boundary address of region 1 monitored on Peripheral bus
@@ -193,7 +185,7 @@ typedef union {
uint32_t core_0_area_pif_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_max_reg_t;
} bus_monitor_core_0_area_pif_1_max_reg_t;
/** Type of core_0_area_pc register
* Region monitoring HP CPU PC status register
@@ -206,7 +198,7 @@ typedef union {
uint32_t core_0_area_pc:32;
};
uint32_t val;
} assist_debug_core_0_area_pc_reg_t;
} bus_monitor_core_0_area_pc_reg_t;
/** Type of core_0_area_sp register
* Region monitoring HP CPU SP status register
@@ -219,7 +211,7 @@ typedef union {
uint32_t core_0_area_sp:32;
};
uint32_t val;
} assist_debug_core_0_area_sp_reg_t;
} bus_monitor_core_0_area_sp_reg_t;
/** Type of core_0_sp_min register
* Configures stack monitoring lower boundary address
@@ -232,7 +224,7 @@ typedef union {
uint32_t core_0_sp_min:32;
};
uint32_t val;
} assist_debug_core_0_sp_min_reg_t;
} bus_monitor_core_0_sp_min_reg_t;
/** Type of core_0_sp_max register
* Configures stack monitoring upper boundary address
@@ -245,7 +237,7 @@ typedef union {
uint32_t core_0_sp_max:32;
};
uint32_t val;
} assist_debug_core_0_sp_max_reg_t;
} bus_monitor_core_0_sp_max_reg_t;
/** Type of core_0_sp_pc register
* Stack monitoring HP CPU PC status register
@@ -258,7 +250,7 @@ typedef union {
uint32_t core_0_sp_pc:32;
};
uint32_t val;
} assist_debug_core_0_sp_pc_reg_t;
} bus_monitor_core_0_sp_pc_reg_t;
/** Group: interrupt configuration register */
@@ -309,18 +301,10 @@ typedef union {
* region.
*/
uint32_t core_0_sp_spill_max_raw:1;
/** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt status
*/
uint32_t core_0_iram0_exception_monitor_raw:1;
/** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
* DBUS busy monitor initerrupt status
*/
uint32_t core_0_dram0_exception_monitor_raw:1;
uint32_t reserved_12:20;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_raw_reg_t;
} bus_monitor_core_0_intr_raw_reg_t;
/** Type of core_0_intr_ena register
* core0 monitor interrupt enable register
@@ -367,18 +351,10 @@ typedef union {
* Core0 stackpoint overflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_max_intr_ena:1;
/** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt enable
*/
uint32_t core_0_iram0_exception_monitor_intr_ena:1;
/** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt enable
*/
uint32_t core_0_dram0_exception_monitor_intr_ena:1;
uint32_t reserved_12:20;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_ena_reg_t;
} bus_monitor_core_0_intr_ena_reg_t;
/** Type of core_0_intr_clr register
* core0 monitor interrupt clear register
@@ -427,18 +403,10 @@ typedef union {
* monitored region.
*/
uint32_t core_0_sp_spill_max_clr:1;
/** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt clr
*/
uint32_t core_0_iram0_exception_monitor_clr:1;
/** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt clr
*/
uint32_t core_0_dram0_exception_monitor_clr:1;
uint32_t reserved_12:20;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_clr_reg_t;
} bus_monitor_core_0_intr_clr_reg_t;
/** Group: pc recording configuration register */
@@ -448,21 +416,21 @@ typedef union {
typedef union {
struct {
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
* Configures whether to enable PC logging.\\
* 0: Disable\\
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
* Configures whether to enable PC logging.
* 0: Disable
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time
*/
uint32_t core_0_rcd_recorden:1;
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
* Configures whether to enable HP CPU debugging.\\
* 0: Disable\\
* 1: HP CPU outputs PC\\
* Configures whether to enable HP CPU debugging.
* 0: Disable
* 1: HP CPU outputs PC
*/
uint32_t core_0_rcd_pdebugen:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_rcd_en_reg_t;
} bus_monitor_core_0_rcd_en_reg_t;
/** Group: pc recording status register */
@@ -477,7 +445,7 @@ typedef union {
uint32_t core_0_rcd_pdebugpc:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugpc_reg_t;
} bus_monitor_core_0_rcd_pdebugpc_reg_t;
/** Type of core_0_rcd_pdebugsp register
* PC logging register
@@ -490,142 +458,10 @@ typedef union {
uint32_t core_0_rcd_pdebugsp:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugsp_reg_t;
} bus_monitor_core_0_rcd_pdebugsp_reg_t;
/** Group: exception monitor register */
/** Type of core_0_iram0_exception_monitor_0 register
* exception monitor status register0
*/
typedef union {
struct {
/** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
uint32_t core_0_iram0_recording_addr_0:30;
/** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
uint32_t core_0_iram0_recording_wr_0:1;
/** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
uint32_t core_0_iram0_recording_loadstore_0:1;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
/** Type of core_0_iram0_exception_monitor_1 register
* exception monitor status register1
*/
typedef union {
struct {
/** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
uint32_t core_0_iram0_recording_addr_1:30;
/** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
uint32_t core_0_iram0_recording_wr_1:1;
/** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
uint32_t core_0_iram0_recording_loadstore_1:1;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
/** Type of core_0_dram0_exception_monitor_0 register
* exception monitor status register2
*/
typedef union {
struct {
/** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
uint32_t core_0_dram0_recording_wr_0:1;
/** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
uint32_t core_0_dram0_recording_byteen_0:4;
uint32_t reserved_5:27;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
/** Type of core_0_dram0_exception_monitor_1 register
* exception monitor status register3
*/
typedef union {
struct {
/** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
uint32_t core_0_dram0_recording_addr_0:30;
uint32_t reserved_30:2;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
/** Type of core_0_dram0_exception_monitor_2 register
* exception monitor status register4
*/
typedef union {
struct {
/** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
uint32_t core_0_dram0_recording_pc_0:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
/** Type of core_0_dram0_exception_monitor_3 register
* exception monitor status register5
*/
typedef union {
struct {
/** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
uint32_t core_0_dram0_recording_wr_1:1;
/** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
uint32_t core_0_dram0_recording_byteen_1:4;
uint32_t reserved_5:27;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
/** Type of core_0_dram0_exception_monitor_4 register
* exception monitor status register6
*/
typedef union {
struct {
/** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
uint32_t core_0_dram0_recording_addr_1:30;
uint32_t reserved_30:2;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
/** Type of core_0_dram0_exception_monitor_5 register
* exception monitor status register7
*/
typedef union {
struct {
/** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
uint32_t core_0_dram0_recording_pc_1:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
/** Type of core_x_iram0_dram0_exception_monitor_0 register
* exception monitor status register8
*/
@@ -638,7 +474,7 @@ typedef union {
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
} bus_monitor_core_x_iram0_dram0_exception_monitor_0_reg_t;
/** Type of core_x_iram0_dram0_exception_monitor_1 register
* exception monitor status register9
@@ -652,7 +488,7 @@ typedef union {
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
} bus_monitor_core_x_iram0_dram0_exception_monitor_1_reg_t;
/** Group: cpu status registers */
@@ -667,7 +503,7 @@ typedef union {
uint32_t core_0_lastpc_before_exc:32;
};
uint32_t val;
} assist_debug_core_0_lastpc_before_exception_reg_t;
} bus_monitor_core_0_lastpc_before_exception_reg_t;
/** Type of core_0_debug_mode register
* cpu status register
@@ -675,21 +511,21 @@ typedef union {
typedef union {
struct {
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
* 1: In debugging mode\\
* 0: Not in debugging mode\\
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.
* 1: In debugging mode
* 0: Not in debugging mode
*/
uint32_t core_0_debug_mode:1;
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
* Represents the status of the RISC-V CPU (HP CPU) debug module.\\
* 1: Active status\\
* Other: Inactive status\\
* Represents the status of the RISC-V CPU (HP CPU) debug module.
* 1: Active status
* Other: Inactive status
*/
uint32_t core_0_debug_module_active:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_debug_mode_reg_t;
} bus_monitor_core_0_debug_mode_reg_t;
/** Group: Configuration Registers */
@@ -699,15 +535,15 @@ typedef union {
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to enable the register clock gating. \\
* 0: Disable\\
* 1: Enable\\
* Configures whether to enable the register clock gating.
* 0: Disable
* 1: Enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} assist_debug_clock_gate_reg_t;
} bus_monitor_clock_gate_reg_t;
/** Type of date register
* Version control register
@@ -721,52 +557,45 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} assist_debug_date_reg_t;
} bus_monitor_date_reg_t;
typedef struct {
volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
volatile bus_monitor_core_0_montr_ena_reg_t core_0_montr_ena;
volatile bus_monitor_core_0_intr_raw_reg_t core_0_intr_raw;
volatile bus_monitor_core_0_intr_ena_reg_t core_0_intr_ena;
volatile bus_monitor_core_0_intr_clr_reg_t core_0_intr_clr;
volatile bus_monitor_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
volatile bus_monitor_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
volatile bus_monitor_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
volatile bus_monitor_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
volatile bus_monitor_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
volatile bus_monitor_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
volatile bus_monitor_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
volatile bus_monitor_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
volatile bus_monitor_core_0_area_pc_reg_t core_0_area_pc;
volatile bus_monitor_core_0_area_sp_reg_t core_0_area_sp;
volatile bus_monitor_core_0_sp_min_reg_t core_0_sp_min;
volatile bus_monitor_core_0_sp_max_reg_t core_0_sp_max;
volatile bus_monitor_core_0_sp_pc_reg_t core_0_sp_pc;
volatile bus_monitor_core_0_rcd_en_reg_t core_0_rcd_en;
volatile bus_monitor_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
volatile bus_monitor_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
uint32_t reserved_050[8];
volatile bus_monitor_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
volatile bus_monitor_core_0_debug_mode_reg_t core_0_debug_mode;
uint32_t reserved_078[34];
volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
volatile assist_debug_clock_gate_reg_t clock_gate;
volatile bus_monitor_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
volatile bus_monitor_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
volatile bus_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_10c[188];
volatile assist_debug_date_reg_t date;
} assist_debug_dev_t;
volatile bus_monitor_date_reg_t date;
} bus_monitor_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
extern bus_monitor_dev_t BUS_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
_Static_assert(sizeof(bus_monitor_dev_t) == 0x400, "Invalid size of bus_monitor_dev_t structure");
#endif
#ifdef __cplusplus

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components/soc/esp32c5/register/soc/cpu_apm_reg.h Normal file
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components/soc/esp32c5/register/soc/cpu_apm_struct.h Normal file
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@@ -0,0 +1,404 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} cpu_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t regionn_addr_start_l:12;
/** regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:7;
/** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, start address of region n.
*/
uint32_t regionn_addr_start_h:13;
};
uint32_t val;
} cpu_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region n.
*/
uint32_t regionn_addr_end_l:12;
/** regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:7;
/** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, end address of region n.
*/
uint32_t regionn_addr_end_h:13;
};
uint32_t val;
} cpu_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} cpu_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} cpu_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} cpu_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37769360;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} cpu_apm_date_reg_t;
typedef struct {
volatile cpu_apm_region_filter_en_reg_t region_filter_en;
volatile cpu_apm_regionn_addr_start_reg_t region0_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region0_addr_end;
volatile cpu_apm_regionn_attr_reg_t region0_attr;
volatile cpu_apm_regionn_addr_start_reg_t region1_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region1_addr_end;
volatile cpu_apm_regionn_attr_reg_t region1_attr;
volatile cpu_apm_regionn_addr_start_reg_t region2_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region2_addr_end;
volatile cpu_apm_regionn_attr_reg_t region2_attr;
volatile cpu_apm_regionn_addr_start_reg_t region3_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region3_addr_end;
volatile cpu_apm_regionn_attr_reg_t region3_attr;
volatile cpu_apm_regionn_addr_start_reg_t region4_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region4_addr_end;
volatile cpu_apm_regionn_attr_reg_t region4_attr;
volatile cpu_apm_regionn_addr_start_reg_t region5_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region5_addr_end;
volatile cpu_apm_regionn_attr_reg_t region5_attr;
volatile cpu_apm_regionn_addr_start_reg_t region6_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region6_addr_end;
volatile cpu_apm_regionn_attr_reg_t region6_attr;
volatile cpu_apm_regionn_addr_start_reg_t region7_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region7_addr_end;
volatile cpu_apm_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile cpu_apm_func_ctrl_reg_t func_ctrl;
volatile cpu_apm_m0_status_reg_t m0_status;
volatile cpu_apm_m0_status_clr_reg_t m0_status_clr;
volatile cpu_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile cpu_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile cpu_apm_m1_status_reg_t m1_status;
volatile cpu_apm_m1_status_clr_reg_t m1_status_clr;
volatile cpu_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile cpu_apm_m1_exception_info1_reg_t m1_exception_info1;
uint32_t reserved_0e8[12];
volatile cpu_apm_int_en_reg_t int_en;
uint32_t reserved_11c[439];
volatile cpu_apm_clock_gate_reg_t clock_gate;
volatile cpu_apm_date_reg_t date;
} cpu_apm_dev_t;
extern cpu_apm_dev_t CPU_APM;
#ifndef __cplusplus
_Static_assert(sizeof(cpu_apm_dev_t) == 0x800, "Invalid size of cpu_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

118
components/soc/esp32c5/register/soc/ecc_mult_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -65,69 +65,71 @@ extern "C" {
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done. \\
* 0: No effect\\
* 1: Start calculation of ECC Accelerator\\
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator. \\
* 0: No effect\\
* 1: Reset\\
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* Configures the key length mode bit of ECC Accelerator. \\
* 0: P-192\\
* 1: P-256\\
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: SM2
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH 0x00000003U
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_V 0x00000003U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11. \\
* 0: n(order of curve)\\
* 1: p(mod base of curve)\\
/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(3))
#define ECC_MULT_MOD_BASE (BIT(4))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 3
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
* Configures the work mode of ECC Accelerator.\\
* 0: Point Multi mode\\
* 1: Reserved\\
* 2: Point Verif mode\\
* 3: Point Verif + Multi mode\\
* 4: Jacobian Point Multi mode\\
* 5: Reserved\\
* 6: Jacobian Point Verif mode\\
* 7: Point Verif + Jacobian Point Multi mode\\
* 8: Mod Add mode\\
* 9. Mod Sub mode\\
* 10: Mod Multi mode\\
* 11: Mod Div mode\\
#define ECC_MULT_MOD_BASE_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 4
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
* Configures the security mode of ECC Accelerator.\\
* 0: no secure function enabled.\\
* 1: enable constant-time calculation in all point multiplication modes.\\
#define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
#define ECC_MULT_SECURITY_MODE (BIT(8))
#define ECC_MULT_SECURITY_MODE (BIT(9))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 8
#define ECC_MULT_SECURITY_MODE_S 9
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
@@ -137,18 +139,18 @@ extern "C" {
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate. \\
* 0: No effect\\
* 1: Force on\\
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate. \\
* 0: No effect\\
* 1: Force on\\
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
@@ -159,7 +161,7 @@ extern "C" {
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37752928;
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
@@ -171,37 +173,37 @@ extern "C" {
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 32
#define ECC_MULT_K_MEM_SIZE_BYTES 48
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130)
#define ECC_MULT_PX_MEM_SIZE_BYTES 48
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160)
#define ECC_MULT_PY_MEM_SIZE_BYTES 48
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
#define ECC_MULT_QX_MEM_SIZE_BYTES 32
#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190)
#define ECC_MULT_QX_MEM_SIZE_BYTES 48
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
#define ECC_MULT_QY_MEM_SIZE_BYTES 32
#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0)
#define ECC_MULT_QY_MEM_SIZE_BYTES 48
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1a0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}

100
components/soc/esp32c5/register/soc/ecc_mult_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -78,67 +78,69 @@ typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done. \\
* 0: No effect\\
* 1: Start calculation of ECC Accelerator\\
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator. \\
* 0: No effect\\
* 1: Reset\\
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0;
* Configures the key length mode bit of ECC Accelerator. \\
* 0: P-192\\
* 1: P-256\\
/** key_length : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: SM2
*/
uint32_t key_length:1;
/** mod_base : R/W; bitpos: [3]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11. \\
* 0: n(order of curve)\\
* 1: p(mod base of curve)\\
uint32_t key_length:2;
/** mod_base : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
uint32_t mod_base:1;
/** work_mode : R/W; bitpos: [7:4]; default: 0;
* Configures the work mode of ECC Accelerator.\\
* 0: Point Multi mode\\
* 1: Reserved\\
* 2: Point Verif mode\\
* 3: Point Verif + Multi mode\\
* 4: Jacobian Point Multi mode\\
* 5: Reserved\\
* 6: Jacobian Point Verif mode\\
* 7: Point Verif + Jacobian Point Multi mode\\
* 8: Mod Add mode\\
* 9. Mod Sub mode\\
* 10: Mod Multi mode\\
* 11: Mod Div mode\\
/** work_mode : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
uint32_t work_mode:4;
/** security_mode : R/W; bitpos: [8]; default: 0;
* Configures the security mode of ECC Accelerator.\\
* 0: no secure function enabled.\\
* 1: enable constant-time calculation in all point multiplication modes.\\
/** security_mode : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
uint32_t security_mode:1;
uint32_t reserved_9:20;
uint32_t reserved_10:19;
/** verification_result : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
uint32_t verification_result:1;
/** clk_en : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate. \\
* 0: No effect\\
* 1: Force on\\
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t clk_en:1;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate. \\
* 0: No effect\\
* 1: Force on\\
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mem_clock_gate_force_on:1;
};
@@ -152,7 +154,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37752928;
/** date : R/W; bitpos: [27:0]; default: 37781792;
* ECC mult version control register
*/
uint32_t date:28;
@@ -171,18 +173,18 @@ typedef struct {
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[8];
volatile uint32_t px[8];
volatile uint32_t py[8];
volatile uint32_t qx[8];
volatile uint32_t qy[8];
volatile uint32_t qz[8];
volatile uint32_t k[12];
volatile uint32_t px[12];
volatile uint32_t py[12];
volatile uint32_t qx[12];
volatile uint32_t qy[12];
volatile uint32_t qz[12];
} ecc_mult_dev_t;
extern ecc_mult_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x1c0, "Invalid size of ecc_mult_dev_t structure");
_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus

360
components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h Normal file
View File

@@ -0,0 +1,360 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2.
*/
#define ECDSA_ECC_CURVE 0x00000003U
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000003U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(4))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 4
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(5))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 5
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(6))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
* invalid.
*/
#define ECDSA_SHA_MODE 0x0000000FU
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x0000000FU
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
#define ECDSA_R_MEM_SIZE_BYTES 48
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
#define ECDSA_S_MEM_SIZE_BYTES 48
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
#define ECDSA_Z_MEM_SIZE_BYTES 48
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
#define ECDSA_QAX_MEM_SIZE_BYTES 48
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
#define ECDSA_QAY_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

348
components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h Normal file
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@@ -0,0 +1,348 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2.
*/
uint32_t ecc_curve:2;
/** software_set_k : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
uint32_t reserved_7:25;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [3:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
* invalid.
*/
uint32_t sha_mode:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37785984;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[16];
uint32_t reserved_2c0[72];
volatile uint32_t r[12];
volatile uint32_t s[12];
volatile uint32_t z[12];
volatile uint32_t qax[12];
volatile uint32_t qay[12];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

4407
components/soc/esp32c5/register/soc/efuse_reg_eco2.h Normal file
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3723
components/soc/esp32c5/register/soc/efuse_struct_eco2.h Normal file
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129
components/soc/esp32c5/register/soc/hp_system_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,9 +16,9 @@ extern "C" {
*/
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
@@ -32,10 +32,9 @@ extern "C" {
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot
* mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
@@ -43,9 +42,9 @@ extern "C" {
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode. \\
* 0: Disable\\
* 1: Enable\\
* mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
@@ -58,6 +57,7 @@ extern "C" {
#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_CACHE_USAGE (BIT(0))
#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
@@ -84,11 +84,11 @@ extern "C" {
#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to enable anti-DPA attack. Valid only when
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
* 0: Disable\\
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
* 0: Disable
* 1-3: Enable. The larger the number, the higher the security level, which represents
* the ability to resist DPA attacks, with increased computational overhead of the
* hardware crypto-accelerators at the same time. \\
* hardware crypto-accelerators at the same time.
*/
#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
@@ -96,9 +96,9 @@ extern "C" {
#define HP_SYSTEM_SEC_DPA_LEVEL_S 0
/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
* eFuse) to control DPA level. \\
* 0: Select EFUSE_SEC_DPA_LEVEL\\
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
* eFuse) to control DPA level.
* 0: Select EFUSE_SEC_DPA_LEVEL
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL
*/
#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
@@ -126,9 +126,9 @@ extern "C" {
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
@@ -173,9 +173,9 @@ extern "C" {
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.\\
* 0: No effect\\
* 1: Clear timeout interrupt\\
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
@@ -183,9 +183,9 @@ extern "C" {
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
@@ -219,11 +219,14 @@ extern "C" {
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
* MODEM_PERI_TIMEOUT configuration register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
@@ -231,6 +234,7 @@ extern "C" {
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
@@ -238,6 +242,7 @@ extern "C" {
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
@@ -246,10 +251,13 @@ extern "C" {
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
* MODEM_PERI_TIMEOUT_ADDR register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
@@ -258,11 +266,14 @@ extern "C" {
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
* MODEM_PERI_TIMEOUT_UID register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
@@ -293,9 +304,9 @@ extern "C" {
*/
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38)
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
* 0: Unlock \\
* 1: Lock \\
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
@@ -321,9 +332,9 @@ extern "C" {
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40)
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.\\
* 0: Disable\\
* 1: Enable\\
* LP CPU.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0))
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
@@ -340,10 +351,13 @@ extern "C" {
/** HP_SYSTEM_MEM_TEST_CONF_REG register
* MEM_TEST configuration register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44)
/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_HP_MEM_WPULSE 0x00000007U
#define HP_SYSTEM_HP_MEM_WPULSE_M (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
@@ -351,6 +365,7 @@ extern "C" {
#define HP_SYSTEM_HP_MEM_WPULSE_S 0
/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_HP_MEM_WA 0x00000007U
#define HP_SYSTEM_HP_MEM_WA_M (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
@@ -358,12 +373,25 @@ extern "C" {
#define HP_SYSTEM_HP_MEM_WA_S 3
/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_HP_MEM_RA 0x00000003U
#define HP_SYSTEM_HP_MEM_RA_M (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
#define HP_SYSTEM_HP_MEM_RA_V 0x00000003U
#define HP_SYSTEM_HP_MEM_RA_S 6
/** HP_SYSTEM_SDIO_SPRF_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SDIO_SPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x6c)
/** HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 12816;
* sdio mem separate control signal.
*/
#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SDIO_SPRF_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_SPROM_CTRL_REG register
* reserved
*/
@@ -431,12 +459,36 @@ extern "C" {
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_V 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_S 4
/** HP_SYSTEM_AXI_MST_PRI_REG register
* AXI mst priority configuration register
*/
#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_SYSTEM_BASE + 0x88)
/** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
#define HP_SYSTEM_DMA_PRIORITY (BIT(0))
#define HP_SYSTEM_DMA_PRIORITY_M (HP_SYSTEM_DMA_PRIORITY_V << HP_SYSTEM_DMA_PRIORITY_S)
#define HP_SYSTEM_DMA_PRIORITY_V 0x00000001U
#define HP_SYSTEM_DMA_PRIORITY_S 0
/** HP_SYSTEM_CACHE_PRIORITY : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
#define HP_SYSTEM_CACHE_PRIORITY (BIT(1))
#define HP_SYSTEM_CACHE_PRIORITY_M (HP_SYSTEM_CACHE_PRIORITY_V << HP_SYSTEM_CACHE_PRIORITY_S)
#define HP_SYSTEM_CACHE_PRIORITY_V 0x00000001U
#define HP_SYSTEM_CACHE_PRIORITY_S 1
/** HP_SYSTEM_RND_ECO_REG register
* redcy eco register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_REDCY_ENA (BIT(0))
#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
@@ -444,6 +496,7 @@ extern "C" {
#define HP_SYSTEM_REDCY_ENA_S 0
/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_REDCY_RESULT (BIT(1))
#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
@@ -452,10 +505,13 @@ extern "C" {
/** HP_SYSTEM_RND_ECO_LOW_REG register
* redcy eco low register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
@@ -464,10 +520,13 @@ extern "C" {
/** HP_SYSTEM_RND_ECO_HIGH_REG register
* redcy eco high register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
@@ -476,10 +535,13 @@ extern "C" {
/** HP_SYSTEM_DEBUG_REG register
* HP-SYSTEM debug register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x3f4)
/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
* Reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_FPGA_DEBUG (BIT(0))
#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S)
@@ -488,10 +550,13 @@ extern "C" {
/** HP_SYSTEM_CLOCK_GATE_REG register
* HP-SYSTEM clock gating configure register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define HP_SYSTEM_CLK_EN (BIT(0))
#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)

118
components/soc/esp32c5/register/soc/hp_system_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,9 +17,9 @@ extern "C" {
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
@@ -27,17 +27,16 @@ typedef union {
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot
* mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode. \\
* 0: Disable\\
* 1: Enable\\
* mode.
* 0: Disable
* 1: Enable
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
@@ -52,6 +51,7 @@ typedef union {
struct {
/** cache_usage : HRO; bitpos: [0]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t cache_usage:1;
uint32_t reserved_1:7;
@@ -76,18 +76,18 @@ typedef union {
struct {
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to enable anti-DPA attack. Valid only when
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
* 0: Disable\\
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
* 0: Disable
* 1-3: Enable. The larger the number, the higher the security level, which represents
* the ability to resist DPA attacks, with increased computational overhead of the
* hardware crypto-accelerators at the same time. \\
* hardware crypto-accelerators at the same time.
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
* eFuse) to control DPA level. \\
* 0: Select EFUSE_SEC_DPA_LEVEL\\
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
* eFuse) to control DPA level.
* 0: Select EFUSE_SEC_DPA_LEVEL
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL
*/
uint32_t sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
@@ -119,9 +119,9 @@ typedef union {
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
* 0: Unlock \\
* 1: Lock \\
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
@@ -150,9 +150,9 @@ typedef union {
struct {
/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.\\
* 0: Disable\\
* 1: Enable\\
* LP CPU.
* 0: Disable
* 1: Enable
*/
uint32_t core_debug_runstall_enable:1;
/** core_runstalled : RO; bitpos: [1]; default: 0;
@@ -172,14 +172,17 @@ typedef union {
struct {
/** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t hp_mem_wpulse:3;
/** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t hp_mem_wa:3;
/** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t hp_mem_ra:2;
uint32_t reserved_8:24;
@@ -187,6 +190,19 @@ typedef union {
uint32_t val;
} hp_system_mem_test_conf_reg_t;
/** Type of sdio_sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sdio_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 12816;
* sdio mem separate control signal.
*/
uint32_t sdio_sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sdio_sprf_ctrl_reg_t;
/** Type of sprom_ctrl register
* reserved
*/
@@ -257,6 +273,26 @@ typedef union {
uint32_t val;
} hp_system_bitscrambler_peri_sel_reg_t;
/** Type of axi_mst_pri register
* AXI mst priority configuration register
*/
typedef union {
struct {
/** dma_priority : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t dma_priority:1;
/** cache_priority : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t cache_priority:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_axi_mst_pri_reg_t;
/** Type of clock_gate register
* HP-SYSTEM clock gating configure register
*/
@@ -264,6 +300,7 @@ typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@@ -289,9 +326,9 @@ typedef union {
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
@@ -338,16 +375,16 @@ typedef union {
*/
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.\\
* 0: No effect\\
* 1: Clear timeout interrupt\\
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
@@ -391,14 +428,17 @@ typedef union {
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t modem_peri_timeout_thres:16;
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t modem_peri_timeout_int_clear:1;
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t modem_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
@@ -413,6 +453,7 @@ typedef union {
struct {
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t modem_peri_timeout_addr:32;
};
@@ -427,6 +468,7 @@ typedef union {
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t modem_peri_timeout_uid:7;
uint32_t reserved_7:25;
@@ -443,10 +485,12 @@ typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
@@ -461,6 +505,7 @@ typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t redcy_low:32;
};
@@ -474,6 +519,7 @@ typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t redcy_high:32;
};
@@ -489,6 +535,7 @@ typedef union {
struct {
/** fpga_debug : R/W; bitpos: [0]; default: 1;
* Reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t fpga_debug:1;
uint32_t reserved_1:31;
@@ -532,13 +579,16 @@ typedef struct {
volatile hp_system_rom_table_reg_t rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
volatile hp_system_mem_test_conf_reg_t mem_test_conf;
uint32_t reserved_048[10];
uint32_t reserved_048[9];
volatile hp_system_sdio_sprf_ctrl_reg_t sdio_sprf_ctrl;
volatile hp_system_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t sprf_ctrl;
volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl;
volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
uint32_t reserved_084[215];
uint32_t reserved_084;
volatile hp_system_axi_mst_pri_reg_t axi_mst_pri;
uint32_t reserved_08c[213];
volatile hp_system_rnd_eco_reg_t rnd_eco;
volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;

12
components/soc/esp32c5/register/soc/huk_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -198,12 +198,20 @@ extern "C" {
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
#define HUK_UPDATE_REQ (BIT(5))
#define HUK_UPDATE_REQ_M (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
#define HUK_UPDATE_REQ_V 0x00000001U
#define HUK_UPDATE_REQ_S 5
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU

11
components/soc/esp32c5/register/soc/huk_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -191,7 +191,12 @@ typedef union {
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
uint32_t reserved_5:27;
/** update_req : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
uint32_t update_req:1;
uint32_t reserved_6:26;
};
uint32_t val;
} huk_status_reg_t;
@@ -203,7 +208,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
/** date : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
uint32_t date:28;

837
components/soc/esp32c5/register/soc/interrupt_matrix_reg.h
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File diff suppressed because it is too large Load Diff

826
components/soc/esp32c5/register/soc/interrupt_matrix_struct.h
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File diff suppressed because it is too large Load Diff

395
components/soc/esp32c5/register/soc/keymng_reg_eco2.h Normal file
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@@ -0,0 +1,395 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_REG_CG_FORCE_ON_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 5
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 10
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_S 11
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_S 12
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
* ecdsa_key_384_h. Others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
#define KEYMNG_KEY_FLASH_VLD_S 2
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
#define KEYMNG_KEY_HMAC_VLD_S 3
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_DS_VLD (BIT(4))
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
#define KEYMNG_KEY_DS_VLD_S 4
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
#define KEYMNG_KEY_PSRAM_VLD_S 5
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* Key Manager clock gate control register
*/
typedef union {
struct {
/** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t reg_cg_force_on:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Key Manager interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_raw_reg_t;
/** Type of int_st register
* Key Manager interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_st_reg_t;
/** Type of int_ena register
* Key Manager interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_ena_reg_t;
/** Type of int_clr register
* Key Manager interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_clr_reg_t;
/** Group: Static configuration registers */
/** Type of static register
* Key Manager static configuration register
*/
typedef union {
struct {
/** use_efuse_key : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
uint32_t use_efuse_key:5;
/** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
uint32_t rnd_switch_cycle:5;
/** use_sw_init_key : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
uint32_t use_sw_init_key:1;
/** flash_key_len : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
uint32_t flash_key_len:1;
/** psram_key_len : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
uint32_t psram_key_len:1;
uint32_t reserved_13:19;
};
uint32_t val;
} keymng_static_reg_t;
/** Type of lock register
* Key Manager static configuration locker register
*/
typedef union {
struct {
/** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
uint32_t use_efuse_key_lock:5;
/** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
uint32_t rnd_switch_cycle_lock:1;
/** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
uint32_t use_sw_init_key_lock:1;
/** flash_key_len_lock : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
uint32_t flash_key_len_lock:1;
/** psram_key_len_lock : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
uint32_t psram_key_len_lock:1;
uint32_t reserved_9:23;
};
uint32_t val;
} keymng_lock_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* Key Manager configuration register
*/
typedef union {
struct {
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
uint32_t kgen_mode:3;
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
* ecdsa_key_384_h. Others: reserved.
*/
uint32_t key_purpose:4;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* Key Manager control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to conti Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_start_reg_t;
/** Group: State registers */
/** Type of state register
* Key Manager state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_state_reg_t;
/** Group: Result registers */
/** Type of result register
* Key Manager operation result register
*/
typedef union {
struct {
/** proc_result : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
uint32_t proc_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_result_reg_t;
/** Type of key_vld register
* Key Manager key status register
*/
typedef union {
struct {
/** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ecdsa_192_vld:1;
/** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0;
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ecdsa_256_vld:1;
/** key_flash_vld : RO; bitpos: [2]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_flash_vld:1;
/** key_hmac_vld : RO; bitpos: [3]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_hmac_vld:1;
/** key_ds_vld : RO; bitpos: [4]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ds_vld:1;
/** key_psram_vld : RO; bitpos: [5]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_psram_vld:1;
/** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0;
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ecdsa_384_vld:1;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_key_vld_reg_t;
/** Type of huk_vld register
* Key Manager HUK status register
*/
typedef union {
struct {
/** huk_valid : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
uint32_t huk_valid:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_huk_vld_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37781824;
* Key Manager version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} keymng_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static_conf;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
volatile keymng_state_reg_t state;
volatile keymng_result_reg_t result;
volatile keymng_key_vld_reg_t key_vld;
volatile keymng_huk_vld_reg_t huk_vld;
uint32_t reserved_038[49];
volatile keymng_date_reg_t date;
volatile uint32_t assist_info[16];
volatile uint32_t public_info[16];
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
extern keymng_dev_t KEYMNG;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
* Configure brownout mode0
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* enable suspend spi when brownout interrupt or not
* 1:enable
* 0:disable
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* enable power down RF when brownout interrupt or not
* 1:enable
* 0:disable
*/
#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* set the undervoltage hold time for triggering brownout interrupt
*/
#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* set the undervoltage hold time for triggering brownout reset
*/
#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* clear brownout count or not
* 1: clear
* 0: no operation
*/
#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* enable brownout interrupt or not
* 1: enable
* 0: disable
*/
#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* select brownout reset level
* 1: system reset
* 0: chip reset
*/
#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* enable brownout reset or not
* 1: enable
* 0: disable
*/
#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANA_BOD_MODE1_CNTL_REG register
* Configure brownout mode1
*/
#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* enable brownout mode1 reset or not
* 1: enable
* 0: disable
*/
#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANA_CK_GLITCH_CNTL_REG register
* Configure power glitch
*/
#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0;
* enable powerglitch or not
*/
#define LP_ANA_PWR_GLITCH_RESET_ENA 0x0000000FU
#define LP_ANA_PWR_GLITCH_RESET_ENA_M (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S)
#define LP_ANA_PWR_GLITCH_RESET_ENA_V 0x0000000FU
#define LP_ANA_PWR_GLITCH_RESET_ENA_S 27
/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* reserved
*/
#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANA_FIB_ENABLE_REG register
* configure FIB REG
*/
#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
* configure analog fib by software
*/
#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_S 0
/** LP_ANA_INT_RAW_REG register
* interrpt raw register
*/
#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 interrupt raw register
*/
#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANA_INT_ST_REG register
* interrpt status register
*/
#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* brownout mode0 interrupt status register
*/
#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANA_INT_ENA_REG register
* interrpt enable register
*/
#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* brownout mode0 interrupt enable register
*/
#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANA_INT_CLR_REG register
* interrpt clear register
*/
#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* brownout mode0 interrupt clear register
*/
#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANA_LP_INT_RAW_REG register
* lp interrupt raw register
*/
#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt raw register
*/
#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANA_LP_INT_ST_REG register
* lp interrupt status register
*/
#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt status register
*/
#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANA_LP_INT_ENA_REG register
* lp interrupt enable register
*/
#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt enable register
*/
#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANA_LP_INT_CLR_REG register
* lp interrupt clear register
*/
#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt clear register
*/
#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANA_DATE_REG register
* version register
*/
#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:1]; default: 18387264;
* version register
*/
#define LP_ANA_LP_ANA_DATE 0x3FFFFFFFU
#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
#define LP_ANA_LP_ANA_DATE_V 0x3FFFFFFFU
#define LP_ANA_LP_ANA_DATE_S 1
/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* reserved
*/
#define LP_ANA_CLK_EN (BIT(31))
#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
#define LP_ANA_CLK_EN_V 0x00000001U
#define LP_ANA_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

271
components/soc/esp32c5/register/soc/lp_analog_peri_struct_eco2.h Normal file
View File

@@ -0,0 +1,271 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of bod_mode0_cntl register
* Configure brownout mode0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* enable suspend spi when brownout interrupt or not
* 1:enable
* 0:disable
*/
uint32_t bod_mode0_close_flash_ena:1;
/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* enable power down RF when brownout interrupt or not
* 1:enable
* 0:disable
*/
uint32_t bod_mode0_pd_rf_ena:1;
/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* set the undervoltage hold time for triggering brownout interrupt
*/
uint32_t bod_mode0_intr_wait:10;
/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* set the undervoltage hold time for triggering brownout reset
*/
uint32_t bod_mode0_reset_wait:10;
/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* clear brownout count or not
* 1: clear
* 0: no operation
*/
uint32_t bod_mode0_cnt_clr:1;
/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* enable brownout interrupt or not
* 1: enable
* 0: disable
*/
uint32_t bod_mode0_intr_ena:1;
/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* select brownout reset level
* 1: system reset
* 0: chip reset
*/
uint32_t bod_mode0_reset_sel:1;
/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* enable brownout reset or not
* 1: enable
* 0: disable
*/
uint32_t bod_mode0_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of bod_mode1_cntl register
* Configure brownout mode1
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* enable brownout mode1 reset or not
* 1: enable
* 0: disable
*/
uint32_t bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* Configure power glitch
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** pwr_glitch_reset_ena : R/W; bitpos: [30:27]; default: 0;
* enable powerglitch or not
*/
uint32_t pwr_glitch_reset_ena:4;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of fib_enable register
* configure FIB REG
*/
typedef union {
struct {
/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
* configure analog fib by software
*/
uint32_t ana_fib_ena:32;
};
uint32_t val;
} lp_ana_fib_enable_reg_t;
/** Type of int_raw register
* interrpt raw register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 interrupt raw register
*/
uint32_t bod_mode0_int_raw:1;
};
uint32_t val;
} lp_ana_int_raw_reg_t;
/** Type of int_st register
* interrpt status register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
* brownout mode0 interrupt status register
*/
uint32_t bod_mode0_int_st:1;
};
uint32_t val;
} lp_ana_int_st_reg_t;
/** Type of int_ena register
* interrpt enable register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
* brownout mode0 interrupt enable register
*/
uint32_t bod_mode0_int_ena:1;
};
uint32_t val;
} lp_ana_int_ena_reg_t;
/** Type of int_clr register
* interrpt clear register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
* brownout mode0 interrupt clear register
*/
uint32_t bod_mode0_int_clr:1;
};
uint32_t val;
} lp_ana_int_clr_reg_t;
/** Type of lp_int_raw register
* lp interrupt raw register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt raw register
*/
uint32_t bod_mode0_lp_int_raw:1;
};
uint32_t val;
} lp_ana_lp_int_raw_reg_t;
/** Type of lp_int_st register
* lp interrupt status register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt status register
*/
uint32_t bod_mode0_lp_int_st:1;
};
uint32_t val;
} lp_ana_lp_int_st_reg_t;
/** Type of lp_int_ena register
* lp interrupt enable register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt enable register
*/
uint32_t bod_mode0_lp_int_ena:1;
};
uint32_t val;
} lp_ana_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* lp interrupt clear register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt clear register
*/
uint32_t bod_mode0_lp_int_clr:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Type of date register
* version register
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** lp_ana_date : R/W; bitpos: [30:1]; default: 18387264;
* version register
*/
uint32_t lp_ana_date:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_ana_date_reg_t;
typedef struct {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;
volatile lp_ana_int_ena_reg_t int_ena;
volatile lp_ana_int_clr_reg_t int_clr;
volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
volatile lp_ana_lp_int_st_reg_t lp_int_st;
volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_030[243];
volatile lp_ana_date_reg_t date;
} lp_ana_dev_t;
extern lp_ana_dev_t LP_ANA_PERI;
#ifndef __cplusplus
_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

99
components/soc/esp32c5/register/soc/lp_aon_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -160,10 +160,13 @@ extern "C" {
/** LP_AON_GPIO_HOLD1_REG register
* reserved
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
@@ -174,22 +177,28 @@ extern "C" {
* configure system register
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FORCE_DOWNLOAD_BOOT_STATUS : RO; bitpos: [29]; default: 0;
* get force download mode status
/** LP_AON_FORCE_DOWNLOAD_BOOT_STATUS : RO; bitpos: [28:27]; default: 0;
* get force download mode status,
* bit1:download boot1
* bit0:download boot0
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS (BIT(29))
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS 0x00000003U
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_M (LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V << LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S 29
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V 0x00000003U
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S 27
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30:29]; default: 0;
* enable chip entry download mode or not
* 1: enable
* 0: no operation
* 00: no operation
* 01:force download boot0(uart/usb)
* 10:force download boot1(uart/sdio)
* 11: no operation
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30))
#define LP_AON_FORCE_DOWNLOAD_BOOT 0x00000003U
#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000003U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 29
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* enable hp system reset by software or not
* 1: reset
@@ -224,6 +233,7 @@ extern "C" {
#define LP_AON_CPU_CORE0_SW_RESET_S 28
/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29))
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
@@ -233,6 +243,7 @@ extern "C" {
* configure core boot address
* 1: ROM
* 0: lp memory
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30))
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
@@ -242,6 +253,7 @@ extern "C" {
* disable bypass core dreset
* 1: enable bypass
* 0: disable bypass
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31))
#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
@@ -363,10 +375,13 @@ extern "C" {
/** LP_AON_SDIO_ACTIVE_REG register
* configure sdio act dnum
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
@@ -403,10 +418,13 @@ extern "C" {
/** LP_AON_SAR_CCT_REG register
* configure sar cct
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
* configure sar cct
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_SAR2_PWDET_CCT 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
@@ -415,12 +433,15 @@ extern "C" {
/** LP_AON_MODEM_BUS_REG register
* configure modem sync bridge
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58)
/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0;
* enable modem sync bridge or not
* 1: enable
* 0: disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31))
#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S)
@@ -429,10 +450,13 @@ extern "C" {
/** LP_AON_SPRAM_CTRL_REG register
* configure lp memory power status
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60)
/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* configure lp memory power status
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S)
@@ -441,10 +465,13 @@ extern "C" {
/** LP_AON_SPRF_CTRL_REG register
* configure memory in lp system power status
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64)
/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* configure memory in lp system power status
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S)
@@ -453,10 +480,13 @@ extern "C" {
/** LP_AON_DEBUG_SEL0_REG register
* reserved
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_DEBUG_SEL0_REG (DR_REG_LP_AON_BASE + 0x68)
/** LP_AON_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_LP_DEBUG_SEL0 0x0000007FU
#define LP_AON_LP_DEBUG_SEL0_M (LP_AON_LP_DEBUG_SEL0_V << LP_AON_LP_DEBUG_SEL0_S)
@@ -464,6 +494,7 @@ extern "C" {
#define LP_AON_LP_DEBUG_SEL0_S 0
/** LP_AON_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_LP_DEBUG_SEL1 0x0000007FU
#define LP_AON_LP_DEBUG_SEL1_M (LP_AON_LP_DEBUG_SEL1_V << LP_AON_LP_DEBUG_SEL1_S)
@@ -471,6 +502,7 @@ extern "C" {
#define LP_AON_LP_DEBUG_SEL1_S 7
/** LP_AON_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_LP_DEBUG_SEL2 0x0000007FU
#define LP_AON_LP_DEBUG_SEL2_M (LP_AON_LP_DEBUG_SEL2_V << LP_AON_LP_DEBUG_SEL2_S)
@@ -478,6 +510,7 @@ extern "C" {
#define LP_AON_LP_DEBUG_SEL2_S 14
/** LP_AON_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_LP_DEBUG_SEL3 0x0000007FU
#define LP_AON_LP_DEBUG_SEL3_M (LP_AON_LP_DEBUG_SEL3_V << LP_AON_LP_DEBUG_SEL3_S)
@@ -486,10 +519,13 @@ extern "C" {
/** LP_AON_DEBUG_SEL1_REG register
* need des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_DEBUG_SEL1_REG (DR_REG_LP_AON_BASE + 0x6c)
/** LP_AON_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_LP_DEBUG_SEL4 0x0000007FU
#define LP_AON_LP_DEBUG_SEL4_M (LP_AON_LP_DEBUG_SEL4_V << LP_AON_LP_DEBUG_SEL4_S)
@@ -549,6 +585,7 @@ extern "C" {
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20
/** LP_AON_AON_BYPASS : R/W; bitpos: [31]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_AON_BYPASS (BIT(31))
#define LP_AON_AON_BYPASS_M (LP_AON_AON_BYPASS_V << LP_AON_AON_BYPASS_S)
@@ -600,11 +637,47 @@ extern "C" {
#define LP_AON_HUK_MEM_FORCE_PU_V 0x00000001U
#define LP_AON_HUK_MEM_FORCE_PU_S 3
/** LP_AON_PUF_MEM_SW_REG register
* configure the power switch of PUFMEM
*/
#define LP_AON_PUF_MEM_SW_REG (DR_REG_LP_AON_BASE + 0x80)
/** LP_AON_PUF_MEM_SW : R/W; bitpos: [0]; default: 1;
* power switch of PD_LPPUFMEM
*/
#define LP_AON_PUF_MEM_SW (BIT(0))
#define LP_AON_PUF_MEM_SW_M (LP_AON_PUF_MEM_SW_V << LP_AON_PUF_MEM_SW_S)
#define LP_AON_PUF_MEM_SW_V 0x00000001U
#define LP_AON_PUF_MEM_SW_S 0
/** LP_AON_PUF_MEM_ISO_REG register
* configure the iso of PD_PUFMEM
*/
#define LP_AON_PUF_MEM_ISO_REG (DR_REG_LP_AON_BASE + 0x84)
/** LP_AON_PUF_MEM_ISO : R/W; bitpos: [0]; default: 0;
* ISO enable of PD_LPPUFMEM to PD_SYS
*/
#define LP_AON_PUF_MEM_ISO (BIT(0))
#define LP_AON_PUF_MEM_ISO_M (LP_AON_PUF_MEM_ISO_V << LP_AON_PUF_MEM_ISO_S)
#define LP_AON_PUF_MEM_ISO_V 0x00000001U
#define LP_AON_PUF_MEM_ISO_S 0
/** LP_AON_PUF_MEM_DISCHARGE_REG register
* configure the discharge gate of PUFMEM
*/
#define LP_AON_PUF_MEM_DISCHARGE_REG (DR_REG_LP_AON_BASE + 0x88)
/** LP_AON_PUF_MEM_DISCHARGE : R/W; bitpos: [0]; default: 0;
* discharge gate of LPPUFMEM
*/
#define LP_AON_PUF_MEM_DISCHARGE (BIT(0))
#define LP_AON_PUF_MEM_DISCHARGE_M (LP_AON_PUF_MEM_DISCHARGE_V << LP_AON_PUF_MEM_DISCHARGE_S)
#define LP_AON_PUF_MEM_DISCHARGE_V 0x00000001U
#define LP_AON_PUF_MEM_DISCHARGE_S 0
/** LP_AON_DATE_REG register
* reserved
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36774512;
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37818656;
* version register
*/
#define LP_AON_DATE 0x7FFFFFFFU

88
components/soc/esp32c5/register/soc/lp_aon_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -178,6 +178,7 @@ typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t gpio_hold1:32;
};
@@ -189,17 +190,23 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** force_download_boot_status : RO; bitpos: [29]; default: 0;
* get force download mode status
uint32_t reserved_0:27;
/** force_download_boot_status : RO; bitpos: [28:27]; default: 0;
* get force download mode status,
* bit1:download boot1
* bit0:download boot0
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t force_download_boot_status:1;
/** force_download_boot : R/W; bitpos: [30]; default: 0;
uint32_t force_download_boot_status:2;
/** force_download_boot : R/W; bitpos: [30:29]; default: 0;
* enable chip entry download mode or not
* 1: enable
* 0: no operation
* 00: no operation
* 01:force download boot0(uart/usb)
* 10:force download boot1(uart/sdio)
* 11: no operation
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t force_download_boot:1;
uint32_t force_download_boot:2;
/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* enable hp system reset by software or not
* 1: reset
@@ -230,18 +237,21 @@ typedef union {
uint32_t cpu_core0_sw_reset:1;
/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t cpu_core0_ocd_halt_on_reset:1;
/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
* configure core boot address
* 1: ROM
* 0: lp memory
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t cpu_core0_stat_vector_sel:1;
/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
* disable bypass core dreset
* 1: enable bypass
* 0: disable bypass
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t cpu_core0_dreset_mask:1;
};
@@ -356,6 +366,7 @@ typedef union {
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t sdio_act_dnum:10;
};
@@ -394,6 +405,7 @@ typedef union {
uint32_t reserved_0:29;
/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
* configure sar cct
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t sar2_pwdet_cct:3;
};
@@ -410,6 +422,7 @@ typedef union {
* enable modem sync bridge or not
* 1: enable
* 0: disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t modem_sync_bridge_en:1;
};
@@ -423,18 +436,22 @@ typedef union {
struct {
/** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t lp_debug_sel0:7;
/** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t lp_debug_sel1:7;
/** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t lp_debug_sel2:7;
/** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t lp_debug_sel3:7;
uint32_t reserved_28:4;
@@ -449,6 +466,7 @@ typedef union {
struct {
/** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t lp_debug_sel4:7;
uint32_t reserved_7:25;
@@ -498,6 +516,7 @@ typedef union {
uint32_t reserved_30:1;
/** aon_bypass : R/W; bitpos: [31]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t aon_bypass:1;
};
@@ -543,12 +562,54 @@ typedef union {
uint32_t val;
} lp_aon_mem_ctrl_reg_t;
/** Type of puf_mem_sw register
* configure the power switch of PUFMEM
*/
typedef union {
struct {
/** puf_mem_sw_reg : R/W; bitpos: [0]; default: 1;
* power switch of PD_LPPUFMEM
*/
uint32_t puf_mem_sw_reg:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_aon_puf_mem_sw_reg_t;
/** Type of puf_mem_iso register
* configure the iso of PD_PUFMEM
*/
typedef union {
struct {
/** puf_mem_iso_reg : R/W; bitpos: [0]; default: 0;
* ISO enable of PD_LPPUFMEM to PD_SYS
*/
uint32_t puf_mem_iso_reg:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_aon_puf_mem_iso_reg_t;
/** Type of puf_mem_discharge register
* configure the discharge gate of PUFMEM
*/
typedef union {
struct {
/** puf_mem_discharge_reg : R/W; bitpos: [0]; default: 0;
* discharge gate of LPPUFMEM
*/
uint32_t puf_mem_discharge_reg:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_aon_puf_mem_discharge_reg_t;
/** Type of date register
* reserved
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36774512;
/** date : R/W; bitpos: [30:0]; default: 37818656;
* version register
*/
uint32_t date:31;
@@ -569,6 +630,7 @@ typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* configure lp memory power status
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t spram_mem_aux_ctrl:32;
};
@@ -582,6 +644,7 @@ typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* configure memory in lp system power status
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t sprf_mem_aux_ctrl:32;
};
@@ -622,7 +685,10 @@ typedef struct {
volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1;
volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2;
volatile lp_aon_mem_ctrl_reg_t mem_ctrl;
uint32_t reserved_080[223];
volatile lp_aon_puf_mem_sw_reg_t puf_mem_sw;
volatile lp_aon_puf_mem_iso_reg_t puf_mem_iso;
volatile lp_aon_puf_mem_discharge_reg_t puf_mem_discharge;
uint32_t reserved_08c[220];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;

434
components/soc/esp32c5/register/soc/lp_apm0_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,14 +15,14 @@ extern "C" {
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n(0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n(0-7) to enable region $n.
* 0: disable
* 1: enable
*/
#define LP_APM0_REGION_FILTER_EN 0x0000000FU
#define LP_APM0_REGION_FILTER_EN 0x000000FFU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_V 0x000000FFU
#define LP_APM0_REGION_FILTER_EN_S 0
/** LP_APM0_REGION0_ADDR_START_REG register
@@ -421,6 +421,402 @@ extern "C" {
#define LP_APM0_REGION3_LOCK_V 0x00000001U
#define LP_APM0_REGION3_LOCK_S 11
/** LP_APM0_REGION4_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION4_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x34)
/** LP_APM0_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 4
*/
#define LP_APM0_REGION4_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION4_ADDR_START_M (LP_APM0_REGION4_ADDR_START_V << LP_APM0_REGION4_ADDR_START_S)
#define LP_APM0_REGION4_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION4_ADDR_START_S 0
/** LP_APM0_REGION4_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION4_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x38)
/** LP_APM0_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 4
*/
#define LP_APM0_REGION4_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION4_ADDR_END_M (LP_APM0_REGION4_ADDR_END_V << LP_APM0_REGION4_ADDR_END_S)
#define LP_APM0_REGION4_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION4_ADDR_END_S 0
/** LP_APM0_REGION4_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION4_ATTR_REG (DR_REG_LP_APM0_BASE + 0x3c)
/** LP_APM0_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 4.
*/
#define LP_APM0_REGION4_R0_X (BIT(0))
#define LP_APM0_REGION4_R0_X_M (LP_APM0_REGION4_R0_X_V << LP_APM0_REGION4_R0_X_S)
#define LP_APM0_REGION4_R0_X_V 0x00000001U
#define LP_APM0_REGION4_R0_X_S 0
/** LP_APM0_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 4.
*/
#define LP_APM0_REGION4_R0_W (BIT(1))
#define LP_APM0_REGION4_R0_W_M (LP_APM0_REGION4_R0_W_V << LP_APM0_REGION4_R0_W_S)
#define LP_APM0_REGION4_R0_W_V 0x00000001U
#define LP_APM0_REGION4_R0_W_S 1
/** LP_APM0_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 4.
*/
#define LP_APM0_REGION4_R0_R (BIT(2))
#define LP_APM0_REGION4_R0_R_M (LP_APM0_REGION4_R0_R_V << LP_APM0_REGION4_R0_R_S)
#define LP_APM0_REGION4_R0_R_V 0x00000001U
#define LP_APM0_REGION4_R0_R_S 2
/** LP_APM0_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 4.
*/
#define LP_APM0_REGION4_R1_X (BIT(4))
#define LP_APM0_REGION4_R1_X_M (LP_APM0_REGION4_R1_X_V << LP_APM0_REGION4_R1_X_S)
#define LP_APM0_REGION4_R1_X_V 0x00000001U
#define LP_APM0_REGION4_R1_X_S 4
/** LP_APM0_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 4.
*/
#define LP_APM0_REGION4_R1_W (BIT(5))
#define LP_APM0_REGION4_R1_W_M (LP_APM0_REGION4_R1_W_V << LP_APM0_REGION4_R1_W_S)
#define LP_APM0_REGION4_R1_W_V 0x00000001U
#define LP_APM0_REGION4_R1_W_S 5
/** LP_APM0_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 4.
*/
#define LP_APM0_REGION4_R1_R (BIT(6))
#define LP_APM0_REGION4_R1_R_M (LP_APM0_REGION4_R1_R_V << LP_APM0_REGION4_R1_R_S)
#define LP_APM0_REGION4_R1_R_V 0x00000001U
#define LP_APM0_REGION4_R1_R_S 6
/** LP_APM0_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 4.
*/
#define LP_APM0_REGION4_R2_X (BIT(8))
#define LP_APM0_REGION4_R2_X_M (LP_APM0_REGION4_R2_X_V << LP_APM0_REGION4_R2_X_S)
#define LP_APM0_REGION4_R2_X_V 0x00000001U
#define LP_APM0_REGION4_R2_X_S 8
/** LP_APM0_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 4.
*/
#define LP_APM0_REGION4_R2_W (BIT(9))
#define LP_APM0_REGION4_R2_W_M (LP_APM0_REGION4_R2_W_V << LP_APM0_REGION4_R2_W_S)
#define LP_APM0_REGION4_R2_W_V 0x00000001U
#define LP_APM0_REGION4_R2_W_S 9
/** LP_APM0_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 4.
*/
#define LP_APM0_REGION4_R2_R (BIT(10))
#define LP_APM0_REGION4_R2_R_M (LP_APM0_REGION4_R2_R_V << LP_APM0_REGION4_R2_R_S)
#define LP_APM0_REGION4_R2_R_V 0x00000001U
#define LP_APM0_REGION4_R2_R_S 10
/** LP_APM0_REGION4_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION4_LOCK (BIT(11))
#define LP_APM0_REGION4_LOCK_M (LP_APM0_REGION4_LOCK_V << LP_APM0_REGION4_LOCK_S)
#define LP_APM0_REGION4_LOCK_V 0x00000001U
#define LP_APM0_REGION4_LOCK_S 11
/** LP_APM0_REGION5_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION5_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x40)
/** LP_APM0_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 5
*/
#define LP_APM0_REGION5_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION5_ADDR_START_M (LP_APM0_REGION5_ADDR_START_V << LP_APM0_REGION5_ADDR_START_S)
#define LP_APM0_REGION5_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION5_ADDR_START_S 0
/** LP_APM0_REGION5_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION5_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x44)
/** LP_APM0_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 5
*/
#define LP_APM0_REGION5_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION5_ADDR_END_M (LP_APM0_REGION5_ADDR_END_V << LP_APM0_REGION5_ADDR_END_S)
#define LP_APM0_REGION5_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION5_ADDR_END_S 0
/** LP_APM0_REGION5_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION5_ATTR_REG (DR_REG_LP_APM0_BASE + 0x48)
/** LP_APM0_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 5.
*/
#define LP_APM0_REGION5_R0_X (BIT(0))
#define LP_APM0_REGION5_R0_X_M (LP_APM0_REGION5_R0_X_V << LP_APM0_REGION5_R0_X_S)
#define LP_APM0_REGION5_R0_X_V 0x00000001U
#define LP_APM0_REGION5_R0_X_S 0
/** LP_APM0_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 5.
*/
#define LP_APM0_REGION5_R0_W (BIT(1))
#define LP_APM0_REGION5_R0_W_M (LP_APM0_REGION5_R0_W_V << LP_APM0_REGION5_R0_W_S)
#define LP_APM0_REGION5_R0_W_V 0x00000001U
#define LP_APM0_REGION5_R0_W_S 1
/** LP_APM0_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 5.
*/
#define LP_APM0_REGION5_R0_R (BIT(2))
#define LP_APM0_REGION5_R0_R_M (LP_APM0_REGION5_R0_R_V << LP_APM0_REGION5_R0_R_S)
#define LP_APM0_REGION5_R0_R_V 0x00000001U
#define LP_APM0_REGION5_R0_R_S 2
/** LP_APM0_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 5.
*/
#define LP_APM0_REGION5_R1_X (BIT(4))
#define LP_APM0_REGION5_R1_X_M (LP_APM0_REGION5_R1_X_V << LP_APM0_REGION5_R1_X_S)
#define LP_APM0_REGION5_R1_X_V 0x00000001U
#define LP_APM0_REGION5_R1_X_S 4
/** LP_APM0_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 5.
*/
#define LP_APM0_REGION5_R1_W (BIT(5))
#define LP_APM0_REGION5_R1_W_M (LP_APM0_REGION5_R1_W_V << LP_APM0_REGION5_R1_W_S)
#define LP_APM0_REGION5_R1_W_V 0x00000001U
#define LP_APM0_REGION5_R1_W_S 5
/** LP_APM0_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 5.
*/
#define LP_APM0_REGION5_R1_R (BIT(6))
#define LP_APM0_REGION5_R1_R_M (LP_APM0_REGION5_R1_R_V << LP_APM0_REGION5_R1_R_S)
#define LP_APM0_REGION5_R1_R_V 0x00000001U
#define LP_APM0_REGION5_R1_R_S 6
/** LP_APM0_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 5.
*/
#define LP_APM0_REGION5_R2_X (BIT(8))
#define LP_APM0_REGION5_R2_X_M (LP_APM0_REGION5_R2_X_V << LP_APM0_REGION5_R2_X_S)
#define LP_APM0_REGION5_R2_X_V 0x00000001U
#define LP_APM0_REGION5_R2_X_S 8
/** LP_APM0_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 5.
*/
#define LP_APM0_REGION5_R2_W (BIT(9))
#define LP_APM0_REGION5_R2_W_M (LP_APM0_REGION5_R2_W_V << LP_APM0_REGION5_R2_W_S)
#define LP_APM0_REGION5_R2_W_V 0x00000001U
#define LP_APM0_REGION5_R2_W_S 9
/** LP_APM0_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 5.
*/
#define LP_APM0_REGION5_R2_R (BIT(10))
#define LP_APM0_REGION5_R2_R_M (LP_APM0_REGION5_R2_R_V << LP_APM0_REGION5_R2_R_S)
#define LP_APM0_REGION5_R2_R_V 0x00000001U
#define LP_APM0_REGION5_R2_R_S 10
/** LP_APM0_REGION5_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION5_LOCK (BIT(11))
#define LP_APM0_REGION5_LOCK_M (LP_APM0_REGION5_LOCK_V << LP_APM0_REGION5_LOCK_S)
#define LP_APM0_REGION5_LOCK_V 0x00000001U
#define LP_APM0_REGION5_LOCK_S 11
/** LP_APM0_REGION6_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION6_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4c)
/** LP_APM0_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 6
*/
#define LP_APM0_REGION6_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION6_ADDR_START_M (LP_APM0_REGION6_ADDR_START_V << LP_APM0_REGION6_ADDR_START_S)
#define LP_APM0_REGION6_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION6_ADDR_START_S 0
/** LP_APM0_REGION6_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION6_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x50)
/** LP_APM0_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 6
*/
#define LP_APM0_REGION6_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION6_ADDR_END_M (LP_APM0_REGION6_ADDR_END_V << LP_APM0_REGION6_ADDR_END_S)
#define LP_APM0_REGION6_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION6_ADDR_END_S 0
/** LP_APM0_REGION6_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION6_ATTR_REG (DR_REG_LP_APM0_BASE + 0x54)
/** LP_APM0_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 6.
*/
#define LP_APM0_REGION6_R0_X (BIT(0))
#define LP_APM0_REGION6_R0_X_M (LP_APM0_REGION6_R0_X_V << LP_APM0_REGION6_R0_X_S)
#define LP_APM0_REGION6_R0_X_V 0x00000001U
#define LP_APM0_REGION6_R0_X_S 0
/** LP_APM0_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 6.
*/
#define LP_APM0_REGION6_R0_W (BIT(1))
#define LP_APM0_REGION6_R0_W_M (LP_APM0_REGION6_R0_W_V << LP_APM0_REGION6_R0_W_S)
#define LP_APM0_REGION6_R0_W_V 0x00000001U
#define LP_APM0_REGION6_R0_W_S 1
/** LP_APM0_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 6.
*/
#define LP_APM0_REGION6_R0_R (BIT(2))
#define LP_APM0_REGION6_R0_R_M (LP_APM0_REGION6_R0_R_V << LP_APM0_REGION6_R0_R_S)
#define LP_APM0_REGION6_R0_R_V 0x00000001U
#define LP_APM0_REGION6_R0_R_S 2
/** LP_APM0_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 6.
*/
#define LP_APM0_REGION6_R1_X (BIT(4))
#define LP_APM0_REGION6_R1_X_M (LP_APM0_REGION6_R1_X_V << LP_APM0_REGION6_R1_X_S)
#define LP_APM0_REGION6_R1_X_V 0x00000001U
#define LP_APM0_REGION6_R1_X_S 4
/** LP_APM0_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 6.
*/
#define LP_APM0_REGION6_R1_W (BIT(5))
#define LP_APM0_REGION6_R1_W_M (LP_APM0_REGION6_R1_W_V << LP_APM0_REGION6_R1_W_S)
#define LP_APM0_REGION6_R1_W_V 0x00000001U
#define LP_APM0_REGION6_R1_W_S 5
/** LP_APM0_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 6.
*/
#define LP_APM0_REGION6_R1_R (BIT(6))
#define LP_APM0_REGION6_R1_R_M (LP_APM0_REGION6_R1_R_V << LP_APM0_REGION6_R1_R_S)
#define LP_APM0_REGION6_R1_R_V 0x00000001U
#define LP_APM0_REGION6_R1_R_S 6
/** LP_APM0_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 6.
*/
#define LP_APM0_REGION6_R2_X (BIT(8))
#define LP_APM0_REGION6_R2_X_M (LP_APM0_REGION6_R2_X_V << LP_APM0_REGION6_R2_X_S)
#define LP_APM0_REGION6_R2_X_V 0x00000001U
#define LP_APM0_REGION6_R2_X_S 8
/** LP_APM0_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 6.
*/
#define LP_APM0_REGION6_R2_W (BIT(9))
#define LP_APM0_REGION6_R2_W_M (LP_APM0_REGION6_R2_W_V << LP_APM0_REGION6_R2_W_S)
#define LP_APM0_REGION6_R2_W_V 0x00000001U
#define LP_APM0_REGION6_R2_W_S 9
/** LP_APM0_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 6.
*/
#define LP_APM0_REGION6_R2_R (BIT(10))
#define LP_APM0_REGION6_R2_R_M (LP_APM0_REGION6_R2_R_V << LP_APM0_REGION6_R2_R_S)
#define LP_APM0_REGION6_R2_R_V 0x00000001U
#define LP_APM0_REGION6_R2_R_S 10
/** LP_APM0_REGION6_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION6_LOCK (BIT(11))
#define LP_APM0_REGION6_LOCK_M (LP_APM0_REGION6_LOCK_V << LP_APM0_REGION6_LOCK_S)
#define LP_APM0_REGION6_LOCK_V 0x00000001U
#define LP_APM0_REGION6_LOCK_S 11
/** LP_APM0_REGION7_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION7_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x58)
/** LP_APM0_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 7
*/
#define LP_APM0_REGION7_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION7_ADDR_START_M (LP_APM0_REGION7_ADDR_START_V << LP_APM0_REGION7_ADDR_START_S)
#define LP_APM0_REGION7_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION7_ADDR_START_S 0
/** LP_APM0_REGION7_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION7_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x5c)
/** LP_APM0_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 7
*/
#define LP_APM0_REGION7_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION7_ADDR_END_M (LP_APM0_REGION7_ADDR_END_V << LP_APM0_REGION7_ADDR_END_S)
#define LP_APM0_REGION7_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION7_ADDR_END_S 0
/** LP_APM0_REGION7_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION7_ATTR_REG (DR_REG_LP_APM0_BASE + 0x60)
/** LP_APM0_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 7.
*/
#define LP_APM0_REGION7_R0_X (BIT(0))
#define LP_APM0_REGION7_R0_X_M (LP_APM0_REGION7_R0_X_V << LP_APM0_REGION7_R0_X_S)
#define LP_APM0_REGION7_R0_X_V 0x00000001U
#define LP_APM0_REGION7_R0_X_S 0
/** LP_APM0_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 7.
*/
#define LP_APM0_REGION7_R0_W (BIT(1))
#define LP_APM0_REGION7_R0_W_M (LP_APM0_REGION7_R0_W_V << LP_APM0_REGION7_R0_W_S)
#define LP_APM0_REGION7_R0_W_V 0x00000001U
#define LP_APM0_REGION7_R0_W_S 1
/** LP_APM0_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 7.
*/
#define LP_APM0_REGION7_R0_R (BIT(2))
#define LP_APM0_REGION7_R0_R_M (LP_APM0_REGION7_R0_R_V << LP_APM0_REGION7_R0_R_S)
#define LP_APM0_REGION7_R0_R_V 0x00000001U
#define LP_APM0_REGION7_R0_R_S 2
/** LP_APM0_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 7.
*/
#define LP_APM0_REGION7_R1_X (BIT(4))
#define LP_APM0_REGION7_R1_X_M (LP_APM0_REGION7_R1_X_V << LP_APM0_REGION7_R1_X_S)
#define LP_APM0_REGION7_R1_X_V 0x00000001U
#define LP_APM0_REGION7_R1_X_S 4
/** LP_APM0_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 7.
*/
#define LP_APM0_REGION7_R1_W (BIT(5))
#define LP_APM0_REGION7_R1_W_M (LP_APM0_REGION7_R1_W_V << LP_APM0_REGION7_R1_W_S)
#define LP_APM0_REGION7_R1_W_V 0x00000001U
#define LP_APM0_REGION7_R1_W_S 5
/** LP_APM0_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 7.
*/
#define LP_APM0_REGION7_R1_R (BIT(6))
#define LP_APM0_REGION7_R1_R_M (LP_APM0_REGION7_R1_R_V << LP_APM0_REGION7_R1_R_S)
#define LP_APM0_REGION7_R1_R_V 0x00000001U
#define LP_APM0_REGION7_R1_R_S 6
/** LP_APM0_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 7.
*/
#define LP_APM0_REGION7_R2_X (BIT(8))
#define LP_APM0_REGION7_R2_X_M (LP_APM0_REGION7_R2_X_V << LP_APM0_REGION7_R2_X_S)
#define LP_APM0_REGION7_R2_X_V 0x00000001U
#define LP_APM0_REGION7_R2_X_S 8
/** LP_APM0_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 7.
*/
#define LP_APM0_REGION7_R2_W (BIT(9))
#define LP_APM0_REGION7_R2_W_M (LP_APM0_REGION7_R2_W_V << LP_APM0_REGION7_R2_W_S)
#define LP_APM0_REGION7_R2_W_V 0x00000001U
#define LP_APM0_REGION7_R2_W_S 9
/** LP_APM0_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 7.
*/
#define LP_APM0_REGION7_R2_R (BIT(10))
#define LP_APM0_REGION7_R2_R_M (LP_APM0_REGION7_R2_R_V << LP_APM0_REGION7_R2_R_S)
#define LP_APM0_REGION7_R2_R_V 0x00000001U
#define LP_APM0_REGION7_R2_R_S 10
/** LP_APM0_REGION7_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION7_LOCK (BIT(11))
#define LP_APM0_REGION7_LOCK_M (LP_APM0_REGION7_LOCK_V << LP_APM0_REGION7_LOCK_S)
#define LP_APM0_REGION7_LOCK_V 0x00000001U
#define LP_APM0_REGION7_LOCK_S 11
/** LP_APM0_FUNC_CTRL_REG register
* APM function control register
*/
@@ -438,9 +834,9 @@ extern "C" {
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
@@ -463,12 +859,12 @@ extern "C" {
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
* Represents exception region
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION 0x000000FFU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_V 0x000000FFU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode
@@ -502,9 +898,9 @@ extern "C" {
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures APM M0 interrupt enable.\\
* 0: disable \\
* 1: enable \\
* Configures APM M0 interrupt enable.
* 0: disable
* 1: enable
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
@@ -516,9 +912,9 @@ extern "C" {
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)

52
components/soc/esp32c5/register/soc/lp_apm0_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,13 +16,13 @@ extern "C" {
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n(0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n(0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
@@ -133,9 +133,9 @@ typedef union {
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
@@ -166,11 +166,11 @@ typedef union {
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
/** m0_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
uint32_t m0_exception_region:8;
uint32_t reserved_8:8;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode
*/
@@ -207,9 +207,9 @@ typedef union {
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures APM M0 interrupt enable.\\
* 0: disable \\
* 1: enable \\
* Configures APM M0 interrupt enable.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
@@ -225,9 +225,9 @@ typedef union {
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@@ -266,7 +266,19 @@ typedef struct {
volatile lp_apm0_regionn_addr_start_reg_t region3_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region3_addr_end;
volatile lp_apm0_regionn_attr_reg_t region3_attr;
uint32_t reserved_034[36];
volatile lp_apm0_regionn_addr_start_reg_t region4_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region4_addr_end;
volatile lp_apm0_regionn_attr_reg_t region4_attr;
volatile lp_apm0_regionn_addr_start_reg_t region5_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region5_addr_end;
volatile lp_apm0_regionn_attr_reg_t region5_attr;
volatile lp_apm0_regionn_addr_start_reg_t region6_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region6_addr_end;
volatile lp_apm0_regionn_attr_reg_t region6_attr;
volatile lp_apm0_regionn_addr_start_reg_t region7_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region7_addr_end;
volatile lp_apm0_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile lp_apm0_func_ctrl_reg_t func_ctrl;
volatile lp_apm0_m0_status_reg_t m0_status;
volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;

452
components/soc/esp32c5/register/soc/lp_apm_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,14 +15,14 @@ extern "C" {
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n (0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN 0x000000FFU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_V 0x000000FFU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
@@ -421,6 +421,402 @@ extern "C" {
#define LP_APM_REGION3_LOCK_V 0x00000001U
#define LP_APM_REGION3_LOCK_S 11
/** LP_APM_REGION4_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION4_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x34)
/** LP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 4.
*/
#define LP_APM_REGION4_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION4_ADDR_START_M (LP_APM_REGION4_ADDR_START_V << LP_APM_REGION4_ADDR_START_S)
#define LP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION4_ADDR_START_S 0
/** LP_APM_REGION4_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION4_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x38)
/** LP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 4.
*/
#define LP_APM_REGION4_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION4_ADDR_END_M (LP_APM_REGION4_ADDR_END_V << LP_APM_REGION4_ADDR_END_S)
#define LP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION4_ADDR_END_S 0
/** LP_APM_REGION4_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION4_ATTR_REG (DR_REG_LP_APM_BASE + 0x3c)
/** LP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 4.
*/
#define LP_APM_REGION4_R0_X (BIT(0))
#define LP_APM_REGION4_R0_X_M (LP_APM_REGION4_R0_X_V << LP_APM_REGION4_R0_X_S)
#define LP_APM_REGION4_R0_X_V 0x00000001U
#define LP_APM_REGION4_R0_X_S 0
/** LP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 4.
*/
#define LP_APM_REGION4_R0_W (BIT(1))
#define LP_APM_REGION4_R0_W_M (LP_APM_REGION4_R0_W_V << LP_APM_REGION4_R0_W_S)
#define LP_APM_REGION4_R0_W_V 0x00000001U
#define LP_APM_REGION4_R0_W_S 1
/** LP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 4.
*/
#define LP_APM_REGION4_R0_R (BIT(2))
#define LP_APM_REGION4_R0_R_M (LP_APM_REGION4_R0_R_V << LP_APM_REGION4_R0_R_S)
#define LP_APM_REGION4_R0_R_V 0x00000001U
#define LP_APM_REGION4_R0_R_S 2
/** LP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 4.
*/
#define LP_APM_REGION4_R1_X (BIT(4))
#define LP_APM_REGION4_R1_X_M (LP_APM_REGION4_R1_X_V << LP_APM_REGION4_R1_X_S)
#define LP_APM_REGION4_R1_X_V 0x00000001U
#define LP_APM_REGION4_R1_X_S 4
/** LP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 4.
*/
#define LP_APM_REGION4_R1_W (BIT(5))
#define LP_APM_REGION4_R1_W_M (LP_APM_REGION4_R1_W_V << LP_APM_REGION4_R1_W_S)
#define LP_APM_REGION4_R1_W_V 0x00000001U
#define LP_APM_REGION4_R1_W_S 5
/** LP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 4.
*/
#define LP_APM_REGION4_R1_R (BIT(6))
#define LP_APM_REGION4_R1_R_M (LP_APM_REGION4_R1_R_V << LP_APM_REGION4_R1_R_S)
#define LP_APM_REGION4_R1_R_V 0x00000001U
#define LP_APM_REGION4_R1_R_S 6
/** LP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 4.
*/
#define LP_APM_REGION4_R2_X (BIT(8))
#define LP_APM_REGION4_R2_X_M (LP_APM_REGION4_R2_X_V << LP_APM_REGION4_R2_X_S)
#define LP_APM_REGION4_R2_X_V 0x00000001U
#define LP_APM_REGION4_R2_X_S 8
/** LP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 4.
*/
#define LP_APM_REGION4_R2_W (BIT(9))
#define LP_APM_REGION4_R2_W_M (LP_APM_REGION4_R2_W_V << LP_APM_REGION4_R2_W_S)
#define LP_APM_REGION4_R2_W_V 0x00000001U
#define LP_APM_REGION4_R2_W_S 9
/** LP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 4.
*/
#define LP_APM_REGION4_R2_R (BIT(10))
#define LP_APM_REGION4_R2_R_M (LP_APM_REGION4_R2_R_V << LP_APM_REGION4_R2_R_S)
#define LP_APM_REGION4_R2_R_V 0x00000001U
#define LP_APM_REGION4_R2_R_S 10
/** LP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION4_LOCK (BIT(11))
#define LP_APM_REGION4_LOCK_M (LP_APM_REGION4_LOCK_V << LP_APM_REGION4_LOCK_S)
#define LP_APM_REGION4_LOCK_V 0x00000001U
#define LP_APM_REGION4_LOCK_S 11
/** LP_APM_REGION5_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION5_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x40)
/** LP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 5.
*/
#define LP_APM_REGION5_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION5_ADDR_START_M (LP_APM_REGION5_ADDR_START_V << LP_APM_REGION5_ADDR_START_S)
#define LP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION5_ADDR_START_S 0
/** LP_APM_REGION5_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION5_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x44)
/** LP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 5.
*/
#define LP_APM_REGION5_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION5_ADDR_END_M (LP_APM_REGION5_ADDR_END_V << LP_APM_REGION5_ADDR_END_S)
#define LP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION5_ADDR_END_S 0
/** LP_APM_REGION5_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION5_ATTR_REG (DR_REG_LP_APM_BASE + 0x48)
/** LP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 5.
*/
#define LP_APM_REGION5_R0_X (BIT(0))
#define LP_APM_REGION5_R0_X_M (LP_APM_REGION5_R0_X_V << LP_APM_REGION5_R0_X_S)
#define LP_APM_REGION5_R0_X_V 0x00000001U
#define LP_APM_REGION5_R0_X_S 0
/** LP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 5.
*/
#define LP_APM_REGION5_R0_W (BIT(1))
#define LP_APM_REGION5_R0_W_M (LP_APM_REGION5_R0_W_V << LP_APM_REGION5_R0_W_S)
#define LP_APM_REGION5_R0_W_V 0x00000001U
#define LP_APM_REGION5_R0_W_S 1
/** LP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 5.
*/
#define LP_APM_REGION5_R0_R (BIT(2))
#define LP_APM_REGION5_R0_R_M (LP_APM_REGION5_R0_R_V << LP_APM_REGION5_R0_R_S)
#define LP_APM_REGION5_R0_R_V 0x00000001U
#define LP_APM_REGION5_R0_R_S 2
/** LP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 5.
*/
#define LP_APM_REGION5_R1_X (BIT(4))
#define LP_APM_REGION5_R1_X_M (LP_APM_REGION5_R1_X_V << LP_APM_REGION5_R1_X_S)
#define LP_APM_REGION5_R1_X_V 0x00000001U
#define LP_APM_REGION5_R1_X_S 4
/** LP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 5.
*/
#define LP_APM_REGION5_R1_W (BIT(5))
#define LP_APM_REGION5_R1_W_M (LP_APM_REGION5_R1_W_V << LP_APM_REGION5_R1_W_S)
#define LP_APM_REGION5_R1_W_V 0x00000001U
#define LP_APM_REGION5_R1_W_S 5
/** LP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 5.
*/
#define LP_APM_REGION5_R1_R (BIT(6))
#define LP_APM_REGION5_R1_R_M (LP_APM_REGION5_R1_R_V << LP_APM_REGION5_R1_R_S)
#define LP_APM_REGION5_R1_R_V 0x00000001U
#define LP_APM_REGION5_R1_R_S 6
/** LP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 5.
*/
#define LP_APM_REGION5_R2_X (BIT(8))
#define LP_APM_REGION5_R2_X_M (LP_APM_REGION5_R2_X_V << LP_APM_REGION5_R2_X_S)
#define LP_APM_REGION5_R2_X_V 0x00000001U
#define LP_APM_REGION5_R2_X_S 8
/** LP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 5.
*/
#define LP_APM_REGION5_R2_W (BIT(9))
#define LP_APM_REGION5_R2_W_M (LP_APM_REGION5_R2_W_V << LP_APM_REGION5_R2_W_S)
#define LP_APM_REGION5_R2_W_V 0x00000001U
#define LP_APM_REGION5_R2_W_S 9
/** LP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 5.
*/
#define LP_APM_REGION5_R2_R (BIT(10))
#define LP_APM_REGION5_R2_R_M (LP_APM_REGION5_R2_R_V << LP_APM_REGION5_R2_R_S)
#define LP_APM_REGION5_R2_R_V 0x00000001U
#define LP_APM_REGION5_R2_R_S 10
/** LP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION5_LOCK (BIT(11))
#define LP_APM_REGION5_LOCK_M (LP_APM_REGION5_LOCK_V << LP_APM_REGION5_LOCK_S)
#define LP_APM_REGION5_LOCK_V 0x00000001U
#define LP_APM_REGION5_LOCK_S 11
/** LP_APM_REGION6_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION6_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4c)
/** LP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 6.
*/
#define LP_APM_REGION6_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION6_ADDR_START_M (LP_APM_REGION6_ADDR_START_V << LP_APM_REGION6_ADDR_START_S)
#define LP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION6_ADDR_START_S 0
/** LP_APM_REGION6_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION6_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x50)
/** LP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 6.
*/
#define LP_APM_REGION6_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION6_ADDR_END_M (LP_APM_REGION6_ADDR_END_V << LP_APM_REGION6_ADDR_END_S)
#define LP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION6_ADDR_END_S 0
/** LP_APM_REGION6_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION6_ATTR_REG (DR_REG_LP_APM_BASE + 0x54)
/** LP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 6.
*/
#define LP_APM_REGION6_R0_X (BIT(0))
#define LP_APM_REGION6_R0_X_M (LP_APM_REGION6_R0_X_V << LP_APM_REGION6_R0_X_S)
#define LP_APM_REGION6_R0_X_V 0x00000001U
#define LP_APM_REGION6_R0_X_S 0
/** LP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 6.
*/
#define LP_APM_REGION6_R0_W (BIT(1))
#define LP_APM_REGION6_R0_W_M (LP_APM_REGION6_R0_W_V << LP_APM_REGION6_R0_W_S)
#define LP_APM_REGION6_R0_W_V 0x00000001U
#define LP_APM_REGION6_R0_W_S 1
/** LP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 6.
*/
#define LP_APM_REGION6_R0_R (BIT(2))
#define LP_APM_REGION6_R0_R_M (LP_APM_REGION6_R0_R_V << LP_APM_REGION6_R0_R_S)
#define LP_APM_REGION6_R0_R_V 0x00000001U
#define LP_APM_REGION6_R0_R_S 2
/** LP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 6.
*/
#define LP_APM_REGION6_R1_X (BIT(4))
#define LP_APM_REGION6_R1_X_M (LP_APM_REGION6_R1_X_V << LP_APM_REGION6_R1_X_S)
#define LP_APM_REGION6_R1_X_V 0x00000001U
#define LP_APM_REGION6_R1_X_S 4
/** LP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 6.
*/
#define LP_APM_REGION6_R1_W (BIT(5))
#define LP_APM_REGION6_R1_W_M (LP_APM_REGION6_R1_W_V << LP_APM_REGION6_R1_W_S)
#define LP_APM_REGION6_R1_W_V 0x00000001U
#define LP_APM_REGION6_R1_W_S 5
/** LP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 6.
*/
#define LP_APM_REGION6_R1_R (BIT(6))
#define LP_APM_REGION6_R1_R_M (LP_APM_REGION6_R1_R_V << LP_APM_REGION6_R1_R_S)
#define LP_APM_REGION6_R1_R_V 0x00000001U
#define LP_APM_REGION6_R1_R_S 6
/** LP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 6.
*/
#define LP_APM_REGION6_R2_X (BIT(8))
#define LP_APM_REGION6_R2_X_M (LP_APM_REGION6_R2_X_V << LP_APM_REGION6_R2_X_S)
#define LP_APM_REGION6_R2_X_V 0x00000001U
#define LP_APM_REGION6_R2_X_S 8
/** LP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 6.
*/
#define LP_APM_REGION6_R2_W (BIT(9))
#define LP_APM_REGION6_R2_W_M (LP_APM_REGION6_R2_W_V << LP_APM_REGION6_R2_W_S)
#define LP_APM_REGION6_R2_W_V 0x00000001U
#define LP_APM_REGION6_R2_W_S 9
/** LP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 6.
*/
#define LP_APM_REGION6_R2_R (BIT(10))
#define LP_APM_REGION6_R2_R_M (LP_APM_REGION6_R2_R_V << LP_APM_REGION6_R2_R_S)
#define LP_APM_REGION6_R2_R_V 0x00000001U
#define LP_APM_REGION6_R2_R_S 10
/** LP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION6_LOCK (BIT(11))
#define LP_APM_REGION6_LOCK_M (LP_APM_REGION6_LOCK_V << LP_APM_REGION6_LOCK_S)
#define LP_APM_REGION6_LOCK_V 0x00000001U
#define LP_APM_REGION6_LOCK_S 11
/** LP_APM_REGION7_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION7_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x58)
/** LP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 7.
*/
#define LP_APM_REGION7_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION7_ADDR_START_M (LP_APM_REGION7_ADDR_START_V << LP_APM_REGION7_ADDR_START_S)
#define LP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION7_ADDR_START_S 0
/** LP_APM_REGION7_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION7_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x5c)
/** LP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 7.
*/
#define LP_APM_REGION7_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION7_ADDR_END_M (LP_APM_REGION7_ADDR_END_V << LP_APM_REGION7_ADDR_END_S)
#define LP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION7_ADDR_END_S 0
/** LP_APM_REGION7_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION7_ATTR_REG (DR_REG_LP_APM_BASE + 0x60)
/** LP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 7.
*/
#define LP_APM_REGION7_R0_X (BIT(0))
#define LP_APM_REGION7_R0_X_M (LP_APM_REGION7_R0_X_V << LP_APM_REGION7_R0_X_S)
#define LP_APM_REGION7_R0_X_V 0x00000001U
#define LP_APM_REGION7_R0_X_S 0
/** LP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 7.
*/
#define LP_APM_REGION7_R0_W (BIT(1))
#define LP_APM_REGION7_R0_W_M (LP_APM_REGION7_R0_W_V << LP_APM_REGION7_R0_W_S)
#define LP_APM_REGION7_R0_W_V 0x00000001U
#define LP_APM_REGION7_R0_W_S 1
/** LP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 7.
*/
#define LP_APM_REGION7_R0_R (BIT(2))
#define LP_APM_REGION7_R0_R_M (LP_APM_REGION7_R0_R_V << LP_APM_REGION7_R0_R_S)
#define LP_APM_REGION7_R0_R_V 0x00000001U
#define LP_APM_REGION7_R0_R_S 2
/** LP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 7.
*/
#define LP_APM_REGION7_R1_X (BIT(4))
#define LP_APM_REGION7_R1_X_M (LP_APM_REGION7_R1_X_V << LP_APM_REGION7_R1_X_S)
#define LP_APM_REGION7_R1_X_V 0x00000001U
#define LP_APM_REGION7_R1_X_S 4
/** LP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 7.
*/
#define LP_APM_REGION7_R1_W (BIT(5))
#define LP_APM_REGION7_R1_W_M (LP_APM_REGION7_R1_W_V << LP_APM_REGION7_R1_W_S)
#define LP_APM_REGION7_R1_W_V 0x00000001U
#define LP_APM_REGION7_R1_W_S 5
/** LP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 7.
*/
#define LP_APM_REGION7_R1_R (BIT(6))
#define LP_APM_REGION7_R1_R_M (LP_APM_REGION7_R1_R_V << LP_APM_REGION7_R1_R_S)
#define LP_APM_REGION7_R1_R_V 0x00000001U
#define LP_APM_REGION7_R1_R_S 6
/** LP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 7.
*/
#define LP_APM_REGION7_R2_X (BIT(8))
#define LP_APM_REGION7_R2_X_M (LP_APM_REGION7_R2_X_V << LP_APM_REGION7_R2_X_S)
#define LP_APM_REGION7_R2_X_V 0x00000001U
#define LP_APM_REGION7_R2_X_S 8
/** LP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 7.
*/
#define LP_APM_REGION7_R2_W (BIT(9))
#define LP_APM_REGION7_R2_W_M (LP_APM_REGION7_R2_W_V << LP_APM_REGION7_R2_W_S)
#define LP_APM_REGION7_R2_W_V 0x00000001U
#define LP_APM_REGION7_R2_W_S 9
/** LP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 7.
*/
#define LP_APM_REGION7_R2_R (BIT(10))
#define LP_APM_REGION7_R2_R_M (LP_APM_REGION7_R2_R_V << LP_APM_REGION7_R2_R_S)
#define LP_APM_REGION7_R2_R_V 0x00000001U
#define LP_APM_REGION7_R2_R_S 10
/** LP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION7_LOCK (BIT(11))
#define LP_APM_REGION7_LOCK_M (LP_APM_REGION7_LOCK_V << LP_APM_REGION7_LOCK_S)
#define LP_APM_REGION7_LOCK_V 0x00000001U
#define LP_APM_REGION7_LOCK_S 11
/** LP_APM_FUNC_CTRL_REG register
* APM function control register
*/
@@ -445,9 +841,9 @@ extern "C" {
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
@@ -470,12 +866,12 @@ extern "C" {
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION 0x000000FFU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_V 0x000000FFU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
@@ -509,9 +905,9 @@ extern "C" {
*/
#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
@@ -534,12 +930,12 @@ extern "C" {
* M1 exception_info0 register
*/
#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION 0x000000FFU
#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_V 0x000000FFU
#define LP_APM_M1_EXCEPTION_REGION_S 0
/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
@@ -573,18 +969,18 @@ extern "C" {
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
#define LP_APM_M1_APM_INT_EN (BIT(1))
#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
@@ -596,9 +992,9 @@ extern "C" {
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)

70
components/soc/esp32c5/register/soc/lp_apm_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,13 +16,13 @@ extern "C" {
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n (0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
@@ -137,9 +137,9 @@ typedef union {
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
@@ -170,11 +170,11 @@ typedef union {
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
/** m0_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
uint32_t m0_exception_region:8;
uint32_t reserved_8:8;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
@@ -211,9 +211,9 @@ typedef union {
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
@@ -244,11 +244,11 @@ typedef union {
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [3:0]; default: 0;
/** m1_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:4;
uint32_t reserved_4:12;
uint32_t m1_exception_region:8;
uint32_t reserved_8:8;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
@@ -285,15 +285,15 @@ typedef union {
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
@@ -309,9 +309,9 @@ typedef union {
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@@ -350,7 +350,19 @@ typedef struct {
volatile lp_apm_regionn_addr_start_reg_t region3_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region3_addr_end;
volatile lp_apm_regionn_attr_reg_t region3_attr;
uint32_t reserved_034[36];
volatile lp_apm_regionn_addr_start_reg_t region4_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region4_addr_end;
volatile lp_apm_regionn_attr_reg_t region4_attr;
volatile lp_apm_regionn_addr_start_reg_t region5_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region5_addr_end;
volatile lp_apm_regionn_attr_reg_t region5_attr;
volatile lp_apm_regionn_addr_start_reg_t region6_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region6_addr_end;
volatile lp_apm_regionn_attr_reg_t region6_attr;
volatile lp_apm_regionn_addr_start_reg_t region7_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region7_addr_end;
volatile lp_apm_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;

1211
components/soc/esp32c5/register/soc/lp_tee_reg.h
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File diff suppressed because it is too large Load Diff

956
components/soc/esp32c5/register/soc/lp_tee_struct.h
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File diff suppressed because it is too large Load Diff

156
components/soc/esp32c5/register/soc/lp_wdt_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,6 +17,7 @@ extern "C" {
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
/** LP_WDT_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FFU
#define LP_WDT_WDT_CHIP_RESET_WIDTH_M (LP_WDT_WDT_CHIP_RESET_WIDTH_V << LP_WDT_WDT_CHIP_RESET_WIDTH_S)
@@ -24,21 +25,26 @@ extern "C" {
#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 0
/** LP_WDT_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_WDT_WDT_CHIP_RESET_EN (BIT(8))
#define LP_WDT_WDT_CHIP_RESET_EN_M (LP_WDT_WDT_CHIP_RESET_EN_V << LP_WDT_WDT_CHIP_RESET_EN_S)
#define LP_WDT_WDT_CHIP_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_CHIP_RESET_EN_S 8
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
* Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable
* \\1:Disable
* Configure whether or not pause RWDT when chip is in sleep mode.
* 0:Enable
* 1:Disable
*/
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
* Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable
* Configure whether or not to enable RWDT to reset CPU.
* 0:Disable
* 1:Enable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
@@ -46,67 +52,89 @@ extern "C" {
#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
* Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable
* \\1:Enable
* Configure whether or not enable RWDT when chip is in SPI boot mode.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
* Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
* Configure the HP core reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
* Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
* Configure the HP CPU reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
* Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage3.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG3 0x00000007U
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
#define LP_WDT_WDT_STG3_V 0x00000007U
#define LP_WDT_WDT_STG3_S 19
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
* Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage2.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG2 0x00000007U
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
#define LP_WDT_WDT_STG2_V 0x00000007U
#define LP_WDT_WDT_STG2_S 22
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
* Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage1.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG1 0x00000007U
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
#define LP_WDT_WDT_STG1_V 0x00000007U
#define LP_WDT_WDT_STG1_S 25
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
* Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage0.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG0 0x00000007U
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
#define LP_WDT_WDT_STG0_V 0x00000007U
#define LP_WDT_WDT_STG0_S 28
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable RWDT.\\0:Disable \\1:Enable
* Configure whether or not to enable RWDT.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_WDT_EN (BIT(31))
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
@@ -118,7 +146,8 @@ extern "C" {
*/
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
* Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage0.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
@@ -130,7 +159,8 @@ extern "C" {
*/
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
* Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage1.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
@@ -142,7 +172,8 @@ extern "C" {
*/
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage2.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
@@ -154,7 +185,8 @@ extern "C" {
*/
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage3.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
@@ -166,7 +198,9 @@ extern "C" {
*/
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT
* Configure this bit to feed the RWDT.
* 0: Invalid
* 1: Feed RWDT
*/
#define LP_WDT_RTC_WDT_FEED (BIT(31))
#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
@@ -178,9 +212,10 @@ extern "C" {
*/
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
* Configure this field to lock or unlock RWDT`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
@@ -192,44 +227,53 @@ extern "C" {
*/
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
* Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes
* Represents the SWD whether has generated the reset signal.
* 0 :No
* 1: Yes
*/
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
#define LP_WDT_SWD_RESET_FLAG_S 0
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
* Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable
* \\1: Enable
* Configure this bit to enable to feed SWD automatically by hardware.
* 0: Disable
* 1: Enable
*/
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
* Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag
* Configure this bit to clear SWD reset flag.
* 0:Invalid
* 1: Clear the reset flag
*/
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
* Configure the SWD signal length that output to analog circuit. \\ Measurement unit:
* LP\_DYN\_FAST\_CLK
* Configure the SWD signal length that output to analog circuit.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
* Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD
* Configure this bit to disable the SWD.
* 0: Enable the SWD
* 1: Disable the SWD
*/
#define LP_WDT_SWD_DISABLE (BIT(30))
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
#define LP_WDT_SWD_DISABLE_V 0x00000001U
#define LP_WDT_SWD_DISABLE_S 30
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD
* Configure this bit to feed the SWD.
* 0: Invalid
* 1: Feed SWD
*/
#define LP_WDT_SWD_FEED (BIT(31))
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
@@ -241,9 +285,10 @@ extern "C" {
*/
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
* Configure this field to lock or unlock SWD`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
@@ -255,14 +300,18 @@ extern "C" {
*/
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes
* Represents the SWD whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes
* Represents the RWDT whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
@@ -274,16 +323,18 @@ extern "C" {
*/
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
* Represents the SWD whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
* Represents the SWD whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ST_S 30
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
* Represents the RWDT whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
* Represents the RWDT whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
@@ -295,16 +346,18 @@ extern "C" {
*/
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
* Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable
* \\1:Enable
* Configure whether or not to enable the SWD to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable
* \\1:Enable
* Configure whether or not to enable the RWDT to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
@@ -316,16 +369,18 @@ extern "C" {
*/
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0:
* No\\1: Yes
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.
* 0: No
* 1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0:
* No\\1: Yes
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.
* 0: No
* 1: Yes
*/
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
@@ -345,6 +400,7 @@ extern "C" {
#define LP_WDT_LP_WDT_DATE_S 0
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_WDT_CLK_EN (BIT(31))
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)

156
components/soc/esp32c5/register/soc/lp_wdt_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,60 +18,88 @@ typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wdt_chip_reset_en:1;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
* Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable
* \\1:Disable
* Configure whether or not pause RWDT when chip is in sleep mode.
* 0:Enable
* 1:Disable
*/
uint32_t wdt_pause_in_slp:1;
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
* Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable
* Configure whether or not to enable RWDT to reset CPU.
* 0:Disable
* 1:Enable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
* Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable
* \\1:Enable
* Configure whether or not enable RWDT when chip is in SPI boot mode.
* 0:Disable
* 1:Enable
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
* Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
* Configure the HP core reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
* Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
* Configure the HP CPU reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
* Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage3.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg3:3;
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
* Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage2.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg2:3;
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
* Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage1.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg1:3;
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
* Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
* Configure the timeout action of stage0.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg0:3;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable RWDT.\\0:Disable \\1:Enable
* Configure whether or not to enable RWDT.
* 0:Disable
* 1:Enable
*/
uint32_t wdt_en:1;
};
@@ -84,7 +112,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
* Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage0.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg0_hold:32;
};
@@ -97,7 +126,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
* Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage1.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg1_hold:32;
};
@@ -110,7 +140,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage2.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg2_hold:32;
};
@@ -123,7 +154,8 @@ typedef union {
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK
* Configure the timeout time for stage3.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg3_hold:32;
};
@@ -137,7 +169,9 @@ typedef union {
struct {
uint32_t reserved_0:31;
/** rtc_wdt_feed : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT
* Configure this bit to feed the RWDT.
* 0: Invalid
* 1: Feed RWDT
*/
uint32_t rtc_wdt_feed:1;
};
@@ -150,9 +184,10 @@ typedef union {
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
* Configure this field to lock or unlock RWDT`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
uint32_t wdt_wkey:32;
};
@@ -165,30 +200,39 @@ typedef union {
typedef union {
struct {
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
* Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes
* Represents the SWD whether has generated the reset signal.
* 0 :No
* 1: Yes
*/
uint32_t swd_reset_flag:1;
uint32_t reserved_1:17;
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
* Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable
* \\1: Enable
* Configure this bit to enable to feed SWD automatically by hardware.
* 0: Disable
* 1: Enable
*/
uint32_t swd_auto_feed_en:1;
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
* Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag
* Configure this bit to clear SWD reset flag.
* 0:Invalid
* 1: Clear the reset flag
*/
uint32_t swd_rst_flag_clr:1;
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
* Configure the SWD signal length that output to analog circuit. \\ Measurement unit:
* LP\_DYN\_FAST\_CLK
* Configure the SWD signal length that output to analog circuit.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t swd_signal_width:10;
/** swd_disable : R/W; bitpos: [30]; default: 0;
* Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD
* Configure this bit to disable the SWD.
* 0: Enable the SWD
* 1: Disable the SWD
*/
uint32_t swd_disable:1;
/** swd_feed : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD
* Configure this bit to feed the SWD.
* 0: Invalid
* 1: Feed SWD
*/
uint32_t swd_feed:1;
};
@@ -201,9 +245,10 @@ typedef union {
typedef union {
struct {
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
* Configure this field to lock or unlock SWD`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
uint32_t swd_wkey:32;
};
@@ -217,11 +262,15 @@ typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes
* Represents the SWD whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
uint32_t super_wdt_int_raw:1;
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes
* Represents the RWDT whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
uint32_t lp_wdt_int_raw:1;
};
@@ -235,13 +284,15 @@ typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
* Represents the SWD whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
* Represents the SWD whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
uint32_t super_wdt_int_st:1;
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
* Represents the RWDT whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
* Represents the RWDT whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
uint32_t lp_wdt_int_st:1;
};
@@ -255,13 +306,15 @@ typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
* Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable
* \\1:Enable
* Configure whether or not to enable the SWD to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
uint32_t super_wdt_int_ena:1;
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable
* \\1:Enable
* Configure whether or not to enable the RWDT to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
uint32_t lp_wdt_int_ena:1;
};
@@ -275,13 +328,15 @@ typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0:
* No\\1: Yes
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.
* 0: No
* 1: Yes
*/
uint32_t super_wdt_int_clr:1;
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0:
* No\\1: Yes
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.
* 0: No
* 1: Yes
*/
uint32_t lp_wdt_int_clr:1;
};
@@ -299,6 +354,7 @@ typedef union {
uint32_t lp_wdt_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t clk_en:1;
};

135
components/soc/esp32c5/register/soc/mem_monitor_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,26 +16,26 @@ extern "C" {
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[1]: Configures word monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[2]: Configures halfword monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[3]: Configures byte monitoring. \\
* 0: Disable \\
* 1: Enable\\
* Configures monitoring modes.bit[0]: Configures write monitoring.
* 0: Disable
* 1: Enable
* bit[1]: Configures word monitoring.
* 0: Disable
* 1: Enable
* bit[2]: Configures halfword monitoring.
* 0: Disable
* 1: Enable
* bit[3]: Configures byte monitoring.
* 0: Disable
* 1: Enable
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 0
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
* Configures the writing mode for recorded data.1: Loop mode\\
* 0: Non-loop mode\\
* Configures the writing mode for recorded data.1: Loop mode
* 0: Non-loop mode
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
@@ -43,9 +43,9 @@ extern "C" {
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
* enable HP CPU bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* enable HP CPU bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
@@ -54,9 +54,9 @@ extern "C" {
#define MEM_MONITOR_LOG_CORE_ENA_S 8
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
* to enable DMA_0 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_0 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
@@ -65,9 +65,9 @@ extern "C" {
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
* to enable DMA_1 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_1 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
@@ -81,9 +81,9 @@ extern "C" {
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
* to enable DMA_2 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_2 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
@@ -92,9 +92,9 @@ extern "C" {
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
* to enable DMA_3 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_3 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
@@ -121,21 +121,21 @@ extern "C" {
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
* Configures whether to mask the least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[1]: Configures whether to mask the second least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[2]: Configures whether to mask the second most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[3]: Configures whether to mask the most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
@@ -174,9 +174,9 @@ extern "C" {
/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the HP CPU bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the HP CPU bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S)
@@ -184,8 +184,8 @@ extern "C" {
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0
/** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0;
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
* 0: Not update\\
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update
* 0: Not update
*/
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31))
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S)
@@ -200,9 +200,9 @@ extern "C" {
/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_0 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_0 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S)
@@ -211,9 +211,9 @@ extern "C" {
/** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_1 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_1 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S)
@@ -222,9 +222,9 @@ extern "C" {
/** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_2 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_2 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S)
@@ -233,9 +233,9 @@ extern "C" {
/** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_3 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_3 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S)
@@ -285,8 +285,8 @@ extern "C" {
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
* 0: Not update (default) \\
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update
* 0: Not update (default)
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
@@ -298,17 +298,16 @@ extern "C" {
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* Represents whether data overflows the storage space.0: Not Overflow\\
* 1: Overflow\\
* Represents whether data overflows the storage space.0: Not Overflow
* 1: Overflow
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
* clear\\
* 1: Clear\\
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not clear
* 1: Clear
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
@@ -320,8 +319,8 @@ extern "C" {
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the register clock gating.0: Disable\\
* 1: Enable\\
* Configures whether to enable the register clock gating.0: Disable
* 1: Enable
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)

135
components/soc/esp32c5/register/soc/mem_monitor_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,47 +17,47 @@ extern "C" {
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[1]: Configures word monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[2]: Configures halfword monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[3]: Configures byte monitoring. \\
* 0: Disable \\
* 1: Enable\\
* Configures monitoring modes.bit[0]: Configures write monitoring.
* 0: Disable
* 1: Enable
* bit[1]: Configures word monitoring.
* 0: Disable
* 1: Enable
* bit[2]: Configures halfword monitoring.
* 0: Disable
* 1: Enable
* bit[3]: Configures byte monitoring.
* 0: Disable
* 1: Enable
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
* Configures the writing mode for recorded data.1: Loop mode\\
* 0: Non-loop mode\\
* Configures the writing mode for recorded data.1: Loop mode
* 0: Non-loop mode
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_5:3;
/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
* enable HP CPU bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* enable HP CPU bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t log_core_ena:8;
/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
* to enable DMA_0 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_0 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t log_dma_0_ena:8;
/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
* to enable DMA_1 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_1 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t log_dma_1_ena:8;
@@ -72,17 +72,17 @@ typedef union {
struct {
/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
* to enable DMA_2 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_2 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t log_dma_2_ena:8;
/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
* to enable DMA_3 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* to enable DMA_3 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t log_dma_3_ena:8;
@@ -112,21 +112,21 @@ typedef union {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
* Configures whether to mask the least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[1]: Configures whether to mask the second least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[2]: Configures whether to mask the second most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[3]: Configures whether to mask the most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
@@ -169,16 +169,16 @@ typedef union {
/** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the HP CPU bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the HP CPU bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t log_mon_addr_core_update:8;
uint32_t reserved_8:23;
/** log_mon_addr_all_update : WT; bitpos: [31]; default: 0;
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
* 0: Not update\\
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update
* 0: Not update
*/
uint32_t log_mon_addr_all_update:1;
};
@@ -194,33 +194,33 @@ typedef union {
/** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_0 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_0 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t log_mon_addr_dma_0_update:8;
/** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_1 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_1 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t log_mon_addr_dma_1_update:8;
/** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_2 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_2 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t log_mon_addr_dma_2_update:8;
/** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_3 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
* monitored address space of the DMA_3 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t log_mon_addr_dma_3_update:8;
};
@@ -274,8 +274,8 @@ typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
* 0: Not update (default) \\
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update
* 0: Not update (default)
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
@@ -289,14 +289,13 @@ typedef union {
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* Represents whether data overflows the storage space.0: Not Overflow\\
* 1: Overflow\\
* Represents whether data overflows the storage space.0: Not Overflow
* 1: Overflow
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
* clear\\
* 1: Clear\\
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not clear
* 1: Clear
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
@@ -312,8 +311,8 @@ typedef union {
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the register clock gating.0: Disable\\
* 1: Enable\\
* Configures whether to enable the register clock gating.0: Disable
* 1: Enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;

23
components/soc/esp32c5/register/soc/parl_io_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -447,6 +447,25 @@ extern "C" {
#define PARL_IO_TX_CLK_O_INV_V 0x00000001U
#define PARL_IO_TX_CLK_O_INV_S 31
/** PARL_IO_TX_CS_CFG_REG register
* Parallel IO tx_cs_o generate configuration
*/
#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c)
/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0;
* configure the delay between data tx end and tx_cs_o posedge
*/
#define PARL_IO_TX_CS_STOP_DELAY 0x0000FFFFU
#define PARL_IO_TX_CS_STOP_DELAY_M (PARL_IO_TX_CS_STOP_DELAY_V << PARL_IO_TX_CS_STOP_DELAY_S)
#define PARL_IO_TX_CS_STOP_DELAY_V 0x0000FFFFU
#define PARL_IO_TX_CS_STOP_DELAY_S 0
/** PARL_IO_TX_CS_START_DELAY : R/W; bitpos: [31:16]; default: 0;
* configure the delay between tx_cs_o negedge and data tx start
*/
#define PARL_IO_TX_CS_START_DELAY 0x0000FFFFU
#define PARL_IO_TX_CS_START_DELAY_M (PARL_IO_TX_CS_START_DELAY_V << PARL_IO_TX_CS_START_DELAY_S)
#define PARL_IO_TX_CS_START_DELAY_V 0x0000FFFFU
#define PARL_IO_TX_CS_START_DELAY_S 16
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
@@ -463,7 +482,7 @@ extern "C" {
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160;
* Version of this register file
*/
#define PARL_IO_DATE 0x0FFFFFFFU

26
components/soc/esp32c5/register/soc/parl_io_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -436,6 +436,25 @@ typedef union {
} parl_io_tx_clk_cfg_reg_t;
/** Group: PARL_TX_CS Configuration */
/** Type of tx_cs_cfg register
* Parallel IO tx_cs_o generate configuration
*/
typedef union {
struct {
/** tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0;
* configure the delay between data tx end and tx_cs_o posedge
*/
uint32_t tx_cs_stop_delay:16;
/** tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0;
* configure the delay between tx_cs_o negedge and data tx start
*/
uint32_t tx_cs_start_delay:16;
};
uint32_t val;
} parl_io_tx_cs_cfg_reg_t;
/** Group: PARL_IO Clock Configuration */
/** Type of clk register
* Parallel IO clk configuration register
@@ -458,7 +477,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725920;
/** date : R/W; bitpos: [27:0]; default: 37786160;
* Version of this register file
*/
uint32_t date:28;
@@ -488,7 +507,8 @@ typedef struct parl_io_dev_t {
volatile parl_io_tx_st0_reg_t tx_st0;
volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
uint32_t reserved_04c[53];
volatile parl_io_tx_cs_cfg_reg_t tx_cs_cfg;
uint32_t reserved_050[52];
volatile parl_io_clk_reg_t clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t version;

1446
components/soc/esp32c5/register/soc/pcnt_reg_eco2.h Normal file
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523
components/soc/esp32c5/register/soc/pcnt_struct_eco2.h Normal file
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@@ -0,0 +1,523 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* Configures the maximum threshold for the filter. Any pulses with width less than
* this will be ignored when the filter is enabled.
* Measurement unit: APB_CLK cycles.
*/
uint32_t filter_thres_un:10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un:1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un:1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
* the high limit interrupt.
*/
uint32_t thr_h_lim_en_un:1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
* the low limit interrupt.
*/
uint32_t thr_l_lim_en_un:1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un:1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un:1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a negative edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch0_neg_mode_un:2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a positive edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch0_pos_mode_un:2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode_un:2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode_un:2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a negative edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch1_neg_mode_un:2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a positive edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch1_pos_mode_un:2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode_un:2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode_un:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thres0 value for unit n.
*/
uint32_t cnt_thres0_un:16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thres1 value for unit n.
*/
uint32_t cnt_thres1_un:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thr_h_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_h_lim_un:16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thr_l_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_l_lim_un:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of u0_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 0.
*/
uint32_t cnt_h_step_u0:16;
/** cnt_l_step_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 0.
*/
uint32_t cnt_l_step_u0:16;
};
uint32_t val;
} pcnt_u0_conf3_reg_t;
/** Type of u1_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 1.
*/
uint32_t cnt_h_step_u1:16;
/** cnt_l_step_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 1.
*/
uint32_t cnt_l_step_u1:16;
};
uint32_t val;
} pcnt_u1_conf3_reg_t;
/** Type of u2_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 2.
*/
uint32_t cnt_h_step_u2:16;
/** cnt_l_step_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 2.
*/
uint32_t cnt_l_step_u2:16;
};
uint32_t val;
} pcnt_u2_conf3_reg_t;
/** Type of u3_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 3.
*/
uint32_t cnt_h_step_u3:16;
/** cnt_l_step_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 3.
*/
uint32_t cnt_l_step_u3:16;
};
uint32_t val;
} pcnt_u3_conf3_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
/** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
* Configures this bit to enable unit 0's step comparator.
*/
uint32_t dalta_change_en_u0:1;
/** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
* Configures this bit to enable unit 1's step comparator.
*/
uint32_t dalta_change_en_u1:1;
/** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
* Configures this bit to enable unit 2's step comparator.
*/
uint32_t dalta_change_en_u2:1;
/** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
* Configures this bit to enable unit 3's step comparator.
*/
uint32_t dalta_change_en_u3:1;
uint32_t reserved_12:4;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* Represents the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* Represents the pulse counter status of PCNT_Un corresponding to 0.
* 0: pulse counter decreases from positive to 0
* 1: pulse counter increases from negative to 0
* 2: pulse counter is negative
* 3: pulse counter is positive
*/
uint32_t cnt_thr_zero_mode_un:2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* Represents the latched value of thres1 event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thres1 and thres1 event is valid
*/
uint32_t cnt_thr_thres1_lat_un:1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* Represents the latched value of thres0 event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thres0 and thres0 event is valid
*/
uint32_t cnt_thr_thres0_lat_un:1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* Represents the latched value of low limit event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thr_l_lim and low limit event is valid.
*/
uint32_t cnt_thr_l_lim_lat_un:1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* Represents the latched value of high limit event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thr_h_lim and high limit event is valid.
*/
uint32_t cnt_thr_h_lim_lat_un:1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* Represents the latched value of zero threshold event of PCNT_Un when threshold
* event interrupt is valid.
* 0: others
* 1: the current pulse counter equals to 0 and zero threshold event is valid.
*/
uint32_t cnt_thr_zero_lat_un:1;
/** cnt_thr_h_step_lat_un : RO; bitpos: [7]; default: 0;
* Represents the latched value of step counter event of PCNT_Un when step counter
* event interrupt is valid. 1: the current pulse counter decrement equals to
* reg_cnt_step and step counter event is valid. 0: others
*/
uint32_t cnt_thr_h_step_lat_un:1;
/** cnt_thr_l_step_lat_un : RO; bitpos: [8]; default: 0;
* Represents the latched value of step counter event of PCNT_Un when step counter
* event interrupt is valid. 1: the current pulse counter increment equals to
* reg_cnt_step and step counter event is valid. 0: others
*/
uint32_t cnt_thr_l_step_lat_un:1;
uint32_t reserved_9:23;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 37778192;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_u0_conf3_reg_t u0_conf3;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_u1_conf3_reg_t u1_conf3;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_u2_conf3_reg_t u2_conf3;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_u3_conf3_reg_t u3_conf3;
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

8
components/soc/esp32c5/register/soc/reg_base.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,6 +32,9 @@
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM_BASE 0x60014000
#define DR_REG_PARL_IO_BASE 0x60015000
#define DR_REG_HINF_BASE 0x60016000
#define DR_REG_SLC_BASE 0x60017000
#define DR_REG_SLC_HOST_BASE 0x60018000
#define DR_REG_PVT_MONITOR_BASE 0x60019000
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
@@ -65,6 +68,7 @@
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_LP_APM0_BASE 0x60099800
#define DR_REG_CPU_APM_BASE 0x6009A000
#define DR_REG_MISC_BASE 0x6009F000
/**
@@ -107,7 +111,7 @@
*
*/
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_BUS_MONITOR_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM
#define DR_REG_CLINT_M_BASE 0x20000000

44
components/soc/esp32c5/register/soc/rsa_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -64,9 +64,9 @@ extern "C" {
*/
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.\\
* 0: Not complete\\
* 1: Completed\\
* Represents whether or not the RSA memory completes initialization.
* 0: Not complete
* 1: Completed
*/
#define RSA_QUERY_CLEAN (BIT(0))
#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
@@ -78,9 +78,9 @@ extern "C" {
*/
#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
* Configures whether or not to starts the modular exponentiation. \\
* 0: No effect\\
* 1: Start\\
* Configures whether or not to starts the modular exponentiation.
* 0: No effect
* 1: Start
*/
#define RSA_SET_START_MODEXP (BIT(0))
#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
@@ -92,9 +92,9 @@ extern "C" {
*/
#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the modular multiplication.\\
* 0: No effect\\
* 1: Start\\
* Configures whether or not to start the modular multiplication.
* 0: No effect
* 1: Start
*/
#define RSA_SET_START_MODMULT (BIT(0))
#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
@@ -106,9 +106,9 @@ extern "C" {
*/
#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the multiplication.\\
* 0: No effect\\
* 1: Start\\
* Configures whether or not to start the multiplication.
* 0: No effect
* 1: Start
*/
#define RSA_SET_START_MULT (BIT(0))
#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
@@ -120,9 +120,9 @@ extern "C" {
*/
#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
* Represents the RSA status.\\
* 0: Busy\\
* 1: Idle\\
* Represents the RSA status.
* 0: Busy
* 1: Idle
*/
#define RSA_QUERY_IDLE (BIT(0))
#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
@@ -146,9 +146,9 @@ extern "C" {
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option. \\
* 0: Acceleration\\
* 1: No acceleration (default)\\
* Configures the constant_time option.
* 0: Acceleration
* 1: No acceleration (default)
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
@@ -160,9 +160,9 @@ extern "C" {
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the search option. \\
* 0: No acceleration (default)\\
* 1: Acceleration\\
* Configures the search option.
* 0: No acceleration (default)
* 1: Acceleration
* This option should be used together with RSA_SEARCH_POS_REG.
*/
#define RSA_SEARCH_ENABLE (BIT(0))

44
components/soc/esp32c5/register/soc/rsa_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -46,9 +46,9 @@ typedef union {
typedef union {
struct {
/** set_start_modexp : WT; bitpos: [0]; default: 0;
* Configures whether or not to starts the modular exponentiation. \\
* 0: No effect\\
* 1: Start\\
* Configures whether or not to starts the modular exponentiation.
* 0: No effect
* 1: Start
*/
uint32_t set_start_modexp:1;
uint32_t reserved_1:31;
@@ -62,9 +62,9 @@ typedef union {
typedef union {
struct {
/** set_start_modmult : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the modular multiplication.\\
* 0: No effect\\
* 1: Start\\
* Configures whether or not to start the modular multiplication.
* 0: No effect
* 1: Start
*/
uint32_t set_start_modmult:1;
uint32_t reserved_1:31;
@@ -78,9 +78,9 @@ typedef union {
typedef union {
struct {
/** set_start_mult : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the multiplication.\\
* 0: No effect\\
* 1: Start\\
* Configures whether or not to start the multiplication.
* 0: No effect
* 1: Start
*/
uint32_t set_start_mult:1;
uint32_t reserved_1:31;
@@ -94,9 +94,9 @@ typedef union {
typedef union {
struct {
/** query_idle : RO; bitpos: [0]; default: 0;
* Represents the RSA status.\\
* 0: Busy\\
* 1: Idle\\
* Represents the RSA status.
* 0: Busy
* 1: Idle
*/
uint32_t query_idle:1;
uint32_t reserved_1:31;
@@ -110,9 +110,9 @@ typedef union {
typedef union {
struct {
/** constant_time : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option. \\
* 0: Acceleration\\
* 1: No acceleration (default)\\
* Configures the constant_time option.
* 0: Acceleration
* 1: No acceleration (default)
*/
uint32_t constant_time:1;
uint32_t reserved_1:31;
@@ -126,9 +126,9 @@ typedef union {
typedef union {
struct {
/** search_enable : R/W; bitpos: [0]; default: 0;
* Configures the search option. \\
* 0: No acceleration (default)\\
* 1: Acceleration\\
* Configures the search option.
* 0: No acceleration (default)
* 1: Acceleration
* This option should be used together with RSA_SEARCH_POS_REG.
*/
uint32_t search_enable:1;
@@ -160,9 +160,9 @@ typedef union {
typedef union {
struct {
/** query_clean : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.\\
* 0: Not complete\\
* 1: Completed\\
* Represents whether or not the RSA memory completes initialization.
* 0: Not complete
* 1: Completed
*/
uint32_t query_clean:1;
uint32_t reserved_1:31;

576
components/soc/esp32c5/register/soc/sdio_hinf_reg.h Normal file
View File

@@ -0,0 +1,576 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HINF_CFG_DATA0_REG register
* Configure sdio cis content
*/
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
#define HINF_DEVICE_ID_FN1 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_S 0
/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
#define HINF_USER_ID_FN1 0x0000FFFFU
#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
#define HINF_USER_ID_FN1_V 0x0000FFFFU
#define HINF_USER_ID_FN1_S 16
/** HINF_CFG_DATA1_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
#define HINF_SDIO_ENABLE_V 0x00000001U
#define HINF_SDIO_ENABLE_S 0
/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
#define HINF_SDIO_IOREADY1_V 0x00000001U
#define HINF_SDIO_IOREADY1_S 1
/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
#define HINF_HIGHSPEED_ENABLE_V 0x00000001U
#define HINF_HIGHSPEED_ENABLE_S 2
/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
#define HINF_HIGHSPEED_MODE_V 0x00000001U
#define HINF_HIGHSPEED_MODE_S 3
/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
#define HINF_SDIO_CD_ENABLE_V 0x00000001U
#define HINF_SDIO_CD_ENABLE_S 4
/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
#define HINF_SDIO_IOREADY2_V 0x00000001U
#define HINF_SDIO_IOREADY2_S 5
/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
#define HINF_SDIO_INT_MASK_V 0x00000001U
#define HINF_SDIO_INT_MASK_S 6
/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
#define HINF_IOENABLE2_V 0x00000001U
#define HINF_IOENABLE2_S 7
/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
#define HINF_CD_DISABLE_V 0x00000001U
#define HINF_CD_DISABLE_S 8
/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
#define HINF_FUNC1_EPS_V 0x00000001U
#define HINF_FUNC1_EPS_S 9
/** HINF_EMP : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S)
#define HINF_EMP_V 0x00000001U
#define HINF_EMP_S 10
/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
#define HINF_IOENABLE1_V 0x00000001U
#define HINF_IOENABLE1_S 11
/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
#define HINF_SDIO_VER 0x00000FFFU
#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
#define HINF_SDIO_VER_V 0x00000FFFU
#define HINF_SDIO_VER_S 12
/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
#define HINF_FUNC2_EPS (BIT(24))
#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
#define HINF_FUNC2_EPS_V 0x00000001U
#define HINF_FUNC2_EPS_S 24
/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
#define HINF_SDIO20_CONF 0x0000007FU
#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
#define HINF_SDIO20_CONF_V 0x0000007FU
#define HINF_SDIO20_CONF_S 25
/** HINF_CFG_TIMING_REG register
* Timing configuration registers
*/
#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
#define HINF_NCRC 0x00000007U
#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S)
#define HINF_NCRC_V 0x00000007U
#define HINF_NCRC_S 0
/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_S 3
/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_S 10
/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
#define HINF_SDCLK_STOP_THRES 0x000007FFU
#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
#define HINF_SDCLK_STOP_THRES_V 0x000007FFU
#define HINF_SDCLK_STOP_THRES_S 16
/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_S 28
/** HINF_CFG_UPDATE_REG register
* update sdio configurations
*/
#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
#define HINF_CONF_UPDATE (BIT(0))
#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
#define HINF_CONF_UPDATE_V 0x00000001U
#define HINF_CONF_UPDATE_S 0
/** HINF_CFG_DATA7_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
#define HINF_PIN_STATE 0x000000FFU
#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
#define HINF_PIN_STATE_V 0x000000FFU
#define HINF_PIN_STATE_S 0
/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
#define HINF_CHIP_STATE 0x000000FFU
#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
#define HINF_CHIP_STATE_V 0x000000FFU
#define HINF_CHIP_STATE_S 8
/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
#define HINF_SDIO_RST_V 0x00000001U
#define HINF_SDIO_RST_S 16
/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
#define HINF_SDIO_IOREADY0_V 0x00000001U
#define HINF_SDIO_IOREADY0_S 17
/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
#define HINF_SDIO_MEM_PD (BIT(18))
#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
#define HINF_SDIO_MEM_PD_V 0x00000001U
#define HINF_SDIO_MEM_PD_S 18
/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
#define HINF_ESDIO_DATA1_INT_EN (BIT(19))
#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U
#define HINF_ESDIO_DATA1_INT_EN_S 19
/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20))
#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_SW_S 20
/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21))
#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U
#define HINF_DDR50_BLK_LEN_FIX_EN_S 21
/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
#define HINF_CLK_EN (BIT(22))
#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S)
#define HINF_CLK_EN_V 0x00000001U
#define HINF_CLK_EN_S 22
/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
#define HINF_SDDR50 (BIT(23))
#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S)
#define HINF_SDDR50_V 0x00000001U
#define HINF_SDDR50_S 23
/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
#define HINF_SSDR104 (BIT(24))
#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S)
#define HINF_SSDR104_V 0x00000001U
#define HINF_SSDR104_S 24
/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
#define HINF_SSDR50 (BIT(25))
#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S)
#define HINF_SSDR50_V 0x00000001U
#define HINF_SSDR50_S 25
/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
#define HINF_SDTD (BIT(26))
#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S)
#define HINF_SDTD_V 0x00000001U
#define HINF_SDTD_S 26
/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
#define HINF_SDTA (BIT(27))
#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S)
#define HINF_SDTA_V 0x00000001U
#define HINF_SDTA_S 27
/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
#define HINF_SDTC (BIT(28))
#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S)
#define HINF_SDTC_V 0x00000001U
#define HINF_SDTC_S 28
/** HINF_SAI : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
#define HINF_SAI (BIT(29))
#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S)
#define HINF_SAI_V 0x00000001U
#define HINF_SAI_S 29
/** HINF_SDIO_WAKEUP_CLR : R/W; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
#define HINF_SDIO_WAKEUP_CLR (BIT(30))
#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U
#define HINF_SDIO_WAKEUP_CLR_S 30
/** HINF_CIS_CONF_W0_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
#define HINF_CIS_CONF_W0 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_S 0
/** HINF_CIS_CONF_W1_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
#define HINF_CIS_CONF_W1 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_S 0
/** HINF_CIS_CONF_W2_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
#define HINF_CIS_CONF_W2 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_S 0
/** HINF_CIS_CONF_W3_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
#define HINF_CIS_CONF_W3 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_S 0
/** HINF_CIS_CONF_W4_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
#define HINF_CIS_CONF_W4 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_S 0
/** HINF_CIS_CONF_W5_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
#define HINF_CIS_CONF_W5 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_S 0
/** HINF_CIS_CONF_W6_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
#define HINF_CIS_CONF_W6 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_S 0
/** HINF_CIS_CONF_W7_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
#define HINF_CIS_CONF_W7 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_S 0
/** HINF_CFG_DATA16_REG register
* SDIO cis configuration register
*/
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
#define HINF_DEVICE_ID_FN2 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_S 0
/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
#define HINF_USER_ID_FN2 0x0000FFFFU
#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
#define HINF_USER_ID_FN2_V 0x0000FFFFU
#define HINF_USER_ID_FN2_S 16
/** HINF_CFG_UHS1_INT_MODE_REG register
* configure int to start and end ahead of time in uhs1 mode
*/
#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_END_AHEAD_MODE 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_S 0
/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_END_AHEAD_MODE 0x00000003U
#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
#define HINF_INT_END_AHEAD_MODE_V 0x00000003U
#define HINF_INT_END_AHEAD_MODE_S 2
/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_S 4
/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_ST_AHEAD_MODE 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_S 6
/** HINF_CONF_STATUS_REG register
* func0 config0 status
*/
#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
#define HINF_FUNC0_CONFIG0 0x000000FFU
#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
#define HINF_FUNC0_CONFIG0_V 0x000000FFU
#define HINF_FUNC0_CONFIG0_S 0
/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
#define HINF_SDR25_ST (BIT(8))
#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
#define HINF_SDR25_ST_V 0x00000001U
#define HINF_SDR25_ST_S 8
/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
#define HINF_SDR50_ST (BIT(9))
#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
#define HINF_SDR50_ST_V 0x00000001U
#define HINF_SDR50_ST_S 9
/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
#define HINF_SDR104_ST (BIT(10))
#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
#define HINF_SDR104_ST_V 0x00000001U
#define HINF_SDR104_ST_S 10
/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
#define HINF_DDR50_ST (BIT(11))
#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
#define HINF_DDR50_ST_V 0x00000001U
#define HINF_DDR50_ST_S 11
/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
#define HINF_TUNE_ST 0x00000007U
#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
#define HINF_TUNE_ST_V 0x00000007U
#define HINF_TUNE_ST_S 12
/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15))
#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_ST_S 15
/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
#define HINF_SDIO_SWITCH_END (BIT(16))
#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
#define HINF_SDIO_SWITCH_END_V 0x00000001U
#define HINF_SDIO_SWITCH_END_S 16
/** HINF_SDIO_SLAVE_LDO_CONF_REG register
* sdio slave ldo control register
*/
#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
#define HINF_LDO_READY_CTL_IN_EN (BIT(0))
#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U
#define HINF_LDO_READY_CTL_IN_EN_S 0
/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
#define HINF_LDO_READY_THRES 0x0000001FU
#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
#define HINF_LDO_READY_THRES_V 0x0000001FU
#define HINF_LDO_READY_THRES_S 1
/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
#define HINF_LDO_READY_IGNORE_EN (BIT(6))
#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U
#define HINF_LDO_READY_IGNORE_EN_S 6
/** HINF_SDIO_DATE_REG register
* ******* Description ***********
*/
#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 37822544;
* sdio version date.
*/
#define HINF_SDIO_DATE 0xFFFFFFFFU
#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
#define HINF_SDIO_DATE_V 0xFFFFFFFFU
#define HINF_SDIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/register/soc/sdio_hinf_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration registers */
/** Type of cfg_data0 register
* Configure sdio cis content
*/
typedef union {
struct {
/** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
uint32_t device_id_fn1:16;
/** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
uint32_t user_id_fn1:16;
};
uint32_t val;
} hinf_cfg_data0_reg_t;
/** Type of cfg_data1 register
* SDIO configuration register
*/
typedef union {
struct {
/** sdio_enable : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
uint32_t sdio_enable:1;
/** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready1:1;
/** highspeed_enable : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
uint32_t highspeed_enable:1;
/** highspeed_mode : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
uint32_t highspeed_mode:1;
/** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
uint32_t sdio_cd_enable:1;
/** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready2:1;
/** sdio_int_mask : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
uint32_t sdio_int_mask:1;
/** ioenable2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
uint32_t ioenable2:1;
/** cd_disable : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
uint32_t cd_disable:1;
/** func1_eps : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
uint32_t func1_eps:1;
/** emp : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
uint32_t emp:1;
/** ioenable1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
uint32_t ioenable1:1;
/** sdio_ver : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
uint32_t sdio_ver:12;
/** func2_eps : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
uint32_t func2_eps:1;
/** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
uint32_t sdio20_conf:7;
};
uint32_t val;
} hinf_cfg_data1_reg_t;
/** Type of cfg_timing register
* Timing configuration registers
*/
typedef union {
struct {
/** ncrc : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
uint32_t ncrc:3;
/** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
uint32_t pst_end_cmd_low_value:7;
/** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
uint32_t pst_end_data_low_value:6;
/** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
uint32_t sdclk_stop_thres:11;
uint32_t reserved_27:1;
/** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
uint32_t sample_clk_divider:4;
};
uint32_t val;
} hinf_cfg_timing_reg_t;
/** Type of cfg_update register
* update sdio configurations
*/
typedef union {
struct {
/** conf_update : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
uint32_t conf_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hinf_cfg_update_reg_t;
/** Type of cfg_data7 register
* SDIO configuration register
*/
typedef union {
struct {
/** pin_state : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
uint32_t pin_state:8;
/** chip_state : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
uint32_t chip_state:8;
/** sdio_rst : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
uint32_t sdio_rst:1;
/** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
uint32_t sdio_ioready0:1;
/** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
uint32_t sdio_mem_pd:1;
/** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
uint32_t esdio_data1_int_en:1;
/** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
uint32_t sdio_switch_volt_sw:1;
/** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
uint32_t ddr50_blk_len_fix_en:1;
/** clk_en : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
uint32_t clk_en:1;
/** sddr50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
uint32_t sddr50:1;
/** ssdr104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
uint32_t ssdr104:1;
/** ssdr50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
uint32_t ssdr50:1;
/** sdtd : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
uint32_t sdtd:1;
/** sdta : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
uint32_t sdta:1;
/** sdtc : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
uint32_t sdtc:1;
/** sai : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
uint32_t sai:1;
/** sdio_wakeup_clr : R/W; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
uint32_t sdio_wakeup_clr:1;
uint32_t reserved_31:1;
};
uint32_t val;
} hinf_cfg_data7_reg_t;
/** Type of cis_conf_w0 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
uint32_t cis_conf_w0:32;
};
uint32_t val;
} hinf_cis_conf_w0_reg_t;
/** Type of cis_conf_w1 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
uint32_t cis_conf_w1:32;
};
uint32_t val;
} hinf_cis_conf_w1_reg_t;
/** Type of cis_conf_w2 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
uint32_t cis_conf_w2:32;
};
uint32_t val;
} hinf_cis_conf_w2_reg_t;
/** Type of cis_conf_w3 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
uint32_t cis_conf_w3:32;
};
uint32_t val;
} hinf_cis_conf_w3_reg_t;
/** Type of cis_conf_w4 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
uint32_t cis_conf_w4:32;
};
uint32_t val;
} hinf_cis_conf_w4_reg_t;
/** Type of cis_conf_w5 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
uint32_t cis_conf_w5:32;
};
uint32_t val;
} hinf_cis_conf_w5_reg_t;
/** Type of cis_conf_w6 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
uint32_t cis_conf_w6:32;
};
uint32_t val;
} hinf_cis_conf_w6_reg_t;
/** Type of cis_conf_w7 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
uint32_t cis_conf_w7:32;
};
uint32_t val;
} hinf_cis_conf_w7_reg_t;
/** Type of cfg_data16 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
uint32_t device_id_fn2:16;
/** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
uint32_t user_id_fn2:16;
};
uint32_t val;
} hinf_cfg_data16_reg_t;
/** Type of cfg_uhs1_int_mode register
* configure int to start and end ahead of time in uhs1 mode
*/
typedef union {
struct {
/** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_end_ahead_mode:2;
/** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_end_ahead_mode:2;
/** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_st_ahead_mode:2;
/** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_st_ahead_mode:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hinf_cfg_uhs1_int_mode_reg_t;
/** Type of sdio_slave_ldo_conf register
* sdio slave ldo control register
*/
typedef union {
struct {
/** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
uint32_t ldo_ready_ctl_in_en:1;
/** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
uint32_t ldo_ready_thres:5;
/** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
uint32_t ldo_ready_ignore_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hinf_sdio_slave_ldo_conf_reg_t;
/** Group: Status registers */
/** Type of conf_status register
* func0 config0 status
*/
typedef union {
struct {
/** func0_config0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
uint32_t func0_config0:8;
/** sdr25_st : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
uint32_t sdr25_st:1;
/** sdr50_st : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
uint32_t sdr50_st:1;
/** sdr104_st : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
uint32_t sdr104_st:1;
/** ddr50_st : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
uint32_t ddr50_st:1;
/** tune_st : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
uint32_t tune_st:3;
/** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
uint32_t sdio_switch_volt_st:1;
/** sdio_switch_end : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
uint32_t sdio_switch_end:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hinf_conf_status_reg_t;
/** Group: Version register */
/** Type of sdio_date register
* ******* Description ***********
*/
typedef union {
struct {
/** sdio_date : R/W; bitpos: [31:0]; default: 37822544;
* sdio version date.
*/
uint32_t sdio_date:32;
};
uint32_t val;
} hinf_sdio_date_reg_t;
typedef struct {
volatile hinf_cfg_data0_reg_t cfg_data0;
volatile hinf_cfg_data1_reg_t cfg_data1;
volatile hinf_cfg_timing_reg_t cfg_timing;
volatile hinf_cfg_update_reg_t cfg_update;
uint32_t reserved_010[3];
volatile hinf_cfg_data7_reg_t cfg_data7;
volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
volatile hinf_cfg_data16_reg_t cfg_data16;
volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
uint32_t reserved_048[3];
volatile hinf_conf_status_reg_t conf_status;
uint32_t reserved_058[22];
volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
uint32_t reserved_0b4[18];
volatile hinf_sdio_date_reg_t sdio_date;
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifndef __cplusplus
_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/register/soc/sha_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,23 +15,26 @@ extern "C" {
* Configures SHA algorithm
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the SHA algorithm. \\
* 0: SHA-1\\
* 1: SHA-224\\
* 2: SHA-256\\
/** SHA_MODE : R/W; bitpos: [3:0]; default: 2;
* Configures the SHA algorithm.
* 0: SHA-1
* 1: SHA2-224
* 2: SHA2-256
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE 0x0000000FU
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x00000007U
#define SHA_MODE_V 0x0000000FU
#define SHA_MODE_S 0
/** SHA_T_STRING_REG register
* SHA 512/t configuration register 0.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
* Sha t_string (used if and only if mode == SHA_512/t).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SHA_T_STRING 0xFFFFFFFFU
#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S)
@@ -40,60 +43,63 @@ extern "C" {
/** SHA_T_LENGTH_REG register
* SHA 512/t configuration register 1.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
/** SHA_T_LENGTH : R/W; bitpos: [6:0]; default: 0;
* Sha t_length (used if and only if mode == SHA_512/t).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SHA_T_LENGTH 0x0000003FU
#define SHA_T_LENGTH 0x0000007FU
#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
#define SHA_T_LENGTH_V 0x0000003FU
#define SHA_T_LENGTH_V 0x0000007FU
#define SHA_T_LENGTH_S 0
/** SHA_DMA_BLOCK_NUM_REG register
* Block number register (only effective for DMA-SHA)
*/
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0;
* Configures the DMA-SHA block number.
*/
#define SHA_DMA_BLOCK_NUM 0x0000003FU
#define SHA_DMA_BLOCK_NUM 0x0000FFFFU
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU
#define SHA_DMA_BLOCK_NUM_S 0
/** SHA_START_REG register
* Starts the SHA accelerator for Typical SHA operation
*/
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
/** SHA_START : RO; bitpos: [31:1]; default: 0;
* Write 1 to start Typical SHA calculation.
/** SHA_START : WO; bitpos: [0]; default: 0;
* Start typical sha.
*/
#define SHA_START 0x7FFFFFFFU
#define SHA_START (BIT(0))
#define SHA_START_M (SHA_START_V << SHA_START_S)
#define SHA_START_V 0x7FFFFFFFU
#define SHA_START_S 1
#define SHA_START_V 0x00000001U
#define SHA_START_S 0
/** SHA_CONTINUE_REG register
* Continues SHA operation (only effective in Typical SHA mode)
*/
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
* Write 1 to continue Typical SHA calculation.
/** SHA_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue typical sha.
*/
#define SHA_CONTINUE 0x7FFFFFFFU
#define SHA_CONTINUE (BIT(0))
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
#define SHA_CONTINUE_V 0x7FFFFFFFU
#define SHA_CONTINUE_S 1
#define SHA_CONTINUE_V 0x00000001U
#define SHA_CONTINUE_S 0
/** SHA_BUSY_REG register
* Represents if SHA Accelerator is busy or not
*/
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents the states of SHA accelerator. \\
* 0: idle\\
* 1: busy\\
* Represents the states of SHA accelerator.
* 0: idle
* 1: busy
*/
#define SHA_BUSY_STATE (BIT(0))
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
@@ -152,7 +158,7 @@ extern "C" {
* Version control register
*/
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291;
* Version control register.
*/
#define SHA_DATE 0x3FFFFFFFU
@@ -160,17 +166,33 @@ extern "C" {
#define SHA_DATE_V 0x3FFFFFFFU
#define SHA_DATE_S 0
/** SHA_DMA_RX_RESET_REG register
* DMA RX FIFO Reset Signal
*/
#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30)
/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0;
* Write 1 to reset DMA RX FIFO
*/
#define SHA_DMA_RX_RESET (BIT(0))
#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S)
#define SHA_DMA_RX_RESET_V 0x00000001U
#define SHA_DMA_RX_RESET_S 0
/** SHA_H_MEM register
* Sha H memory which contains intermediate hash or final hash.
* SHA1, SHA2-256, SM3 H memory which contains intermediate hash or final hash.
* SHA1, SHA2-256, SM3 : 0x00~0x20 (R/W)
* SHA2-512 : 0x00~0x40 (R/W)
*/
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
#define SHA_H_MEM_SIZE_BYTES 64
/** SHA_M_MEM register
* Sha M memory which contains message.
* SHA1, SHA2-256, SM3 M memory which contains message.
* SHA1, SHA2-256, SM3 : 0x00~0x40
* SHA2-512 : 0x00~0x80
*/
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
#define SHA_M_MEM_SIZE_BYTES 64
#define SHA_M_MEM_SIZE_BYTES 128
#ifdef __cplusplus
}

75
components/soc/esp32c5/register/soc/sha_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,14 +16,14 @@ extern "C" {
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Configures the SHA algorithm. \\
* 0: SHA-1\\
* 1: SHA-224\\
* 2: SHA-256\\
/** mode : R/W; bitpos: [3:0]; default: 2;
* Configures the SHA algorithm.
* 0: SHA-1
* 1: SHA2-224
* 2: SHA2-256
*/
uint32_t mode:3;
uint32_t reserved_3:29;
uint32_t mode:4;
uint32_t reserved_4:28;
};
uint32_t val;
} sha_mode_reg_t;
@@ -33,11 +33,11 @@ typedef union {
*/
typedef union {
struct {
/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
/** dma_block_num : R/W; bitpos: [15:0]; default: 0;
* Configures the DMA-SHA block number.
*/
uint32_t dma_block_num:6;
uint32_t reserved_6:26;
uint32_t dma_block_num:16;
uint32_t reserved_16:16;
};
uint32_t val;
} sha_dma_block_num_reg_t;
@@ -47,11 +47,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** start : RO; bitpos: [31:1]; default: 0;
* Write 1 to start Typical SHA calculation.
/** start : WO; bitpos: [0]; default: 0;
* Start typical sha.
*/
uint32_t start:31;
uint32_t start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_start_reg_t;
@@ -61,11 +61,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** conti : RO; bitpos: [31:1]; default: 0;
* Write 1 to continue Typical SHA calculation.
/** conti : WO; bitpos: [0]; default: 0;
* Continue typical sha.
*/
uint32_t conti:31;
uint32_t conti:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_continue_reg_t;
@@ -98,6 +98,20 @@ typedef union {
uint32_t val;
} sha_dma_continue_reg_t;
/** Type of dma_rx_reset register
* DMA RX FIFO Reset Signal
*/
typedef union {
struct {
/** dma_rx_reset : WO; bitpos: [0]; default: 0;
* Write 1 to reset DMA RX FIFO
*/
uint32_t dma_rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_rx_reset_reg_t;
/** Group: Configuration Register */
/** Type of t_string register
@@ -107,6 +121,7 @@ typedef union {
struct {
/** t_string : R/W; bitpos: [31:0]; default: 0;
* Sha t_string (used if and only if mode == SHA_512/t).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t t_string:32;
};
@@ -118,11 +133,12 @@ typedef union {
*/
typedef union {
struct {
/** t_length : R/W; bitpos: [5:0]; default: 0;
/** t_length : R/W; bitpos: [6:0]; default: 0;
* Sha t_length (used if and only if mode == SHA_512/t).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t t_length:6;
uint32_t reserved_6:26;
uint32_t t_length:7;
uint32_t reserved_7:25;
};
uint32_t val;
} sha_t_length_reg_t;
@@ -135,9 +151,9 @@ typedef union {
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Represents the states of SHA accelerator. \\
* 0: idle\\
* 1: busy\\
* Represents the states of SHA accelerator.
* 0: idle
* 1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
@@ -182,7 +198,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538972713;
/** date : R/W; bitpos: [29:0]; default: 539232291;
* Version control register.
*/
uint32_t date:30;
@@ -207,15 +223,16 @@ typedef struct {
volatile sha_clear_irq_reg_t clear_irq;
volatile sha_irq_ena_reg_t irq_ena;
volatile sha_date_reg_t date;
uint32_t reserved_030[4];
volatile sha_dma_rx_reset_reg_t dma_rx_reset;
uint32_t reserved_034[3];
volatile uint32_t h[16];
volatile uint32_t m[16];
volatile uint32_t m[32];
} sha_dev_t;
extern sha_dev_t SHA;
#ifndef __cplusplus
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure");
#endif
#ifdef __cplusplus

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components/soc/esp32c5/register/soc/timer_group_reg.h
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@@ -1,7 +1,7 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -17,18 +17,18 @@ extern "C" {
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* Configures whether or not to enable the timer 0 alarm function. This bit will be
* automatically cleared once an alarm occurs.\\
* 0: Disable \\
* 1: Enable \\
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* Configures whether or not to reset the timer 0 's clock divider counter. \\
* 0: No effect \\
* 1: Reset \\
* Configures whether or not to reset the timer 0 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
@@ -43,28 +43,27 @@ extern "C" {
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* Configures whether or not to enable the timer 0 auto-reload function at the time of
* alarm. \\
* 0: No effect \\
* 1: Enable \\
* alarm.
* 0: No effect
* 1: Enable
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* Configures the counting direction of the timer 0 time-base counter. \\
* 0: Decrement \\
* 1: Increment \\
*
* Configures the counting direction of the timer 0 time-base counter.
* 0: Decrement
* 1: Increment
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* Configures whether or not to enable the timer 0 time-base counter. \\
* 0: Disable \\
* 1: Enable \\
* Configures whether or not to enable the timer 0 time-base counter.
* 0: Disable
* 1: Enable
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
@@ -77,8 +76,8 @@ extern "C" {
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* Represents the low 32 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG. \\
* Measurement unit: T0_clk \\
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
@@ -91,8 +90,8 @@ extern "C" {
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* Represents the high 22 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG. \\
* Measurement unit: T0_clk \\
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
@@ -104,9 +103,9 @@ extern "C" {
*/
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* Configures to latch the counter value. \\
* 0: Latch \\
* 1: Latch \\
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
@@ -119,8 +118,8 @@ extern "C" {
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1. \\
* Measurement unit: T0_clk \\
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
@@ -133,8 +132,8 @@ extern "C" {
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1. \\
* Measurement unit: T0_clk \\
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
@@ -147,8 +146,8 @@ extern "C" {
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Configures low 32 bits of the value that a reload will load onto timer 0 time-base
* counter. \\
* Measurement unit: T0_clk \\
* counter.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
@@ -161,8 +160,8 @@ extern "C" {
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* Configures high 22 bits of the value that a reload will load onto timer 0 time-base
* counter. \\
* Measurement unit: T0_clk \\
* counter.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
@@ -188,9 +187,9 @@ extern "C" {
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled. \\
* 0: Mask \\
* 1: Unmask \\
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
@@ -198,19 +197,18 @@ extern "C" {
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled. \\
* 0: Mask \\
* 1: Unmask \\
*
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* Configures whether to enable flash boot protection.\\
* 0: Disable \\
* 1: Enable \\
* Configures whether to enable flash boot protection.
* 0: Disable
* 1: Enable
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
@@ -218,17 +216,17 @@ extern "C" {
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* Configures the system reset signal length. Valid only when write protection is
* disabled. \\
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8 \\
* 1: 16 \\
* 2: 24 \\
* 3: 32 \\
* 4: 40 \\
* 5: 64 \\
* 6: 128 \\
* 7: 256 \\
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
@@ -237,17 +235,17 @@ extern "C" {
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* Configures the CPU reset signal length. Valid only when write protection is
* disabled.\\
* Measurement unit: mwdt_clk \\
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8 \\
* 1: 16 \\
* 2: 24 \\
* 3: 32 \\
* 4: 40 \\
* 5: 64 \\
* 6: 128 \\
* 7: 256 \\
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
@@ -255,9 +253,9 @@ extern "C" {
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* Configures to update the WDT configuration registers.\\
* 0: No effect \\
* 1: Update \\
* Configures to update the WDT configuration registers.
* 0: No effect
* 1: Update
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
@@ -289,11 +287,11 @@ extern "C" {
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Configures the timeout action of stage 0. Valid only when write protection is
* disabled. \\
* 0: No effect \\
* 1: Interrupt \\
* 2: Reset CPU \\
* 3: Reset system \\
* disabled.
* 0: No effect
* 1: Interrupt
* 2: Reset CPU
* 3: Reset system
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
@@ -301,9 +299,9 @@ extern "C" {
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not to enable the MWDT. Valid only when write protection is
* disabled. \\
* 0: Disable \\
* 1: Enable \\
* disabled.
* 0: Disable
* 1: Enable
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
@@ -315,9 +313,9 @@ extern "C" {
*/
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* Configures whether to reset WDT 's clock divider counter. \\
* 0: No effect \\
* 1: Reset \\
* Configures whether to reset WDT 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
@@ -325,8 +323,8 @@ extern "C" {
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* Configures MWDT clock prescaler value. Valid only when write protection is
* disabled. \\
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. \\
* disabled.
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
@@ -339,8 +337,7 @@ extern "C" {
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Configures the stage 0 timeout value. Valid only when write protection is disabled.
* \\
* Measurement unit: mwdt_clk \\
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
@@ -352,9 +349,8 @@ extern "C" {
*/
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Configures the stage 1 timeout value. Valid only when write protection is
* disabled.\\
* Measurement unit: mwdt_clk \\
* Configures the stage 1 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
@@ -367,8 +363,7 @@ extern "C" {
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 2 timeout value. Valid only when write protection is disabled.
* \\
* Measurement unit: mwdt_clk \\
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
@@ -381,8 +376,7 @@ extern "C" {
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 3 timeout value. Valid only when write protection is disabled.
* \\
* Measurement unit: mwdt_clk \\
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
@@ -418,35 +412,35 @@ extern "C" {
*/
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* Configures the frequency calculation mode. \\
* 0: one-shot frequency calculation \\
* 1: periodic frequency calculation \\
* Configures the frequency calculation mode.
* 0: one-shot frequency calculation
* 1: periodic frequency calculation
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* Represents whether one-shot frequency calculation is done.\\
* 0: Not done \\
* 1: Done \\
* Represents whether one-shot frequency calculation is done.
* 0: Not done
* 1: Done
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Configures the time to calculate RTC slow clock's frequency. \\
* Measurement unit: XTAL_CLK \\
* Configures the time to calculate RTC slow clock's frequency.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Configures whether to enable one-shot frequency calculation. \\
* 0: Disable \\
* 1: Enable \\
* Configures whether to enable one-shot frequency calculation.
* 0: Disable
* 1: Enable
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
@@ -458,9 +452,9 @@ extern "C" {
*/
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* Represents whether periodic frequency calculation is done. \\
* 0: Not done \\
* 1: Done \\
* Represents whether periodic frequency calculation is done.
* 0: Not done
* 1: Done
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
@@ -556,17 +550,17 @@ extern "C" {
*/
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* Represents whether RTC frequency calculation is timeout. \\
* 0: No timeout \\
* 1: Timeout \\
* Represents whether RTC frequency calculation is timeout.
* 0: No timeout
* 1: Timeout
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Configures the cycles that reset frequency calculation timeout. \\
* Measurement unit: XTAL_CLK \\
* Configures the cycles that reset frequency calculation timeout.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
@@ -574,8 +568,8 @@ extern "C" {
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Configures the threshold value for the RTC frequency calculation timer. If the
* timer's value exceeds this threshold, a timeout is triggered.\\
* Measurement unit: XTAL_CLK \\
* timer's value exceeds this threshold, a timeout is triggered.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
@@ -599,18 +593,18 @@ extern "C" {
*/
#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
* Configures whether to enable timer's ETM task and event. \\
* 0: Disable \\
* 1: Enable \\
* Configures whether to enable timer's ETM task and event.
* 0: Disable
* 1: Enable
*/
#define TIMG_ETM_EN (BIT(28))
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
#define TIMG_ETM_EN_V 0x00000001U
#define TIMG_ETM_EN_S 28
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Configures whether to enable gate clock signal for registers. \\
* 0: Force clock on for registers \\
* 1: Support clock only when registers are read or written to by software. \\
* Configures whether to enable gate clock signal for registers.
* 0: Force clock on for registers
* 1: Support clock only when registers are read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)

417
components/soc/esp32c5/register/soc/timer_group_struct.h
View File

@@ -1,7 +1,7 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -10,173 +10,173 @@
extern "C" {
#endif
/** Group: Timer Control and configuration registers */
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
* Timer 0 configuration register
*/
typedef union {
struct {
uint32_t reserved_0: 10;
uint32_t reserved_0:10;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* Configures whether or not to enable the timer alarm function. This bit will be
* automatically cleared once an alarm occurs.\\
* 0: Disable \\
* 1: Enable \\
* Configures whether or not to enable the timer 0 alarm function. This bit will be
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
uint32_t tx_alarm_en: 1;
uint32_t reserved_11: 1;
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* Configures whether or not to reset the timer's clock divider counter. \\
* 0: No effect \\
* 1: Reset \\
* Configures whether or not to reset the timer 0 's clock divider counter.
* 0: No effect
* 1: Reset
*/
uint32_t tx_divcnt_rst: 1;
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Represents the timer clock (Tx_clk) prescaler value.
* Represents the timer 0 clock (T0_clk) prescaler value.
*/
uint32_t tx_divider: 16;
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* Configures whether or not to enable the timer auto-reload function at the time of
* alarm. \\
* 0: No effect \\
* 1: Enable \\
* Configures whether or not to enable the timer 0 auto-reload function at the time of
* alarm.
* 0: No effect
* 1: Enable
*/
uint32_t tx_autoreload: 1;
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* Configures the counting direction of the timer time-base counter. \\
* 0: Decrement \\
* 1: Increment \\
*
* Configures the counting direction of the timer 0 time-base counter.
* 0: Decrement
* 1: Increment
*/
uint32_t tx_increase: 1;
uint32_t tx_increase:1;
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
* Configures whether or not to enable the timer time-base counter. \\
* 0: Disable \\
* 1: Enable \\
* Configures whether or not to enable the timer 0 time-base counter.
* 0: Disable
* 1: Enable
*/
uint32_t tx_en: 1;
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
* Timer 0 current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* Represents the low 32 bits of the time-base counter of timer x. Valid only after
* writing to TIMG_T0UPDATE_REG. \\
* Measurement unit: Tx_clk \\
* Represents the low 32 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
uint32_t tx_lo: 32;
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer x current value, high 22 bits
* Timer 0 current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* Represents the high 22 bits of the time-base counter of timer x. Valid only after
* writing to TIMG_T0UPDATE_REG. \\
* Measurement unit: Tx_clk \\
* Represents the high 22 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
uint32_t tx_hi: 22;
uint32_t reserved_22: 10;
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_TxLO_REG or TIMGn_TxHI_REG
* Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
*/
typedef union {
struct {
uint32_t reserved_0: 31;
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* Configures to latch the counter value. \\
* 0: Latch \\
* 1: Latch \\
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
uint32_t tx_update: 1;
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer x alarm value, low 32 bits
* Timer 0 alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Configures the low 32 bits of timer x alarm trigger time-base counter value. Valid
* only when TIMG_Tx_ALARM_EN is 1. \\
* Measurement unit: Tx_clk \\
* Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
uint32_t tx_alarm_lo: 32;
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer x alarm value, high bits
* Timer 0 alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Configures the high 22 bits of timer x alarm trigger time-base counter value. Valid
* only when TIMG_Tx_ALARM_EN is 1. \\
* Measurement unit: Tx_clk \\
* Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
uint32_t tx_alarm_hi: 22;
uint32_t reserved_22: 10;
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer x reload value, low 32 bits
* Timer 0 reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Configures low 32 bits of the value that a reload will load onto timer x time-base
* counter. \\
* Measurement unit: Tx_clk \\
* Configures low 32 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
uint32_t tx_load_lo: 32;
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer x reload value, high 22 bits
* Timer 0 reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* Configures high 22 bits of the value that a reload will load onto timer x time-base
* counter. \\
* Measurement unit: Tx_clk \\
* Configures high 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
uint32_t tx_load_hi: 22;
uint32_t reserved_22: 10;
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_TxLOADLO_REG or TIMG_TxLOADHI_REG
* Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
* Write any value to trigger a timer x time-base counter reload.
* Write any value to trigger a timer 0 time-base counter reload.
*
*/
uint32_t tx_load: 32;
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
@@ -188,98 +188,97 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0: 12;
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled. \\
* 0: Mask \\
* 1: Unmask \\
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
uint32_t wdt_appcpu_reset_en: 1;
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled. \\
* 0: Mask \\
* 1: Unmask \\
*
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
uint32_t wdt_procpu_reset_en: 1;
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* Configures whether to enable flash boot protection.\\
* 0: Disable \\
* 1: Enable \\
* Configures whether to enable flash boot protection.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_flashboot_mod_en: 1;
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* Configures the system reset signal length. Valid only when write protection is
* disabled. \\
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8 \\
* 1: 16 \\
* 2: 24 \\
* 3: 32 \\
* 4: 40 \\
* 5: 64 \\
* 6: 128 \\
* 7: 256 \\
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
uint32_t wdt_sys_reset_length: 3;
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* Configures the CPU reset signal length. Valid only when write protection is
* disabled.\\
* Measurement unit: mwdt_clk \\
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8 \\
* 1: 16 \\
* 2: 24 \\
* 3: 32 \\
* 4: 40 \\
* 5: 64 \\
* 6: 128 \\
* 7: 256 \\
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
uint32_t wdt_cpu_reset_length: 3;
uint32_t reserved_21: 1;
uint32_t wdt_cpu_reset_length:3;
uint32_t reserved_21:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* Configures to update the WDT configuration registers.\\
* 0: No effect \\
* 1: Update \\
* Configures to update the WDT configuration registers.
* 0: No effect
* 1: Update
*/
uint32_t wdt_conf_update_en: 1;
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg3: 2;
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg2: 2;
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg1: 2;
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Configures the timeout action of stage 0. Valid only when write protection is
* disabled. \\
* 0: No effect \\
* 1: Interrupt \\
* 2: Reset CPU \\
* 3: Reset system \\
* disabled.
* 0: No effect
* 1: Interrupt
* 2: Reset CPU
* 3: Reset system
*/
uint32_t wdt_stg0: 2;
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not to enable the MWDT. Valid only when write protection is
* disabled. \\
* 0: Disable \\
* 1: Enable \\
* disabled.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_en: 1;
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
@@ -290,18 +289,18 @@ typedef union {
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* Configures whether to reset WDT 's clock divider counter. \\
* 0: No effect \\
* 1: Reset \\
* Configures whether to reset WDT 's clock divider counter.
* 0: No effect
* 1: Reset
*/
uint32_t wdt_divcnt_rst: 1;
uint32_t reserved_1: 15;
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* Configures MWDT clock prescaler value. Valid only when write protection is
* disabled. \\
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE. \\
* disabled.
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale: 16;
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
@@ -313,10 +312,9 @@ typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Configures the stage 0 timeout value. Valid only when write protection is disabled.
* \\
* Measurement unit: mwdt_clk \\
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg0_hold: 32;
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
@@ -327,11 +325,10 @@ typedef union {
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Configures the stage 1 timeout value. Valid only when write protection is
* disabled.\\
* Measurement unit: mwdt_clk \\
* Configures the stage 1 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg1_hold: 32;
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
@@ -343,10 +340,9 @@ typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 2 timeout value. Valid only when write protection is disabled.
* \\
* Measurement unit: mwdt_clk \\
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg2_hold: 32;
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
@@ -358,10 +354,9 @@ typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 3 timeout value. Valid only when write protection is disabled.
* \\
* Measurement unit: mwdt_clk \\
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg3_hold: 32;
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
@@ -374,7 +369,7 @@ typedef union {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. Valid only when write protection is disabled.
*/
uint32_t wdt_feed: 32;
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
@@ -387,7 +382,7 @@ typedef union {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* Configures a different value than its reset value to enable write protection.
*/
uint32_t wdt_wkey: 32;
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
@@ -399,31 +394,31 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0: 12;
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Configures the frequency calculation mode. \\
* 0: one-shot frequency calculation \\
* 1: periodic frequency calculation \\
* Configures the frequency calculation mode.
* 0: one-shot frequency calculation
* 1: periodic frequency calculation
*/
uint32_t rtc_cali_start_cycling: 1;
uint32_t reserved_13: 2;
uint32_t rtc_cali_start_cycling:1;
uint32_t reserved_13:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Represents whether one-shot frequency calculation is done.\\
* 0: Not done \\
* 1: Done \\
* Represents whether one-shot frequency calculation is done.
* 0: Not done
* 1: Done
*/
uint32_t rtc_cali_rdy: 1;
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Configures the time to calculate RTC slow clock's frequency. \\
* Measurement unit: XTAL_CLK \\
* Configures the time to calculate RTC slow clock's frequency.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_max: 15;
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Configures whether to enable one-shot frequency calculation. \\
* 0: Disable \\
* 1: Enable \\
* Configures whether to enable one-shot frequency calculation.
* 0: Disable
* 1: Enable
*/
uint32_t rtc_cali_start: 1;
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
@@ -434,17 +429,17 @@ typedef union {
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Represents whether periodic frequency calculation is done. \\
* 0: Not done \\
* 1: Done \\
* Represents whether periodic frequency calculation is done.
* 0: Not done
* 1: Done
*/
uint32_t rtc_cali_cycling_data_vld: 1;
uint32_t reserved_1: 6;
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Represents the value countered by XTAL_CLK when one-shot or periodic frequency
* calculation is done. It is used to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value: 25;
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
@@ -455,23 +450,23 @@ typedef union {
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* Represents whether RTC frequency calculation is timeout. \\
* 0: No timeout \\
* 1: Timeout \\
* Represents whether RTC frequency calculation is timeout.
* 0: No timeout
* 1: Timeout
*/
uint32_t rtc_cali_timeout: 1;
uint32_t reserved_1: 2;
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Configures the cycles that reset frequency calculation timeout. \\
* Measurement unit: XTAL_CLK \\
* Configures the cycles that reset frequency calculation timeout.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_timeout_rst_cnt: 4;
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Configures the threshold value for the RTC frequency calculation timer. If the
* timer's value exceeds this threshold, a timeout is triggered.\\
* Measurement unit: XTAL_CLK \\
* timer's value exceeds this threshold, a timeout is triggered.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_timeout_thres: 25;
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
@@ -486,13 +481,13 @@ typedef union {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_ena: 1;
uint32_t reserved_1: 1;
uint32_t t0_int_ena:1;
uint32_t reserved_1:1;
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena: 1;
uint32_t reserved_3: 29;
uint32_t wdt_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
@@ -505,13 +500,13 @@ typedef union {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit of the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_raw: 1;
uint32_t reserved_1: 1;
uint32_t t0_int_raw:1;
uint32_t reserved_1:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit of the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw: 1;
uint32_t reserved_3: 29;
uint32_t wdt_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
@@ -524,13 +519,13 @@ typedef union {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit of the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_st: 1;
uint32_t reserved_1: 1;
uint32_t t0_int_st:1;
uint32_t reserved_1:1;
/** wdt_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit of the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st: 1;
uint32_t reserved_3: 29;
uint32_t wdt_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_st_timers_reg_t;
@@ -543,13 +538,13 @@ typedef union {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_clr: 1;
uint32_t reserved_1: 1;
uint32_t t0_int_clr:1;
uint32_t reserved_1:1;
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr: 1;
uint32_t reserved_3: 29;
uint32_t wdt_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
@@ -564,8 +559,8 @@ typedef union {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
* Version control register
*/
uint32_t ntimgs_date: 28;
uint32_t reserved_28: 4;
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
@@ -577,20 +572,20 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0: 28;
uint32_t reserved_0:28;
/** etm_en : R/W; bitpos: [28]; default: 1;
* Configures whether to enable timer's ETM task and event. \\
* 0: Disable \\
* 1: Enable \\
* Configures whether to enable timer's ETM task and event.
* 0: Disable
* 1: Enable
*/
uint32_t etm_en: 1;
uint32_t reserved_29: 2;
uint32_t etm_en:1;
uint32_t reserved_29:2;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Configures whether to enable gate clock signal for registers. \\
* 0: Force clock on for registers \\
* 1: Support clock only when registers are read or written to by software. \\
* Configures whether to enable gate clock signal for registers.
* 0: Force clock on for registers
* 1: Support clock only when registers are read or written to by software.
*/
uint32_t clk_en: 1;
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;

163
components/soc/esp32c5/register/soc/trace_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -54,9 +54,9 @@ extern "C" {
/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Configures whether to update the value of
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\
* 0: Not update\\
* 1: Update\\
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
* 0: Not update
* 1: Update
*/
#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0))
#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
@@ -68,15 +68,20 @@ extern "C" {
*/
#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
* Represent whether the FIFO is empty. \\1: Empty \\0: Not empty
* Represent whether the FIFO is empty.
* 1: Empty
* 0: Not empty
*/
#define TRACE_FIFO_EMPTY (BIT(0))
#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
#define TRACE_FIFO_EMPTY_V 0x00000001U
#define TRACE_FIFO_EMPTY_S 0
/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
* Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
* state because hart is halted or in reset \\3: Lost state\\
* Represent the state of the encoder:
* 0: Idle state
* 1: Working state
* 2: Wait state because hart is halted or in reset
* 3: Lost state
*/
#define TRACE_WORK_STATUS 0x00000003U
#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
@@ -145,29 +150,36 @@ extern "C" {
*/
#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
* Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\
* Configure whether to enable the encoder.
* 0: Invalid
* 1: Enable
*/
#define TRACE_TRIGGER_ON (BIT(0))
#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
#define TRACE_TRIGGER_ON_V 0x00000001U
#define TRACE_TRIGGER_ON_S 0
/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
* Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\
* Configure whether to disable the encoder.
* 0: Invalid
* 1: Disable
*/
#define TRACE_TRIGGER_OFF (BIT(1))
#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
#define TRACE_TRIGGER_OFF_V 0x00000001U
#define TRACE_TRIGGER_OFF_S 1
/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
* Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\
* Configure the memory writing mode.
* 0: Non-loop mode.
* 1: Loop mode
*/
#define TRACE_MEM_LOOP (BIT(2))
#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
#define TRACE_MEM_LOOP_V 0x00000001U
#define TRACE_MEM_LOOP_S 2
/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
* Configure whether or not enable automatic restart function for the encoder.\\0:
* Disable\\1: Enable\\
* Configure whether or not enable automatic restart function for the encoder.
* 0: Disable
* 1: Enable
*/
#define TRACE_RESTART_ENA (BIT(3))
#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
@@ -179,7 +191,9 @@ extern "C" {
*/
#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24)
/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
* Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\
* Configure whether to enable the trigger signal.
* 0: Disable
* 1:enable
*/
#define TRACE_DM_TRIGGER_ENA (BIT(0))
#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
@@ -188,28 +202,36 @@ extern "C" {
/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
* Configure whether to reset, when enabled, if cpu have reset, the encoder will
* output a packet to report the address of the last instruction, and upon reset
* deassertion, the encoder start again.\\0: Disable\\0: Enable\\
* deassertion, the encoder start again.
* 0: Disable
* 0: Enable
*/
#define TRACE_RESET_ENA (BIT(1))
#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
#define TRACE_RESET_ENA_V 0x00000001U
#define TRACE_RESET_ENA_S 1
/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\
* Configure whether to enable the halt signal.
* 1: Disable
* 1: Enable
*/
#define TRACE_HALT_ENA (BIT(2))
#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
#define TRACE_HALT_ENA_V 0x00000001U
#define TRACE_HALT_ENA_S 2
/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
* Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\
* Configure whether to enable the stall signal.
* 0: Disable.
* 1: Enable
*/
#define TRACE_STALL_ENA (BIT(3))
#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
#define TRACE_STALL_ENA_V 0x00000001U
#define TRACE_STALL_ENA_S 3
/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
* Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\
* Configure the address mode.
* 0: Delta address mode.
* 1: Full address mode.
*/
#define TRACE_FULL_ADDRESS (BIT(4))
#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
@@ -217,8 +239,9 @@ extern "C" {
#define TRACE_FULL_ADDRESS_S 4
/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
* Configure whether or not enable implicit exception mode. When enabled,, do not sent
* exception address, only exception cause in exception packets.\\1: enabled\\0:
* disabled\\
* exception address, only exception cause in exception packets.
* 1: enabled
* 0: disabled
*/
#define TRACE_IMPLICIT_EXCEPT (BIT(5))
#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
@@ -230,23 +253,27 @@ extern "C" {
*/
#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28)
/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
* Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable
* Configure whether to enable filtering.
* 0: Disable, always match.
* 1: Enable
*/
#define TRACE_FILTER_EN (BIT(0))
#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
#define TRACE_FILTER_EN_V 0x00000001U
#define TRACE_FILTER_EN_S 0
/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
* Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable,
* the comparator must be high in order for the filter to match
* Configure whether to enable the comparator match mode.
* 0: Disable
* 1: Enable, the comparator must be high in order for the filter to match
*/
#define TRACE_MATCH_COMP (BIT(1))
#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
#define TRACE_MATCH_COMP_V 0x00000001U
#define TRACE_MATCH_COMP_S 1
/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable,
* match privilege levels specified by
* Configure whether to enable the privilege match mode.
* 0: Disable
* 1: Enable, match privilege levels specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
*/
#define TRACE_MATCH_PRIVILEGE (BIT(2))
@@ -254,8 +281,9 @@ extern "C" {
#define TRACE_MATCH_PRIVILEGE_V 0x00000001U
#define TRACE_MATCH_PRIVILEGE_S 2
/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
* Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start
* matching from exception cause codes specified by
* Configure whether to enable ecause match mode.
* 0: Disable
* 1: Enable, start matching from exception cause codes specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
* matching upon return from the 1st matching exception.
*/
@@ -264,8 +292,9 @@ extern "C" {
#define TRACE_MATCH_ECAUSE_V 0x00000001U
#define TRACE_MATCH_ECAUSE_S 3
/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
* Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable,
* start matching from a trap with the interrupt level codes specified by
* Configure whether to enable the interrupt match mode.
* 0: Disable
* 1: Enable, start matching from a trap with the interrupt level codes specified by
* \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
* stop matching upon return from the 1st matching trap.
*/
@@ -280,8 +309,9 @@ extern "C" {
#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c)
/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
* Configures the privilege level for matching. Valid only when
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User
* mode. \\1: Machine mode
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
* 0: User mode.
* 1: Machine mode
*/
#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0))
#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
@@ -289,8 +319,9 @@ extern "C" {
#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0
/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
* Configures the interrupt level for match. Valid only when when
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0:
* itype=2. \\0: itype=2.
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
* 0: itype=2.
* 0: itype=2.
*/
#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1))
#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
@@ -309,16 +340,23 @@ extern "C" {
*/
#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30)
/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
* Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\
* Configures the input of the primary comparator for matching:
* 0: iaddr
* 1: tval
*/
#define TRACE_P_INPUT (BIT(0))
#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
#define TRACE_P_INPUT_V 0x00000001U
#define TRACE_P_INPUT_S 0
/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
* Configures the function for the primary comparator. \\0: Equal, \\1: Not equal,
* \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
* equal, \\Other: Always match
* Configures the function for the primary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
#define TRACE_P_FUNCTION 0x00000007U
#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
@@ -326,24 +364,32 @@ extern "C" {
#define TRACE_P_FUNCTION_S 2
/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
* Configure whether to explicitly report an instruction address matched against the
* primary comparator. \\0:Not report \\1:Report
* primary comparator.
* 0:Not report
* 1:Report
*/
#define TRACE_P_NOTIFY (BIT(5))
#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
#define TRACE_P_NOTIFY_V 0x00000001U
#define TRACE_P_NOTIFY_S 5
/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
* Configures the input of the secondary comparator for matching: \\0: iaddr \\1:
* tval\\
* Configures the input of the secondary comparator for matching:
* 0: iaddr
* 1: tval
*/
#define TRACE_S_INPUT (BIT(8))
#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
#define TRACE_S_INPUT_V 0x00000001U
#define TRACE_S_INPUT_S 8
/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
* Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal,
* \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
* equal, \\Other: Always match
* Configures the function for the secondary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
#define TRACE_S_FUNCTION 0x00000007U
#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
@@ -358,10 +404,12 @@ extern "C" {
#define TRACE_S_NOTIFY_V 0x00000001U
#define TRACE_S_NOTIFY_S 13
/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
* Configures the comparator match mode: \\0: Only the primary comparator matches \\1:
* Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or
* secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary
* comparator matches and stop filtering when the secondary comparator matches\\
* Configures the comparator match mode:
* 0: Only the primary comparator matches
* 1: Both primary and secondary comparator matches(P\&\&S)
* 2:Neither primary or secondary comparator matches !(P\&\&S)
* 3: Start filtering when the primary comparator matches and stop filtering when the
* secondary comparator matches
*/
#define TRACE_MATCH_MODE 0x00000003U
#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
@@ -404,9 +452,11 @@ extern "C" {
#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU
#define TRACE_RESYNC_PROLONGED_S 0
/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
* Configures the synchronization mode: \\0: Disable the synchronization counter \\1:
* Invalid \\2: Synchronization counter counts by packet \\3: Synchronization counter
* counts by cycle\\
* Configures the synchronization mode:
* 0: Disable the synchronization counter
* 1: Invalid
* 2: Synchronization counter counts by packet
* 3: Synchronization counter counts by cycle
*/
#define TRACE_RESYNC_MODE 0x00000003U
#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
@@ -418,8 +468,12 @@ extern "C" {
*/
#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
* Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4
* \\4:INCR8 \\Others:Invalid
* Configures the AHB burst mode.
* 0: SINGLE
* 1: INCR(length not defined)
* 2:INCR4
* 4:INCR8
* Others:Invalid
*/
#define TRACE_HBURST 0x00000007U
#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S)
@@ -438,9 +492,10 @@ extern "C" {
*/
#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44)
/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures register clock gating. \\0: Support clock only when the application
* writes registers to save power. \\1:Always force the clock on for registers \\ This
* bit doesn't affect register access.
* Configures register clock gating.
* 0: Support clock only when the application writes registers to save power.
* 1:Always force the clock on for registers
* This bit doesn't affect register access.
*/
#define TRACE_CLK_EN (BIT(0))
#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S)

163
components/soc/esp32c5/register/soc/trace_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -58,9 +58,9 @@ typedef union {
/** mem_current_addr_update : WT; bitpos: [0]; default: 0;
* Configures whether to update the value of
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\
* 0: Not update\\
* 1: Update\\
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
* 0: Not update
* 1: Update
*/
uint32_t mem_current_addr_update:1;
uint32_t reserved_1:31;
@@ -76,12 +76,17 @@ typedef union {
typedef union {
struct {
/** fifo_empty : RO; bitpos: [0]; default: 1;
* Represent whether the FIFO is empty. \\1: Empty \\0: Not empty
* Represent whether the FIFO is empty.
* 1: Empty
* 0: Not empty
*/
uint32_t fifo_empty:1;
/** work_status : RO; bitpos: [2:1]; default: 0;
* Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
* state because hart is halted or in reset \\3: Lost state\\
* Represent the state of the encoder:
* 0: Idle state
* 1: Working state
* 2: Wait state because hart is halted or in reset
* 3: Lost state
*/
uint32_t work_status:2;
uint32_t reserved_3:29;
@@ -153,20 +158,27 @@ typedef union {
typedef union {
struct {
/** trigger_on : WT; bitpos: [0]; default: 0;
* Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\
* Configure whether to enable the encoder.
* 0: Invalid
* 1: Enable
*/
uint32_t trigger_on:1;
/** trigger_off : WT; bitpos: [1]; default: 0;
* Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\
* Configure whether to disable the encoder.
* 0: Invalid
* 1: Disable
*/
uint32_t trigger_off:1;
/** mem_loop : R/W; bitpos: [2]; default: 1;
* Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\
* Configure the memory writing mode.
* 0: Non-loop mode.
* 1: Loop mode
*/
uint32_t mem_loop:1;
/** restart_ena : R/W; bitpos: [3]; default: 1;
* Configure whether or not enable automatic restart function for the encoder.\\0:
* Disable\\1: Enable\\
* Configure whether or not enable automatic restart function for the encoder.
* 0: Disable
* 1: Enable
*/
uint32_t restart_ena:1;
uint32_t reserved_4:28;
@@ -180,31 +192,42 @@ typedef union {
typedef union {
struct {
/** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
* Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\
* Configure whether to enable the trigger signal.
* 0: Disable
* 1:enable
*/
uint32_t dm_trigger_ena:1;
/** reset_ena : R/W; bitpos: [1]; default: 0;
* Configure whether to reset, when enabled, if cpu have reset, the encoder will
* output a packet to report the address of the last instruction, and upon reset
* deassertion, the encoder start again.\\0: Disable\\0: Enable\\
* deassertion, the encoder start again.
* 0: Disable
* 0: Enable
*/
uint32_t reset_ena:1;
/** halt_ena : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\
* Configure whether to enable the halt signal.
* 1: Disable
* 1: Enable
*/
uint32_t halt_ena:1;
/** stall_ena : R/W; bitpos: [3]; default: 0;
* Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\
* Configure whether to enable the stall signal.
* 0: Disable.
* 1: Enable
*/
uint32_t stall_ena:1;
/** full_address : R/W; bitpos: [4]; default: 0;
* Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\
* Configure the address mode.
* 0: Delta address mode.
* 1: Full address mode.
*/
uint32_t full_address:1;
/** implicit_except : R/W; bitpos: [5]; default: 0;
* Configure whether or not enable implicit exception mode. When enabled,, do not sent
* exception address, only exception cause in exception packets.\\1: enabled\\0:
* disabled\\
* exception address, only exception cause in exception packets.
* 1: enabled
* 0: disabled
*/
uint32_t implicit_except:1;
uint32_t reserved_6:26;
@@ -218,30 +241,36 @@ typedef union {
typedef union {
struct {
/** filter_en : R/W; bitpos: [0]; default: 0;
* Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable
* Configure whether to enable filtering.
* 0: Disable, always match.
* 1: Enable
*/
uint32_t filter_en:1;
/** match_comp : R/W; bitpos: [1]; default: 0;
* Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable,
* the comparator must be high in order for the filter to match
* Configure whether to enable the comparator match mode.
* 0: Disable
* 1: Enable, the comparator must be high in order for the filter to match
*/
uint32_t match_comp:1;
/** match_privilege : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable,
* match privilege levels specified by
* Configure whether to enable the privilege match mode.
* 0: Disable
* 1: Enable, match privilege levels specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
*/
uint32_t match_privilege:1;
/** match_ecause : R/W; bitpos: [3]; default: 0;
* Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start
* matching from exception cause codes specified by
* Configure whether to enable ecause match mode.
* 0: Disable
* 1: Enable, start matching from exception cause codes specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
* matching upon return from the 1st matching exception.
*/
uint32_t match_ecause:1;
/** match_interrupt : R/W; bitpos: [4]; default: 0;
* Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable,
* start matching from a trap with the interrupt level codes specified by
* Configure whether to enable the interrupt match mode.
* 0: Disable
* 1: Enable, start matching from a trap with the interrupt level codes specified by
* \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
* stop matching upon return from the 1st matching trap.
*/
@@ -258,14 +287,16 @@ typedef union {
struct {
/** match_choice_privilege : R/W; bitpos: [0]; default: 0;
* Configures the privilege level for matching. Valid only when
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User
* mode. \\1: Machine mode
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
* 0: User mode.
* 1: Machine mode
*/
uint32_t match_choice_privilege:1;
/** match_value_interrupt : R/W; bitpos: [1]; default: 0;
* Configures the interrupt level for match. Valid only when when
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0:
* itype=2. \\0: itype=2.
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
* 0: itype=2.
* 0: itype=2.
*/
uint32_t match_value_interrupt:1;
/** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
@@ -283,32 +314,47 @@ typedef union {
typedef union {
struct {
/** p_input : R/W; bitpos: [0]; default: 0;
* Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\
* Configures the input of the primary comparator for matching:
* 0: iaddr
* 1: tval
*/
uint32_t p_input:1;
uint32_t reserved_1:1;
/** p_function : R/W; bitpos: [4:2]; default: 0;
* Configures the function for the primary comparator. \\0: Equal, \\1: Not equal,
* \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
* equal, \\Other: Always match
* Configures the function for the primary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
uint32_t p_function:3;
/** p_notify : R/W; bitpos: [5]; default: 0;
* Configure whether to explicitly report an instruction address matched against the
* primary comparator. \\0:Not report \\1:Report
* primary comparator.
* 0:Not report
* 1:Report
*/
uint32_t p_notify:1;
uint32_t reserved_6:2;
/** s_input : R/W; bitpos: [8]; default: 0;
* Configures the input of the secondary comparator for matching: \\0: iaddr \\1:
* tval\\
* Configures the input of the secondary comparator for matching:
* 0: iaddr
* 1: tval
*/
uint32_t s_input:1;
uint32_t reserved_9:1;
/** s_function : R/W; bitpos: [12:10]; default: 0;
* Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal,
* \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
* equal, \\Other: Always match
* Configures the function for the secondary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
uint32_t s_function:3;
/** s_notify : R/W; bitpos: [13]; default: 0;
@@ -318,10 +364,12 @@ typedef union {
uint32_t s_notify:1;
uint32_t reserved_14:2;
/** match_mode : R/W; bitpos: [17:16]; default: 0;
* Configures the comparator match mode: \\0: Only the primary comparator matches \\1:
* Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or
* secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary
* comparator matches and stop filtering when the secondary comparator matches\\
* Configures the comparator match mode:
* 0: Only the primary comparator matches
* 1: Both primary and secondary comparator matches(P\&\&S)
* 2:Neither primary or secondary comparator matches !(P\&\&S)
* 3: Start filtering when the primary comparator matches and stop filtering when the
* secondary comparator matches
*/
uint32_t match_mode:2;
uint32_t reserved_18:14;
@@ -365,9 +413,11 @@ typedef union {
*/
uint32_t resync_prolonged:24;
/** resync_mode : R/W; bitpos: [25:24]; default: 0;
* Configures the synchronization mode: \\0: Disable the synchronization counter \\1:
* Invalid \\2: Synchronization counter counts by packet \\3: Synchronization counter
* counts by cycle\\
* Configures the synchronization mode:
* 0: Disable the synchronization counter
* 1: Invalid
* 2: Synchronization counter counts by packet
* 3: Synchronization counter counts by cycle
*/
uint32_t resync_mode:2;
uint32_t reserved_26:6;
@@ -381,8 +431,12 @@ typedef union {
typedef union {
struct {
/** hburst : R/W; bitpos: [2:0]; default: 0;
* Configures the AHB burst mode. \\0: SIGNAL \\1: INCR(length not defined) \\2:INCR4
* \\4:INCR8 \\Others:Invalid
* Configures the AHB burst mode.
* 0: SINGLE
* 1: INCR(length not defined)
* 2:INCR4
* 4:INCR8
* Others:Invalid
*/
uint32_t hburst:3;
/** max_incr : R/W; bitpos: [5:3]; default: 0;
@@ -402,9 +456,10 @@ typedef union {
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures register clock gating. \\0: Support clock only when the application
* writes registers to save power. \\1:Always force the clock on for registers \\ This
* bit doesn't affect register access.
* Configures register clock gating.
* 0: Support clock only when the application writes registers to save power.
* 1:Always force the clock on for registers
* This bit doesn't affect register access.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;

388
components/soc/esp32c5/register/soc/uart_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,7 +16,7 @@ extern "C" {
*/
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
* Represents the data UART $n read from FIFO.\\
* Represents the data UART $n read from FIFO.
* Measurement unit: byte.
*/
#define UART_RXFIFO_RD_BYTE 0x000000FFU
@@ -628,16 +628,17 @@ extern "C" {
*/
#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
* Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
* clock cycle.\\Pulses whose width is lower than this value will be ignored.
* Configures the width of a pulse to be filtered.
* Measurement unit: UART Core's clock cycle.
* Pulses whose width is lower than this value will be ignored.
*/
#define UART_GLITCH_FILT 0x000000FFU
#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
#define UART_GLITCH_FILT_V 0x000000FFU
#define UART_GLITCH_FILT_S 0
/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable RX signal filter.\\
* 0: Disable\\
* Configures whether or not to enable RX signal filter.
* 0: Disable
* 1: Enable
*/
#define UART_GLITCH_FILT_EN (BIT(8))
@@ -711,204 +712,202 @@ extern "C" {
*/
#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
/** UART_PARITY : R/W; bitpos: [0]; default: 0;
* Configures the parity check mode.\\
* 0: Even parity\\
* 1: Odd parity\\
* Configures the parity check mode.
* 0: Even parity
* 1: Odd parity
*/
#define UART_PARITY (BIT(0))
#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S)
#define UART_PARITY_V 0x00000001U
#define UART_PARITY_S 0
/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enable UART parity check.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART parity check.
* 0: Disable
* 1: Enable
*/
#define UART_PARITY_EN (BIT(1))
#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S)
#define UART_PARITY_EN_V 0x00000001U
#define UART_PARITY_EN_S 1
/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
* Configures the number of data bits.\\
* 0: 5 bits\\
* 1: 6 bits\\
* 2: 7 bits\\
* 3: 8 bits\\
* Configures the number of data bits.
* 0: 5 bits
* 1: 6 bits
* 2: 7 bits
* 3: 8 bits
*/
#define UART_BIT_NUM 0x00000003U
#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S)
#define UART_BIT_NUM_V 0x00000003U
#define UART_BIT_NUM_S 2
/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
* Configures the number of stop bits.\\
* 0: Invalid. No effect\\
* 1: 1 bits\\
* 2: 1.5 bits\\
* 3: 2 bits\\
* Configures the number of stop bits.
* 0: Invalid. No effect
* 1: 1 bits
* 2: 1.5 bits
* 3: 2 bits
*/
#define UART_STOP_BIT_NUM 0x00000003U
#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
#define UART_STOP_BIT_NUM_V 0x00000003U
#define UART_STOP_BIT_NUM_S 4
/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
* Configures whether or not to send NULL characters when finishing data
* transmission.\\
* 0: Not send\\
* 1: Send\\
* Configures whether or not to send NULL characters when finishing data transmission.
* 0: Not send
* 1: Send
*/
#define UART_TXD_BRK (BIT(6))
#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S)
#define UART_TXD_BRK_V 0x00000001U
#define UART_TXD_BRK_S 6
/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable IrDA loopback test.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable IrDA loopback test.
* 0: Disable
* 1: Enable
*/
#define UART_IRDA_DPLX (BIT(7))
#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
#define UART_IRDA_DPLX_V 0x00000001U
#define UART_IRDA_DPLX_S 7
/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable the IrDA transmitter.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the IrDA transmitter.
* 0: Disable
* 1: Enable
*/
#define UART_IRDA_TX_EN (BIT(8))
#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
#define UART_IRDA_TX_EN_V 0x00000001U
#define UART_IRDA_TX_EN_S 8
/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
* Configures the 11th bit of the IrDA transmitter.\\
* 0: This bit is 0.\\
* 1: This bit is the same as the 10th bit.\\
* Configures the 11th bit of the IrDA transmitter.
* 0: This bit is 0.
* 1: This bit is the same as the 10th bit.
*/
#define UART_IRDA_WCTL (BIT(9))
#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
#define UART_IRDA_WCTL_V 0x00000001U
#define UART_IRDA_WCTL_S 9
/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
* Configures whether or not to invert the level of the IrDA transmitter.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of the IrDA transmitter.
* 0: Not invert
* 1: Invert
*/
#define UART_IRDA_TX_INV (BIT(10))
#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
#define UART_IRDA_TX_INV_V 0x00000001U
#define UART_IRDA_TX_INV_S 10
/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the level of the IrDA receiver.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of the IrDA receiver.
* 0: Not invert
* 1: Invert
*/
#define UART_IRDA_RX_INV (BIT(11))
#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
#define UART_IRDA_RX_INV_V 0x00000001U
#define UART_IRDA_RX_INV_S 11
/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
* Configures whether or not to enable UART loopback test.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART loopback test.
* 0: Disable
* 1: Enable
*/
#define UART_LOOPBACK (BIT(12))
#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S)
#define UART_LOOPBACK_V 0x00000001U
#define UART_LOOPBACK_S 12
/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
* Configures whether or not to enable flow control for the transmitter.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable flow control for the transmitter.
* 0: Disable
* 1: Enable
*/
#define UART_TX_FLOW_EN (BIT(13))
#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
#define UART_TX_FLOW_EN_V 0x00000001U
#define UART_TX_FLOW_EN_S 13
/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
* Configures whether or not to enable IrDA protocol.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable IrDA protocol.
* 0: Disable
* 1: Enable
*/
#define UART_IRDA_EN (BIT(14))
#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S)
#define UART_IRDA_EN_V 0x00000001U
#define UART_IRDA_EN_S 14
/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
* Configures whether or not to invert the level of UART RXD signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART RXD signal.
* 0: Not invert
* 1: Invert
*/
#define UART_RXD_INV (BIT(15))
#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S)
#define UART_RXD_INV_V 0x00000001U
#define UART_RXD_INV_S 15
/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
* Configures whether or not to invert the level of UART TXD signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART TXD signal.
* 0: Not invert
* 1: Invert
*/
#define UART_TXD_INV (BIT(16))
#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S)
#define UART_TXD_INV_V 0x00000001U
#define UART_TXD_INV_S 16
/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
* Configures whether or not to disable data overflow detection for the UART
* receiver.\\
* 0: Enable\\
* 1: Disable\\
* Configures whether or not to disable data overflow detection for the UART receiver.
* 0: Enable
* 1: Disable
*/
#define UART_DIS_RX_DAT_OVF (BIT(17))
#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
#define UART_DIS_RX_DAT_OVF_V 0x00000001U
#define UART_DIS_RX_DAT_OVF_S 17
/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
* Configures whether or not to store the received data with errors into FIFO.\\
* 0: Store\\
* 1: Not store\\
* Configures whether or not to store the received data with errors into FIFO.
* 0: Store
* 1: Not store
*/
#define UART_ERR_WR_MASK (BIT(18))
#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
#define UART_ERR_WR_MASK_V 0x00000001U
#define UART_ERR_WR_MASK_S 18
/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
* Configures whether or not to enable baud rate detection.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable baud rate detection.
* 0: Disable
* 1: Enable
*/
#define UART_AUTOBAUD_EN (BIT(19))
#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
#define UART_AUTOBAUD_EN_V 0x00000001U
#define UART_AUTOBAUD_EN_S 19
/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable clock gating for UART memory.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable clock gating for UART memory.
* 0: Disable
* 1: Enable
*/
#define UART_MEM_CLK_EN (BIT(20))
#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
#define UART_MEM_CLK_EN_V 0x00000001U
#define UART_MEM_CLK_EN_S 20
/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
* Configures the RTS signal used in software flow control.\\
* 0: The UART transmitter is allowed to send data.\\
* 1: The UART transmitted is not allowed to send data.\\
* Configures the RTS signal used in software flow control.
* 0: The UART transmitter is allowed to send data.
* 1: The UART transmitted is not allowed to send data.
*/
#define UART_SW_RTS (BIT(21))
#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S)
#define UART_SW_RTS_V 0x00000001U
#define UART_SW_RTS_S 21
/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
* Configures whether or not to reset the UART RX FIFO.\\
* 0: Not reset\\
* 1: Reset\\
* Configures whether or not to reset the UART RX FIFO.
* 0: Not reset
* 1: Reset
*/
#define UART_RXFIFO_RST (BIT(22))
#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
#define UART_RXFIFO_RST_V 0x00000001U
#define UART_RXFIFO_RST_S 22
/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
* Configures whether or not to reset the UART TX FIFO.\\
* 0: Not reset\\
* 1: Reset\\
* Configures whether or not to reset the UART TX FIFO.
* 0: Not reset
* 1: Reset
*/
#define UART_TXFIFO_RST (BIT(23))
#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
@@ -920,68 +919,70 @@ extern "C" {
*/
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
* Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
* Configures the threshold for RX FIFO being full.
* Measurement unit: byte.
*/
#define UART_RXFIFO_FULL_THRHD 0x000000FFU
#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU
#define UART_RXFIFO_FULL_THRHD_S 0
/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
* Configures the threshold for TX FIFO being empty.\\Measurement unit: byte.
* Configures the threshold for TX FIFO being empty.
* Measurement unit: byte.
*/
#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU
#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU
#define UART_TXFIFO_EMPTY_THRHD_S 8
/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
* Configures whether or not to invert the level of UART CTS signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART CTS signal.
* 0: Not invert
* 1: Invert
*/
#define UART_CTS_INV (BIT(16))
#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S)
#define UART_CTS_INV_V 0x00000001U
#define UART_CTS_INV_S 16
/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
* Configures whether or not to invert the level of UART DSR signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART DSR signal.
* 0: Not invert
* 1: Invert
*/
#define UART_DSR_INV (BIT(17))
#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S)
#define UART_DSR_INV_V 0x00000001U
#define UART_DSR_INV_S 17
/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
* Configures whether or not to invert the level of UART RTS signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART RTS signal.
* 0: Not invert
* 1: Invert
*/
#define UART_RTS_INV (BIT(18))
#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S)
#define UART_RTS_INV_V 0x00000001U
#define UART_RTS_INV_S 18
/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
* Configures whether or not to invert the level of UART DTR signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART DTR signal.
* 0: Not invert
* 1: Invert
*/
#define UART_DTR_INV (BIT(19))
#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S)
#define UART_DTR_INV_V 0x00000001U
#define UART_DTR_INV_S 19
/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
* Configures the DTR signal used in software flow control.\\
* 0: Data to be transmitted is not ready.\\
* 1: Data to be transmitted is ready.\\
* Configures the DTR signal used in software flow control.
* 0: Data to be transmitted is not ready.
* 1: Data to be transmitted is ready.
*/
#define UART_SW_DTR (BIT(20))
#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S)
#define UART_SW_DTR_V 0x00000001U
#define UART_SW_DTR_S 20
/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
* Configures clock gating.\\
* 0: Support clock only when the application writes registers.\\
* 1: Always force the clock on for registers.\\
* Configures clock gating.
* 0: Support clock only when the application writes registers.
* 1: Always force the clock on for registers.
*/
#define UART_CLK_EN (BIT(21))
#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S)
@@ -994,16 +995,17 @@ extern "C" {
#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
* Configures the maximum number of data bytes that can be received during hardware
* flow control.\\Measurement unit: byte.
* flow control.
* Measurement unit: byte.
*/
#define UART_RX_FLOW_THRHD 0x000000FFU
#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
#define UART_RX_FLOW_THRHD_V 0x000000FFU
#define UART_RX_FLOW_THRHD_S 0
/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable the UART receiver.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the UART receiver.
* 0: Disable
* 1: Enable
*/
#define UART_RX_FLOW_EN (BIT(8))
#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
@@ -1081,20 +1083,20 @@ extern "C" {
#define UART_WK_CHAR_NUM_V 0x00000007U
#define UART_WK_CHAR_NUM_S 18
/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
* Configures whether or not to mask wakeup characters.\\
* 0: Not mask\\
* 1: Mask\\
* Configures whether or not to mask wakeup characters.
* 0: Not mask
* 1: Mask
*/
#define UART_WK_CHAR_MASK 0x0000001FU
#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
#define UART_WK_CHAR_MASK_V 0x0000001FU
#define UART_WK_CHAR_MASK_S 21
/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
* Configures which wakeup mode to select.\\
* 0: Mode 0\\
* 1: Mode 1\\
* 2: Mode 2\\
* 3: Mode 3\\
* Configures which wakeup mode to select.
* 0: Mode 0
* 1: Mode 1
* 2: Mode 2
* 3: Mode 3
*/
#define UART_WK_MODE_SEL 0x00000003U
#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
@@ -1121,64 +1123,63 @@ extern "C" {
#define UART_XOFF_CHAR_S 8
/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
* Configures whether the UART transmitter can send XON or XOFF characters when it is
* disabled.\\
* 0: Cannot send\\
* 1: Can send\\
* disabled.
* 0: Cannot send
* 1: Can send
*/
#define UART_XON_XOFF_STILL_SEND (BIT(16))
#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
#define UART_XON_XOFF_STILL_SEND_V 0x00000001U
#define UART_XON_XOFF_STILL_SEND_S 16
/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable software flow control.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable software flow control.
* 0: Disable
* 1: Enable
*/
#define UART_SW_FLOW_CON_EN (BIT(17))
#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
#define UART_SW_FLOW_CON_EN_V 0x00000001U
#define UART_SW_FLOW_CON_EN_S 17
/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
* Configures whether or not to remove flow control characters from the received
* data.\\
* 0: Not move\\
* 1: Move\\
* Configures whether or not to remove flow control characters from the received data.
* 0: Not move
* 1: Move
*/
#define UART_XONOFF_DEL (BIT(18))
#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
#define UART_XONOFF_DEL_V 0x00000001U
#define UART_XONOFF_DEL_S 18
/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
* Configures whether the transmitter continues to sending data.\\
* 0: Not send\\
* 1: Send\\
* Configures whether the transmitter continues to sending data.
* 0: Not send
* 1: Send
*/
#define UART_FORCE_XON (BIT(19))
#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S)
#define UART_FORCE_XON_V 0x00000001U
#define UART_FORCE_XON_S 19
/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
* Configures whether or not to stop the transmitter from sending data.\\
* 0: Not stop\\
* 1: Stop\\
* Configures whether or not to stop the transmitter from sending data.
* 0: Not stop
* 1: Stop
*/
#define UART_FORCE_XOFF (BIT(20))
#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
#define UART_FORCE_XOFF_V 0x00000001U
#define UART_FORCE_XOFF_S 20
/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
* Configures whether or not to send XON characters.\\
* 0: Not send\\
* 1: Send\\
* Configures whether or not to send XON characters.
* 0: Not send
* 1: Send
*/
#define UART_SEND_XON (BIT(21))
#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S)
#define UART_SEND_XON_V 0x00000001U
#define UART_SEND_XON_S 21
/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
* Configures whether or not to send XOFF characters.\\
* 0: Not send\\
* 1: Send\\
* Configures whether or not to send XOFF characters.
* 0: Not send
* 1: Send
*/
#define UART_SEND_XOFF (BIT(22))
#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
@@ -1191,7 +1192,8 @@ extern "C" {
#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
* Configures the threshold for data in RX FIFO to send XON characters in software
* flow control.\\Measurement unit: byte.
* flow control.
* Measurement unit: byte.
*/
#define UART_XON_THRESHOLD 0x000000FFU
#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
@@ -1199,7 +1201,8 @@ extern "C" {
#define UART_XON_THRESHOLD_S 0
/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
* Configures the threshold for data in RX FIFO to send XOFF characters in software
* flow control.\\Measurement unit: byte.
* flow control.
* Measurement unit: byte.
*/
#define UART_XOFF_THRESHOLD 0x000000FFU
#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
@@ -1212,7 +1215,8 @@ extern "C" {
#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
* Configures the number of NULL characters to be sent after finishing data
* transmission.\\Valid only when UART_TXD_BRK is 1.
* transmission.
* Valid only when UART_TXD_BRK is 1.
*/
#define UART_TX_BRK_NUM 0x000000FFU
#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
@@ -1225,16 +1229,16 @@ extern "C" {
#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
* Configures the threshold to generate a frame end signal when the receiver takes
* more time to receive one data byte data.\\Measurement unit: bit time (the time to
* transmit 1 bit).
* more time to receive one data byte data.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_RX_IDLE_THRHD 0x000003FFU
#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
#define UART_RX_IDLE_THRHD_V 0x000003FFU
#define UART_RX_IDLE_THRHD_S 0
/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
* Configures the interval between two data transfers.\\Measurement unit: bit time
* (the time to transmit 1 bit).
* Configures the interval between two data transfers.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_TX_IDLE_NUM 0x000003FFU
#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
@@ -1246,27 +1250,27 @@ extern "C" {
*/
#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable RS485 mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable RS485 mode.
* 0: Disable
* 1: Enable
*/
#define UART_RS485_EN (BIT(0))
#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S)
#define UART_RS485_EN_V 0x00000001U
#define UART_RS485_EN_S 0
/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
* Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\
* 0: Not add\\
* 1: Add\\
* Configures whether or not to add a turnaround delay of 1 bit before the start bit.
* 0: Not add
* 1: Add
*/
#define UART_DL0_EN (BIT(1))
#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S)
#define UART_DL0_EN_V 0x00000001U
#define UART_DL0_EN_S 1
/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
* Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\
* 0: Not add\\
* 1: Add\\
* Configures whether or not to add a turnaround delay of 1 bit after the stop bit.
* 0: Not add
* 1: Add
*/
#define UART_DL1_EN (BIT(2))
#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S)
@@ -1274,9 +1278,9 @@ extern "C" {
#define UART_DL1_EN_S 2
/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable the receiver for data reception when the
* transmitter is transmitting data in RS485 mode.\\
* 0: Disable\\
* 1: Enable\\
* transmitter is transmitting data in RS485 mode.
* 0: Disable
* 1: Enable
*/
#define UART_RS485TX_RX_EN (BIT(3))
#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
@@ -1284,25 +1288,25 @@ extern "C" {
#define UART_RS485TX_RX_EN_S 3
/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
* Configures whether to enable the RS485 transmitter for data transmission when the
* RS485 receiver is busy.\\
* 0: Disable\\
* 1: Enable\\
* RS485 receiver is busy.
* 0: Disable
* 1: Enable
*/
#define UART_RS485RXBY_TX_EN (BIT(4))
#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
#define UART_RS485RXBY_TX_EN_V 0x00000001U
#define UART_RS485RXBY_TX_EN_S 4
/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
* Configures the delay of internal data signals in the receiver.\\Measurement unit:
* bit time (the time to transmit 1 bit)..
* Configures the delay of internal data signals in the receiver.
* Measurement unit: bit time (the time to transmit 1 bit)..
*/
#define UART_RS485_RX_DLY_NUM (BIT(5))
#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
#define UART_RS485_RX_DLY_NUM_V 0x00000001U
#define UART_RS485_RX_DLY_NUM_S 5
/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
* Configures the delay of internal data signals in the transmitter.\\Measurement
* unit: bit time (the time to transmit 1 bit).
* Configures the delay of internal data signals in the transmitter.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_RS485_TX_DLY_NUM 0x0000000FU
#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
@@ -1314,8 +1318,8 @@ extern "C" {
*/
#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
* Configures the idle time before the receiver receives the first
* AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
* Configures the idle time before the receiver receives the first AT_CMD.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_PRE_IDLE_NUM 0x0000FFFFU
#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
@@ -1327,8 +1331,8 @@ extern "C" {
*/
#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
* Configures the interval between the last AT_CMD and subsequent data.\\Measurement
* unit: bit time (the time to transmit 1 bit).
* Configures the interval between the last AT_CMD and subsequent data.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_POST_IDLE_NUM 0x0000FFFFU
#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
@@ -1340,8 +1344,8 @@ extern "C" {
*/
#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
* Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
* (the time to transmit 1 bit).
* Configures the interval between two AT_CMD characters.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_RX_GAP_TOUT 0x0000FFFFU
#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
@@ -1391,9 +1395,9 @@ extern "C" {
*/
#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable UART receiver's timeout function.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART receiver's timeout function.
* 0: Disable
* 1: Enable
*/
#define UART_RX_TOUT_EN (BIT(0))
#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
@@ -1407,7 +1411,7 @@ extern "C" {
#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U
#define UART_RX_TOUT_FLOW_DIS_S 1
/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
* Configures the amount of time that the bus can remain idle before timeout.\\
* Configures the amount of time that the bus can remain idle before timeout.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
#define UART_RX_TOUT_THRHD 0x000003FFU
@@ -1504,7 +1508,8 @@ extern "C" {
#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* Represents the minimum duration time of a low-level pulse. It is used for baud rate
* detection.\\Measurement unit: APB_CLK clock cycle.
* detection.
* Measurement unit: APB_CLK clock cycle.
*/
#define UART_LOWPULSE_MIN_CNT 0x00000FFFU
#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
@@ -1517,7 +1522,8 @@ extern "C" {
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* Represents the maximum duration time for a high-level pulse. It is used for baud
* rate detection.\\Measurement unit: APB_CLK clock cycle.
* rate detection.
* Measurement unit: APB_CLK clock cycle.
*/
#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU
#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
@@ -1541,18 +1547,18 @@ extern "C" {
*/
#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable UART TX clock.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART TX clock.
* 0: Disable
* 1: Enable
*/
#define UART_TX_SCLK_EN (BIT(24))
#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
#define UART_TX_SCLK_EN_V 0x00000001U
#define UART_TX_SCLK_EN_S 24
/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
* Configures whether or not to enable UART RX clock.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART RX clock.
* 0: Disable
* 1: Enable
*/
#define UART_RX_SCLK_EN (BIT(25))
#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
@@ -1590,36 +1596,36 @@ extern "C" {
*/
#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
* Represents whether or not the APB TX asynchronous FIFO is full.\\
* 0: Not full\\
* 1: Full\\
* Represents whether or not the APB TX asynchronous FIFO is full.
* 0: Not full
* 1: Full
*/
#define UART_TX_AFIFO_FULL (BIT(0))
#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
#define UART_TX_AFIFO_FULL_V 0x00000001U
#define UART_TX_AFIFO_FULL_S 0
/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
* Represents whether or not the APB TX asynchronous FIFO is empty.\\
* 0: Not empty\\
* 1: Empty\\
* Represents whether or not the APB TX asynchronous FIFO is empty.
* 0: Not empty
* 1: Empty
*/
#define UART_TX_AFIFO_EMPTY (BIT(1))
#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
#define UART_TX_AFIFO_EMPTY_V 0x00000001U
#define UART_TX_AFIFO_EMPTY_S 1
/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
* Represents whether or not the APB RX asynchronous FIFO is full.\\
* 0: Not full\\
* 1: Full\\
* Represents whether or not the APB RX asynchronous FIFO is full.
* 0: Not full
* 1: Full
*/
#define UART_RX_AFIFO_FULL (BIT(2))
#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
#define UART_RX_AFIFO_FULL_V 0x00000001U
#define UART_RX_AFIFO_FULL_S 2
/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
* Represents whether or not the APB RX asynchronous FIFO is empty.\\
* 0: Not empty\\
* 1: Empty\\
* Represents whether or not the APB RX asynchronous FIFO is empty.
* 0: Not empty
* 1: Empty
*/
#define UART_RX_AFIFO_EMPTY (BIT(3))
#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
@@ -1631,9 +1637,9 @@ extern "C" {
*/
#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
* Configures whether or not to synchronize registers.\\
* 0: Not synchronize\\
* 1: Synchronize\\
* Configures whether or not to synchronize registers.
* 0: Not synchronize
* 1: Synchronize
*/
#define UART_REG_UPDATE (BIT(0))
#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S)

393
components/soc/esp32c5/register/soc/uart_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,11 +16,12 @@ extern "C" {
*/
typedef union {
struct {
/** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
* Represents the data UART $n read from FIFO.\\
/** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
* Represents the data UART $n read from FIFO.
* Measurement unit: byte.
*/
uint32_t rxfifo_rd_byte:32;
uint32_t rxfifo_rd_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} uart_fifo_reg_t;
@@ -50,9 +51,9 @@ typedef union {
typedef union {
struct {
/** rx_tout_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable UART receiver's timeout function.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART receiver's timeout function.
* 0: Disable
* 1: Enable
*/
uint32_t rx_tout_en:1;
/** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
@@ -60,7 +61,7 @@ typedef union {
*/
uint32_t rx_tout_flow_dis:1;
/** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
* Configures the amount of time that the bus can remain idle before timeout.\\
* Configures the amount of time that the bus can remain idle before timeout.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t rx_tout_thrhd:10;
@@ -458,13 +459,14 @@ typedef union {
typedef union {
struct {
/** glitch_filt : R/W; bitpos: [7:0]; default: 8;
* Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
* clock cycle.\\Pulses whose width is lower than this value will be ignored.
* Configures the width of a pulse to be filtered.
* Measurement unit: UART Core's clock cycle.
* Pulses whose width is lower than this value will be ignored.
*/
uint32_t glitch_filt:8;
/** glitch_filt_en : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable RX signal filter.\\
* 0: Disable\\
* Configures whether or not to enable RX signal filter.
* 0: Disable
* 1: Enable
*/
uint32_t glitch_filt_en:1;
@@ -479,141 +481,139 @@ typedef union {
typedef union {
struct {
/** parity : R/W; bitpos: [0]; default: 0;
* Configures the parity check mode.\\
* 0: Even parity\\
* 1: Odd parity\\
* Configures the parity check mode.
* 0: Even parity
* 1: Odd parity
*/
uint32_t parity:1;
/** parity_en : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enable UART parity check.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART parity check.
* 0: Disable
* 1: Enable
*/
uint32_t parity_en:1;
/** bit_num : R/W; bitpos: [3:2]; default: 3;
* Configures the number of data bits.\\
* 0: 5 bits\\
* 1: 6 bits\\
* 2: 7 bits\\
* 3: 8 bits\\
* Configures the number of data bits.
* 0: 5 bits
* 1: 6 bits
* 2: 7 bits
* 3: 8 bits
*/
uint32_t bit_num:2;
/** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
* Configures the number of stop bits.\\
* 0: Invalid. No effect\\
* 1: 1 bits\\
* 2: 1.5 bits\\
* 3: 2 bits\\
* Configures the number of stop bits.
* 0: Invalid. No effect
* 1: 1 bits
* 2: 1.5 bits
* 3: 2 bits
*/
uint32_t stop_bit_num:2;
/** txd_brk : R/W; bitpos: [6]; default: 0;
* Configures whether or not to send NULL characters when finishing data
* transmission.\\
* 0: Not send\\
* 1: Send\\
* Configures whether or not to send NULL characters when finishing data transmission.
* 0: Not send
* 1: Send
*/
uint32_t txd_brk:1;
/** irda_dplx : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable IrDA loopback test.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable IrDA loopback test.
* 0: Disable
* 1: Enable
*/
uint32_t irda_dplx:1;
/** irda_tx_en : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable the IrDA transmitter.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the IrDA transmitter.
* 0: Disable
* 1: Enable
*/
uint32_t irda_tx_en:1;
/** irda_wctl : R/W; bitpos: [9]; default: 0;
* Configures the 11th bit of the IrDA transmitter.\\
* 0: This bit is 0.\\
* 1: This bit is the same as the 10th bit.\\
* Configures the 11th bit of the IrDA transmitter.
* 0: This bit is 0.
* 1: This bit is the same as the 10th bit.
*/
uint32_t irda_wctl:1;
/** irda_tx_inv : R/W; bitpos: [10]; default: 0;
* Configures whether or not to invert the level of the IrDA transmitter.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of the IrDA transmitter.
* 0: Not invert
* 1: Invert
*/
uint32_t irda_tx_inv:1;
/** irda_rx_inv : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the level of the IrDA receiver.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of the IrDA receiver.
* 0: Not invert
* 1: Invert
*/
uint32_t irda_rx_inv:1;
/** loopback : R/W; bitpos: [12]; default: 0;
* Configures whether or not to enable UART loopback test.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART loopback test.
* 0: Disable
* 1: Enable
*/
uint32_t loopback:1;
/** tx_flow_en : R/W; bitpos: [13]; default: 0;
* Configures whether or not to enable flow control for the transmitter.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable flow control for the transmitter.
* 0: Disable
* 1: Enable
*/
uint32_t tx_flow_en:1;
/** irda_en : R/W; bitpos: [14]; default: 0;
* Configures whether or not to enable IrDA protocol.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable IrDA protocol.
* 0: Disable
* 1: Enable
*/
uint32_t irda_en:1;
/** rxd_inv : R/W; bitpos: [15]; default: 0;
* Configures whether or not to invert the level of UART RXD signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART RXD signal.
* 0: Not invert
* 1: Invert
*/
uint32_t rxd_inv:1;
/** txd_inv : R/W; bitpos: [16]; default: 0;
* Configures whether or not to invert the level of UART TXD signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART TXD signal.
* 0: Not invert
* 1: Invert
*/
uint32_t txd_inv:1;
/** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
* Configures whether or not to disable data overflow detection for the UART
* receiver.\\
* 0: Enable\\
* 1: Disable\\
* Configures whether or not to disable data overflow detection for the UART receiver.
* 0: Enable
* 1: Disable
*/
uint32_t dis_rx_dat_ovf:1;
/** err_wr_mask : R/W; bitpos: [18]; default: 0;
* Configures whether or not to store the received data with errors into FIFO.\\
* 0: Store\\
* 1: Not store\\
* Configures whether or not to store the received data with errors into FIFO.
* 0: Store
* 1: Not store
*/
uint32_t err_wr_mask:1;
/** autobaud_en : R/W; bitpos: [19]; default: 0;
* Configures whether or not to enable baud rate detection.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable baud rate detection.
* 0: Disable
* 1: Enable
*/
uint32_t autobaud_en:1;
/** mem_clk_en : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable clock gating for UART memory.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable clock gating for UART memory.
* 0: Disable
* 1: Enable
*/
uint32_t mem_clk_en:1;
/** sw_rts : R/W; bitpos: [21]; default: 0;
* Configures the RTS signal used in software flow control.\\
* 0: The UART transmitter is allowed to send data.\\
* 1: The UART transmitted is not allowed to send data.\\
* Configures the RTS signal used in software flow control.
* 0: The UART transmitter is allowed to send data.
* 1: The UART transmitted is not allowed to send data.
*/
uint32_t sw_rts:1;
/** rxfifo_rst : R/W; bitpos: [22]; default: 0;
* Configures whether or not to reset the UART RX FIFO.\\
* 0: Not reset\\
* 1: Reset\\
* Configures whether or not to reset the UART RX FIFO.
* 0: Not reset
* 1: Reset
*/
uint32_t rxfifo_rst:1;
/** txfifo_rst : R/W; bitpos: [23]; default: 0;
* Configures whether or not to reset the UART TX FIFO.\\
* 0: Not reset\\
* 1: Reset\\
* Configures whether or not to reset the UART TX FIFO.
* 0: Not reset
* 1: Reset
*/
uint32_t txfifo_rst:1;
uint32_t reserved_24:8;
@@ -627,47 +627,49 @@ typedef union {
typedef union {
struct {
/** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
* Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
* Configures the threshold for RX FIFO being full.
* Measurement unit: byte.
*/
uint32_t rxfifo_full_thrhd:8;
/** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
* Configures the threshold for TX FIFO being empty.\\Measurement unit: byte.
* Configures the threshold for TX FIFO being empty.
* Measurement unit: byte.
*/
uint32_t txfifo_empty_thrhd:8;
/** cts_inv : R/W; bitpos: [16]; default: 0;
* Configures whether or not to invert the level of UART CTS signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART CTS signal.
* 0: Not invert
* 1: Invert
*/
uint32_t cts_inv:1;
/** dsr_inv : R/W; bitpos: [17]; default: 0;
* Configures whether or not to invert the level of UART DSR signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART DSR signal.
* 0: Not invert
* 1: Invert
*/
uint32_t dsr_inv:1;
/** rts_inv : R/W; bitpos: [18]; default: 0;
* Configures whether or not to invert the level of UART RTS signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART RTS signal.
* 0: Not invert
* 1: Invert
*/
uint32_t rts_inv:1;
/** dtr_inv : R/W; bitpos: [19]; default: 0;
* Configures whether or not to invert the level of UART DTR signal.\\
* 0: Not invert\\
* 1: Invert\\
* Configures whether or not to invert the level of UART DTR signal.
* 0: Not invert
* 1: Invert
*/
uint32_t dtr_inv:1;
/** sw_dtr : R/W; bitpos: [20]; default: 0;
* Configures the DTR signal used in software flow control.\\
* 0: Data to be transmitted is not ready.\\
* 1: Data to be transmitted is ready.\\
* Configures the DTR signal used in software flow control.
* 0: Data to be transmitted is not ready.
* 1: Data to be transmitted is ready.
*/
uint32_t sw_dtr:1;
/** clk_en : R/W; bitpos: [21]; default: 0;
* Configures clock gating.\\
* 0: Support clock only when the application writes registers.\\
* 1: Always force the clock on for registers.\\
* Configures clock gating.
* 0: Support clock only when the application writes registers.
* 1: Always force the clock on for registers.
*/
uint32_t clk_en:1;
uint32_t reserved_22:10;
@@ -682,13 +684,14 @@ typedef union {
struct {
/** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
* Configures the maximum number of data bytes that can be received during hardware
* flow control.\\Measurement unit: byte.
* flow control.
* Measurement unit: byte.
*/
uint32_t rx_flow_thrhd:8;
/** rx_flow_en : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable the UART receiver.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the UART receiver.
* 0: Disable
* 1: Enable
*/
uint32_t rx_flow_en:1;
uint32_t reserved_9:23;
@@ -753,17 +756,17 @@ typedef union {
*/
uint32_t wk_char_num:3;
/** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
* Configures whether or not to mask wakeup characters.\\
* 0: Not mask\\
* 1: Mask\\
* Configures whether or not to mask wakeup characters.
* 0: Not mask
* 1: Mask
*/
uint32_t wk_char_mask:5;
/** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
* Configures which wakeup mode to select.\\
* 0: Mode 0\\
* 1: Mode 1\\
* 2: Mode 2\\
* 3: Mode 3\\
* Configures which wakeup mode to select.
* 0: Mode 0
* 1: Mode 1
* 2: Mode 2
* 3: Mode 3
*/
uint32_t wk_mode_sel:2;
uint32_t reserved_28:4;
@@ -786,46 +789,45 @@ typedef union {
uint32_t xoff_character:8;
/** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
* Configures whether the UART transmitter can send XON or XOFF characters when it is
* disabled.\\
* 0: Cannot send\\
* 1: Can send\\
* disabled.
* 0: Cannot send
* 1: Can send
*/
uint32_t xon_xoff_still_send:1;
/** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable software flow control.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable software flow control.
* 0: Disable
* 1: Enable
*/
uint32_t sw_flow_con_en:1;
/** xonoff_del : R/W; bitpos: [18]; default: 0;
* Configures whether or not to remove flow control characters from the received
* data.\\
* 0: Not move\\
* 1: Move\\
* Configures whether or not to remove flow control characters from the received data.
* 0: Not move
* 1: Move
*/
uint32_t xonoff_del:1;
/** force_xon : R/W; bitpos: [19]; default: 0;
* Configures whether the transmitter continues to sending data.\\
* 0: Not send\\
* 1: Send\\
* Configures whether the transmitter continues to sending data.
* 0: Not send
* 1: Send
*/
uint32_t force_xon:1;
/** force_xoff : R/W; bitpos: [20]; default: 0;
* Configures whether or not to stop the transmitter from sending data.\\
* 0: Not stop\\
* 1: Stop\\
* Configures whether or not to stop the transmitter from sending data.
* 0: Not stop
* 1: Stop
*/
uint32_t force_xoff:1;
/** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
* Configures whether or not to send XON characters.\\
* 0: Not send\\
* 1: Send\\
* Configures whether or not to send XON characters.
* 0: Not send
* 1: Send
*/
uint32_t send_xon:1;
/** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
* Configures whether or not to send XOFF characters.\\
* 0: Not send\\
* 1: Send\\
* Configures whether or not to send XOFF characters.
* 0: Not send
* 1: Send
*/
uint32_t send_xoff:1;
uint32_t reserved_23:9;
@@ -840,12 +842,14 @@ typedef union {
struct {
/** xon_threshold : R/W; bitpos: [7:0]; default: 0;
* Configures the threshold for data in RX FIFO to send XON characters in software
* flow control.\\Measurement unit: byte.
* flow control.
* Measurement unit: byte.
*/
uint32_t xon_threshold:8;
/** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
* Configures the threshold for data in RX FIFO to send XOFF characters in software
* flow control.\\Measurement unit: byte.
* flow control.
* Measurement unit: byte.
*/
uint32_t xoff_threshold:8;
uint32_t reserved_16:16;
@@ -860,7 +864,8 @@ typedef union {
struct {
/** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
* Configures the number of NULL characters to be sent after finishing data
* transmission.\\Valid only when UART_TXD_BRK is 1.
* transmission.
* Valid only when UART_TXD_BRK is 1.
*/
uint32_t tx_brk_num:8;
uint32_t reserved_8:24;
@@ -875,13 +880,13 @@ typedef union {
struct {
/** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
* Configures the threshold to generate a frame end signal when the receiver takes
* more time to receive one data byte data.\\Measurement unit: bit time (the time to
* transmit 1 bit).
* more time to receive one data byte data.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t rx_idle_thrhd:10;
/** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
* Configures the interval between two data transfers.\\Measurement unit: bit time
* (the time to transmit 1 bit).
* Configures the interval between two data transfers.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t tx_idle_num:10;
uint32_t reserved_20:12;
@@ -895,45 +900,45 @@ typedef union {
typedef union {
struct {
/** rs485_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable RS485 mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable RS485 mode.
* 0: Disable
* 1: Enable
*/
uint32_t rs485_en:1;
/** dl0_en : R/W; bitpos: [1]; default: 0;
* Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\
* 0: Not add\\
* 1: Add\\
* Configures whether or not to add a turnaround delay of 1 bit before the start bit.
* 0: Not add
* 1: Add
*/
uint32_t dl0_en:1;
/** dl1_en : R/W; bitpos: [2]; default: 0;
* Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\
* 0: Not add\\
* 1: Add\\
* Configures whether or not to add a turnaround delay of 1 bit after the stop bit.
* 0: Not add
* 1: Add
*/
uint32_t dl1_en:1;
/** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable the receiver for data reception when the
* transmitter is transmitting data in RS485 mode.\\
* 0: Disable\\
* 1: Enable\\
* transmitter is transmitting data in RS485 mode.
* 0: Disable
* 1: Enable
*/
uint32_t rs485tx_rx_en:1;
/** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
* Configures whether to enable the RS485 transmitter for data transmission when the
* RS485 receiver is busy.\\
* 0: Disable\\
* 1: Enable\\
* RS485 receiver is busy.
* 0: Disable
* 1: Enable
*/
uint32_t rs485rxby_tx_en:1;
/** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
* Configures the delay of internal data signals in the receiver.\\Measurement unit:
* bit time (the time to transmit 1 bit)..
* Configures the delay of internal data signals in the receiver.
* Measurement unit: bit time (the time to transmit 1 bit)..
*/
uint32_t rs485_rx_dly_num:1;
/** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
* Configures the delay of internal data signals in the transmitter.\\Measurement
* unit: bit time (the time to transmit 1 bit).
* Configures the delay of internal data signals in the transmitter.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t rs485_tx_dly_num:4;
uint32_t reserved_10:22;
@@ -948,15 +953,15 @@ typedef union {
struct {
uint32_t reserved_0:24;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable UART TX clock.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART TX clock.
* 0: Disable
* 1: Enable
*/
uint32_t tx_sclk_en:1;
/** rx_sclk_en : R/W; bitpos: [25]; default: 1;
* Configures whether or not to enable UART RX clock.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable UART RX clock.
* 0: Disable
* 1: Enable
*/
uint32_t rx_sclk_en:1;
/** tx_rst_core : R/W; bitpos: [26]; default: 0;
@@ -1079,27 +1084,27 @@ typedef union {
typedef union {
struct {
/** tx_afifo_full : RO; bitpos: [0]; default: 0;
* Represents whether or not the APB TX asynchronous FIFO is full.\\
* 0: Not full\\
* 1: Full\\
* Represents whether or not the APB TX asynchronous FIFO is full.
* 0: Not full
* 1: Full
*/
uint32_t tx_afifo_full:1;
/** tx_afifo_empty : RO; bitpos: [1]; default: 1;
* Represents whether or not the APB TX asynchronous FIFO is empty.\\
* 0: Not empty\\
* 1: Empty\\
* Represents whether or not the APB TX asynchronous FIFO is empty.
* 0: Not empty
* 1: Empty
*/
uint32_t tx_afifo_empty:1;
/** rx_afifo_full : RO; bitpos: [2]; default: 0;
* Represents whether or not the APB RX asynchronous FIFO is full.\\
* 0: Not full\\
* 1: Full\\
* Represents whether or not the APB RX asynchronous FIFO is full.
* 0: Not full
* 1: Full
*/
uint32_t rx_afifo_full:1;
/** rx_afifo_empty : RO; bitpos: [3]; default: 1;
* Represents whether or not the APB RX asynchronous FIFO is empty.\\
* 0: Not empty\\
* 1: Empty\\
* Represents whether or not the APB RX asynchronous FIFO is empty.
* 0: Not empty
* 1: Empty
*/
uint32_t rx_afifo_empty:1;
uint32_t reserved_4:28;
@@ -1115,8 +1120,8 @@ typedef union {
typedef union {
struct {
/** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
* Configures the idle time before the receiver receives the first
* AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
* Configures the idle time before the receiver receives the first AT_CMD.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t pre_idle_num:16;
uint32_t reserved_16:16;
@@ -1130,8 +1135,8 @@ typedef union {
typedef union {
struct {
/** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
* Configures the interval between the last AT_CMD and subsequent data.\\Measurement
* unit: bit time (the time to transmit 1 bit).
* Configures the interval between the last AT_CMD and subsequent data.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t post_idle_num:16;
uint32_t reserved_16:16;
@@ -1145,8 +1150,8 @@ typedef union {
typedef union {
struct {
/** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
* Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
* (the time to transmit 1 bit).
* Configures the interval between two AT_CMD characters.
* Measurement unit: bit time (the time to transmit 1 bit).
*/
uint32_t rx_gap_tout:16;
uint32_t reserved_16:16;
@@ -1211,7 +1216,8 @@ typedef union {
struct {
/** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
* Represents the minimum duration time of a low-level pulse. It is used for baud rate
* detection.\\Measurement unit: APB_CLK clock cycle.
* detection.
* Measurement unit: APB_CLK clock cycle.
*/
uint32_t lowpulse_min_cnt:12;
uint32_t reserved_12:20;
@@ -1226,7 +1232,8 @@ typedef union {
struct {
/** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
* Represents the maximum duration time for a high-level pulse. It is used for baud
* rate detection.\\Measurement unit: APB_CLK clock cycle.
* rate detection.
* Measurement unit: APB_CLK clock cycle.
*/
uint32_t highpulse_min_cnt:12;
uint32_t reserved_12:20;
@@ -1269,9 +1276,9 @@ typedef union {
typedef union {
struct {
/** reg_update : R/W/SC; bitpos: [0]; default: 0;
* Configures whether or not to synchronize registers.\\
* 0: Not synchronize\\
* 1: Synchronize\\
* Configures whether or not to synchronize registers.
* 0: Not synchronize
* 1: Synchronize
*/
uint32_t reg_update:1;
uint32_t reserved_1:31;

305
components/soc/esp32c5/register/soc/uhci_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,7 +14,7 @@ extern "C" {
/** UHCI_CONF0_REG register
* UHCI configuration register
*/
#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
* Write 1 and then write 0 to reset the decoder state machine.
*/
@@ -30,57 +30,56 @@ extern "C" {
#define UHCI_RX_RST_V 0x00000001U
#define UHCI_RX_RST_S 1
/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7;
* Configures to select which uart to connect with UHCI.\\
* 0: UART0\\
* 1: UART1\\
* Configures to select which uart to connect with UHCI.
* 0: UART0
* 1: UART1
*/
#define UHCI_UART_SEL 0x00000007U
#define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S)
#define UHCI_UART_SEL_V 0x00000007U
#define UHCI_UART_SEL_S 2
/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
* Configures whether or not to separate the data frame with a special character.\\
* 0: Not separate\\
* 1: Separate\\
* Configures whether or not to separate the data frame with a special character.
* 0: Not separate
* 1: Separate
*/
#define UHCI_SEPER_EN (BIT(5))
#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
#define UHCI_SEPER_EN_V 0x00000001U
#define UHCI_SEPER_EN_S 5
/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
* Configures whether or not to encode the data packet with a formatting header.\\
* 0: Not use formatting header\\
* 1: Use formatting header\\
* Configures whether or not to encode the data packet with a formatting header.
* 0: Not use formatting header
* 1: Use formatting header
*/
#define UHCI_HEAD_EN (BIT(6))
#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
#define UHCI_HEAD_EN_V 0x00000001U
#define UHCI_HEAD_EN_S 6
/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
* Configures whether or not to enable the reception of the 16-bit CRC.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the reception of the 16-bit CRC.
* 0: Disable
* 1: Enable
*/
#define UHCI_CRC_REC_EN (BIT(7))
#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
#define UHCI_CRC_REC_EN_V 0x00000001U
#define UHCI_CRC_REC_EN_S 7
/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
* Configures whether or not to stop receiving data when UART is idle.\\
* 0: Not stop\\
* 1: Stop\\
* Configures whether or not to stop receiving data when UART is idle.
* 0: Not stop
* 1: Stop
*/
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U
#define UHCI_UART_IDLE_EOF_EN_S 8
/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
* Configures when the UHCI decoder stops receiving data.\\
* 0: Stops after receiving 0xC0\\
* Configures when the UHCI decoder stops receiving data.
* 0: Stops after receiving 0xC0
* 1: Stops when the number of received data bytes reach the specified value. When
* UHCI_HEAD_EN is 1, the specified value is the data length indicated by the UHCI
* packet header. when UHCI_HEAD_EN is 0, the specified value is the configured
* value.\\
* packet header. when UHCI_HEAD_EN is 0, the specified value is the configured value.
*/
#define UHCI_LEN_EOF_EN (BIT(9))
#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
@@ -88,18 +87,18 @@ extern "C" {
#define UHCI_LEN_EOF_EN_S 9
/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
* Configures whether or not to enable data integrity check by appending a 16 bit
* CCITT-CRC to the end of the data.\\
* 0: Disable\\
* 1: Enable\\
* CCITT-CRC to the end of the data.
* 0: Disable
* 1: Enable
*/
#define UHCI_ENCODE_CRC_EN (BIT(10))
#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
#define UHCI_ENCODE_CRC_EN_V 0x00000001U
#define UHCI_ENCODE_CRC_EN_S 10
/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
* Configures clock gating.\\
* 0: Support clock only when the application writes registers.\\
* 1: Always force the clock on for registers.\\
* Configures clock gating.
* 0: Support clock only when the application writes registers.
* 1: Always force the clock on for registers.
*/
#define UHCI_CLK_EN (BIT(11))
#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
@@ -107,9 +106,9 @@ extern "C" {
#define UHCI_CLK_EN_S 11
/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
* Configures whether or not to stop UHCI from receiving data after UART has received
* a NULL frame.\\
* 0: Not stop\\
* 1: Stop\\
* a NULL frame.
* 0: Not stop
* 1: Stop
*/
#define UHCI_UART_RX_BRK_EOF_EN (BIT(12))
#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
@@ -119,7 +118,7 @@ extern "C" {
/** UHCI_INT_RAW_REG register
* Raw interrupt status
*/
#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4)
#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of UHCI_RX_START_INT.
*/
@@ -187,7 +186,7 @@ extern "C" {
/** UHCI_INT_ST_REG register
* Masked interrupt status
*/
#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8)
#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of UHCI_RX_START_INT.
*/
@@ -255,7 +254,7 @@ extern "C" {
/** UHCI_INT_ENA_REG register
* Interrupt enable bits
*/
#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xc)
#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable UHCI_RX_START_INT.
*/
@@ -323,7 +322,7 @@ extern "C" {
/** UHCI_INT_CLR_REG register
* Interrupt clear bits
*/
#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10)
#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear UHCI_RX_START_INT.
*/
@@ -391,12 +390,12 @@ extern "C" {
/** UHCI_CONF1_REG register
* UHCI configuration register
*/
#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14)
#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable header checksum validation when UHCI receives a
* data packet.\\
* 0: Disable\\
* 1: Enable\\
* data packet.
* 0: Disable
* 1: Enable
*/
#define UHCI_CHECK_SUM_EN (BIT(0))
#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
@@ -404,19 +403,19 @@ extern "C" {
#define UHCI_CHECK_SUM_EN_S 0
/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
* Configures whether or not to enable the sequence number check when UHCI receives a
* data packet.\\
* 0: Disable\\
* 1: Enable\\
* data packet.
* 0: Disable
* 1: Enable
*/
#define UHCI_CHECK_SEQ_EN (BIT(1))
#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
#define UHCI_CHECK_SEQ_EN_V 0x00000001U
#define UHCI_CHECK_SEQ_EN_S 1
/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable CRC calculation.\\
* 0: Disable\\
* 1: Enable\\
* Valid only when the Data Integrity Check Present bit in UHCI packet is 1.\\
* Configures whether or not to enable CRC calculation.
* 0: Disable
* 1: Enable
* Valid only when the Data Integrity Check Present bit in UHCI packet is 1.
*/
#define UHCI_CRC_DISABLE (BIT(2))
#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
@@ -424,18 +423,18 @@ extern "C" {
#define UHCI_CRC_DISABLE_S 2
/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
* Configures whether or not to save the packet header when UHCI receives a data
* packet.\\
* 0: Not save\\
* 1: Save\\
* packet.
* 0: Not save
* 1: Save
*/
#define UHCI_SAVE_HEAD (BIT(3))
#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
#define UHCI_SAVE_HEAD_V 0x00000001U
#define UHCI_SAVE_HEAD_S 3
/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
* Configures whether or not to encode the data packet with a checksum.\\
* 0: Not use checksum\\
* 1: Use checksum\\
* Configures whether or not to encode the data packet with a checksum.
* 0: Not use checksum
* 1: Use checksum
*/
#define UHCI_TX_CHECK_SUM_RE (BIT(4))
#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
@@ -443,19 +442,18 @@ extern "C" {
#define UHCI_TX_CHECK_SUM_RE_S 4
/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
* Configures whether or not to encode the data packet with an acknowledgment when a
* reliable packet is to be transmitted.\\
* 0: Not use acknowledgement\\
* 1: Use acknowledgement\\
* reliable packet is to be transmitted.
* 0: Not use acknowledgement
* 1: Use acknowledgement
*/
#define UHCI_TX_ACK_NUM_RE (BIT(5))
#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
#define UHCI_TX_ACK_NUM_RE_V 0x00000001U
#define UHCI_TX_ACK_NUM_RE_S 5
/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
* Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT
* state.\\
* 0: No\\
* 1: Yes\\
* Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT state.
* 0: No
* 1: Yes
*/
#define UHCI_WAIT_SW_START (BIT(7))
#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
@@ -472,17 +470,17 @@ extern "C" {
/** UHCI_STATE0_REG register
* UHCI receive status
*/
#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18)
#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
* Represents the error type when DMA has received a packet with error.\\
* 0: Invalid. No effect\\
* 1: Checksum error in the HCI packet\\
* 2: Sequence number error in the HCI packet\\
* 3: CRC bit error in the HCI packet\\
* Represents the error type when DMA has received a packet with error.
* 0: Invalid. No effect
* 1: Checksum error in the HCI packet
* 2: Sequence number error in the HCI packet
* 3: CRC bit error in the HCI packet
* 4: 0xC0 is found but the received HCI packet is not complete\
* 5: 0xC0 is not found when the HCI packet has been received\\
* 6: CRC check error\\
* 7: Invalid. No effect\\
* 5: 0xC0 is not found when the HCI packet has been received
* 6: CRC check error
* 7: Invalid. No effect
*/
#define UHCI_RX_ERR_CAUSE 0x00000007U
#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
@@ -499,7 +497,7 @@ extern "C" {
/** UHCI_STATE1_REG register
* UHCI transmit status
*/
#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1c)
#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
* Represents the UHCI encoder status.
*/
@@ -511,20 +509,20 @@ extern "C" {
/** UHCI_ESCAPE_CONF_REG register
* Escape character configuration
*/
#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20)
#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
* Configures whether or not to decode character 0xC0 when DMA receives data.\\
* 0: Not decode\\
* 1: Decode\\
* Configures whether or not to decode character 0xC0 when DMA receives data.
* 0: Not decode
* 1: Decode
*/
#define UHCI_TX_C0_ESC_EN (BIT(0))
#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
#define UHCI_TX_C0_ESC_EN_V 0x00000001U
#define UHCI_TX_C0_ESC_EN_S 0
/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
* Configures whether or not to decode character 0xDB when DMA receives data.\\
* 0: Not decode\\
* 1: Decode\\
* Configures whether or not to decode character 0xDB when DMA receives data.
* 0: Not decode
* 1: Decode
*/
#define UHCI_TX_DB_ESC_EN (BIT(1))
#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
@@ -532,9 +530,9 @@ extern "C" {
#define UHCI_TX_DB_ESC_EN_S 1
/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
* Configures whether or not to decode flow control character 0x11 when DMA receives
* data.\\
* 0: Not decode\\
* 1: Decode\\
* data.
* 0: Not decode
* 1: Decode
*/
#define UHCI_TX_11_ESC_EN (BIT(2))
#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
@@ -542,29 +540,27 @@ extern "C" {
#define UHCI_TX_11_ESC_EN_S 2
/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
* Configures whether or not to decode flow control character 0x13 when DMA receives
* data.\\
* 0: Not decode\\
* 1: Decode\\
* data.
* 0: Not decode
* 1: Decode
*/
#define UHCI_TX_13_ESC_EN (BIT(3))
#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
#define UHCI_TX_13_ESC_EN_V 0x00000001U
#define UHCI_TX_13_ESC_EN_S 3
/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
* Configures whether or not to replace 0xC0 by special characters when DMA sends
* data.\\
* 0: Not replace\\
* 1: Replace\\
* Configures whether or not to replace 0xC0 by special characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
#define UHCI_RX_C0_ESC_EN (BIT(4))
#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
#define UHCI_RX_C0_ESC_EN_V 0x00000001U
#define UHCI_RX_C0_ESC_EN_S 4
/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
* Configures whether or not to replace 0xDB by special characters when DMA sends
* data.\\
* 0: Not replace\\
* 1: Replace\\
* Configures whether or not to replace 0xDB by special characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
#define UHCI_RX_DB_ESC_EN (BIT(5))
#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
@@ -572,9 +568,9 @@ extern "C" {
#define UHCI_RX_DB_ESC_EN_S 5
/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
* Configures whether or not to replace flow control character 0x11 by special
* characters when DMA sends data.\\
* 0: Not replace\\
* 1: Replace\\
* characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
#define UHCI_RX_11_ESC_EN (BIT(6))
#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
@@ -582,9 +578,9 @@ extern "C" {
#define UHCI_RX_11_ESC_EN_S 6
/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
* Configures whether or not to replace flow control character 0x13 by special
* characters when DMA sends data.\\
* 0: Not replace\\
* 1: Replace\\
* characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
#define UHCI_RX_13_ESC_EN (BIT(7))
#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
@@ -594,9 +590,10 @@ extern "C" {
/** UHCI_HUNG_CONF_REG register
* Timeout configuration
*/
#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24)
#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
* Configures the timeout value for DMA data reception.\\Measurement unit: ms.
* Configures the timeout value for DMA data reception.
* Measurement unit: ms.
*/
#define UHCI_TXFIFO_TIMEOUT 0x000000FFU
#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
@@ -610,16 +607,17 @@ extern "C" {
#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U
#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
* Configures whether or not to enable the data reception timeout for TX FIFO.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the data reception timeout for TX FIFO.
* 0: Disable
* 1: Enable
*/
#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U
#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
* Configures the timeout value for DMA to read data from RAM.\\Measurement unit: ms.
* Configures the timeout value for DMA to read data from RAM.
* Measurement unit: ms.
*/
#define UHCI_RXFIFO_TIMEOUT 0x000000FFU
#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
@@ -633,9 +631,9 @@ extern "C" {
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
* Configures whether or not to enable the DMA data transmission timeout.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the DMA data transmission timeout.
* 0: Disable
* 1: Enable
*/
#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
@@ -645,7 +643,7 @@ extern "C" {
/** UHCI_ACK_NUM_REG register
* UHCI ACK number configuration
*/
#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28)
#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
* Configures the number of acknowledgements used in software flow control.
*/
@@ -654,9 +652,9 @@ extern "C" {
#define UHCI_ACK_NUM_V 0x00000007U
#define UHCI_ACK_NUM_S 0
/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
* Configures whether or not load acknowledgements.\\
* 0: Not load\\
* 1: Load\\
* Configures whether or not load acknowledgements.
* 0: Not load
* 1: Load
*/
#define UHCI_ACK_NUM_LOAD (BIT(3))
#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
@@ -666,7 +664,7 @@ extern "C" {
/** UHCI_RX_HEAD_REG register
* UHCI packet header register
*/
#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2c)
#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
* Represents the header of the current received packet.
*/
@@ -678,17 +676,17 @@ extern "C" {
/** UHCI_QUICK_SENT_REG register
* UHCI quick send configuration register
*/
#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30)
#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
* Configures the source of data to be transmitted in single_send mode.\\
* 0: Q0 register\\
* 1: Q1 register\\
* 2: Q2 register\\
* 3: Q3 register\\
* 4: Q4 register\\
* 5: Q5 register\\
* 6: Q6 register\\
* 7: Invalid. No effect\\
* Configures the source of data to be transmitted in single_send mode.
* 0: Q0 register
* 1: Q1 register
* 2: Q2 register
* 3: Q3 register
* 4: Q4 register
* 5: Q5 register
* 6: Q6 register
* 7: Invalid. No effect
*/
#define UHCI_SINGLE_SEND_NUM 0x00000007U
#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
@@ -702,24 +700,24 @@ extern "C" {
#define UHCI_SINGLE_SEND_EN_V 0x00000001U
#define UHCI_SINGLE_SEND_EN_S 3
/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
* Configures the source of data to be transmitted in always_send mode.\\
* 0: Q0 register\\
* 1: Q1 register\\
* 2: Q2 register\\
* 3: Q3 register\\
* 4: Q4 register\\
* 5: Q5 register\\
* 6: Q6 register\\
* 7: Invalid. No effect\\
* Configures the source of data to be transmitted in always_send mode.
* 0: Q0 register
* 1: Q1 register
* 2: Q2 register
* 3: Q3 register
* 4: Q4 register
* 5: Q5 register
* 6: Q6 register
* 7: Invalid. No effect
*/
#define UHCI_ALWAYS_SEND_NUM 0x00000007U
#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U
#define UHCI_ALWAYS_SEND_NUM_S 4
/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable always_send mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable always_send mode.
* 0: Disable
* 1: Enable
*/
#define UHCI_ALWAYS_SEND_EN (BIT(7))
#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
@@ -729,7 +727,7 @@ extern "C" {
/** UHCI_REG_Q0_WORD0_REG register
* Q0 WORD0 quick send register
*/
#define UHCI_REG_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34)
#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q0 register.
*/
@@ -741,7 +739,7 @@ extern "C" {
/** UHCI_REG_Q0_WORD1_REG register
* Q0 WORD1 quick send register
*/
#define UHCI_REG_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38)
#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q0 register.
*/
@@ -753,7 +751,7 @@ extern "C" {
/** UHCI_REG_Q1_WORD0_REG register
* Q1 WORD0 quick send register
*/
#define UHCI_REG_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3c)
#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q1 register.
*/
@@ -765,7 +763,7 @@ extern "C" {
/** UHCI_REG_Q1_WORD1_REG register
* Q1 WORD1 quick send register
*/
#define UHCI_REG_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40)
#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q1 register.
*/
@@ -777,7 +775,7 @@ extern "C" {
/** UHCI_REG_Q2_WORD0_REG register
* Q2 WORD0 quick send register
*/
#define UHCI_REG_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44)
#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q2 register.
*/
@@ -789,7 +787,7 @@ extern "C" {
/** UHCI_REG_Q2_WORD1_REG register
* Q2 WORD1 quick send register
*/
#define UHCI_REG_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48)
#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q2 register.
*/
@@ -801,7 +799,7 @@ extern "C" {
/** UHCI_REG_Q3_WORD0_REG register
* Q3 WORD0 quick send register
*/
#define UHCI_REG_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4c)
#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q3 register.
*/
@@ -813,7 +811,7 @@ extern "C" {
/** UHCI_REG_Q3_WORD1_REG register
* Q3 WORD1 quick send register
*/
#define UHCI_REG_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50)
#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q3 register.
*/
@@ -825,7 +823,7 @@ extern "C" {
/** UHCI_REG_Q4_WORD0_REG register
* Q4 WORD0 quick send register
*/
#define UHCI_REG_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54)
#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q4 register.
*/
@@ -837,7 +835,7 @@ extern "C" {
/** UHCI_REG_Q4_WORD1_REG register
* Q4 WORD1 quick send register
*/
#define UHCI_REG_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58)
#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q4 register.
*/
@@ -849,7 +847,7 @@ extern "C" {
/** UHCI_REG_Q5_WORD0_REG register
* Q5 WORD0 quick send register
*/
#define UHCI_REG_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5c)
#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q5 register.
*/
@@ -861,7 +859,7 @@ extern "C" {
/** UHCI_REG_Q5_WORD1_REG register
* Q5 WORD1 quick send register
*/
#define UHCI_REG_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60)
#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q5 register.
*/
@@ -873,7 +871,7 @@ extern "C" {
/** UHCI_REG_Q6_WORD0_REG register
* Q6 WORD0 quick send register
*/
#define UHCI_REG_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64)
#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q6 register.
*/
@@ -885,7 +883,7 @@ extern "C" {
/** UHCI_REG_Q6_WORD1_REG register
* Q6 WORD1 quick register
*/
#define UHCI_REG_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68)
#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q6 register.
*/
@@ -897,7 +895,7 @@ extern "C" {
/** UHCI_ESC_CONF0_REG register
* Escape sequence configuration register 0
*/
#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6c)
#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
* Configures separators to encode data packets. The default value is 0xC0.
*/
@@ -923,7 +921,7 @@ extern "C" {
/** UHCI_ESC_CONF1_REG register
* Escape sequence configuration register 1
*/
#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70)
#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
* Configures the character that needs to be encoded. The default value is 0xDB used
* as the first character of SLIP escape sequence.
@@ -950,7 +948,7 @@ extern "C" {
/** UHCI_ESC_CONF2_REG register
* Escape sequence configuration register 2
*/
#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74)
#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
* Configures a character that need to be encoded. The default value is 0x11 used as a
* flow control character.
@@ -977,7 +975,7 @@ extern "C" {
/** UHCI_ESC_CONF3_REG register
* Escape sequence configuration register 3
*/
#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78)
#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
* Configures the character that needs to be decoded. The default value is 0x13 used
* as a flow control character.
@@ -1004,10 +1002,11 @@ extern "C" {
/** UHCI_PKT_THRES_REG register
* Configuration register for packet length
*/
#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7c)
#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
* Configures the maximum value of the packet length.\\Measurement unit: byte.\\Valid
* only when UHCI_HEAD_EN is 0.
* Configures the maximum value of the packet length.
* Measurement unit: byte.
* Valid only when UHCI_HEAD_EN is 0.
*/
#define UHCI_PKT_THRS 0x00001FFFU
#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
@@ -1017,7 +1016,7 @@ extern "C" {
/** UHCI_DATE_REG register
* UHCI version control register
*/
#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80)
#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
* Version control register.
*/

239
components/soc/esp32c5/register/soc/uhci_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,62 +25,61 @@ typedef union {
*/
uint32_t rx_rst:1;
/** uart_sel : R/W; bitpos: [4:2]; default: 7;
* Configures to select which uart to connect with UHCI.\\
* 0: UART0\\
* 1: UART1\\
* Configures to select which uart to connect with UHCI.
* 0: UART0
* 1: UART1
*/
uint32_t uart_sel:3;
/** seper_en : R/W; bitpos: [5]; default: 1;
* Configures whether or not to separate the data frame with a special character.\\
* 0: Not separate\\
* 1: Separate\\
* Configures whether or not to separate the data frame with a special character.
* 0: Not separate
* 1: Separate
*/
uint32_t seper_en:1;
/** head_en : R/W; bitpos: [6]; default: 1;
* Configures whether or not to encode the data packet with a formatting header.\\
* 0: Not use formatting header\\
* 1: Use formatting header\\
* Configures whether or not to encode the data packet with a formatting header.
* 0: Not use formatting header
* 1: Use formatting header
*/
uint32_t head_en:1;
/** crc_rec_en : R/W; bitpos: [7]; default: 1;
* Configures whether or not to enable the reception of the 16-bit CRC.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the reception of the 16-bit CRC.
* 0: Disable
* 1: Enable
*/
uint32_t crc_rec_en:1;
/** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
* Configures whether or not to stop receiving data when UART is idle.\\
* 0: Not stop\\
* 1: Stop\\
* Configures whether or not to stop receiving data when UART is idle.
* 0: Not stop
* 1: Stop
*/
uint32_t uart_idle_eof_en:1;
/** len_eof_en : R/W; bitpos: [9]; default: 1;
* Configures when the UHCI decoder stops receiving data.\\
* 0: Stops after receiving 0xC0\\
* Configures when the UHCI decoder stops receiving data.
* 0: Stops after receiving 0xC0
* 1: Stops when the number of received data bytes reach the specified value. When
* UHCI_HEAD_EN is 1, the specified value is the data length indicated by the UHCI
* packet header. when UHCI_HEAD_EN is 0, the specified value is the configured
* value.\\
* packet header. when UHCI_HEAD_EN is 0, the specified value is the configured value.
*/
uint32_t len_eof_en:1;
/** encode_crc_en : R/W; bitpos: [10]; default: 1;
* Configures whether or not to enable data integrity check by appending a 16 bit
* CCITT-CRC to the end of the data.\\
* 0: Disable\\
* 1: Enable\\
* CCITT-CRC to the end of the data.
* 0: Disable
* 1: Enable
*/
uint32_t encode_crc_en:1;
/** clk_en : R/W; bitpos: [11]; default: 0;
* Configures clock gating.\\
* 0: Support clock only when the application writes registers.\\
* 1: Always force the clock on for registers.\\
* Configures clock gating.
* 0: Support clock only when the application writes registers.
* 1: Always force the clock on for registers.
*/
uint32_t clk_en:1;
/** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
* Configures whether or not to stop UHCI from receiving data after UART has received
* a NULL frame.\\
* 0: Not stop\\
* 1: Stop\\
* a NULL frame.
* 0: Not stop
* 1: Stop
*/
uint32_t uart_rx_brk_eof_en:1;
uint32_t reserved_13:19;
@@ -95,51 +94,50 @@ typedef union {
struct {
/** check_sum_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable header checksum validation when UHCI receives a
* data packet.\\
* 0: Disable\\
* 1: Enable\\
* data packet.
* 0: Disable
* 1: Enable
*/
uint32_t check_sum_en:1;
/** check_seq_en : R/W; bitpos: [1]; default: 1;
* Configures whether or not to enable the sequence number check when UHCI receives a
* data packet.\\
* 0: Disable\\
* 1: Enable\\
* data packet.
* 0: Disable
* 1: Enable
*/
uint32_t check_seq_en:1;
/** crc_disable : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable CRC calculation.\\
* 0: Disable\\
* 1: Enable\\
* Valid only when the Data Integrity Check Present bit in UHCI packet is 1.\\
* Configures whether or not to enable CRC calculation.
* 0: Disable
* 1: Enable
* Valid only when the Data Integrity Check Present bit in UHCI packet is 1.
*/
uint32_t crc_disable:1;
/** save_head : R/W; bitpos: [3]; default: 0;
* Configures whether or not to save the packet header when UHCI receives a data
* packet.\\
* 0: Not save\\
* 1: Save\\
* packet.
* 0: Not save
* 1: Save
*/
uint32_t save_head:1;
/** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
* Configures whether or not to encode the data packet with a checksum.\\
* 0: Not use checksum\\
* 1: Use checksum\\
* Configures whether or not to encode the data packet with a checksum.
* 0: Not use checksum
* 1: Use checksum
*/
uint32_t tx_check_sum_re:1;
/** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
* Configures whether or not to encode the data packet with an acknowledgment when a
* reliable packet is to be transmitted.\\
* 0: Not use acknowledgement\\
* 1: Use acknowledgement\\
* reliable packet is to be transmitted.
* 0: Not use acknowledgement
* 1: Use acknowledgement
*/
uint32_t tx_ack_num_re:1;
uint32_t reserved_6:1;
/** wait_sw_start : R/W; bitpos: [7]; default: 0;
* Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT
* state.\\
* 0: No\\
* 1: Yes\\
* Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT state.
* 0: No
* 1: Yes
*/
uint32_t wait_sw_start:1;
/** sw_start : WT; bitpos: [8]; default: 0;
@@ -157,57 +155,55 @@ typedef union {
typedef union {
struct {
/** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to decode character 0xC0 when DMA receives data.\\
* 0: Not decode\\
* 1: Decode\\
* Configures whether or not to decode character 0xC0 when DMA receives data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_c0_esc_en:1;
/** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
* Configures whether or not to decode character 0xDB when DMA receives data.\\
* 0: Not decode\\
* 1: Decode\\
* Configures whether or not to decode character 0xDB when DMA receives data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_db_esc_en:1;
/** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
* Configures whether or not to decode flow control character 0x11 when DMA receives
* data.\\
* 0: Not decode\\
* 1: Decode\\
* data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_11_esc_en:1;
/** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
* Configures whether or not to decode flow control character 0x13 when DMA receives
* data.\\
* 0: Not decode\\
* 1: Decode\\
* data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_13_esc_en:1;
/** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
* Configures whether or not to replace 0xC0 by special characters when DMA sends
* data.\\
* 0: Not replace\\
* 1: Replace\\
* Configures whether or not to replace 0xC0 by special characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_c0_esc_en:1;
/** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
* Configures whether or not to replace 0xDB by special characters when DMA sends
* data.\\
* 0: Not replace\\
* 1: Replace\\
* Configures whether or not to replace 0xDB by special characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_db_esc_en:1;
/** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
* Configures whether or not to replace flow control character 0x11 by special
* characters when DMA sends data.\\
* 0: Not replace\\
* 1: Replace\\
* characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_11_esc_en:1;
/** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to replace flow control character 0x13 by special
* characters when DMA sends data.\\
* 0: Not replace\\
* 1: Replace\\
* characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_13_esc_en:1;
uint32_t reserved_8:24;
@@ -221,7 +217,8 @@ typedef union {
typedef union {
struct {
/** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
* Configures the timeout value for DMA data reception.\\Measurement unit: ms.
* Configures the timeout value for DMA data reception.
* Measurement unit: ms.
*/
uint32_t txfifo_timeout:8;
/** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
@@ -229,13 +226,14 @@ typedef union {
*/
uint32_t txfifo_timeout_shift:3;
/** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
* Configures whether or not to enable the data reception timeout for TX FIFO.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the data reception timeout for TX FIFO.
* 0: Disable
* 1: Enable
*/
uint32_t txfifo_timeout_ena:1;
/** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
* Configures the timeout value for DMA to read data from RAM.\\Measurement unit: ms.
* Configures the timeout value for DMA to read data from RAM.
* Measurement unit: ms.
*/
uint32_t rxfifo_timeout:8;
/** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
@@ -243,9 +241,9 @@ typedef union {
*/
uint32_t rxfifo_timeout_shift:3;
/** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
* Configures whether or not to enable the DMA data transmission timeout.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable the DMA data transmission timeout.
* 0: Disable
* 1: Enable
*/
uint32_t rxfifo_timeout_ena:1;
uint32_t reserved_24:8;
@@ -263,9 +261,9 @@ typedef union {
*/
uint32_t ack_num:3;
/** ack_num_load : WT; bitpos: [3]; default: 0;
* Configures whether or not load acknowledgements.\\
* 0: Not load\\
* 1: Load\\
* Configures whether or not load acknowledgements.
* 0: Not load
* 1: Load
*/
uint32_t ack_num_load:1;
uint32_t reserved_4:28;
@@ -279,15 +277,15 @@ typedef union {
typedef union {
struct {
/** single_send_num : R/W; bitpos: [2:0]; default: 0;
* Configures the source of data to be transmitted in single_send mode.\\
* 0: Q0 register\\
* 1: Q1 register\\
* 2: Q2 register\\
* 3: Q3 register\\
* 4: Q4 register\\
* 5: Q5 register\\
* 6: Q6 register\\
* 7: Invalid. No effect\\
* Configures the source of data to be transmitted in single_send mode.
* 0: Q0 register
* 1: Q1 register
* 2: Q2 register
* 3: Q3 register
* 4: Q4 register
* 5: Q5 register
* 6: Q6 register
* 7: Invalid. No effect
*/
uint32_t single_send_num:3;
/** single_send_en : WT; bitpos: [3]; default: 0;
@@ -295,21 +293,21 @@ typedef union {
*/
uint32_t single_send_en:1;
/** always_send_num : R/W; bitpos: [6:4]; default: 0;
* Configures the source of data to be transmitted in always_send mode.\\
* 0: Q0 register\\
* 1: Q1 register\\
* 2: Q2 register\\
* 3: Q3 register\\
* 4: Q4 register\\
* 5: Q5 register\\
* 6: Q6 register\\
* 7: Invalid. No effect\\
* Configures the source of data to be transmitted in always_send mode.
* 0: Q0 register
* 1: Q1 register
* 2: Q2 register
* 3: Q3 register
* 4: Q4 register
* 5: Q5 register
* 6: Q6 register
* 7: Invalid. No effect
*/
uint32_t always_send_num:3;
/** always_send_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable always_send mode.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether or not to enable always_send mode.
* 0: Disable
* 1: Enable
*/
uint32_t always_send_en:1;
uint32_t reserved_8:24;
@@ -596,8 +594,9 @@ typedef union {
typedef union {
struct {
/** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
* Configures the maximum value of the packet length.\\Measurement unit: byte.\\Valid
* only when UHCI_HEAD_EN is 0.
* Configures the maximum value of the packet length.
* Measurement unit: byte.
* Valid only when UHCI_HEAD_EN is 0.
*/
uint32_t pkt_thrs:13;
uint32_t reserved_13:19;
@@ -799,15 +798,15 @@ typedef union {
typedef union {
struct {
/** rx_err_cause : RO; bitpos: [2:0]; default: 0;
* Represents the error type when DMA has received a packet with error.\\
* 0: Invalid. No effect\\
* 1: Checksum error in the HCI packet\\
* 2: Sequence number error in the HCI packet\\
* 3: CRC bit error in the HCI packet\\
* Represents the error type when DMA has received a packet with error.
* 0: Invalid. No effect
* 1: Checksum error in the HCI packet
* 2: Sequence number error in the HCI packet
* 3: CRC bit error in the HCI packet
* 4: 0xC0 is found but the received HCI packet is not complete\
* 5: 0xC0 is not found when the HCI packet has been received\\
* 6: CRC check error\\
* 7: Invalid. No effect\\
* 5: 0xC0 is not found when the HCI packet has been received
* 6: CRC check error
* 7: Invalid. No effect
*/
uint32_t rx_err_cause:3;
/** decode_state : RO; bitpos: [5:3]; default: 0;

12
components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -640,6 +640,14 @@ extern "C" {
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15
/** USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL : R/W; bitpos: [16]; default: 0;
* Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at
* clock negative edge. 1: tx output at clock positive edge.
*/
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL (BIT(16))
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S)
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V 0x00000001U
#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S 16
/** USB_SERIAL_JTAG_TEST_REG register
* Registers used for debugging the PHY.
@@ -1215,7 +1223,7 @@ extern "C" {
* Date register
*/
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368;
/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 37777456;
* register version.
*/
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU

14
components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -23,7 +23,8 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:32;
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
@@ -115,7 +116,12 @@ typedef union {
* through GPIO Matrix.
*/
uint32_t usb_jtag_bridge_en:1;
uint32_t reserved_16:16;
/** usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0;
* Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at
* clock negative edge. 1: tx output at clock positive edge.
*/
uint32_t usb_phy_tx_edge_sel:1;
uint32_t reserved_17:15;
};
uint32_t val;
} usb_serial_jtag_conf0_reg_t;
@@ -925,7 +931,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36770368;
/** date : R/W; bitpos: [31:0]; default: 37777456;
* register version.
*/
uint32_t date:32;

2
components/soc/esp32h4/include/soc/reg_base.h
View File

@@ -51,7 +51,7 @@
#define DR_REG_INTMTX1_BASE 0x6009B000
#define DR_REG_HP_SYSTEM_BASE 0x6009C000
#define DR_REG_HP_APM_BASE 0x6009D000
#define DR_REG_CPU_APM_REG_BASE 0x6009E000
#define DR_REG_CPU_APM_BASE 0x6009E000
#define DR_REG_TEE_BASE 0x6009F000
#define DR_REG_KEYMNG_BASE 0x600A5000
#define DR_REG_AES_BASE 0x600A6000

2
components/soc/esp32h4/ld/esp32h4.peripherals.ld
View File

@@ -50,7 +50,7 @@ PROVIDE ( INTMTX0 = 0x6009A000 );
PROVIDE ( INTMTX1 = 0x6009B000 );
PROVIDE ( HP_SYSTEM = 0x6009C000 );
PROVIDE ( HP_APM = 0x6009D000 );
PROVIDE ( CPU_APM_REG = 0x6009E000 );
PROVIDE ( CPU_APM = 0x6009E000 );
PROVIDE ( TEE = 0x6009F000 );
PROVIDE ( KEYMNG = 0x600A5000 );
PROVIDE ( AES = 0x600A6000 );

90
components/soc/esp32h4/register/soc/cpu_apm_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** CPU_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_BASE + 0x0)
#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0)
/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
@@ -28,7 +28,7 @@ extern "C" {
/** CPU_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_BASE + 0x4)
#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4)
/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 0.
*/
@@ -54,7 +54,7 @@ extern "C" {
/** CPU_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_BASE + 0x8)
#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x8)
/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 0.
*/
@@ -80,7 +80,7 @@ extern "C" {
/** CPU_APM_REGION0_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_BASE + 0xc)
#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc)
/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 0.
*/
@@ -155,7 +155,7 @@ extern "C" {
/** CPU_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_BASE + 0x10)
#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x10)
/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 1.
*/
@@ -181,7 +181,7 @@ extern "C" {
/** CPU_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_BASE + 0x14)
#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x14)
/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 1.
*/
@@ -207,7 +207,7 @@ extern "C" {
/** CPU_APM_REGION1_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_BASE + 0x18)
#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18)
/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 1.
*/
@@ -282,7 +282,7 @@ extern "C" {
/** CPU_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_BASE + 0x1c)
#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x1c)
/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 2.
*/
@@ -308,7 +308,7 @@ extern "C" {
/** CPU_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_BASE + 0x20)
#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x20)
/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 2.
*/
@@ -334,7 +334,7 @@ extern "C" {
/** CPU_APM_REGION2_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_BASE + 0x24)
#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24)
/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 2.
*/
@@ -409,7 +409,7 @@ extern "C" {
/** CPU_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_BASE + 0x28)
#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x28)
/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 3.
*/
@@ -435,7 +435,7 @@ extern "C" {
/** CPU_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_BASE + 0x2c)
#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x2c)
/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 3.
*/
@@ -461,7 +461,7 @@ extern "C" {
/** CPU_APM_REGION3_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_BASE + 0x30)
#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30)
/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 3.
*/
@@ -536,7 +536,7 @@ extern "C" {
/** CPU_APM_REGION4_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_BASE + 0x34)
#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x34)
/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 4.
*/
@@ -562,7 +562,7 @@ extern "C" {
/** CPU_APM_REGION4_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_BASE + 0x38)
#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x38)
/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 4.
*/
@@ -588,7 +588,7 @@ extern "C" {
/** CPU_APM_REGION4_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_BASE + 0x3c)
#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c)
/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 4.
*/
@@ -663,7 +663,7 @@ extern "C" {
/** CPU_APM_REGION5_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_BASE + 0x40)
#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x40)
/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 5.
*/
@@ -689,7 +689,7 @@ extern "C" {
/** CPU_APM_REGION5_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_BASE + 0x44)
#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x44)
/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 5.
*/
@@ -715,7 +715,7 @@ extern "C" {
/** CPU_APM_REGION5_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_BASE + 0x48)
#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48)
/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 5.
*/
@@ -790,7 +790,7 @@ extern "C" {
/** CPU_APM_REGION6_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_BASE + 0x4c)
#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4c)
/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 6.
*/
@@ -816,7 +816,7 @@ extern "C" {
/** CPU_APM_REGION6_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_BASE + 0x50)
#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x50)
/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 6.
*/
@@ -842,7 +842,7 @@ extern "C" {
/** CPU_APM_REGION6_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_BASE + 0x54)
#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54)
/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 6.
*/
@@ -917,7 +917,7 @@ extern "C" {
/** CPU_APM_REGION7_ADDR_START_REG register
* Region address register
*/
#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_BASE + 0x58)
#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x58)
/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region 7.
*/
@@ -943,7 +943,7 @@ extern "C" {
/** CPU_APM_REGION7_ADDR_END_REG register
* Region address register
*/
#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_BASE + 0x5c)
#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x5c)
/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region 7.
*/
@@ -969,7 +969,7 @@ extern "C" {
/** CPU_APM_REGION7_ATTR_REG register
* Region access authority attribute register
*/
#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_BASE + 0x60)
#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60)
/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 7.
*/
@@ -1044,7 +1044,7 @@ extern "C" {
/** CPU_APM_FUNC_CTRL_REG register
* APM function control register
*/
#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_BASE + 0xc4)
#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4)
/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
@@ -1077,7 +1077,7 @@ extern "C" {
/** CPU_APM_M0_STATUS_REG register
* M0 status register
*/
#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_BASE + 0xc8)
#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8)
/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
@@ -1091,7 +1091,7 @@ extern "C" {
/** CPU_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xcc)
#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc)
/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
@@ -1103,7 +1103,7 @@ extern "C" {
/** CPU_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xd0)
#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0)
/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
@@ -1129,7 +1129,7 @@ extern "C" {
/** CPU_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xd4)
#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4)
/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
@@ -1141,7 +1141,7 @@ extern "C" {
/** CPU_APM_M1_STATUS_REG register
* M1 status register
*/
#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_BASE + 0xd8)
#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8)
/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
@@ -1155,7 +1155,7 @@ extern "C" {
/** CPU_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xdc)
#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc)
/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
@@ -1167,7 +1167,7 @@ extern "C" {
/** CPU_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xe0)
#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0)
/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
@@ -1193,7 +1193,7 @@ extern "C" {
/** CPU_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xe4)
#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4)
/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
@@ -1205,7 +1205,7 @@ extern "C" {
/** CPU_APM_M2_STATUS_REG register
* M2 status register
*/
#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_BASE + 0xe8)
#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_APM_BASE + 0xe8)
/** CPU_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
@@ -1219,7 +1219,7 @@ extern "C" {
/** CPU_APM_M2_STATUS_CLR_REG register
* M2 status clear register
*/
#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xec)
#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xec)
/** CPU_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
@@ -1231,7 +1231,7 @@ extern "C" {
/** CPU_APM_M2_EXCEPTION_INFO0_REG register
* M2 exception_info0 register
*/
#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xf0)
#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xf0)
/** CPU_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
@@ -1257,7 +1257,7 @@ extern "C" {
/** CPU_APM_M2_EXCEPTION_INFO1_REG register
* M2 exception_info1 register
*/
#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xf4)
#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xf4)
/** CPU_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
@@ -1269,7 +1269,7 @@ extern "C" {
/** CPU_APM_M3_STATUS_REG register
* M3 status register
*/
#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_BASE + 0xf8)
#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_APM_BASE + 0xf8)
/** CPU_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
@@ -1283,7 +1283,7 @@ extern "C" {
/** CPU_APM_M3_STATUS_CLR_REG register
* M3 status clear register
*/
#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xfc)
#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xfc)
/** CPU_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
@@ -1295,7 +1295,7 @@ extern "C" {
/** CPU_APM_M3_EXCEPTION_INFO0_REG register
* M3 exception_info0 register
*/
#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0x100)
#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0x100)
/** CPU_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
@@ -1321,7 +1321,7 @@ extern "C" {
/** CPU_APM_M3_EXCEPTION_INFO1_REG register
* M3 exception_info1 register
*/
#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0x104)
#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0x104)
/** CPU_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
@@ -1333,7 +1333,7 @@ extern "C" {
/** CPU_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define CPU_APM_INT_EN_REG (DR_REG_CPU_BASE + 0x118)
#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118)
/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
@@ -1374,7 +1374,7 @@ extern "C" {
/** CPU_APM_CLOCK_GATE_REG register
* Clock gating register
*/
#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_BASE + 0x7f8)
#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8)
/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
@@ -1388,7 +1388,7 @@ extern "C" {
/** CPU_APM_DATE_REG register
* Version control register
*/
#define CPU_APM_DATE_REG (DR_REG_CPU_BASE + 0x7fc)
#define CPU_APM_DATE_REG (DR_REG_CPU_APM_BASE + 0x7fc)
/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37769360;
* Version control register.
*/

2
components/soc/esp32h4/register/soc/cpu_apm_struct.h
View File

@@ -567,7 +567,7 @@ typedef struct {
volatile cpu_apm_date_reg_t apm_date;
} cpu_dev_t;
extern cpu_dev_t CPU_APM_REG;
extern cpu_dev_t CPU_APM;
#ifndef __cplusplus
_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure");