forked from espressif/esp-idf
feat(system): updated reset reasons for H21
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@@ -86,7 +86,6 @@ typedef enum {
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RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
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RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
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TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
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SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
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EFUSE_RESET = 20, /**<20, efuse reset digital core*/
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USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
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USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
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@@ -107,7 +106,6 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
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ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
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ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
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ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
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ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
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@@ -10,8 +10,6 @@
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#include "soc/rtc_periph.h"
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#include "esp32h21/rom/rtc.h"
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// TODO: [ESP32H21] IDF-11900, IDF-11910
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static void esp_reset_reason_clear_hint(void);
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static esp_reset_reason_t s_reset_reason;
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@@ -43,7 +41,6 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
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case RESET_REASON_CORE_RTC_WDT:
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case RESET_REASON_SYS_RTC_WDT:
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case RESET_REASON_SYS_SUPER_WDT:
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case RESET_REASON_CPU0_RTC_WDT:
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case RESET_REASON_CPU0_MWDT0:
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case RESET_REASON_CPU0_MWDT1:
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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@@ -109,7 +109,11 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason]",
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static void do_exception(void)
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{
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setup_values();
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*(int*)(0x0) = 0;
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#ifdef __XTENSA__
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asm("ill"); // should be an invalid operation on xtensa targets
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#elif __riscv
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asm("unimp"); // should be an invalid operation on RISC-V targets
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#endif
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}
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static void do_abort(void)
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