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feat(ulp): updated to reflect eco2 ulp changes

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This commit is contained in:
Marius Vikhammer
2025-04-16 10:38:04 +08:00
parent f66a750af9
commit 2fbbcc6d36
7 changed files with 22 additions and 8 deletions
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4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -1606,3 +1606,7 @@ config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
config SOC_LP_CORE_SUPPORT_ETM
bool
default y
config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
bool
default y

5
components/soc/esp32c5/include/soc/soc_caps.h
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@ -670,5 +670,6 @@
// #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -2190,3 +2190,7 @@ config SOC_LP_CORE_SUPPORT_LP_ADC
config SOC_LP_CORE_SUPPORT_LP_VAD
bool
default y
config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
bool
default y

7
components/soc/esp32p4/include/soc/soc_caps.h
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@ -810,6 +810,7 @@
#define SOC_I3C_MASTER_COMMAND_TABLE_NUM (12)
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */
#define SOC_LP_CORE_SUPPORT_LP_VAD (1) /*!< LP VAD can be accessed from the LP-Core */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */
#define SOC_LP_CORE_SUPPORT_LP_VAD (1) /*!< LP VAD can be accessed from the LP-Core */
#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */

2
components/ulp/Kconfig
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@ -97,7 +97,7 @@ menu "Ultra Low Power (ULP) Co-processor"
depends on ULP_COPROC_TYPE_LP_CORE && SOC_ULP_LP_UART_SUPPORTED
bool
prompt "Enable panic handler which outputs over LP UART"
default "y" if IDF_TARGET_ESP32P4
default "y" if SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
help
Set this option to enable panic handler functionality. If this option is
enabled then the LP Core will output a panic dump over LP UART,

4
examples/system/.build-test-rules.yml
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@ -273,6 +273,10 @@ examples/system/ulp/lp_core/build_system:
examples/system/ulp/lp_core/debugging:
enable:
- if: SOC_LP_CORE_SUPPORTED == 1
disable:
- if: IDF_TARGET == "esp32c5"
temporary: true
reason: binary size too large TODO IDF-13063
depends_components:
- ulp

4
examples/system/ulp/lp_core/debugging/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C6 | ESP32-P4 |
| ----------------- | -------- | -------- |
# LP Core Debugging Example