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fix(parlio_tx): fix error in first transfer and 1 byte transfer

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On p4, the clock was configured in the wrong order causing a dropped
count on the first transmission. And gdma eof event fails to trigger
parlio_tx eof event when transmitting single byte.
This commit is contained in:
Chen Jichang
2024-09-05 17:07:18 +08:00
committed by morris
parent 8af42a08cf
commit 4a10d24b48
1 changed files with 2 additions and 1 deletions
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3
components/driver/parlio/parlio_tx.c
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@ -250,7 +250,8 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par
ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed");
}
#endif
// turn on the tx module clock to sync the register configuration to the module
parlio_ll_tx_enable_clock(hal->regs, true);
parlio_ll_tx_set_clock_source(hal->regs, clk_src);
// set clock division, round up
uint32_t div = (periph_src_clk_hz + config->output_clk_freq_hz - 1) / config->output_clk_freq_hz;