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Merge branch 'fix/cpu_reset_dma' into 'master'

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dma: fixed issue that DMA are not reset when CPU reset

See merge request espressif/esp-idf!41512
This commit is contained in:
Michael (XIAO Xufeng)
2025-10-23 16:26:57 +08:00
parent 6bfcd4b41c 40dd5e3957
commit 746485f640
19 changed files with 75 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/port/soc/esp32/system_internal.c
+7 -2
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@@ -48,8 +48,13 @@ void esp_system_reset_modules_on_exit(void)
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
//UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST |
DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST |
DPORT_UART_MEM_RST | DPORT_PWM0_RST | DPORT_PWM1_RST);
// The DMA inside SPI needs to be reset to avoid memory corruption after restart.
DPORT_SPI_DMA_RST |
DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST |
DPORT_PWM0_RST | DPORT_PWM1_RST |
// The DMA inside I2S needs to be reset to avoid memory corruption after restart.
DPORT_I2S0_RST | DPORT_I2S1_RST |
DPORT_UHCI0_RST | DPORT_UHCI1_RST);
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart and hence
components/esp_system/port/soc/esp32c5/system_internal.c
+6 -1
View File
@@ -52,6 +52,10 @@ void esp_system_reset_modules_on_exit(void)
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
// The DMA inside SDIO slave needs to be reset to avoid memory corruption after restart.
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -59,9 +63,10 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
// CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32c6/system_internal.c
+3
View File
@@ -52,6 +52,8 @@ void esp_system_reset_modules_on_exit(void)
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -62,6 +64,7 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
CLEAR_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32c61/system_internal.c
+6
View File
@@ -55,6 +55,10 @@ void esp_system_reset_modules_on_exit(void)
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
// The DMA inside SDIO slave needs to be reset to avoid memory corruption after restart.
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -63,6 +67,8 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32h2/system_internal.c
+3
View File
@@ -49,6 +49,8 @@ void esp_system_reset_modules_on_exit(void)
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -58,6 +60,7 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32h21/system_internal.c
+3
View File
@@ -50,6 +50,8 @@ void esp_system_reset_modules_on_exit(void)
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -59,6 +61,7 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32h4/system_internal.c
+3
View File
@@ -45,6 +45,8 @@ void esp_system_reset_modules_on_exit(void)
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM0_CONF_REG, PCR_PWM0_RST_EN);
SET_PERI_REG_MASK(PCR_PWM1_CONF_REG, PCR_PWM1_RST_EN);
//ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -55,6 +57,7 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM0_CONF_REG, PCR_PWM0_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM1_CONF_REG, PCR_PWM1_RST_EN);
CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32p4/system_internal.c
+14 -4
View File
@@ -70,28 +70,38 @@ void esp_system_reset_modules_on_exit(void)
}
// Set Peripheral clk rst
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI);
// DMA needs to be reset to avoid memory corruption after restart. Now only AHB supports this.
// For other AXI DMAs, we have already stop them above.
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_STIMER);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART0_CORE);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART1_CORE);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART2_CORE);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART3_CORE);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART4_CORE);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_ADC);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_H264);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_STIMER);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART0_CORE);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART1_CORE);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART2_CORE);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART3_CORE);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART4_CORE);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_ADC);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_H264);
// The DMA inside SDMMC Host needs to be reset to avoid memory corruption after restart.
SET_PERI_REG_MASK(LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG, LP_CLKRST_RST_EN_SDMMC);
CLEAR_PERI_REG_MASK(LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG, LP_CLKRST_RST_EN_SDMMC);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32s2/clk.c
+1 -1
View File
@@ -296,7 +296,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Disable some peripheral clocks. */
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, common_perip_clk);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
components/esp_system/port/soc/esp32s2/system_internal.c
+2 -2
View File
@@ -48,10 +48,10 @@ void esp_system_reset_modules_on_exit(void)
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
// Reset timer/spi/uart
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG,
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST |
DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST);
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
DPORT_REG_WRITE(DPORT_PERIP_RST_EN0_REG, 0);
// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
components/esp_system/port/soc/esp32s3/system_internal.c
+3 -1
View File
@@ -58,7 +58,9 @@ void esp_system_reset_modules_on_exit(void)
// Reset dma and crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
// and hence avoiding any possibility with crypto failure in ROM security workflows.
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST | SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST |
SYSTEM_CRYPTO_HMAC_RST | SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_SHA_RST);
SYSTEM_CRYPTO_HMAC_RST | SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_SHA_RST |
// The DMA inside SDMMC Host needs to be reset to avoid memory corruption after restart.
SYSTEM_SDIO_HOST_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
components/hal/esp32s2/include/hal/adc_ll.h
+2 -2
View File
@@ -957,8 +957,8 @@ static inline void _adc_ll_enable_bus_clock(bool enable)
*/
static inline void _adc_ll_reset_register(void)
{
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_APB_SARADC_RST);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_APB_SARADC_RST);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_APB_SARADC_RST);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_APB_SARADC_RST);
}
// SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way
#define adc_ll_reset_register(...) do { \
components/hal/esp32s2/include/hal/clk_gate_ll.h
+1 -1
View File
@@ -90,7 +90,7 @@ static inline uint32_t periph_ll_get_rst_en_reg(shared_periph_module_t periph)
case PERIPH_WIFI_BT_COMMON_MODULE:
return DPORT_CORE_RST_EN_REG;
default:
return DPORT_PERIP_RST_EN_REG;
return DPORT_PERIP_RST_EN0_REG;
}
}
components/hal/esp32s2/include/hal/i2s_ll.h
+2 -2
View File
@@ -117,8 +117,8 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
static inline void i2s_ll_reset_register(int i2s_id)
{
(void) i2s_id;
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_I2S0_RST);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
components/hal/esp32s2/include/hal/ledc_ll.h
+2 -2
View File
@@ -69,9 +69,9 @@ static inline void ledc_ll_enable_bus_clock(bool enable)
static inline void ledc_ll_enable_reset_reg(bool enable)
{
if (enable) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_LEDC_RST);
} else {
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_LEDC_RST);
}
}
components/hal/esp32s2/include/hal/pcnt_ll.h
+2 -2
View File
@@ -480,8 +480,8 @@ static inline void pcnt_ll_enable_bus_clock(int group_id, bool enable)
static inline void pcnt_ll_reset_register(int group_id)
{
(void)group_id;
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_PCNT_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_PCNT_RST);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
components/hal/esp32s2/include/hal/spi_ll.h
+10 -10
View File
@@ -161,16 +161,16 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id)
{
switch (host_id) {
case SPI1_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI01_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI01_RST);
break;
case SPI2_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI2_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI2_RST);
break;
case SPI3_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI3_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI3_RST);
break;
default: HAL_ASSERT(false);
}
@@ -1280,12 +1280,12 @@ static inline void spi_dma_ll_reset_register(spi_host_device_t host_id)
{
switch (host_id) {
case SPI2_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI2_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI2_DMA_RST);
break;
case SPI3_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_DMA_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI3_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_SPI3_DMA_RST);
break;
default:
HAL_ASSERT(false);
components/hal/esp32s2/include/hal/uart_ll.h
+5 -5
View File
@@ -72,7 +72,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
(uart_num == 1) ? DPORT_UART1_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
(uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
}
@@ -112,12 +112,12 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num) {
case 0:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_UART_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_UART_RST);
break;
case 1:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_UART1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN0_REG, DPORT_UART1_RST);
break;
default:
abort();
components/soc/esp32s2/register/soc/system_reg.h
-1
View File
@@ -402,7 +402,6 @@ extern "C" {
#define DPORT_CRYPTO_AES_CLK_EN_V 0x1
#define DPORT_CRYPTO_AES_CLK_EN_S 1
#define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG
#define DPORT_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x048)
/* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */