refactor(soc): sort esp32c6 soc headers

components/soc/esp32c6/include/soc/dport_access.h

@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32c6/include/soc/soc.h

@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 

components/soc/esp32c6/include/soc/system_reg.h

@@ -7,6 +7,6 @@
 #include "soc/hp_system_reg.h"
 
 // TODO: IDF-5720
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
 #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0

components/soc/esp32c6/register/soc/assist_debug_reg.h

@@ -92,7 +92,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
+ *  DBUS busy monitor enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
@@ -270,7 +270,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
+ *  DBUS busy monitor interrupt enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
@@ -491,7 +491,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
 /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
+ *  core0 sp region configuration register
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
@@ -515,7 +515,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
 /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
+ *  This register stores the PC when trigger stack monitor.
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
@@ -542,7 +542,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
@@ -554,7 +554,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;

components/soc/esp32c6/register/soc/assist_debug_struct.h

@@ -61,7 +61,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_ena:1;
         /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
+         *  DBUS busy monitor enable
          */
         uint32_t core_0_dram0_exception_monitor_ena:1;
         uint32_t reserved_12:20;
@@ -205,7 +205,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
+         *  core0 sp region configuration register
          */
         uint32_t core_0_sp_min:32;
     };
@@ -231,7 +231,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
+         *  This register stores the PC when trigger stack monitor.
          */
         uint32_t core_0_sp_pc:32;
     };
@@ -348,7 +348,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_rls:1;
         /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
+         *  DBUS busy monitor interrupt enable
          */
         uint32_t core_0_dram0_exception_monitor_rls:1;
         uint32_t reserved_12:20;
@@ -415,7 +415,7 @@ typedef union {
 } assist_debug_core_0_intr_clr_reg_t;
 
 
-/** Group: pc reording configuration register */
+/** Group: pc recording configuration register */
 /** Type of core_0_rcd_en register
  *  record enable configuration register
  */
@@ -435,9 +435,9 @@ typedef union {
 } assist_debug_core_0_rcd_en_reg_t;
 
 
-/** Group: pc reording status register */
+/** Group: pc recording status register */
 /** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -450,7 +450,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugpc_reg_t;
 
 /** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -463,7 +463,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugsp_reg_t;
 
 
-/** Group: exception monitor regsiter */
+/** Group: exception monitor register */
 /** Type of core_0_iram0_exception_monitor_0 register
  *  exception monitor status register0
  */

components/soc/esp32c6/register/soc/ecc_mult_reg.h

@@ -64,7 +64,7 @@ extern "C" {
  */
 #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
 /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
  *  the caculatrion is done.
  */
 #define ECC_MULT_START    (BIT(0))

components/soc/esp32c6/register/soc/ecc_mult_struct.h

@@ -77,7 +77,7 @@ typedef union {
 typedef union {
     struct {
         /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
          *  the caculatrion is done.
          */
         uint32_t start:1;

components/soc/esp32c6/register/soc/efuse_reg.h

@@ -7,7 +7,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
-#include "efuse_defs.h"
+#include "soc/efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -264,14 +264,14 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFH    0x00000003U
 #define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
 #define EFUSE_USB_DREFH_V  0x00000003U
 #define EFUSE_USB_DREFH_S  21
 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFL    0x00000003U
 #define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
@@ -2390,7 +2390,7 @@ extern "C" {
 #define EFUSE_CLK_EN_S  16
 
 /** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;

components/soc/esp32c6/register/soc/efuse_struct.h

@@ -239,11 +239,11 @@ typedef union {
          */
         uint32_t dis_download_manual_encrypt:1;
         /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefh:2;
         /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefl:2;
         /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
@@ -2024,7 +2024,7 @@ typedef union {
 } efuse_clk_reg_t;
 
 /** Type of conf register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 typedef union {
     struct {

components/soc/esp32c6/register/soc/extmem_reg.h

@@ -243,8 +243,8 @@ ould be used together with CACHE_LOCK_ADDR_REG.*/
 #define EXTMEM_L1_CACHE_SYNC_DONE_S  4
 /* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
 /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
-hardware after writeback-invalidate operation done. Note that this bit and the o
-ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
+hardware after writeback-invalidate operation done. Note that this bit and the
+other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
 , that is, those bits can not be set to 1 at the same time..*/
 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
@@ -262,16 +262,16 @@ those bits can not be set to 1 at the same time..*/
 /* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
 /*description: The bit is used to enable clean operation. It will be cleared by hardware after
 clean operation done. Note that this bit and the other sync-bits (invalidate_ena
-, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
-e bits can not be set to 1 at the same time..*/
+, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+bits can not be set to 1 at the same time..*/
 #define EXTMEM_L1_CACHE_CLEAN_ENA    (BIT(1))
 #define EXTMEM_L1_CACHE_CLEAN_ENA_M  (BIT(1))
 #define EXTMEM_L1_CACHE_CLEAN_ENA_V  0x1
 #define EXTMEM_L1_CACHE_CLEAN_ENA_S  1
 /* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
 /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done. Note that this bit and the other sync-bits (clea
-n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+after invalidate operation done. Note that this bit and the other sync-bits (clean_ena,
+writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
  those bits can not be set to 1 at the same time..*/
 #define EXTMEM_L1_CACHE_INVALIDATE_ENA    (BIT(0))
 #define EXTMEM_L1_CACHE_INVALIDATE_ENA_M  (BIT(0))
@@ -452,15 +452,15 @@ SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
 
 #define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x15C)
 /* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus1 accesses L1-DCache..*/
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+to bus1 accesses L1-DCache..*/
 #define EXTMEM_L1_DBUS_OVF_INT_CLR    (BIT(5))
 #define EXTMEM_L1_DBUS_OVF_INT_CLR_M  (BIT(5))
 #define EXTMEM_L1_DBUS_OVF_INT_CLR_V  0x1
 #define EXTMEM_L1_DBUS_OVF_INT_CLR_S  5
 /* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus0 accesses L1-DCache..*/
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+to bus0 accesses L1-DCache..*/
 #define EXTMEM_L1_IBUS_OVF_INT_CLR    (BIT(4))
 #define EXTMEM_L1_IBUS_OVF_INT_CLR_M  (BIT(4))
 #define EXTMEM_L1_IBUS_OVF_INT_CLR_V  0x1
@@ -526,8 +526,8 @@ o cpu accesses L1-DCache..*/
 
 #define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x174)
 /* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
-ue to cpu accesses L1-DCache..*/
+/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+to cpu accesses L1-DCache..*/
 #define EXTMEM_L1_CACHE_FAIL_INT_ST    (BIT(4))
 #define EXTMEM_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
 #define EXTMEM_L1_CACHE_FAIL_INT_ST_V  0x1
@@ -740,7 +740,7 @@ ror occurs..*/
 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V  0x1
 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S  13
 /* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
+/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error
 r..*/
 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
@@ -778,7 +778,7 @@ load-operation is done..*/
 
 #define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x238)
 /* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
+/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
 y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
 #define EXTMEM_L1_CACHE_SYNC_RST    (BIT(4))
 #define EXTMEM_L1_CACHE_SYNC_RST_M  (BIT(4))
@@ -808,7 +808,7 @@ rks in L1-Cache..*/
 #define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_EXTMEM_BASE + 0x244)
 /* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
 /*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
-llocate request is responsed but not completed..*/
+llocate request is responded but not completed..*/
 #define EXTMEM_L1_CACHE_UNALLOC_CLR    (BIT(4))
 #define EXTMEM_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
 #define EXTMEM_L1_CACHE_UNALLOC_CLR_V  0x1
@@ -823,7 +823,7 @@ th the others fields inside this register..*/
 #define EXTMEM_L1_CACHE_MEM_OBJECT_V  0x1
 #define EXTMEM_L1_CACHE_MEM_OBJECT_S  10
 /* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
+/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
 h the others fields inside this register..*/
 #define EXTMEM_L1_CACHE_TAG_OBJECT    (BIT(4))
 #define EXTMEM_L1_CACHE_TAG_OBJECT_M  (BIT(4))
@@ -841,8 +841,8 @@ h the others fields inside this register..*/
 
 #define EXTMEM_L1_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x250)
 /* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
+/*description: Those bits stores the virtual address which will decide where inside the specified
+tag memory object will be accessed..*/
 #define EXTMEM_L1_CACHE_VADDR    0xFFFFFFFF
 #define EXTMEM_L1_CACHE_VADDR_M  ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
 #define EXTMEM_L1_CACHE_VADDR_V  0xFFFFFFFF

components/soc/esp32c6/register/soc/extmem_struct.h

@@ -5115,12 +5115,12 @@ typedef union {
     struct {
         /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache0_unalloc_clr:1;
         /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache1_unalloc_clr:1;
         /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
@@ -5133,7 +5133,7 @@ typedef union {
         uint32_t l1_icache3_unalloc_clr:1;
         /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_cache_unalloc_clr:1;
         uint32_t reserved_5:27;
@@ -5149,7 +5149,7 @@ typedef union {
         uint32_t reserved_0:5;
         /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l2_cache_unalloc_clr:1;
         uint32_t reserved_6:26;

components/soc/esp32c6/register/soc/hardware_lock_reg.h

@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** ATOMIC_ADDR_LOCK_REG register
- *  hardware lock regsiter
+ *  hardware lock register
  */
 #define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
 /** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
@@ -24,7 +24,7 @@ extern "C" {
 #define ATOMIC_LOCK_S  0
 
 /** ATOMIC_LR_ADDR_REG register
- *  gloable lr address regsiter
+ *  gloable lr address register
  */
 #define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
 /** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
@@ -36,7 +36,7 @@ extern "C" {
 #define ATOMIC_GLOABLE_LR_ADDR_S  0
 
 /** ATOMIC_LR_VALUE_REG register
- *  gloable lr value regsiter
+ *  gloable lr value register
  */
 #define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
 /** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
@@ -48,11 +48,11 @@ extern "C" {
 #define ATOMIC_GLOABLE_LR_VALUE_S  0
 
 /** ATOMIC_LOCK_STATUS_REG register
- *  lock status regsiter
+ *  lock status register
  */
 #define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
 /** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
- *  read hareware lock status for debug
+ *  read hardware lock status for debug
  */
 #define ATOMIC_LOCK_STATUS    0x00000003U
 #define ATOMIC_LOCK_STATUS_M  (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)

components/soc/esp32c6/register/soc/hardware_lock_struct.h

@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of addr_lock register
- *  hardware lock regsiter
+ *  hardware lock register
  */
 typedef union {
     struct {
@@ -26,7 +26,7 @@ typedef union {
 } atomic_addr_lock_reg_t;
 
 /** Type of lr_addr register
- *  gloable lr address regsiter
+ *  gloable lr address register
  */
 typedef union {
     struct {
@@ -39,7 +39,7 @@ typedef union {
 } atomic_lr_addr_reg_t;
 
 /** Type of lr_value register
- *  gloable lr value regsiter
+ *  gloable lr value register
  */
 typedef union {
     struct {
@@ -52,12 +52,12 @@ typedef union {
 } atomic_lr_value_reg_t;
 
 /** Type of lock_status register
- *  lock status regsiter
+ *  lock status register
  */
 typedef union {
     struct {
         /** lock_status : RO; bitpos: [1:0]; default: 0;
-         *  read hareware lock status for debug
+         *  read hardware lock status for debug
          */
         uint32_t lock_status:2;
         uint32_t reserved_2:30;

components/soc/esp32c6/register/soc/hp_system_reg.h

@@ -78,7 +78,7 @@ extern "C" {
  *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
  *  the number, the stronger the ability to resist DPA attacks and the higher the
  *  security level, but it will increase the computational overhead of the hardware
- *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+ *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
  */
 #define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
 #define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)

components/soc/esp32c6/register/soc/hp_system_struct.h

@@ -70,7 +70,7 @@ typedef union {
          *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
          *  the number, the stronger the ability to resist DPA attacks and the higher the
          *  security level, but it will increase the computational overhead of the hardware
-         *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+         *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
          */
         uint32_t sec_dpa_level:2;
         /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;

components/soc/esp32c6/register/soc/i2s_reg.h

@@ -361,7 +361,7 @@ extern "C" {
 #define I2S_TX_PCM_BYPASS_V  0x00000001U
 #define I2S_TX_PCM_BYPASS_S  12
 /** I2S_TX_STOP_EN : R/W; bitpos: [13]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
  */
 #define I2S_TX_STOP_EN    (BIT(13))
 #define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)

components/soc/esp32c6/register/soc/i2s_struct.h

@@ -494,7 +494,7 @@ typedef union {
          */
         uint32_t tx_pcm_bypass:1;
         /** tx_stop_en : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
          */
         uint32_t tx_stop_en:1;
         uint32_t reserved_14:1;

components/soc/esp32c6/register/soc/io_mux_reg.h

@@ -5,7 +5,7 @@
  */
 
 #pragma once
-#include "soc.h"
+#include "soc/soc.h"
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */

components/soc/esp32c6/register/soc/lp_uart_reg.h

@@ -100,7 +100,7 @@ extern "C" {
 #define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
 #define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
 /** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
  *  uart_sw_flow_con_en is set to 1.
  */
 #define LP_UART_SW_XON_INT_RAW    (BIT(9))
@@ -261,7 +261,7 @@ extern "C" {
 #define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
 #define LP_UART_TX_BRK_DONE_INT_ST_S  12
 /** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
  *  is set to 1.
  */
 #define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
@@ -671,7 +671,7 @@ extern "C" {
 #define LP_UART_STOP_BIT_NUM_V  0x00000003U
 #define LP_UART_STOP_BIT_NUM_S  4
 /** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
  *  is done.
  */
 #define LP_UART_TXD_BRK    (BIT(6))
@@ -1151,7 +1151,7 @@ extern "C" {
  */
 #define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
 /** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
+ *  This is the enable bit for uart receiver's timeout function.
  */
 #define LP_UART_RX_TOUT_EN    (BIT(0))
 #define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)

components/soc/esp32c6/register/soc/lp_uart_struct.h

@@ -49,7 +49,7 @@ typedef union {
 typedef union {
     struct {
         /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
+         *  This is the enable bit for uart receiver's timeout function.
          */
         uint32_t rx_tout_en:1;
         /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
@@ -120,7 +120,7 @@ typedef union {
          */
         uint32_t rxfifo_tout:1;
         /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
          *  uart_sw_flow_con_en is set to 1.
          */
         uint32_t sw_xon:1;
@@ -224,7 +224,7 @@ typedef union {
          */
         uint32_t tx_brk_done:1;
         /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
          *  is set to 1.
          */
         uint32_t tx_brk_idle_done:1;
@@ -466,7 +466,7 @@ typedef union {
          */
         uint32_t stop_bit_num:2;
         /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
          *  is done.
          */
         uint32_t txd_brk:1;
@@ -1115,7 +1115,7 @@ typedef struct lp_uart_dev_t {
     volatile lp_uart_id_reg_t id;
 } lp_uart_dev_t;
 
-// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h
+// We map the LP_UART instance to the uart_dev_t struct for convenience of using the same HAL/LL. See soc/uart_struct.h
 // extern lp_uart_dev_t LP_UART;
 
 #ifndef __cplusplus

components/soc/esp32c6/register/soc/mcpwm_reg.h

@@ -894,7 +894,7 @@ extern "C" {
 #define MCPWM_DB0_RED_S  0
 
 /** MCPWM_CARRIER0_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64)
 /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
@@ -1575,7 +1575,7 @@ extern "C" {
 #define MCPWM_DB1_RED_S  0
 
 /** MCPWM_CARRIER1_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
 /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
@@ -2256,7 +2256,7 @@ extern "C" {
 #define MCPWM_DB2_RED_S  0
 
 /** MCPWM_CARRIER2_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
 /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
@@ -2621,7 +2621,7 @@ extern "C" {
 #define MCPWM_CAP0_MODE_V  0x00000003U
 #define MCPWM_CAP0_MODE_S  1
 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
+ *  Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
  *  1
  */
 #define MCPWM_CAP0_PRESCALE    0x000000FFU
@@ -2664,7 +2664,7 @@ extern "C" {
 #define MCPWM_CAP1_MODE_V  0x00000003U
 #define MCPWM_CAP1_MODE_S  1
 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
+ *  Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
  *  1
  */
 #define MCPWM_CAP1_PRESCALE    0x000000FFU
@@ -2707,7 +2707,7 @@ extern "C" {
 #define MCPWM_CAP2_MODE_V  0x00000003U
 #define MCPWM_CAP2_MODE_S  1
 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
+ *  Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
  *  1
  */
 #define MCPWM_CAP2_PRESCALE    0x000000FFU

components/soc/esp32c6/register/soc/mcpwm_struct.h

@@ -462,7 +462,7 @@ typedef union {
 } mcpwm_dt_red_cfg_reg_t;
 
 /** Type of carrier_cfg register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 typedef union {
     struct {
@@ -734,7 +734,7 @@ typedef union {
          */
         uint32_t capn_mode:2;
         /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
+         *  Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
          *  1
          */
         uint32_t capn_prescale:8;

components/soc/esp32c6/register/soc/mem_monitor_reg.h

@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
+ *  log config register
  */
 #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
 /** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
@@ -39,7 +39,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
 
 /** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
+ *  check data register
  */
 #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
 /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
@@ -64,7 +64,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_DATA_MASK_S  0
 
 /** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
 /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
@@ -76,7 +76,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MIN_S  0
 
 /** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
 /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;

components/soc/esp32c6/register/soc/mem_monitor_struct.h

@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of log_setting register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -35,7 +35,7 @@ typedef union {
 } mem_monitor_log_setting_reg_t;
 
 /** Type of log_check_data register
- *  check data regsiter
+ *  check data register
  */
 typedef union {
     struct {
@@ -63,7 +63,7 @@ typedef union {
 } mem_monitor_log_data_mask_reg_t;
 
 /** Type of log_min register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
@@ -76,7 +76,7 @@ typedef union {
 } mem_monitor_log_min_reg_t;
 
 /** Type of log_max register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {

components/soc/esp32c6/register/soc/parl_io_reg.h

@@ -31,7 +31,7 @@ extern "C" {
 #define PARL_IO_RX_START_V  0x00000001U
 #define PARL_IO_RX_START_S  1
 /** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0;
- *  Configures rx receieved data byte length.
+ *  Configures rx received data byte length.
  */
 #define PARL_IO_RX_DATA_BYTELEN    0x0000FFFFU
 #define PARL_IO_RX_DATA_BYTELEN_M  (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S)
@@ -251,7 +251,7 @@ extern "C" {
 #define PARL_IO_TX_READY_S  31
 
 /** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
@@ -277,7 +277,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ENA_S  2
 
 /** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18)
 /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
@@ -303,7 +303,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_RAW_S  2
 
 /** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
@@ -329,7 +329,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ST_S  2
 
 /** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20)
 /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;

components/soc/esp32c6/register/soc/parl_io_struct.h

@@ -26,7 +26,7 @@ typedef union {
          */
         uint32_t rx_start:1;
         /** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0;
-         *  Configures rx receieved data byte length.
+         *  Configures rx received data byte length.
          */
         uint32_t rx_data_bytelen:16;
         /** rx_sw_en : R/W; bitpos: [18]; default: 0;
@@ -213,7 +213,7 @@ typedef union {
 
 /** Group: PARL_IO Interrupt Configuration and Status */
 /** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 typedef union {
     struct {
@@ -235,7 +235,7 @@ typedef union {
 } parl_io_int_ena_reg_t;
 
 /** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 typedef union {
     struct {
@@ -257,7 +257,7 @@ typedef union {
 } parl_io_int_raw_reg_t;
 
 /** Type of int_st register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 typedef union {
     struct {
@@ -279,7 +279,7 @@ typedef union {
 } parl_io_int_st_reg_t;
 
 /** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 typedef union {
     struct {

components/soc/esp32c6/register/soc/pcr_reg.h

@@ -201,7 +201,7 @@ extern "C" {
 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
 /** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
  *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
  *  low-speed clock-source such as XTAL/FOSC.
  */
 #define PCR_MSPI_FAST_LS_DIV_NUM    0x000000FFU
@@ -210,7 +210,7 @@ extern "C" {
 #define PCR_MSPI_FAST_LS_DIV_NUM_S  0
 /** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
  *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
  *  high-speed clock-source such as SPLL.
  */
 #define PCR_MSPI_FAST_HS_DIV_NUM    0x000000FFU
@@ -1163,7 +1163,7 @@ extern "C" {
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+ *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
  *  divided by 3.
  */
 #define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
@@ -1666,8 +1666,8 @@ extern "C" {
  */
 #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
 /** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+ *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
  *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
  */
 #define PCR_CPU_LS_DIV_NUM    0x000000FFU
@@ -1675,8 +1675,8 @@ extern "C" {
 #define PCR_CPU_LS_DIV_NUM_V  0x000000FFU
 #define PCR_CPU_LS_DIV_NUM_S  0
 /** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
+ *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed
  *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
  */
 #define PCR_CPU_HS_DIV_NUM    0x000000FFU
@@ -1685,7 +1685,7 @@ extern "C" {
 #define PCR_CPU_HS_DIV_NUM_S  8
 /** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0;
  *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
- *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+ *  Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
  */
 #define PCR_CPU_HS_120M_FORCE    (BIT(16))
 #define PCR_CPU_HS_120M_FORCE_M  (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S)
@@ -1697,8 +1697,8 @@ extern "C" {
  */
 #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
 /** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
- *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+ *  Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb
+ *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
  *  low-speed clock-source such as XTAL/FOSC, and should be used together with
  *  PCR_CPU_LS_DIV_NUM.
  */
@@ -1707,8 +1707,8 @@ extern "C" {
 #define PCR_AHB_LS_DIV_NUM_V  0x000000FFU
 #define PCR_AHB_LS_DIV_NUM_S  0
 /** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
+ *  Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is
+ *  div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed
  *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
  */
 #define PCR_AHB_HS_DIV_NUM    0x000000FFU
@@ -1734,7 +1734,7 @@ extern "C" {
 #define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
 #define PCR_APB_DECREASE_DIV_NUM_S  0
 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+ *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
  *  div1(default)/div2/div4 of clk_ahb.
  */
 #define PCR_APB_DIV_NUM    0x000000FFU
@@ -1766,56 +1766,56 @@ extern "C" {
  */
 #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
 /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_240M_CLK_EN    (BIT(0))
 #define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
 #define PCR_PLL_240M_CLK_EN_V  0x00000001U
 #define PCR_PLL_240M_CLK_EN_S  0
 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_160M_CLK_EN    (BIT(1))
 #define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
 #define PCR_PLL_160M_CLK_EN_V  0x00000001U
 #define PCR_PLL_160M_CLK_EN_S  1
 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_120M_CLK_EN    (BIT(2))
 #define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
 #define PCR_PLL_120M_CLK_EN_V  0x00000001U
 #define PCR_PLL_120M_CLK_EN_S  2
 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_80M_CLK_EN    (BIT(3))
 #define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
 #define PCR_PLL_80M_CLK_EN_V  0x00000001U
 #define PCR_PLL_80M_CLK_EN_S  3
 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_48M_CLK_EN    (BIT(4))
 #define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
 #define PCR_PLL_48M_CLK_EN_V  0x00000001U
 #define PCR_PLL_48M_CLK_EN_S  4
 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_40M_CLK_EN    (BIT(5))
 #define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
 #define PCR_PLL_40M_CLK_EN_V  0x00000001U
 #define PCR_PLL_40M_CLK_EN_S  5
 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_20M_CLK_EN    (BIT(6))
 #define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)

components/soc/esp32c6/register/soc/pcr_struct.h

@@ -176,13 +176,13 @@ typedef union {
     struct {
         /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0;
          *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
          *  low-speed clock-source such as XTAL/FOSC.
          */
         uint32_t mspi_fast_ls_div_num:8;
         /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3;
          *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
          *  high-speed clock-source such as SPLL.
          */
         uint32_t mspi_fast_hs_div_num:8;
@@ -1033,7 +1033,7 @@ typedef union {
         uint32_t pvt_monitor_func_clk_div_num:4;
         uint32_t reserved_4:16;
         /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
          *  divided by 3.
          */
         uint32_t pvt_monitor_func_clk_sel:1;
@@ -1499,20 +1499,20 @@ typedef union {
 typedef union {
     struct {
         /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+         *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
          *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
          */
         uint32_t cpu_ls_div_num:8;
         /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
+         *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed
          *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
          */
         uint32_t cpu_hs_div_num:8;
         /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0;
          *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
-         *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+         *  Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
          */
         uint32_t cpu_hs_120m_force:1;
         uint32_t reserved_17:15;
@@ -1526,15 +1526,15 @@ typedef union {
 typedef union {
     struct {
         /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
-         *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+         *  Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb
+         *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
          *  low-speed clock-source such as XTAL/FOSC, and should be used together with
          *  PCR_CPU_LS_DIV_NUM.
          */
         uint32_t ahb_ls_div_num:8;
         /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3;
-         *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
+         *  Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is
+         *  div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed
          *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
          */
         uint32_t ahb_hs_div_num:8;
@@ -1559,7 +1559,7 @@ typedef union {
          */
         uint32_t apb_decrease_div_num:8;
         /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+         *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
          *  div1(default)/div2/div4 of clk_ahb.
          */
         uint32_t apb_div_num:8;
@@ -1574,38 +1574,38 @@ typedef union {
 typedef union {
     struct {
         /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_240m_clk_en:1;
         /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_160m_clk_en:1;
         /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_120m_clk_en:1;
         /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_80m_clk_en:1;
         /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_48m_clk_en:1;
         /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_40m_clk_en:1;
         /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1;
-         *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_20m_clk_en:1;
         uint32_t reserved_7:25;

components/soc/esp32c6/register/soc/pmu_struct.h

@@ -11,7 +11,7 @@
 extern "C" {
 #endif
 
-#include "soc.h"
+#include "soc/soc.h"
 #include "soc/pmu_reg.h"
 
 typedef union {

components/soc/esp32c6/register/soc/sha_reg.h

@@ -156,7 +156,7 @@ extern "C" {
 #define SHA_DATE_S  0
 
 /** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
+ *  Sha H memory which contains intermediate hash or final hash.
  */
 #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
 #define SHA_H_MEM_SIZE_BYTES 64