change(version): Update version to 5.3.1

Merge branch 'fix/flash_encryption_for_esp32p4_v5.3' into 'release/v5.3'
fix(security): Fixed flash encryption for esp32p4 (v5.3) See merge request espressif/esp-idf!33140
2024-09-03 09:37:24 +08:00 · 2024-09-02 19:46:31 +08:00 · 2024-09-02 13:28:30 +05:30 · 2024-08-29 11:02:09 +08:00 · 2024-08-27 15:50:08 +08:00 · 2024-08-21 23:20:44 +08:00
6899 changed files with 810996 additions and 798130 deletions
--- a/.codespellrc
+++ b/.codespellrc
@@ -1,4 +1,4 @@
 [codespell]
-skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*,*.pem
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr,oen
+skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,ot
 write-changes = true
--- a/.github/workflows/pre_commit_check.yml
+++ b/.github/workflows/pre_commit_check.yml
@@ -40,5 +40,3 @@ jobs:
            echo ""
            exit 1
          fi
-          # Run pre-commit for PowerShell scripts check
-          pre-commit run --hook-stage manual check-powershell-scripts --from-ref base_ref --to-ref pr_ref --show-diff-on-failure
--- a/.gitignore
+++ b/.gitignore
@@ -102,7 +102,6 @@ pytest_embedded_log/
 list_job*.txt
 size_info*.txt
 XUNIT_RESULT*.xml
-.manifest_sha

 # clang config (for LSP)
 .clangd
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -30,6 +30,4 @@ include:
  - '.gitlab/ci/integration_test.yml'
  - '.gitlab/ci/host-test.yml'
  - '.gitlab/ci/deploy.yml'
-  - '.gitlab/ci/post_deploy.yml'
-  - '.gitlab/ci/retry_failed_jobs.yml'
  - '.gitlab/ci/test-win.yml'
--- a/.gitlab/CODEOWNERS
+++ b/.gitlab/CODEOWNERS
@@ -2,248 +2,5 @@
 #
 #    https://docs.gitlab.com/ee/user/project/code_owners.html#the-syntax-of-code-owners-files
 #
-# If more than one rule matches a given file, the latest rule is used.
-# The file should be generally kept sorted, except when it is necessary
-# to use a different order due to the fact above. In that case, use
-# '# sort-order-reset' comment line to reset the sort order.
-#
-# Recipes for a few common cases:
-#
-# 1. Specific directory with all its contents:
-#
-#    /components/app_trace/
-#
-#    Note the trailing slash!
-#
-# 2. File with certain extension in any subdirectory of a certain directory:
-#
-#    /examples/**/*.py
-#
-#    This includes an *.py files in /examples/ directory as well.
-#
-# 3. Contents of a directory with a certain name, anywhere in the tree:
-#
-#    test_*_host/
-#
-#    Will match everything under components/efuse/test_efuse_host/,
-#    components/heap/test_multi_heap_host/, components/lwip/test_afl_host/, etc.
-#
-# 4. Same as above, except limited to a specific place in the tree:
-#
-#    /components/esp32*/
-#
-#    Matches everything under /components/esp32, /components/esp32s2, etc.
-#    Doesn't match /tools/some-test/components/esp32s5.
-#
-# 5. Specific file:
-#
-#    /tools/tools.json
-#
-# 6. File with a certain name anywhere in the tree
-#
-#    .gitignore
-#

-* @esp-idf-codeowners/other
-
-/.*                                   @esp-idf-codeowners/tools
-/.codespellrc                         @esp-idf-codeowners/ci
-/.github/workflows/                   @esp-idf-codeowners/ci
-/.gitlab-ci.yml                       @esp-idf-codeowners/ci
-/.gitlab/ci/                          @esp-idf-codeowners/ci
-/.pre-commit-config.yaml              @esp-idf-codeowners/ci
-/.readthedocs.yml                     @esp-idf-codeowners/docs
-/.vale.ini                            @esp-idf-codeowners/docs
-/CMakeLists.txt                       @esp-idf-codeowners/build-config
-/COMPATIBILITY*.md                    @esp-idf-codeowners/peripherals
-/CONTRIBUTING.md                      @esp-idf-codeowners/docs
-/Kconfig                              @esp-idf-codeowners/build-config
-/README*.md                           @esp-idf-codeowners/docs
-/ROADMAP*.md                          @esp-idf-codeowners/docs
-/SUPPORT_POLICY*.md                   @esp-idf-codeowners/docs
-/add_path.sh                          @esp-idf-codeowners/tools
-/conftest.py                          @esp-idf-codeowners/ci
-/export.*                             @esp-idf-codeowners/tools
-/install.*                            @esp-idf-codeowners/tools
-/pytest.ini                           @esp-idf-codeowners/ci
-/sdkconfig.rename                     @esp-idf-codeowners/build-config
-/sonar-project.properties             @esp-idf-codeowners/ci
-
-# sort-order-reset
-
-/components/app_trace/                @esp-idf-codeowners/debugging
-/components/app_update/               @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities
-/components/bootloader*/              @esp-idf-codeowners/system @esp-idf-codeowners/security
-/components/bootloader_support/bootloader_flash/    @esp-idf-codeowners/peripherals
-/components/bt/                       @esp-idf-codeowners/bluetooth
-/components/cmock/                    @esp-idf-codeowners/system
-/components/console/                  @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities/console
-/components/cxx/                      @esp-idf-codeowners/system
-/components/driver/                   @esp-idf-codeowners/peripherals
-/components/efuse/                    @esp-idf-codeowners/system
-/components/esp_adc/                  @esp-idf-codeowners/peripherals
-/components/esp_app_format/           @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities
-/components/esp_bootloader_format/    @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities
-/components/esp_coex/                 @esp-idf-codeowners/wifi @esp-idf-codeowners/bluetooth @esp-idf-codeowners/ieee802154
-/components/esp_common/               @esp-idf-codeowners/system
-/components/esp_driver_*/             @esp-idf-codeowners/peripherals
-/components/esp_driver_sdmmc/         @esp-idf-codeowners/peripherals @esp-idf-codeowners/storage
-/components/esp_eth/                  @esp-idf-codeowners/network
-/components/esp_event/                @esp-idf-codeowners/system
-/components/esp_gdbstub/              @esp-idf-codeowners/debugging
-/components/esp_hid/                  @esp-idf-codeowners/bluetooth
-/components/esp_http_client/          @esp-idf-codeowners/app-utilities
-/components/esp_http_server/          @esp-idf-codeowners/app-utilities
-/components/esp_https_ota/            @esp-idf-codeowners/app-utilities
-/components/esp_https_server/         @esp-idf-codeowners/app-utilities
-/components/esp_hw_support/           @esp-idf-codeowners/system @esp-idf-codeowners/peripherals
-/components/esp_hw_support/lowpower/  @esp-idf-codeowners/power-management
-/components/esp_lcd/                  @esp-idf-codeowners/peripherals
-/components/esp_local_ctrl/           @esp-idf-codeowners/app-utilities
-/components/esp_mm/                   @esp-idf-codeowners/peripherals
-/components/esp_netif/                @esp-idf-codeowners/network
-/components/esp_netif_stack/          @esp-idf-codeowners/network
-/components/esp_partition/            @esp-idf-codeowners/storage
-/components/esp_phy/                  @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/ieee802154
-/components/esp_pm/                   @esp-idf-codeowners/power-management @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/system
-/components/esp_psram/                @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
-/components/esp_ringbuf/              @esp-idf-codeowners/system
-/components/esp_rom/                  @esp-idf-codeowners/system @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi
-/components/esp_security/             @esp-idf-codeowners/security
-/components/esp_system/               @esp-idf-codeowners/system
-/components/esp_timer/                @esp-idf-codeowners/system
-/components/esp-tls/                  @esp-idf-codeowners/app-utilities
-/components/esp_vfs_*/                @esp-idf-codeowners/storage
-/components/esp_vfs_console/          @esp-idf-codeowners/storage @esp-idf-codeowners/system
-/components/esp_wifi/                 @esp-idf-codeowners/wifi
-/components/espcoredump/              @esp-idf-codeowners/debugging
-/components/esptool_py/               @esp-idf-codeowners/tools
-/components/fatfs/                    @esp-idf-codeowners/storage
-/components/freertos/                 @esp-idf-codeowners/system
-/components/hal/                      @esp-idf-codeowners/peripherals
-/components/hal/test_apps/crypto/     @esp-idf-codeowners/peripherals @esp-idf-codeowners/security
-/components/heap/                     @esp-idf-codeowners/system
-/components/http_parser/              @esp-idf-codeowners/app-utilities
-/components/idf_test/                 @esp-idf-codeowners/ci
-/components/ieee802154/               @esp-idf-codeowners/ieee802154
-/components/json/                     @esp-idf-codeowners/app-utilities
-/components/linux/                    @esp-idf-codeowners/system
-/components/log/                      @esp-idf-codeowners/system
-/components/lwip/                     @esp-idf-codeowners/lwip
-/components/mbedtls/                  @esp-idf-codeowners/app-utilities/mbedtls @esp-idf-codeowners/security
-/components/mqtt/                     @esp-idf-codeowners/network
-/components/newlib/                   @esp-idf-codeowners/system @esp-idf-codeowners/toolchain
-/components/nvs_flash/                @esp-idf-codeowners/storage
-/components/nvs_sec_provider/         @esp-idf-codeowners/storage @esp-idf-codeowners/security
-/components/openthread/               @esp-idf-codeowners/ieee802154
-/components/partition_table/          @esp-idf-codeowners/system
-/components/perfmon/                  @esp-idf-codeowners/debugging
-/components/protobuf-c/               @esp-idf-codeowners/app-utilities
-/components/protocomm/                @esp-idf-codeowners/app-utilities/provisioning
-/components/pthread/                  @esp-idf-codeowners/system
-/components/riscv/                    @esp-idf-codeowners/system
-/components/rt/                       @esp-idf-codeowners/system
-/components/sdmmc/                    @esp-idf-codeowners/storage
-/components/soc/                      @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
-/components/spi_flash/                @esp-idf-codeowners/peripherals
-/components/spiffs/                   @esp-idf-codeowners/storage
-/components/tcp_transport/            @esp-idf-codeowners/network
-/components/touch_element/            @esp-idf-codeowners/peripherals
-/components/ulp/                      @esp-idf-codeowners/system
-/components/unity/                    @esp-idf-codeowners/ci
-/components/usb/                      @esp-idf-codeowners/peripherals/usb
-/components/vfs/                      @esp-idf-codeowners/storage
-/components/wear_levelling/           @esp-idf-codeowners/storage
-/components/wifi_provisioning/        @esp-idf-codeowners/app-utilities/provisioning
-/components/wpa_supplicant/           @esp-idf-codeowners/wifi @esp-idf-codeowners/app-utilities/mbedtls
-/components/xtensa/                   @esp-idf-codeowners/system
-
-/docs/                                      @esp-idf-codeowners/docs
-/docs/docs_not_updated/                     @esp-idf-codeowners/all-maintainers
-/docs/**/api-guides/tools/                  @esp-idf-codeowners/tools
-/docs/en/api-guides/core_dump.rst           @esp-idf-codeowners/debugging
-/docs/**/api-guides/wifi*                   @esp-idf-codeowners/wifi
-/docs/**/api-guides/esp-wifi-mesh.rst       @esp-idf-codeowners/wifi
-/docs/en/api-guides/jtag-debugging/         @esp-idf-codeowners/debugging
-/docs/**/api-reference/bluetooth/           @esp-idf-codeowners/bluetooth
-/docs/**/api-reference/network/             @esp-idf-codeowners/network @esp-idf-codeowners/wifi
-/docs/**/api-reference/peripherals/         @esp-idf-codeowners/peripherals
-/docs/**/api-reference/peripherals/usb*     @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
-/docs/**/api-reference/peripherals/usb*/    @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
-/docs/**/api-reference/protocols/           @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/docs/**/api-reference/provisioning/        @esp-idf-codeowners/app-utilities/provisioning
-/docs/**/api-reference/storage/             @esp-idf-codeowners/storage
-/docs/**/api-reference/system/              @esp-idf-codeowners/system
-/docs/**/security/                          @esp-idf-codeowners/security
-/docs/**/migration-guides/                  @esp-idf-codeowners/docs @esp-idf-codeowners/all-maintainers
-/docs/**/contribute/install-pre-commit-hook.rst @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-
-/examples/README.md           @esp-idf-codeowners/docs @esp-idf-codeowners/ci
-/examples/**/*.py             @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-/examples/bluetooth/          @esp-idf-codeowners/bluetooth
-/examples/build_system/       @esp-idf-codeowners/build-config
-/examples/common_components/  @esp-idf-codeowners/system @esp-idf-codeowners/wifi @esp-idf-codeowners/lwip @esp-idf-codeowners/network
-/examples/custom_bootloader/  @esp-idf-codeowners/system
-/examples/cxx/                @esp-idf-codeowners/system
-/examples/ethernet/           @esp-idf-codeowners/network
-/examples/get-started/        @esp-idf-codeowners/system
-/examples/ieee802154/         @esp-idf-codeowners/ieee802154
-/examples/mesh/               @esp-idf-codeowners/wifi
-/examples/network/            @esp-idf-codeowners/network @esp-idf-codeowners/wifi
-/examples/openthread/         @esp-idf-codeowners/ieee802154
-/examples/peripherals/        @esp-idf-codeowners/peripherals
-/examples/peripherals/usb/    @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
-/examples/phy/                @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/ieee802154
-/examples/protocols/          @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/examples/provisioning/       @esp-idf-codeowners/app-utilities/provisioning
-/examples/security/           @esp-idf-codeowners/security
-/examples/storage/            @esp-idf-codeowners/storage
-/examples/system/             @esp-idf-codeowners/system
-/examples/system/ota/         @esp-idf-codeowners/app-utilities
-/examples/wifi/               @esp-idf-codeowners/wifi
-/examples/zigbee/             @esp-idf-codeowners/ieee802154
-
-/tools/                       @esp-idf-codeowners/tools
-/tools/ble/                   @esp-idf-codeowners/app-utilities
-/tools/catch/                 @esp-idf-codeowners/ci
-/tools/ci/                    @esp-idf-codeowners/ci
-/tools/cmake/                 @esp-idf-codeowners/build-config
-/tools/cmake/toolchain-*.cmake      @esp-idf-codeowners/toolchain
-/tools/esp_app_trace/         @esp-idf-codeowners/debugging
-/tools/esp_prov/              @esp-idf-codeowners/app-utilities
-/tools/gdb_panic_server.py    @esp-idf-codeowners/debugging
-/tools/kconfig*/              @esp-idf-codeowners/build-config
-/tools/ldgen/                 @esp-idf-codeowners/build-config
-/tools/mass_mfg/              @esp-idf-codeowners/app-utilities
-/tools/mocks/                 @esp-idf-codeowners/system
-
-/tools/test_apps/                    @esp-idf-codeowners/ci
-/tools/test_apps/README.md           @esp-idf-codeowners/docs @esp-idf-codeowners/ci
-
-## Note: owners here should be the same as the owners for the same example subdir, above
-/tools/test_apps/build_system/       @esp-idf-codeowners/build-config
-/tools/test_apps/configs/            @esp-idf-codeowners/system
-/tools/test_apps/linux_compatible/   @esp-idf-codeowners/system
-/tools/test_apps/peripherals/        @esp-idf-codeowners/peripherals
-/tools/test_apps/phy/                @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/ieee802154
-/tools/test_apps/protocols/          @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/tools/test_apps/security/           @esp-idf-codeowners/security
-/tools/test_apps/storage/            @esp-idf-codeowners/storage
-/tools/test_apps/system/             @esp-idf-codeowners/system
-
-/tools/test_apps/**/*.py             @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-
-/tools/test_build_system/     @esp-idf-codeowners/tools @esp-idf-codeowners/build-config
-
-/tools/tools.json             @esp-idf-codeowners/tools @esp-idf-codeowners/toolchain @esp-idf-codeowners/debugging
-
-/tools/unit-test-app/         @esp-idf-codeowners/system @esp-idf-codeowners/tools
-
-# sort-order-reset
-
-/components/**/test_apps/**/*.py     @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-
-# ignore lists
-/tools/ci/check_copyright_config.yaml                   @esp-idf-codeowners/all-maintainers
-/tools/ci/check_copyright_ignore.txt                    @esp-idf-codeowners/all-maintainers
-/tools/ci/mypy_ignore_list.txt                          @esp-idf-codeowners/tools
+* @esp-idf-codeowners/all-maintainers
--- a/.gitlab/ci/build.yml
+++ b/.gitlab/ci/build.yml
@@ -56,7 +56,7 @@
  variables:
    IDF_TOOLCHAIN: clang
    TEST_BUILD_OPTS_EXTRA: ""
-    TEST_DIR: tools/test_apps/system/clang_build_test
+    TEST_DIR: tools/test_apps/system/cxx_pthread_bluetooth
  script:
    # CI specific options start from "--parallel-count xxx". could ignore when running locally
    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
@@ -112,22 +112,6 @@ fast_template_app:
    BUILD_COMMAND_ARGS: "-p"
 #------------------------------------------------------------------------------

-#######################
-# gnu_static_analyzer #
-#######################
-gcc_static_analyzer:
-  extends:
-    - .build_template_app_template
-    - .rules:build:target_test
-  stage: pre_check
-  tags: [build, shiny]
-  variables:
-    CI_CCACHE_DISABLE: 1
-    ANALYZING_APP: "examples/get-started/hello_world"
-  script:
-    - echo "CONFIG_COMPILER_STATIC_ANALYZER=y" >> ${ANALYZING_APP}/sdkconfig.defaults
-    - python -m idf_build_apps build -vv -p ${ANALYZING_APP} -t all
-
 ########################################
 # Clang Build Apps Without Tests Cases #
 ########################################
@@ -156,12 +140,11 @@ build_clang_test_apps_esp32s3:
  extends:
    - .build_cmake_clang_template
  variables:
-    # https://reviews.llvm.org/D90108.
-    # GNU 'as' lets .weak override .globl since binutils-gdb
-    # https://github.com/bminor/binutils-gdb/commit/5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996)
-    # while MC lets the last directive win (PR38921).
-    # For RISCV chips we use integrated assembler by default, so suppress this warning to pass CI pipeline.
-    TEST_BUILD_OPTS_EXTRA: "--ignore-warning-str 'changed binding to STB_WEAK'"
+    # For RISCV clang generates '.linker-options' sections of type 'llvm_linker_options' in asm files.
+    # See (https://llvm.org/docs/Extensions.html#linker-options-section-linker-options).
+    # Binutils gas ignores them with warning.
+    # TODO: LLVM-112, Use integrated assembler.
+    TEST_BUILD_OPTS_EXTRA: "--ignore-warning-str 'Warning: unrecognized section type'"

 build_clang_test_apps_esp32c3:
  extends:
@@ -181,30 +164,11 @@ build_clang_test_apps_esp32c6:
  extends:
    - .build_clang_test_apps_riscv
    - .rules:build
+  # TODO: c6 builds fail in master due to missing headers
+  allow_failure: true
  variables:
    IDF_TARGET: esp32c6

-build_clang_test_apps_esp32c5:
-  extends:
-    - .build_clang_test_apps_riscv
-    - .rules:build
-  variables:
-    IDF_TARGET: esp32c5
-
-build_clang_test_apps_esp32h2:
-  extends:
-    - .build_clang_test_apps_riscv
-    - .rules:build
-  variables:
-    IDF_TARGET: esp32h2
-
-build_clang_test_apps_esp32p4:
-  extends:
-    - .build_clang_test_apps_riscv
-    - .rules:build
-  variables:
-    IDF_TARGET: esp32p4
-
 ######################
 # Build System Tests #
 ######################
@@ -300,8 +264,6 @@ generate_build_child_pipeline:
  dependencies: # set dependencies to null to avoid missing artifacts issue
  needs:
    - pipeline_variables
-    - job: baseline_manifest_sha
-      optional: true
  artifacts:
    paths:
      - build_child_pipeline.yml
@@ -309,11 +271,7 @@ generate_build_child_pipeline:
      - non_test_related_apps.txt
    expire_in: 1 week
    when: always
-  variables:
-    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
  script:
-    # requires basic pytest dependencies
-    - run_cmd bash install.sh --enable-pytest
    - run_cmd python tools/ci/dynamic_pipelines/scripts/generate_build_child_pipeline.py

 build_child_pipeline:
@@ -330,7 +288,6 @@ build_child_pipeline:
    MR_MODIFIED_FILES: $MR_MODIFIED_FILES
    PARENT_PIPELINE_ID: $CI_PIPELINE_ID
    BUILD_AND_TEST_ALL_APPS: $BUILD_AND_TEST_ALL_APPS
-    REPORT_EXIT_CODE: $REPORT_EXIT_CODE
  # https://gitlab.com/gitlab-org/gitlab/-/issues/214340
  inherit:
    variables: false
--- a/.gitlab/ci/common.yml
+++ b/.gitlab/ci/common.yml
@@ -12,7 +12,6 @@ stages:
  - test_deploy
  - deploy
  - post_deploy
-  - retry_failed_jobs

 variables:
 # System environment
@@ -40,7 +39,7 @@ variables:
  GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
  # we're using .cache folder for caches
  GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.4-dev
+  LATEST_GIT_TAG: v5.3.1

  SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
  # by default we will fetch all submodules
@@ -55,12 +54,15 @@ variables:
  CHECKOUT_REF_SCRIPT: "$CI_PROJECT_DIR/tools/ci/checkout_project_ref.py"

  # Docker images
-  ESP_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-env-v5.5:1"
-  ESP_IDF_DOC_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-doc-env-v5.5:1-1"
-  TARGET_TEST_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/target-test-env-v5.5:1"
+  ESP_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-env-v5.3:1"
+  ESP_IDF_DOC_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-doc-env-v5.3:1-1"
+  TARGET_TEST_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/target-test-env-v5.3:1"
  SONARQUBE_SCANNER_IMAGE: "${CI_DOCKER_REGISTRY}/sonarqube-scanner:5"
  PRE_COMMIT_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-pre-commit:1"

+  # target test repo parameters
+  TEST_ENV_CONFIG_REPO: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/qa/ci-test-runner-configs.git"
+
  # cache python dependencies
  PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip"

@@ -70,7 +72,7 @@ variables:
  CI_PYTHON_CONSTRAINT_BRANCH: ""

  # Update the filename for a specific ESP-IDF release. It is used only with CI_PYTHON_CONSTRAINT_BRANCH.
-  CI_PYTHON_CONSTRAINT_FILE: "espidf.constraints.v5.5.txt"
+  CI_PYTHON_CONSTRAINT_FILE: "espidf.constraints.v5.3.txt"

  # Set this variable to repository name of a Python tool you wish to install and test in the context of ESP-IDF CI.
  # Keep the variable empty when not used.
@@ -81,14 +83,8 @@ variables:
  # This is used only if CI_PYTHON_TOOL_REPO is not empty.
  CI_PYTHON_TOOL_BRANCH: ""

-  # Set this variable to Clang toolchain distro URL to be used.
-  # NOTE: We have separate toolchains for Xtensa and RISCV, therefore jobs for one arch will fail.
-  # This is OK as far as we use CI_CLANG_DISTRO_URL for pre-release tests purposes only.
-  # Keep the variable empty when not used.
-  CI_CLANG_DISTRO_URL: ""
-
  # Set this variable to specify the file name for the known failure cases.
-  KNOWN_FAILURE_CASES_FILE_NAME: "master.txt"
+  KNOWN_FAILURE_CASES_FILE_NAME: "5.3.txt"

  IDF_CI_BUILD: 1

@@ -100,8 +96,6 @@ variables:
  CCACHE_DIR: "/cache/idf_ccache"
  CCACHE_MAXSIZE: "50G"

-  FF_USE_NEW_BASH_EVAL_STRATEGY: "true"
-
 ################################################
 # `before_script` and `after_script` Templates #
 ################################################
@@ -144,21 +138,21 @@ variables:
  # install latest python packages
  # target test jobs
  if [[ "${CI_JOB_STAGE}" == "target_test" ]]; then
-    run_cmd bash install.sh --enable-ci --enable-pytest --enable-test-specific
+    run_cmd bash install.sh --enable-ci --enable-pytest
  elif [[ "${CI_JOB_STAGE}" == "build_doc" ]]; then
    run_cmd bash install.sh --enable-ci --enable-docs
  elif [[ "${CI_JOB_STAGE}" == "build" ]]; then
-    run_cmd bash install.sh --enable-ci
+    run_cmd bash install.sh --enable-ci --enable-pytest
  else
    if ! echo "${CI_JOB_NAME}" | egrep ".*pytest.*"; then
      run_cmd bash install.sh --enable-ci
    else
-      run_cmd bash install.sh --enable-ci --enable-pytest --enable-test-specific
+      run_cmd bash install.sh --enable-ci --enable-pytest
    fi
  fi

  # Install esp-clang if necessary
-  if [[ "$IDF_TOOLCHAIN" == "clang" && -z "$CI_CLANG_DISTRO_URL" ]]; then
+  if [[ "$IDF_TOOLCHAIN" == "clang" ]]; then
    $IDF_PATH/tools/idf_tools.py --non-interactive install esp-clang
  fi

@@ -173,7 +167,7 @@ variables:

  source ./export.sh

-  # Custom clang toolchain
+  # Custom clang
  if [[ ! -z "$CI_CLANG_DISTRO_URL" ]]; then
    echo "Using custom clang from ${CI_CLANG_DISTRO_URL}"
    wget $CI_CLANG_DISTRO_URL
@@ -220,8 +214,6 @@ variables:
    - *common-before_scripts
    # On macOS, these tools need to be installed
    - export IDF_TOOLS_PATH="${HOME}/.espressif_runner_${CI_RUNNER_ID}_${CI_CONCURRENT_ID}"
-    # remove idf-env.json, since it may contains enabled "features"
-    - rm -f $IDF_TOOLS_PATH/idf-env.json
    - $IDF_PATH/tools/idf_tools.py --non-interactive install cmake ninja
    # This adds tools (compilers) and the version-specific Python environment to PATH
    - *setup_tools_and_idf_python_venv
@@ -287,8 +279,8 @@ variables:
    git remote add origin "${CI_REPOSITORY_URL}"
  fi

-.git_checkout_ci_commit_sha: &git_checkout_ci_commit_sha |
-  git checkout $CI_COMMIT_SHA
+.git_checkout_fetch_head: &git_checkout_fetch_head |
+  git checkout FETCH_HEAD
  git clean ${GIT_CLEAN_FLAGS}

 # git diff requires two commits, with different CI env var
@@ -312,7 +304,6 @@ variables:
        git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
        git fetch origin $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
        export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_MERGE_REQUEST_DIFF_BASE_SHA $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA)
-        git fetch origin $CI_COMMIT_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
      # merge request pipelines, when the mr got conflicts
      elif [[ -n $CI_MERGE_REQUEST_DIFF_BASE_SHA ]]; then
        git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
@@ -328,7 +319,7 @@ variables:
        git fetch origin $CI_COMMIT_SHA --depth=2 ${GIT_FETCH_EXTRA_FLAGS}
        export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_COMMIT_SHA~1 $CI_COMMIT_SHA)
      fi
-    - *git_checkout_ci_commit_sha
+    - *git_checkout_fetch_head
    - *common-before_scripts
    - *setup_tools_and_idf_python_venv
    - add_gitlab_ssh_keys
@@ -342,7 +333,7 @@ variables:
    - *git_init
    - *git_fetch_from_mirror_url_if_exists
    - git fetch origin "${CI_COMMIT_SHA}" --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
-    - *git_checkout_ci_commit_sha
+    - *git_checkout_fetch_head
    - *common-before_scripts
    - *setup_tools_and_idf_python_venv
    - add_gitlab_ssh_keys
--- a/.gitlab/ci/danger.yml
+++ b/.gitlab/ci/danger.yml
@@ -1,4 +1,4 @@
-# External DangerJS
+# Extenal DangerJS
 include:
  - project: espressif/shared-ci-dangerjs
    ref: master
@@ -10,6 +10,7 @@ run-danger-mr-linter:
    GIT_STRATEGY: none # no repo checkout
    ENABLE_CHECK_AREA_LABELS: 'true'
    ENABLE_CHECK_DOCS_TRANSLATION: 'true'
+    ENABLE_CHECK_RELEASE_NOTES_DESCRIPTION: 'true'
    ENABLE_CHECK_UPDATED_CHANGELOG: 'false'
  before_script: []
  cache: []
--- a/.gitlab/ci/default-build-test-rules.yml
+++ b/.gitlab/ci/default-build-test-rules.yml
@@ -7,11 +7,12 @@
 #
 # This file should ONLY be used during bringup. Should be reset to empty after the bringup process
 extra_default_build_targets:
+  - esp32p4
  - esp32c5
-  - esp32c61

 bypass_check_test_targets:
-
+  - esp32c5
+  - esp32c61
 #
 # These lines would
 # - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
--- a/.gitlab/ci/docs.yml
+++ b/.gitlab/ci/docs.yml
@@ -102,7 +102,7 @@ check_docs_lang_sync:
  parallel:
    matrix:
      - DOCLANG: ["en", "zh_CN"]
-        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c61", "esp32c5","esp32h2", "esp32p4"]
+        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c5","esp32h2", "esp32p4"]

 check_docs_gh_links:
  image: $ESP_IDF_DOC_ENV_IMAGE
@@ -171,7 +171,6 @@ build_docs_pdf:
    - job: fast_template_app
      artifacts: false
      optional: true
-  allow_failure: true # TODO IDFCI-2216
  artifacts:
    paths:
      - docs/_build/*/*/latex/*
@@ -183,7 +182,6 @@ build_docs_pdf_prod:
    - .build_docs_template
    - .doc-rules:build:docs-full-prod
  dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts
-  allow_failure: true # TODO IDFCI-2216
  artifacts:
    paths:
      - docs/_build/*/*/latex/*
--- a/.gitlab/ci/host-test.yml
+++ b/.gitlab/ci/host-test.yml
@@ -34,16 +34,22 @@ check_public_headers:
    - IDF_TARGET=esp32p4 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
    - IDF_TARGET=esp32c61 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-

+test_nvs_on_host:
+  extends: .host_test_template
+  script:
+    - cd components/nvs_flash/test_nvs_host
+    - make test
+
 test_nvs_coverage:
  extends:
    - .host_test_template
    - .rules:labels:nvs_coverage
  artifacts:
    paths:
-      - components/nvs_flash/host_test/nvs_host_test/coverage_report
+      - components/nvs_flash/test_nvs_host/coverage_report
  script:
-    - cd components/nvs_flash/host_test/nvs_host_test
-    - idf.py build coverage
+    - cd components/nvs_flash/test_nvs_host
+    - make coverage_report
  # the 'long' host tests take approx 11 hours on our current runners. Adding some margin here for possible CPU contention
  timeout: 18 hours

@@ -62,6 +68,22 @@ test_ldgen_on_host:
  variables:
    LC_ALL: C.UTF-8

+test_reproducible_build:
+  extends: .host_test_template
+  script:
+    - ./tools/ci/test_reproducible_build.sh
+  artifacts:
+    when: on_failure
+    paths:
+      - "**/sdkconfig"
+      - "**/build*/*.bin"
+      - "**/build*/*.elf"
+      - "**/build*/*.map"
+      - "**/build*/flasher_args.json"
+      - "**/build*/*.bin"
+      - "**/build*/bootloader/*.bin"
+      - "**/build*/partition_table/*.bin"
+
 test_spiffs_on_host:
  extends: .host_test_template
  script:
@@ -277,16 +299,16 @@ test_pytest_qemu:
    paths:
      - XUNIT_RESULT.xml
      - pytest-embedded/
-      - "**/build*/*.bin"
    reports:
      junit: XUNIT_RESULT.xml
+  allow_failure: true # IDFCI-1752
  parallel:
    matrix:
      - IDF_TARGET: [esp32, esp32c3]
  variables:
    INSTALL_QEMU: 1
  script:
-    - run_cmd python tools/ci/ci_build_apps.py . -v
+    - run_cmd python tools/ci/ci_build_apps.py . -vv
      --target $IDF_TARGET
      --pytest-apps
      -m qemu
@@ -296,7 +318,6 @@ test_pytest_qemu:
    - python tools/ci/get_known_failure_cases_file.py
    - run_cmd pytest
      --target $IDF_TARGET
-      --log-cli-level DEBUG
      -m qemu
      --embedded-services idf,qemu
      --junitxml=XUNIT_RESULT.xml
@@ -315,50 +336,18 @@ test_pytest_linux:
      - "**/build*/build_log.txt"
    reports:
      junit: XUNIT_RESULT.xml
-  script:
-    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -v
-      --target linux
-      --pytest-apps
-      -m host_test
-      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
-      --modified-components ${MR_MODIFIED_COMPONENTS}
-      --modified-files ${MR_MODIFIED_FILES}
-    - python tools/ci/get_known_failure_cases_file.py
-    - run_cmd pytest
-      --target linux
-      -m host_test
-      --embedded-services idf
-      --junitxml=XUNIT_RESULT.xml
-      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
-      --app-info-filepattern \"list_job_*.txt\"
-
-test_pytest_macos:
-  extends:
-    - .host_test_template
-    - .before_script:build:macos
-  tags:
-    - macos_shell
-  artifacts:
-    paths:
-      - XUNIT_RESULT.xml
-      - pytest-embedded/
-      - "**/build*/build_log.txt"
-    reports:
-      junit: XUNIT_RESULT.xml
-  variables:
-    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
  script:
    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -vv
      --target linux
      --pytest-apps
-      -m \"host_test and macos_shell\"
+      -m host_test
      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
      --modified-components ${MR_MODIFIED_COMPONENTS}
      --modified-files ${MR_MODIFIED_FILES}
    - python tools/ci/get_known_failure_cases_file.py
    - run_cmd pytest
      --target linux
-      -m \"host_test and macos_shell\"
+      -m host_test
      --junitxml=XUNIT_RESULT.xml
      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
      --app-info-filepattern \"list_job_*.txt\"
@@ -373,44 +362,5 @@ test_idf_pytest_plugin:
    reports:
      junit: XUNIT_RESULT.xml
  script:
-    - cd ${IDF_PATH}/tools/ci/dynamic_pipelines/tests/test_report_generator
-    - python -m unittest test_report_generator.py
-    - cd ${IDF_PATH}/tools/ci/idf_pytest
+    - cd tools/ci/idf_pytest
    - pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
-
-test_idf_build_apps_load_soc_caps:
-  extends: .host_test_template
-  script:
-    - python tools/ci/check_soc_headers_load_in_idf_build_apps.py
-
-test_nvs_gen_check:
-  extends: .host_test_template
-  artifacts:
-    paths:
-      - XUNIT_RESULT.xml
-      - components/nvs_flash/nvs_partition_tool
-    reports:
-      junit: XUNIT_RESULT.xml
-  variables:
-    LC_ALL: C.UTF-8
-  script:
-    - cd ${IDF_PATH}/components/nvs_flash/nvs_partition_tool
-    - pytest --noconftest test_nvs_gen_check.py --junitxml=XUNIT_RESULT.xml
-
-make_sure_soc_caps_compatible_in_idf_build_apps:
-    extends:
-      - .host_test_template
-      - .rules:dev-push
-    artifacts:
-      paths:
-        - new.json
-        - base.json
-      when: always
-    when: manual
-    script:
-      - python tools/ci/idf_build_apps_dump_soc_caps.py new.json
-      - git fetch --depth=1 origin $CI_MERGE_REQUEST_DIFF_BASE_SHA
-      - git checkout -f $CI_MERGE_REQUEST_DIFF_BASE_SHA
-      - git checkout $CI_COMMIT_SHA -- tools/ci/idf_build_apps_dump_soc_caps.py
-      - python tools/ci/idf_build_apps_dump_soc_caps.py base.json
-      - diff new.json base.json
--- a/.gitlab/ci/post_deploy.yml
+++ b/.gitlab/ci/post_deploy.yml
@@ -1,13 +0,0 @@
-generate_failed_jobs_report:
-  stage: post_deploy
-  tags: [build, shiny]
-  image: $ESP_ENV_IMAGE
-  when: always
-  dependencies: []  # Do not download artifacts from the previous stages
-  artifacts:
-    expire_in: 1 week
-    when: always
-    paths:
-      - job_report.html
-  script:
-    - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type job
--- a/.gitlab/ci/pre_check.yml
+++ b/.gitlab/ci/pre_check.yml
@@ -44,9 +44,6 @@ check_blobs:
    - IDF_TARGET=esp32c2 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
    - IDF_TARGET=esp32c3 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
    - IDF_TARGET=esp32c6 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
-    - IDF_TARGET=esp32c5 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
-    - IDF_TARGET=esp32c61 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
-    - IDF_TARGET=esp32_host $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
    # Check if Coexistence library header files match between IDF and the version used when compiling the libraries
    - IDF_TARGET=esp32 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
    - IDF_TARGET=esp32s2 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
@@ -55,8 +52,6 @@ check_blobs:
    - IDF_TARGET=esp32c3 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
    - IDF_TARGET=esp32c6 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
    - IDF_TARGET=esp32h2 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
-    - IDF_TARGET=esp32c5 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
-    - IDF_TARGET=esp32c61 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
    # Check if Wi-Fi, PHY, BT blobs contain references to specific symbols
    - bash $IDF_PATH/tools/ci/check_blobs.sh

@@ -117,10 +112,8 @@ check_test_scripts_build_test_rules:
  extends:
    - .pre_check_template
    - .before_script:build
-  variables:
-    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
  script:
-    # requires basic pytest dependencies
+    # required pytest related packages
    - run_cmd bash install.sh --enable-pytest
    - python tools/ci/check_build_test_rules.py check-test-scripts examples/ tools/test_apps components

@@ -142,7 +135,6 @@ pipeline_variables:
    # MODIFIED_FILES is a list of files that changed, could be used everywhere
    - MODIFIED_FILES=$(echo "$GIT_DIFF_OUTPUT" | xargs)
    - echo "MODIFIED_FILES=$MODIFIED_FILES" >> pipeline.env
-    - echo "REPORT_EXIT_CODE=0" >> pipeline.env
    # MR_MODIFIED_FILES and MR_MODIFIED_COMPONENTS are semicolon separated lists that is used in MR only
    # for non MR pipeline, these are empty lists
    - |
@@ -165,7 +157,6 @@ pipeline_variables:
      if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
        echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
      fi
-    - python tools/ci/ci_process_description.py
    - cat pipeline.env
    - python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report
  artifacts:
@@ -175,35 +166,3 @@ pipeline_variables:
      - pipeline.env
    expire_in: 1 week
    when: always
-
-baseline_manifest_sha:
-  extends:
-    - .pre_check_template
-    - .rules:dev-push
-  tags: [fast_run, shiny]
-  script:
-    - |
-      if [ -n "$CI_MERGE_REQUEST_DIFF_BASE_SHA" ]; then
-        git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1
-        git checkout FETCH_HEAD
-        idf-build-apps dump-manifest-sha \
-          --manifest-files $(find . -name ".build-test-rules.yml" | xargs) \
-          --output .manifest_sha
-      fi
-  artifacts:
-    paths:
-      - .manifest_sha
-    expire_in: 1 week
-    when: always
-
-redundant_pass_job:
-  stage: pre_check
-  tags: [shiny, fast_run]
-  image: $ESP_ENV_IMAGE
-  dependencies: null
-  before_script: []
-  cache: []
-  extends: []
-  script:
-    - echo "This job is redundant to ensure the 'retry_failed_jobs' job can exist and not be skipped"
-  when: always
--- a/.gitlab/ci/pre_commit.yml
+++ b/.gitlab/ci/pre_commit.yml
@@ -45,36 +45,3 @@ check_pre_commit:
      paths:
        - .cache/submodule_archives
      policy: pull
-
-check_powershell:
-  extends:
-    - .before_script:minimal
-  stage: pre_check
-  image: docker:latest
-  services:
-    - docker:dind
-  tags:
-    - dind
-    - amd64
-  needs:
-    - pipeline_variables
-  variables:
-    # cache pre_commit
-    PRE_COMMIT_HOME: "$CI_PROJECT_DIR/.cache/pre-commit"
-  rules:
-    - changes:
-        - "*.ps1"
-  script:
-    - apk add python3
-    - apk add py3-pip
-    - pip install pre-commit --break-system-packages
-    - pre-commit run --hook-stage manual check-powershell-scripts --files $MODIFIED_FILES
-  cache:
-    - key: pre_commit-cache-${LATEST_GIT_TAG}
-      paths:
-        - .cache/pre-commit
-      policy: pull
-    - key: submodule-cache-${LATEST_GIT_TAG}
-      paths:
-        - .cache/submodule_archives
-      policy: pull
--- a/.gitlab/ci/retry_failed_jobs.yml
+++ b/.gitlab/ci/retry_failed_jobs.yml
@@ -1,15 +0,0 @@
-retry_failed_jobs:
-  stage: retry_failed_jobs
-  tags: [shiny, fast_run]
-  allow_failure: true
-  image: $ESP_ENV_IMAGE
-  dependencies: null
-  before_script: []
-  cache: []
-  extends: []
-  script:
-    - echo "Retrieving and retrying all failed jobs for the pipeline..."
-    - python tools/ci/python_packages/gitlab_api.py retry_failed_jobs $CI_MERGE_REQUEST_PROJECT_ID --pipeline_id $CI_PIPELINE_ID
-  when: manual
-  needs:
-    - redundant_pass_job
--- a/.gitlab/ci/rules.yml
+++ b/.gitlab/ci/rules.yml
@@ -66,8 +66,6 @@
  - "tools/ci/check_esp_memory_utils_headers.sh"
  - "tools/ci/check_blobs.sh"
  - "tools/ci/check_public_headers.py"
-  - "tools/ci/check_register_rw_half_word.cmake"
-  - "tools/ci/check_register_rw_half_word.py"

 .patterns-host_test: &patterns-host_test
  - ".gitlab/ci/host-test.yml"
@@ -83,8 +81,6 @@

  - "tools/idf_monitor.py"

-  - "tools/activate.py"
-
  - "tools/idf.py"
  - "tools/idf_py_actions/**/*"
  - "tools/test_idf_py/**/*"
@@ -98,11 +94,6 @@
  - "tools/test_idf_tools/**/*"
  - "tools/install_util.py"

-  - "tools/export_utils/utils.py"
-  - "tools/export_utils/shell_types.py"
-  - "tools/export_utils/console_output.py"
-  - "tools/export_utils/activate_venv.py"
-
  - "tools/requirements/*"
  - "tools/requirements.json"
  - "tools/requirements_schema.json"
@@ -115,6 +106,8 @@
  - "tools/detect_python.sh"
  - "tools/detect_python.fish"

+  - "tools/ci/test_reproducible_build.sh"
+
  - "tools/gen_soc_caps_kconfig/*"
  - "tools/gen_soc_caps_kconfig/test/test_gen_soc_caps_kconfig.py"

@@ -155,7 +148,6 @@

 .patterns-idf-pytest-plugin: &patterns-idf-pytest-plugin
  - "tools/ci/idf_pytest/**/*"
-  - "tools/ci/dynamic_pipelines/tests/**/*"

 ##############
 # if anchors #
@@ -225,10 +217,6 @@
  rules:
    - <<: *if-tag-release

-.rules:dev-push:
-  rules:
-    - <<: *if-dev-push
-
 # Do not upload caches on dev branches by default
 .rules:upload-python-cache:
  rules:
@@ -261,14 +249,14 @@
    - <<: *if-dev-push
      changes: *patterns-python-files

-#.rules:patterns:static-code-analysis-preview:
-#  rules:
-#    - <<: *if-dev-push
-#      changes: *patterns-c-files
-#    - <<: *if-dev-push
-#      changes: *patterns-python-files
-#    - <<: *if-dev-push
-#      changes: *patterns-sonarqube-files
+.rules:patterns:static-code-analysis-preview:
+  rules:
+    - <<: *if-dev-push
+      changes: *patterns-c-files
+    - <<: *if-dev-push
+      changes: *patterns-python-files
+    - <<: *if-dev-push
+      changes: *patterns-sonarqube-files

 .rules:patterns:idf-pytest-plugin:
  rules:
--- a/.gitlab/ci/static-code-analysis.yml
+++ b/.gitlab/ci/static-code-analysis.yml
@@ -38,84 +38,84 @@ check_pylint:
      fi
    - if [ -z "$files" ]; then echo "No python files found"; exit 0; fi
    - run_cmd pylint --exit-zero --load-plugins=pylint_gitlab --output-format=gitlab-codeclimate:pylint.json $files
+
+# build stage
+# Sonarqube related jobs put here for this reason:
+# Here we have two jobs. code_quality_check and code_quality_report.
 #
-## build stage
-## Sonarqube related jobs put here for this reason:
-## Here we have two jobs. code_quality_check and code_quality_report.
-##
-## code_quality_check will analyze the code changes between your MR and
-## code repo stored in sonarqube server. The analysis result is only shown in
-## the comments under this MR and won't be transferred to the server.
-##
-## code_quality_report will analyze and transfer both of the newly added code
-## and the analysis result to the server.
-##
-## Put in the front to ensure that the newly merged code can be stored in
-## sonarqube server ASAP, in order to avoid reporting unrelated code issues
-#.sonar_scan_template:
-#  stage: build
-#  extends: .pre_check_template
-#  # full clone since this image does not support fetch --shallow-since-cutoff
-#  # shiny runners are used for full clone
-#  tags: [build, shiny]
-#  image: $SONARQUBE_SCANNER_IMAGE
-#  before_script:
-#    - source tools/ci/utils.sh
-#    - export PYTHONPATH="$CI_PROJECT_DIR/tools:$CI_PROJECT_DIR/tools/ci/python_packages:$PYTHONPATH"
-#    - fetch_submodules
-#    # Exclude the submodules, all paths ends with /**
-#    - submodules=$(get_all_submodules)
-#    # get all exclude paths specified in tools/ci/sonar_exclude_list.txt | ignore lines start with # | xargs | replace all <space> to <comma>
-#    - custom_excludes=$(cat $CI_PROJECT_DIR/tools/ci/sonar_exclude_list.txt | grep -v '^#' | xargs | sed -e 's/ /,/g')
-#    # Exclude the report dir as well
-#    - export EXCLUSIONS="$custom_excludes,$submodules"
-#    - export SONAR_SCANNER_OPTS="-Xmx2048m"
-#  variables:
-#    GIT_DEPTH: 0
-#    REPORT_PATTERN: clang_tidy_reports/**/*.txt
-#  artifacts:
-#    paths:
-#      - $REPORT_PATTERN
-#    expire_in: 1 week
-#    when: always
-#  dependencies:  # Here is not a hard dependency relationship, could be skipped when only python files changed. so we do not use "needs" here.
-#    - clang_tidy_check
+# code_quality_check will analyze the code changes between your MR and
+# code repo stored in sonarqube server. The analysis result is only shown in
+# the comments under this MR and won't be transferred to the server.
 #
-#code_quality_check:
-#  extends:
-#    - .sonar_scan_template
-#    - .rules:patterns:static-code-analysis-preview
-#  allow_failure: true  # it's using exit code to indicate the code analysis result,
-#                       # we don't want to block ci when critical issues founded
-#  script:
-#    - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits --src-branch ${CI_COMMIT_REF_NAME} | tr '\n' ',')
-#    # test if this branch have merge request, if not, exit 0
-#    - test -n "$CI_MERGE_REQUEST_IID" || exit 0
-#    - test -n "$CI_MERGE_REQUEST_COMMITS" || exit 0
-#    - sonar-scanner
-#      -Dsonar.analysis.mode=preview
-#      -Dsonar.branch.name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
-#      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
-#      -Dsonar.exclusions=$EXCLUSIONS
-#      -Dsonar.gitlab.ci_merge_request_iid=$CI_MERGE_REQUEST_IID
-#      -Dsonar.gitlab.commit_sha=$CI_MERGE_REQUEST_COMMITS
-#      -Dsonar.gitlab.merge_request_discussion=true
-#      -Dsonar.gitlab.ref_name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
-#      -Dsonar.host.url=$SONAR_HOST_URL
-#      -Dsonar.login=$SONAR_LOGIN
+# code_quality_report will analyze and transfer both of the newly added code
+# and the analysis result to the server.
 #
-#code_quality_report:
-#  extends:
-#    - .sonar_scan_template
-#    - .rules:protected
-#  allow_failure: true  # it's using exit code to indicate the code analysis result,
-#                       # we don't want to block ci when critical issues founded
-#  script:
-#    - sonar-scanner
-#      -Dsonar.branch.name=$CI_COMMIT_REF_NAME
-#      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
-#      -Dsonar.exclusions=$EXCLUSIONS
-#      -Dsonar.gitlab.commit_sha=$PIPELINE_COMMIT_SHA
-#      -Dsonar.gitlab.ref_name=$CI_COMMIT_REF_NAME
-#      -Dsonar.host.url=$SONAR_HOST_URL
-#      -Dsonar.login=$SONAR_LOGIN
+# Put in the front to ensure that the newly merged code can be stored in
+# sonarqube server ASAP, in order to avoid reporting unrelated code issues
+.sonar_scan_template:
+  stage: build
+  extends: .pre_check_template
+  # full clone since this image does not support fetch --shallow-since-cutoff
+  # shiny runners are used for full clone
+  tags: [build, shiny]
+  image: $SONARQUBE_SCANNER_IMAGE
+  before_script:
+    - source tools/ci/utils.sh
+    - export PYTHONPATH="$CI_PROJECT_DIR/tools:$CI_PROJECT_DIR/tools/ci/python_packages:$PYTHONPATH"
+    - fetch_submodules
+    # Exclude the submodules, all paths ends with /**
+    - submodules=$(get_all_submodules)
+    # get all exclude paths specified in tools/ci/sonar_exclude_list.txt | ignore lines start with # | xargs | replace all <space> to <comma>
+    - custom_excludes=$(cat $CI_PROJECT_DIR/tools/ci/sonar_exclude_list.txt | grep -v '^#' | xargs | sed -e 's/ /,/g')
+    # Exclude the report dir as well
+    - export EXCLUSIONS="$custom_excludes,$submodules"
+    - export SONAR_SCANNER_OPTS="-Xmx2048m"
+  variables:
+    GIT_DEPTH: 0
+    REPORT_PATTERN: clang_tidy_reports/**/*.txt
+  artifacts:
+    paths:
+      - $REPORT_PATTERN
+    expire_in: 1 week
+    when: always
+  dependencies:  # Here is not a hard dependency relationship, could be skipped when only python files changed. so we do not use "needs" here.
+    - clang_tidy_check
+
+code_quality_check:
+  extends:
+    - .sonar_scan_template
+    - .rules:patterns:static-code-analysis-preview
+  allow_failure: true  # it's using exit code to indicate the code analysis result,
+                       # we don't want to block ci when critical issues founded
+  script:
+    - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits --src-branch ${CI_COMMIT_REF_NAME} | tr '\n' ',')
+    # test if this branch have merge request, if not, exit 0
+    - test -n "$CI_MERGE_REQUEST_IID" || exit 0
+    - test -n "$CI_MERGE_REQUEST_COMMITS" || exit 0
+    - sonar-scanner
+      -Dsonar.analysis.mode=preview
+      -Dsonar.branch.name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
+      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
+      -Dsonar.exclusions=$EXCLUSIONS
+      -Dsonar.gitlab.ci_merge_request_iid=$CI_MERGE_REQUEST_IID
+      -Dsonar.gitlab.commit_sha=$CI_MERGE_REQUEST_COMMITS
+      -Dsonar.gitlab.merge_request_discussion=true
+      -Dsonar.gitlab.ref_name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
+      -Dsonar.host.url=$SONAR_HOST_URL
+      -Dsonar.login=$SONAR_LOGIN
+
+code_quality_report:
+  extends:
+    - .sonar_scan_template
+    - .rules:protected
+  allow_failure: true  # it's using exit code to indicate the code analysis result,
+                       # we don't want to block ci when critical issues founded
+  script:
+    - sonar-scanner
+      -Dsonar.branch.name=$CI_COMMIT_REF_NAME
+      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
+      -Dsonar.exclusions=$EXCLUSIONS
+      -Dsonar.gitlab.commit_sha=$PIPELINE_COMMIT_SHA
+      -Dsonar.gitlab.ref_name=$CI_COMMIT_REF_NAME
+      -Dsonar.host.url=$SONAR_HOST_URL
+      -Dsonar.login=$SONAR_LOGIN
--- a/.gitlab/merge_request_templates/Minimal_Template.md
+++ b/.gitlab/merge_request_templates/Minimal_Template.md
@@ -13,17 +13,3 @@
 <!-- Either state release notes or write "No release notes" -->

 <!-- ## Breaking change notes --><!-- Optional -->
-
-<!-- ## Dynamic Pipeline Configuration
-```yaml
-Test Case Filters:
-    # Only run tests that match the given substring expression (modified files/components will be ignored):
-    # Please use a list of strings. 
-    # This will run the test cases filtered like `pytest -k "(<list_item_1>) or (<list_item_2>) or ...`
-    # The fast pipeline will fail at the final stage.
-    # For example:
-      - test_sdm and not sdmmc
-      - test_hello_world
-    # This example will include all tests containing 'test_hello_world' in the name,
-    # and include all tests containing 'test_sdm' but not 'sdmmc' in the name.
-``` --><!-- Optional -->
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -53,7 +53,7 @@ repos:
              .*_pb2.py
          )$
  - repo: https://github.com/codespell-project/codespell
-    rev: v2.3.0
+    rev: v2.2.6
    hooks:
      - id: codespell
  - repo: local
@@ -224,11 +224,6 @@ repos:
      name: shellcheck dash (export.sh)
      args: ['--shell', 'dash', '-x']
      files: 'export.sh'
-  - repo: https://github.com/espressif/esp-pwsh-check
-    rev: v1.0.1
-    hooks:
-    - id: check-powershell-scripts
-      stages: [manual]
  - repo: https://github.com/espressif/esp-idf-sbom.git
    rev: v0.13.0
    hooks:
@@ -241,6 +236,6 @@ repos:
        name: Lint rST files in docs folder using Sphinx Lint
        files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$
  - repo: https://github.com/espressif/esp-idf-kconfig.git
-    rev: v2.3.0
+    rev: v2.1.0
    hooks:
      - id: check-kconfig-files
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -16,11 +16,7 @@ endif()
 if(NOT BOOTLOADER_BUILD)

    if(CONFIG_COMPILER_OPTIMIZATION_SIZE)
-        if(CMAKE_C_COMPILER_ID MATCHES "Clang")
-            list(APPEND compile_options "-Oz")
-        else()
-            list(APPEND compile_options "-Os")
-        endif()
+        list(APPEND compile_options "-Os")
        if(CMAKE_C_COMPILER_ID MATCHES "GNU")
            list(APPEND compile_options "-freorder-blocks")
        endif()
@@ -38,11 +34,7 @@ if(NOT BOOTLOADER_BUILD)
 else()  # BOOTLOADER_BUILD

    if(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE)
-        if(CMAKE_C_COMPILER_ID MATCHES "Clang")
-            list(APPEND compile_options "-Oz")
-        else()
-            list(APPEND compile_options "-Os")
-        endif()
+        list(APPEND compile_options "-Os")
        if(CMAKE_C_COMPILER_ID MATCHES "GNU")
            list(APPEND compile_options "-freorder-blocks")
        endif()
@@ -104,7 +96,7 @@ if(CMAKE_C_COMPILER_ID MATCHES "Clang")
    list(APPEND compile_options "-Wno-pointer-bool-conversion")
    # mbedTLS md5.c triggers this warning in md5_test_buf (false positive)
    list(APPEND compile_options "-Wno-string-concatenation")
-    # multiple cases of implicit conversions between unrelated enum types
+    # multiple cases of implict convertions between unrelated enum types
    list(APPEND compile_options "-Wno-enum-conversion")
    # When IRAM_ATTR is specified both in function declaration and definition,
    # it produces different section names, since section names include __COUNTER__.
@@ -144,10 +136,6 @@ if(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE)
    list(APPEND compile_definitions "-DNDEBUG")
 endif()

-if(CONFIG_COMPILER_NO_MERGE_CONSTANTS)
-    list(APPEND compile_options "-fno-merge-constants")
-endif()
-
 if(CONFIG_COMPILER_STACK_CHECK_MODE_NORM)
    list(APPEND compile_options "-fstack-protector")
 elseif(CONFIG_COMPILER_STACK_CHECK_MODE_STRONG)
@@ -160,8 +148,46 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
    list(APPEND compile_options "-fdump-rtl-expand")
 endif()

-__generate_prefix_map(prefix_map_compile_options)
-list(APPEND compile_options ${prefix_map_compile_options})
+if(NOT ${CMAKE_C_COMPILER_VERSION} VERSION_LESS 8.0.0)
+    if(CONFIG_COMPILER_HIDE_PATHS_MACROS)
+        list(APPEND compile_options "-fmacro-prefix-map=${CMAKE_SOURCE_DIR}=.")
+        list(APPEND compile_options "-fmacro-prefix-map=${IDF_PATH}=/IDF")
+    endif()
+
+    if(CONFIG_APP_REPRODUCIBLE_BUILD)
+        idf_build_set_property(DEBUG_PREFIX_MAP_GDBINIT "${BUILD_DIR}/prefix_map_gdbinit")
+
+        list(APPEND compile_options "-fdebug-prefix-map=${IDF_PATH}=/IDF")
+        list(APPEND compile_options "-fdebug-prefix-map=${PROJECT_DIR}=/IDF_PROJECT")
+        list(APPEND compile_options "-fdebug-prefix-map=${BUILD_DIR}=/IDF_BUILD")
+
+        # component dirs
+        idf_build_get_property(python PYTHON)
+        idf_build_get_property(idf_path IDF_PATH)
+        idf_build_get_property(component_dirs BUILD_COMPONENT_DIRS)
+
+        execute_process(
+            COMMAND ${python}
+                "${idf_path}/tools/generate_debug_prefix_map.py"
+                "${BUILD_DIR}"
+                "${component_dirs}"
+            OUTPUT_VARIABLE result
+            RESULT_VARIABLE ret
+        )
+        if(NOT ret EQUAL 0)
+            message(FATAL_ERROR "This is a bug. Please report to https://github.com/espressif/esp-idf/issues")
+        endif()
+
+        spaces2list(result)
+        list(LENGTH component_dirs length)
+        math(EXPR max_index "${length} - 1")
+        foreach(index RANGE ${max_index})
+            list(GET component_dirs ${index} folder)
+            list(GET result ${index} after)
+            list(APPEND compile_options "-fdebug-prefix-map=${folder}=${after}")
+        endforeach()
+    endif()
+endif()

 if(CONFIG_COMPILER_DISABLE_GCC12_WARNINGS)
    list(APPEND compile_options "-Wno-address"
@@ -175,22 +201,10 @@ if(CONFIG_COMPILER_DISABLE_GCC13_WARNINGS)
                                    "-Wno-dangling-reference")
 endif()

-if(CONFIG_COMPILER_DISABLE_GCC14_WARNINGS)
-    list(APPEND compile_options "-Wno-calloc-transposed-args")
-endif()
-
-if(CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS)
-    if(NOT CMAKE_C_COMPILER_ID MATCHES "Clang")
-        idf_build_replace_option_from_property(COMPILE_OPTIONS "-Werror" "-Werror=all")
-    endif()
-endif()
-
 # GCC-specific options
 if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    list(APPEND compile_options "-fstrict-volatile-bitfields")
-    if(CONFIG_COMPILER_STATIC_ANALYZER)
-        list(APPEND compile_options "-fanalyzer")
-    endif()
+    list(APPEND compile_options "-fstrict-volatile-bitfields"
+                                )
 endif()

 if(CONFIG_ESP_SYSTEM_USE_EH_FRAME)
@@ -201,35 +215,8 @@ endif()
 list(APPEND link_options "-fno-lto")

 if(CONFIG_IDF_TARGET_LINUX AND CMAKE_HOST_SYSTEM_NAME STREQUAL "Darwin")
-    # Not all versions of the MacOS linker support the -warn_commons flag.
-    # ld version 1053.12 (and above) have been tested to support it.
-    # Hence, we extract the version string from the linker output
-    # before including the flag.
-
-    # Get the ld version, capturing both stdout and stderr
-    execute_process(
-        COMMAND ${CMAKE_LINKER} -v
-        OUTPUT_VARIABLE LD_VERSION_OUTPUT
-        ERROR_VARIABLE LD_VERSION_ERROR
-        OUTPUT_STRIP_TRAILING_WHITESPACE
-        ERROR_STRIP_TRAILING_WHITESPACE
-    )
-
-    # Combine stdout and stderr
-    set(LD_VERSION_OUTPUT "${LD_VERSION_OUTPUT}\n${LD_VERSION_ERROR}")
-
-    # Extract the version string
-    string(REGEX MATCH "PROJECT:(ld|dyld)-([0-9]+)\\.([0-9]+)" LD_VERSION_MATCH "${LD_VERSION_OUTPUT}")
-    set(LD_VERSION_MAJOR_MINOR "${CMAKE_MATCH_2}.${CMAKE_MATCH_3}")
-
-    message(STATUS "Linker Version: ${LD_VERSION_MAJOR_MINOR}")
-
-    # Compare the version with 1053.12
-    if(LD_VERSION_MAJOR_MINOR VERSION_GREATER_EQUAL "1053.12")
-        list(APPEND link_options "-Wl,-warn_commons")
-    endif()
-
    list(APPEND link_options "-Wl,-dead_strip")
+    list(APPEND link_options "-Wl,-warn_commons")
 else()
    list(APPEND link_options "-Wl,--gc-sections")
    list(APPEND link_options "-Wl,--warn-common")
@@ -251,9 +238,7 @@ if(CMAKE_C_COMPILER_ID MATCHES "GNU")
 endif()

 if(CMAKE_C_COMPILER_ID MATCHES "Clang")
-    list(APPEND compile_options "-fno-use-cxa-atexit")  # TODO IDF-10934
-else()
-    list(APPEND cxx_compile_options "-fuse-cxa-atexit")
+    list(APPEND compile_options "-fno-use-cxa-atexit")
 endif()

 if(COMPILER_RT_LIB_NAME)
--- a/COMPATIBILITY.md
+++ b/COMPATIBILITY.md
@@ -84,18 +84,17 @@ Supported since ESP-IDF v4.4.

 ### ESP32-C2 & ESP8684

-#### v1.0, v1.1
+#### v1.0

 Supported since ESP-IDF v5.0.

+#### v1.1
+
+To be added.
+
 #### v1.2

-| Release branch         | Recommended | Required |
-|------------------------|-------------|----------|
-| release/v5.0           | v5.0.7+     | v5.0     |
-| release/v5.1           | v5.1.4+     | v5.1     |
-| release/v5.2           | v5.2.2+     | v5.2     |
-| release/v5.3 and above | v5.3+       | v5.3     |
+To be added.

 ### ESP32-C6

--- a/COMPATIBILITY_CN.md
+++ b/COMPATIBILITY_CN.md
@@ -84,18 +84,17 @@

 ### ESP32-C2 & ESP8684

-#### v1.0, v1.1
+#### v1.0

 从 ESP-IDF v5.0 开始支持。

+#### v1.1
+
+待更新。
+
 #### v1.2

-| 发布分支                | 推荐版本      | 需求版本  |
-|------------------------|-------------|----------|
-| release/v5.0           | v5.0.7+     | v5.0     |
-| release/v5.1           | v5.1.4+     | v5.1     |
-| release/v5.2           | v5.2.2+     | v5.1     |
-| release/v5.3 及以上     | v5.3+       | v5.3     |
+待更新。

 ### ESP32-C6

--- a/95
+++ b/95
@@ -48,10 +48,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
        bool
        default "y" if IDF_TOOLCHAIN="clang"

-    config IDF_TOOLCHAIN_GCC
-        bool
-        default "y" if IDF_TOOLCHAIN="gcc"
-
    config IDF_TARGET_ARCH_RISCV
        bool
        default "n"
@@ -119,6 +115,28 @@ mainmenu "Espressif IoT Development Framework Configuration"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV

+    # TODO: IDF-9197
+    choice IDF_TARGET_ESP32C5_VERSION
+        prompt "ESP32-C5 version"
+        depends on IDF_TARGET_ESP32C5
+        default IDF_TARGET_ESP32C5_MP_VERSION
+        help
+            ESP32-C5 will support two versions for a period.
+            This option is for internal use only.
+            Select the one that matches your chip model.
+
+        config IDF_TARGET_ESP32C5_BETA3_VERSION
+            bool
+            prompt "ESP32-C5 beta3"
+            select ESPTOOLPY_NO_STUB
+
+        config IDF_TARGET_ESP32C5_MP_VERSION
+            bool
+            prompt "ESP32-C5 MP"
+            select ESPTOOLPY_NO_STUB
+            select IDF_ENV_FPGA
+    endchoice
+
    config IDF_TARGET_ESP32P4
        bool
        default "y" if IDF_TARGET="esp32p4"
@@ -135,6 +153,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default "y" if IDF_TARGET="esp32c61"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV
+        select IDF_ENV_FPGA

    config IDF_TARGET_LINUX
        bool
@@ -150,7 +169,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default 0x000D if IDF_TARGET_ESP32C6
        default 0x0010 if IDF_TARGET_ESP32H2
        default 0x0012 if IDF_TARGET_ESP32P4
-        default 0x0017 if IDF_TARGET_ESP32C5
+        default 0x0011 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_BETA3_VERSION  # TODO: IDF-9197
+        default 0x0017 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_MP_VERSION     # TODO: IDF-9197
        default 0x0014 if IDF_TARGET_ESP32C61
        default 0xFFFF

@@ -323,8 +343,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
            help
                This option sets compiler optimization level (gcc -O argument) for the app.

-                - The "Debug" setting will add the -Og flag to CFLAGS.
-                - The "Size" setting will add the -Os flag to CFLAGS (-Oz with Clang).
+                - The "Debug" setting will add the -0g flag to CFLAGS.
+                - The "Size" setting will add the -0s flag to CFLAGS.
                - The "Performance" setting will add the -O2 flag to CFLAGS.
                - The "None" setting will add the -O0 flag to CFLAGS.

@@ -345,7 +365,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
            config COMPILER_OPTIMIZATION_DEBUG
                bool "Debug (-Og)"
            config COMPILER_OPTIMIZATION_SIZE
-                bool "Optimize for size (-Os with GCC, -Oz with Clang)"
+                bool "Optimize for size (-Os)"
            config COMPILER_OPTIMIZATION_PERF
                bool "Optimize for performance (-O2)"
            config COMPILER_OPTIMIZATION_NONE
@@ -388,21 +408,6 @@ mainmenu "Espressif IoT Development Framework Configuration"

        endchoice # assertions

-        config COMPILER_ASSERT_NDEBUG_EVALUATE
-            bool "Enable the evaluation of the expression inside assert(X) when NDEBUG is set"
-            default y
-            help
-                When NDEBUG is set, assert(X) will not cause code to trigger an assertion.
-                With this option set, assert(X) will still evaluate the expression X, though
-                the result will never cause an assertion. This means that if X is a function
-                then the function will be called.
-
-                This is not according to the standard, which states that the assert(X) should
-                be replaced with ((void)0) if NDEBUG is defined.
-
-                In ESP-IDF v6.0 the default behavior will change to "no" to be in line with the
-                standard.
-
        choice COMPILER_FLOAT_LIB_FROM
            prompt "Compiler float lib source"
            default COMPILER_FLOAT_LIB_FROM_RVFPLIB if ESP_ROM_HAS_RVFPLIB
@@ -524,15 +529,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
            help
                Stack smashing protection.

-        config COMPILER_NO_MERGE_CONSTANTS
-            bool "Disable merging const sections"
-            depends on IDF_TOOLCHAIN_GCC
-            help
-                Disable merging identical constants (string/floating-point) across compilation units.
-                This helps in better size analysis of the application binary as the rodata section
-                distribution is more uniform across libraries. On downside, it may increase
-                the binary size and hence should be used during development phase only.
-
        config COMPILER_WARN_WRITE_STRINGS
            bool "Enable -Wwrite-strings warning flag"
            default "n"
@@ -559,20 +555,6 @@ mainmenu "Espressif IoT Development Framework Configuration"

                This option can be enabled for RISC-V targets only.

-        config COMPILER_DISABLE_DEFAULT_ERRORS
-            bool "Disable errors for default warnings"
-            default "y"
-            help
-                Enable this option if you do not want default warnings to be considered as errors,
-                especially when updating IDF.
-
-                This is a temporary flag that could help to allow upgrade while having
-                some time to address the warnings raised by those default warnings.
-                Alternatives are:
-                1) fix code (preferred),
-                2) remove specific warnings,
-                3) do not consider specific warnings as error.
-
        config COMPILER_DISABLE_GCC12_WARNINGS
            bool "Disable new warnings introduced in GCC 12"
            default "n"
@@ -587,13 +569,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
                Enable this option if use GCC 13 or newer, and want to disable warnings which don't appear with
                GCC 12.

-        config COMPILER_DISABLE_GCC14_WARNINGS
-            bool "Disable new warnings introduced in GCC 14"
-            default "n"
-            help
-                Enable this option if use GCC 14 or newer, and want to disable warnings which don't appear with
-                GCC 13.
-
        config COMPILER_DUMP_RTL_FILES
            bool "Dump RTL files during compilation"
            help
@@ -630,7 +605,7 @@ mainmenu "Espressif IoT Development Framework Configuration"

        choice COMPILER_ORPHAN_SECTIONS
            prompt "Orphan sections handling"
-            default COMPILER_ORPHAN_SECTIONS_WARNING
+            default COMPILER_ORPHAN_SECTIONS_PLACE
            depends on !IDF_TARGET_LINUX
            help
                If the linker finds orphan sections, it attempts to place orphan sections after sections of the same
@@ -641,7 +616,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
            config COMPILER_ORPHAN_SECTIONS_WARNING
                bool "Place with warning"
                help
-                    Places orphan sections with a warning message.
+                    Places orphan sections without a warning message.

            config COMPILER_ORPHAN_SECTIONS_PLACE
                bool "Place silently"
@@ -649,13 +624,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
                    Places orphan sections without a warning/error message.
        endchoice

-        config COMPILER_STATIC_ANALYZER
-            bool "Enable compiler static analyzer"
-            default "n"
-            depends on IDF_TOOLCHAIN_GCC
-            help
-                Enable compiler static analyzer. This may produce false-positive results and increases compile time.
-
    endmenu # Compiler Options

    menu "Component config"
@@ -676,7 +644,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
            - CONFIG_ESPTOOLPY_FLASHFREQ_120M && CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
            - CONFIG_SPIRAM_SPEED_120M && CONFIG_SPIRAM_MODE_OCT
            - CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
+            - CONFIG_MBEDTLS_USE_CRYPTO_ROM_IMPL
            - CONFIG_ESP_WIFI_EAP_TLS1_3
            - CONFIG_ESP_WIFI_ENABLE_ROAMING_APP
-            - CONFIG_USB_HOST_EXT_PORT_SUPPORT_LS
-            - CONFIG_USB_HOST_EXT_PORT_RESET_ATTEMPTS
--- a/README.md
+++ b/README.md
@@ -15,18 +15,17 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li

 The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.

-|Chip         |          v5.0          |         v5.1           |         v5.2           |         v5.3           |          v5.4           |                                                                     |
-|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: |  :--------------------: |:------------------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |                                                                     |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |                                                                     |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |                                                                     |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_S3)           |
-|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-C2)           |
-|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_C6)           |
-|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_H2)           |
-|ESP32-P4     |                        |                        |                        | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-P4)           |
-|ESP32-C5     |                        |                        |                        |                        |  ![alt text][preview]   |[Announcement](https://www.espressif.com/en/news/ESP32-C5)           |
-|ESP32-C61    |                        |                        |                        |                        |  ![alt text][preview]   |[Announcement](https://www.espressif.com/en/products/socs/esp32-c61) |
+|Chip         |          v4.4          |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
+|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
+|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
+|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
+|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
+|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |

 [supported]: https://img.shields.io/badge/-supported-green "supported"
 [preview]: https://img.shields.io/badge/-preview-orange "preview"
--- a/README_CN.md
+++ b/README_CN.md
@@ -15,18 +15,17 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux

 下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。

-|芯片         |          v5.0          |          v5.1          |          v5.2          |          v5.3          |          v5.4          |                                                                           |
-|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------: | :------------------------------------------------------------------------ |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                           |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                           |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                           |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3)           |
-|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2)           |
-|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6)           |
-|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2)           |
-|ESP32-P4     |                        |                        |                        | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4)           |
-|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5)           |
-|ESP32-C61    |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) |
+|芯片         |          v4.4          |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
+|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
+|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
+|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
+|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/en/news/ESP32-P4)      |
+|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |

 [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
 [preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
@@ -123,7 +122,7 @@ ESP-IDF 中的子模块采用相对路径（[详见 .gitmodules 文件](.gitmodu

 * 最新版的文档：https://docs.espressif.com/projects/esp-idf/ ，该文档是由本仓库 [docs 目录](docs) 构建得到。

-* [初学者指南：主要概念和资源](https://www.bilibili.com/video/BV1114y1r7du/)
+* [初学者指南：主要概念和资源](https://www.bilibili.com/video/BV1114y1r7du/) 

 * 可以前往 [esp32.com 论坛](https://esp32.com/) 提问，挖掘社区资源。

--- a/ROADMAP.md
+++ b/ROADMAP.md
@@ -1,123 +0,0 @@
-# ESP-IDF Project Roadmap 2024
-
-This document outlines the goals of ESP-IDF project and is shared for the convenience of our customers. It is important to clarify that this document is not a binding commitment to our customers. Instead, its primary purpose is to offer a clear roadmap and direction for the project's development. By openly sharing this information, we aim to enhance our customers' understanding, promote transparency and ensure alignment with the overarching objectives of the ESP-IDF project.
-
-## Project Overview
-
-### Project Goals
-
-In both minor and major releases, we integrate new chip support to enhance our product range. By expanding the chip matrix, we broaden the scope of our offerings, catering to a wider audience with diverse needs. This proactive approach ensures that our products remain at the forefront of technological advancements, consistently meeting and exceeding customer expectations.
-
-Furthermore, we prioritize bugfix releases for active branches, focusing on improving the stability and performance of products already in production. By addressing bugs promptly, we aim to enhance the overall user experience and provide tangible benefits to customers relying on our solutions. This proactive maintenance strategy reflects our commitment to delivering reliable, high-quality products to our valued customer base.
-
-Below are the main objectives that ESP-IDF project/teams would like to implement in 2024.
-
-   New Chip Support
-
-    -   Add support for ESP32-P4
-    -   Add support for ESP32-C5
-    -   Add support for ESP32-C61
-
-   More Minor Releases
-
-    -   Release IDF v5.3 in 2024
-    -   Release IDF v5.4 at the start of 2025
-
-   More Bugfix Releases
-
-    -   Release v4.4.8 for IDF v4.4 before ESP-IDF v4.4 goes End of Life in July 2024
-    -   Do more bugfix releases for IDF v5.1 before release/5.1 enters maintenance period in June 2024
-    -   Do more bug fixes releases for release/5.2 and release/5.3, and push the two releases to be more stable and production-ready
-
-   Updates of Libraries
-
-    -   Update GDB to 14.2
-    -   Update LLVM to 18.1.2
-    -   Update MbedTLS to 3.6 (LTS)
-    -   Update LWIP to 2.2.0
-    -   Change minimal Python requirement to 3.9
-
-Please note that support status of previous silicones could be found on [ESP-IDF Release and SoC Compatibility](https://github.com/espressif/esp-idf#esp-idf-release-and-soc-compatibility).
-
-### Roadmap Details
-
-The ESP-IDF project prioritizes consistent maintenance and updates to ensure our customers remain at the forefront of technological advancements. Our commitment to ongoing development ensures that customers continuously benefit from the latest innovations in the field.
-
-Moreover, we are dedicated to empowering our customers to leverage newly implemented features and enhanced functionalities through iterative improvements. Our steadfast commitment to pushing boundaries ensures that clients not only keep pace with evolving technology but also extract optimal value from the cutting-edge capabilities of our products.
-
-Below are the main roadmap details for functional areas inside ESP-IDF.
-
-   New Chip Support
-
-    -   Add full support for ESP32-P4 in ESP-IDF v5.3, refer to [ESP32-P4 Support Status](https://github.com/espressif/esp-idf/issues/12996)
-    -   Add preview support for ESP32-C5 in ESP-IDF v5.3 and full support for ESP32-C5 in ESP-IDF v5.4, refer to [ESP32-C5 Support Status](https://github.com/espressif/esp-idf/issues/14021)
-    -   Add preview support for the early samples of ESP32-C61 in ESP-IDF v5.4 and full support for mass production version in ESP-IDF v5.4.x. Refer to [ESP32-C61 Support Status](https://developer.espressif.com/pages/chip-support-status/esp32c61/#esp-idf)
-
-   Bugfix releases
-
-    -   Do bugfix release IDF v4.4.8 and stop maintaining ESP-IDF v4.4 in July 2024
-    -   Release bugfix IDF v5.0.6 and IDF v5.0.7 in 2024 (maintenance period)
-    -   Release bugfix IDF v5.1.3 and IDF v5.1.4 in H1 of 2024, and release IDF v5.1.5 in H2 of 2024
-    -   Push release/5.1 to maintenance period from June 2024
-    -   Do more bug fixes releases for release/5.2 (IDF v5.2.1, IDF v5.2.2, IDF v5.2.3) and release/5.3 (IDF v5.3.1, IDF v5.3.2), and push releases to be more stable and more production-ready
-
-## ESP-IDF Planning information
-
-For the full list of ESP-IDF releases, please visit https://github.com/espressif/esp-idf/releases
-
-### ESP-IDF Major Releases
-
-No Major Releases planned
-
-### ESP-IDF Minor Releases
-
-#### Quarter One
-
-   v5.2-RC1, estimate release date: 2024/02/02
-   v5.2 final release, estimate release date: 2024/02/08
-
-#### Quarter Two
-
-   v5.3-beta1, estimate release date:: 2024/05/13
-   v5.3-beta2, estimate release date:: 2024/05/31
-   v5.3-RC1, estimate release date:: 2024/07/08
-
-#### Quarter Three
-
-   v5.3-RC2, estimate release date:: 2024/07/26
-   v5.3 final release, estimate release date:: 2024/08/02
-
-#### Quarter Four
-
-   v5.4-beta1, estimate release date:: 2024/11/08
-   v5.4-beta2, estimate release date:: 2024/11/29
-   v5.4-RC1, estimate release date:: 2025/01/09
-   v5.4-RC2, estimate release date:: 2025/01/29
-   v5.4 final release, estimate release date: 2025/02/05
-
-### ESP-IDF Bugfix Releases
-
-#### Quarter One
-
-   v5.1.3, estimate release date: 2024/02/08
-   v5.0.6, estimate release date: 2024/02/18
-   v4.4.7, estimate release date:: 2024/03/19
-   v5.2.1, estimate release date:: 2024/03/31
-
-#### Quarter Two
-
-   v5.1.4, estimate release date:: 2024/05/06
-   v5.2.2, estimate release date:: 2024/06/17
-   v4.4.8, estimate release date:: 2024/07/19
-
-#### Quarter Three
-
-   v5.0.7, estimate release date: 2024/08/22
-   v5.3.1, estimate release date: 2024/09/16
-   v5.2.3, estimate release date: 2024/10/10
-
-#### Quarter Four
-
-   v5.1.5, estimate release date: 2024/11/04  (Maintenance period since June 2024)
-   v5.3.2, estimate release date: 2024/12/31
-   v5.2.4, estimate release date: 2025/02/20 (Service period ends Feb. 2025)
--- a/ROADMAP_CN.md
+++ b/ROADMAP_CN.md
@@ -1,123 +0,0 @@
-# ESP-IDF 项目路线图 2024 (v1.0)
-
-本文档概述了 ESP-IDF 项目的年度计划，方便客户据此规划自己的项目周期。需要说明的是该文档并不是我们对客户的约束性承诺。相反，其主要目的是为客户提供 ESP-IDF 项目开发的路线图和方向。通过公开这些信息，我们希望增进客户对 ESP-IDF 项目的理解，提高透明度，并确保与 ESP-IDF 项目的总体目标保持一致。
-
-## 项目总览
-
-### 项目目标
-
-在 ESP-IDF 的主要版本和次要版本中，我们一般会增加对新芯片的支持，以扩展我们的产品线。通过扩展芯片矩阵，拓宽我们的产品范围，并满足广泛受众的各种需求。这样便能保证我们的产品始终处于技术进步的前沿，不断满足客户的需求并超越客户的期望。
-
-此外，ESP-IDF 各活跃分支的 Bugfix 版本发布也是我们项目的重中之重，着力提升已量产产品的稳定性和性能。通过及时解决问题，我们期待提升用户的整体体验，切实惠及使用乐鑫解决方案的客户。通过积极维护 ESP-IDF 的各活跃分支，我们践行了对宝贵的客户群提供可靠、高质量产品的承诺。
-
-以下是 ESP-IDF 项目在 2024 年计划实现的主要目标。
-
-* 新芯片支持
-
-	* 增加对 ESP32-P4 芯片的支持
-	* 增加对 ESP32-C5 芯片的支持
-	* 增加对 ESP32-C61 芯片的支持
-
-* 发布更多的次要版本
-
-	* 在 2024 年发布 IDF v5.3 
-	* 在 2025 年初发布 IDF v5.4
-
-* 发布更多 Bugfix 版本
-
-	* 在 2024 年 7 月底 IDF v4.4 停止维护之前，发布 IDF v4.4.8
-	* 在 2024 年 6 月底，release/5.1 分支进入维护周期之前，发布更多 Bugfix 版本
-	* release/5.2 分支和 release/5.3 分支发布更多 Bugfix 版本，使这两个分支更加稳定和产品化
-
-* 上游库与工具链的更新
-
-	* 将 GDB 升级至 14.2
-	* 将 LLVM 升级至 18.1.2
-	* 更新 MbedTLS 至 3.6（LTS）
-	* 更新 LWIP 至 2.2.0
-	* 将最低 Python 要求更改为 3.9
-
-请注意，获取之前芯片的支持状态，请参阅 [ESP-IDF 发布和 SoC 兼容性](https://github.com/espressif/esp-idf/blob/master/README_CN.md#esp-idf-与乐鑫芯片)。
-
-### 路线图细节
-
-ESP-IDF 项目重视持续维护和更新，确保我们的客户始终处于技术进步的前沿。我们承诺持续进行开发，并将该领域的最新创新成果呈现给客户。
-
-此外，我们也在给客户赋能，客户通过迭代改进便能接触到新开发的功能和更高的性能。我们在突破技术界限方面的坚定承诺，使客户不仅能接触到最新的技术，还能从我们产品的尖端功能中获取最大价值。
-
-以下是 ESP-IDF 路线图的主要信息。
-
-* 新芯片支持
-
-	* 在 ESP-IDF v5.3 中为 ESP32-P4 提供完整支持，参考 [ESP32-P4 支持状态](https://github.com/espressif/esp-idf/issues/12996)
-	* 在 ESP-IDF v5.3 中为 ESP32-C5 提供预览支持，并在 ESP-IDF v5.4 中为 ESP32-C5 提供完整支持，参考 [ESP32-C5 支持状态](https://github.com/espressif/esp-idf/issues/14021)
-	* 在 ESP-IDF v5.4 中增加对 ESP32-C61 早期样品的预览支持，并在 IDF v5.4.x 中增加对 ESP32-C61 量产版本的完整支持，参考 [ESP32-C61 支持状态](https://developer.espressif.com/pages/chip-support-status/esp32c61/#esp-idf)
-
-* Bugfix 版本发布
-
-	* 发布 Bugfix 版本 IDF v4.4.8，并在 2024 年 7 月底停止维护 ESP-IDF v4.4
-	* 2024 年，release/5.0 分支已处于维护周期，发布 IDF v5.0.6 和 IDF v5.0.7
-	* 2024 年上半年发布 Bugfix 版本 IDF v5.1.3 和 IDF v5.1.4，并在 2024 年下半年发布 IDF v5.1.5
-	* 自 2024 年 6 月起，release/5.1 分支进入到维护周期
-	* release/5.2 分支发布更多 Bugfix 版本，包括 IDF v5.2.1、IDF v5.2.2、IDF v5.2.3；release/5.3 分支发布更多 Bugfix 版本，包括 IDF v5.3.1、IDF v5.3.2。通过发布这些 Bugfix 版本，使 release/5.2 分支和 release/5.3 分支更加稳定和产品化。
-
-## ESP-IDF 发布计划
-
-获取 ESP-IDF 的完整发布列表，请访问 https://github.com/espressif/esp-idf/releases
-
-### ESP-IDF 主要版本发布
-
-2024 年，无主要版本发布计划
-
-### ESP-IDF 次要版本发布
-
-#### 第一季度
-
-* v5.2-RC1，预计发布日期：2024/02/02
-* v5.2 正式发布，预计发布日期：2024/02/08
-
-#### 第二季度
-
-* v5.3-beta1，预计发布日期：2024/05/13
-* v5.3-beta2，预计发布日期：2024/05/31
-* v5.3-RC1，预计发布日期：2024/07/08
-
-#### 第三季度
-
-* v5.3-RC2，预计发布日期：2024/07/26
-* v5.3 正式发布，预计发布日期：2024/08/02
-
-#### 第四季度
-
-* v5.4-beta1，预计发布日期：2024/11/08
-* v5.4-beta2，预计发布日期：2024/11/29
-* v5.4-RC1，预计发布日期：2025/01/09
-* v5.4-RC2，预计发布日期：2025/01/29
-* v5.4 正式发布，预计发布日期：2025/02/05
-
-### ESP-IDF Bugfix 版本发布
-
-#### 第一季度
-
-* v5.1.3，预计发布日期：2024/02/08
-* v5.0.6，预计发布日期：2024/02/18
-* v4.4.7，预计发布日期：2024/03/19
-* v5.2.1，预计发布日期：2024/03/31
-
-#### 第二季度
-
-* v5.1.4，预计发布日期：2024/05/06
-* v5.2.2，预计发布日期：2024/06/17
-* v4.4.8，预计发布日期：2024/07/19
-
-#### 第三季度
-
-* v5.0.7，预计发布日期：2024/08/22
-* v5.3.1，预计发布日期：2024/09/16
-* v5.2.3，预计发布日期：2024/10/10
-
-#### 第四季度
-
-* v5.1.5，预计发布日期：2024/11/04（自 2024 年 6 月进入维护周期）
-* v5.3.2，预计发布日期：2024/12/31
-* v5.2.4，预计发布日期：2025/02/20（服务周期截止至 2025 年 2 月）
--- a/components/app_trace/Kconfig
+++ b/components/app_trace/Kconfig
@@ -14,7 +14,6 @@ menu "Application Level Tracing"

        config APPTRACE_DEST_NONE
            bool "None"
-
    endchoice

    config APPTRACE_DEST_UART
@@ -61,7 +60,7 @@ menu "Application Level Tracing"
    endchoice

    config APPTRACE_UART_TX_GPIO
-        int "UART TX on GPIO<num>"
+        int "UART TX on GPIO#"
        depends on APPTRACE_DEST_UART_NOUSB
        range 0 46
        default 12 if IDF_TARGET_ESP32
@@ -71,7 +70,7 @@ menu "Application Level Tracing"
            This GPIO is used for UART TX pin.

    config APPTRACE_UART_RX_GPIO
-        int "UART RX on GPIO<num>"
+        int "UART RX on GPIO#"
        depends on APPTRACE_DEST_UART_NOUSB
        range 0 46
        default 13 if IDF_TARGET_ESP32
@@ -214,7 +213,7 @@ menu "Application Level Tracing"
            depends on APPTRACE_SV_ENABLE
            default APPTRACE_SV_DEST_JTAG
            help
-                SystemView will transfer data through the defined interface.
+                SystemView witt transfer data trough defined interface.

            config APPTRACE_SV_DEST_JTAG
                bool "Data destination JTAG"
--- a/components/app_trace/app_trace.c
+++ b/components/app_trace/app_trace.c
@@ -26,6 +26,8 @@
 #define ESP_APPTRACE_MAX_VPRINTF_ARGS 256
 #define ESP_APPTRACE_HOST_BUF_SIZE 256

+#define ESP_APPTRACE_PRINT_LOCK 0
+
 const static char *TAG = "esp_apptrace";

 /** tracing module internal data */
@@ -88,7 +90,7 @@ void esp_apptrace_down_buffer_config(uint8_t *buf, uint32_t size)
        return;
    }
    // currently down buffer is supported for JTAG interface only
-    // TODO: one more argument should be added to this function to specify HW interface: JTAG, UART0 etc
+    // TODO: one more argument should be added to this function to specify HW inteface: JTAG, UART0 etc
    ch = &s_trace_channels[ESP_APPTRACE_DEST_JTAG];
    if (ch->hw != NULL) {
        if (ch->hw->down_buffer_config != NULL) {
--- a/components/app_trace/app_trace_util.c
+++ b/components/app_trace/app_trace_util.c
@@ -9,14 +9,12 @@
 #include "esp_app_trace_util.h"
 #include "sdkconfig.h"

-#define ESP_APPTRACE_PRINT_LOCK 0
-
 ///////////////////////////////////////////////////////////////////////////////
 ///////////////////////////////// Locks /////////////////////////////////////
 ///////////////////////////////////////////////////////////////////////////////

 #if ESP_APPTRACE_PRINT_LOCK
-static esp_apptrace_lock_t s_log_lock = { .mux = portMUX_INITIALIZER_UNLOCKED };
+static esp_apptrace_lock_t s_log_lock = {.irq_stat = 0, .portmux = portMUX_INITIALIZER_UNLOCKED};
 #endif

 int esp_apptrace_log_lock(void)
@@ -33,7 +31,7 @@ int esp_apptrace_log_lock(void)

 void esp_apptrace_log_unlock(void)
 {
-#if ESP_APPTRACE_PRINT_LOCK
+ #if ESP_APPTRACE_PRINT_LOCK
    esp_apptrace_lock_give(&s_log_lock);
 #endif
 }
@@ -89,7 +87,7 @@ esp_err_t esp_apptrace_lock_give(esp_apptrace_lock_t *lock)
 uint8_t *esp_apptrace_rb_produce(esp_apptrace_rb_t *rb, uint32_t size)
 {
    uint8_t *ptr = rb->data + rb->wr;
-    // check for available space
+    // check for avalable space
    if (rb->rd <= rb->wr) {
        // |?R......W??|
        if (rb->wr + size >= rb->size) {
--- a/components/app_trace/port/riscv/port.c
+++ b/components/app_trace/port/riscv/port.c
@@ -57,13 +57,7 @@ static bool esp_apptrace_riscv_host_data_pending(void);

 const static char *TAG = "esp_apptrace";

-#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-#define APPTRACE_DRAM_ATTR TCM_DRAM_ATTR
-#else
-#define APPTRACE_DRAM_ATTR
-#endif
-
-static APPTRACE_DRAM_ATTR esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES];
+static esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES];

 esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data)
 {
@@ -98,7 +92,7 @@ esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data)
 }

 /* Advertises apptrace control block address to host.
-   This function can be overridden with custom implementation,
+   This function can be overriden with custom implementation,
   e.g. OpenOCD flasher stub use own implementation of it. */
 __attribute__((weak)) int esp_apptrace_advertise_ctrl_block(void *ctrl_block_addr)
 {
@@ -109,7 +103,7 @@ __attribute__((weak)) int esp_apptrace_advertise_ctrl_block(void *ctrl_block_add
 }

 /* Returns up buffers config.
-   This function can be overridden with custom implementation,
+   This function can be overriden with custom implementation,
   e.g. OpenOCD flasher stub use own implementation of it. */
 __attribute__((weak)) void esp_apptrace_get_up_buffers(esp_apptrace_mem_block_t mem_blocks_cfg[2])
 {
@@ -171,7 +165,7 @@ static esp_err_t esp_apptrace_riscv_init(esp_apptrace_riscv_data_t *hw_data)
    }
    // notify host about control block address
    int res = esp_apptrace_advertise_ctrl_block(&s_tracing_ctrl[core_id]);
-    assert(res == 0 && "Failed to send config to host!");
+    assert(res == 0 && "Falied to send config to host!");

    return ESP_OK;
 }
--- a/components/app_trace/sys_view/SEGGER/sbom.yml
+++ b/components/app_trace/sys_view/SEGGER/sbom.yml
@@ -1,6 +0,0 @@
-name: 'SystemView'
-version: '3.42'
-cpe: cpe:2.3:a:segger:systemview:{}:*:*:*:*:*:*:*
-supplier: 'Organization: Espressif Systems (Shanghai) CO LTD'
-originator: 'Organization: SEGGER Microcontroller GmbH'
-description: Real-time recording and visualization tool for embedded systems.
--- a/components/app_trace/test_apps/.build-test-rules.yml
+++ b/components/app_trace/test_apps/.build-test-rules.yml
@@ -8,6 +8,6 @@ components/app_trace/test_apps:
    - driver
    - esp_hw_support
  disable:
-    - if: IDF_TARGET in ["esp32c5", "esp32c61"]
+    - if: IDF_TARGET == "esp32c5"
      temporary: true
-      reason: not support yet # TODO: [ESP32C5] IDF-8705, [ESP32C61] IDF-9306
+      reason: not support yet # TODO: [ESP32C5] IDF-8705
--- a/components/app_update/esp_ota_ops.c
+++ b/components/app_update/esp_ota_ops.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -80,7 +80,7 @@ static const esp_partition_t *read_otadata(esp_ota_select_entry_t *two_otadata)
        return NULL;
    } else {
        memcpy(&two_otadata[0], result, sizeof(esp_ota_select_entry_t));
-        memcpy(&two_otadata[1], result + otadata_partition->erase_size, sizeof(esp_ota_select_entry_t));
+        memcpy(&two_otadata[1], result + SPI_FLASH_SEC_SIZE, sizeof(esp_ota_select_entry_t));
        esp_partition_munmap(ota_data_map);
    }
    return otadata_partition;
@@ -149,7 +149,7 @@ esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp
        if ((image_size == 0) || (image_size == OTA_SIZE_UNKNOWN)) {
            ret = esp_partition_erase_range(partition, 0, partition->size);
        } else {
-            const int aligned_erase_size = (image_size + partition->erase_size - 1) & ~(partition->erase_size - 1);
+            const int aligned_erase_size = (image_size + SPI_FLASH_SEC_SIZE - 1) & ~(SPI_FLASH_SEC_SIZE - 1);
            ret = esp_partition_erase_range(partition, 0, aligned_erase_size);
        }
        if (ret != ESP_OK) {
@@ -157,7 +157,7 @@ esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp
        }
    }

-    new_entry = (ota_ops_entry_t *) calloc(1, sizeof(ota_ops_entry_t));
+    new_entry = (ota_ops_entry_t *) calloc(sizeof(ota_ops_entry_t), 1);
    if (new_entry == NULL) {
        return ESP_ERR_NO_MEM;
    }
@@ -192,14 +192,14 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
        if (it->handle == handle) {
            if (it->need_erase) {
                // must erase the partition before writing to it
-                uint32_t first_sector = it->wrote_size / it->part->erase_size; // first affected sector
-                uint32_t last_sector = (it->wrote_size + size - 1) / it->part->erase_size; // last affected sector
+                uint32_t first_sector = it->wrote_size / SPI_FLASH_SEC_SIZE; // first affected sector
+                uint32_t last_sector = (it->wrote_size + size - 1) / SPI_FLASH_SEC_SIZE; // last affected sector

                ret = ESP_OK;
-                if ((it->wrote_size % it->part->erase_size) == 0) {
-                    ret = esp_partition_erase_range(it->part, it->wrote_size, ((last_sector - first_sector) + 1) * it->part->erase_size);
+                if ((it->wrote_size % SPI_FLASH_SEC_SIZE) == 0) {
+                    ret = esp_partition_erase_range(it->part, it->wrote_size, ((last_sector - first_sector) + 1) * SPI_FLASH_SEC_SIZE);
                } else if (first_sector != last_sector) {
-                    ret = esp_partition_erase_range(it->part, (first_sector + 1) * it->part->erase_size, (last_sector - first_sector) * it->part->erase_size);
+                    ret = esp_partition_erase_range(it->part, (first_sector + 1) * SPI_FLASH_SEC_SIZE, (last_sector - first_sector) * SPI_FLASH_SEC_SIZE);
                }
                if (ret != ESP_OK) {
                    return ret;
@@ -369,11 +369,11 @@ static esp_err_t rewrite_ota_seq(esp_ota_select_entry_t *two_otadata, uint32_t s

    two_otadata[sec_id].ota_seq = seq;
    two_otadata[sec_id].crc = bootloader_common_ota_select_crc(&two_otadata[sec_id]);
-    esp_err_t ret = esp_partition_erase_range(ota_data_partition, sec_id * ota_data_partition->erase_size, ota_data_partition->erase_size);
+    esp_err_t ret = esp_partition_erase_range(ota_data_partition, sec_id * SPI_FLASH_SEC_SIZE, SPI_FLASH_SEC_SIZE);
    if (ret != ESP_OK) {
        return ret;
    } else {
-        return esp_partition_write(ota_data_partition, ota_data_partition->erase_size * sec_id, &two_otadata[sec_id], sizeof(esp_ota_select_entry_t));
+        return esp_partition_write(ota_data_partition, SPI_FLASH_SEC_SIZE * sec_id, &two_otadata[sec_id], sizeof(esp_ota_select_entry_t));
    }
 }

@@ -906,7 +906,7 @@ esp_err_t esp_ota_erase_last_boot_app_partition(void)
    }

    int sec_id = inactive_otadata;
-    err = esp_partition_erase_range(ota_data_partition, sec_id * ota_data_partition->erase_size, ota_data_partition->erase_size);
+    err = esp_partition_erase_range(ota_data_partition, sec_id * SPI_FLASH_SEC_SIZE, SPI_FLASH_SEC_SIZE);
    if (err != ESP_OK) {
        return err;
    }
--- a/components/app_update/include/esp_ota_ops.h
+++ b/components/app_update/include/esp_ota_ops.h
@@ -116,8 +116,6 @@ esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp
 *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
 *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
 *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
- *    - ESP_ERR_INVALID_SIZE: if write would go out of bounds of the partition
- *    - or one of error codes from lower-level flash driver.
 */
 esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);

--- a/components/app_update/test_apps/.build-test-rules.yml
+++ b/components/app_update/test_apps/.build-test-rules.yml
@@ -0,0 +1,7 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/app_update/test_apps:
+  disable:
+    - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32c5"]
+      temporary: true
+      reason: target esp32c6, esp32h2 esp32c5 is not supported yet # TODO: [ESP32C5] IDF-8638
--- a/components/app_update/test_apps/test_app_update/CMakeLists.txt
+++ b/components/app_update/test_apps/test_app_update/CMakeLists.txt
--- a/components/app_update/test_apps/README.md
+++ b/components/app_update/test_apps/README.md
@@ -0,0 +1,2 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
--- a/components/app_update/test_apps/main/CMakeLists.txt
+++ b/components/app_update/test_apps/main/CMakeLists.txt
@@ -0,0 +1,4 @@
+idf_component_register(SRC_DIRS "."
+                       PRIV_INCLUDE_DIRS "."
+                       PRIV_REQUIRES cmock test_utils app_update bootloader_support nvs_flash driver spi_flash
+                      WHOLE_ARCHIVE)
--- a/components/app_update/test_apps/test_app_update/main/app_main.c
+++ b/components/app_update/test_apps/test_app_update/main/app_main.c
--- a/components/app_update/test_apps/test_app_update/main/test_ota_ops.c
+++ b/components/app_update/test_apps/test_app_update/main/test_ota_ops.c
@@ -6,7 +6,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include "esp_log.h"
 #include <freertos/FreeRTOS.h>
 #include <freertos/task.h>
 #include <freertos/semphr.h>
@@ -114,11 +113,3 @@ TEST_CASE("esp_ota_get_partition_description", "[ota]")
    };
    TEST_ESP_ERR(ESP_ERR_NOT_FOUND, bootloader_common_get_partition_description(&not_app_pos, &app_desc1));
 }
-
-TEST_CASE("esp_ota_get_running_partition points to correct address", "[spi_flash]")
-{
-    const esp_partition_t *factory = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, "factory");
-    const esp_partition_t* part = esp_ota_get_running_partition();
-    ESP_LOGI("running bin", "0x%p", (void*)part->address);
-    TEST_ASSERT_EQUAL_HEX32(factory->address, part->address);
-}
--- a/components/app_update/test_apps/test_app_update/main/test_switch_ota.c
+++ b/components/app_update/test_apps/test_app_update/main/test_switch_ota.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -101,6 +101,24 @@ static void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const
    ESP_LOGI(TAG, "finish the copy process");
 }

+#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST)
+/* @brief Copies partition from source partition to destination partition.
+ *
+ * Partitions can be of any types and subtypes.
+ * @param[in] dst_partition - Destination partition
+ * @param[in] src_partition - Source partition
+ */
+static void copy_partition(const esp_partition_t *dst_partition, const esp_partition_t *src_partition)
+{
+    const void *partition_bin = NULL;
+    esp_partition_mmap_handle_t data_map;
+    TEST_ESP_OK(esp_partition_mmap(src_partition, 0, src_partition->size, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map));
+    TEST_ESP_OK(esp_partition_erase_range(dst_partition, 0, dst_partition->size));
+    TEST_ESP_OK(esp_partition_write(dst_partition, 0, (const void *)partition_bin, dst_partition->size));
+    esp_partition_munmap(data_map);
+}
+#endif
+
 /* @brief Get the next partition of OTA for the update.
 *
 * @return The next partition of OTA(OTA0-15).
@@ -159,7 +177,7 @@ static void erase_ota_data(void)
 {
    const esp_partition_t *data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL);
    TEST_ASSERT_NOT_EQUAL(NULL, data_partition);
-    TEST_ESP_OK(esp_partition_erase_range(data_partition, 0, 2 * data_partition->erase_size));
+    TEST_ESP_OK(esp_partition_erase_range(data_partition, 0, 2 * SPI_FLASH_SEC_SIZE));
 }

 /* @brief Reboots ESP using mode deep sleep. This mode guaranty that RTC_DATA_ATTR variables is not reset.
@@ -233,7 +251,7 @@ static void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_selec
        TEST_ASSERT_NOT_EQUAL(NULL, ota_select_map);

        memcpy(ota_data_0, ota_select_map, sizeof(esp_ota_select_entry_t));
-        memcpy(ota_data_1, (uint8_t *)ota_select_map + otadata_partition->erase_size, sizeof(esp_ota_select_entry_t));
+        memcpy(ota_data_1, (uint8_t *)ota_select_map + SPI_FLASH_SEC_SIZE, sizeof(esp_ota_select_entry_t));
        bootloader_munmap(ota_select_map);
    }
 }
@@ -246,7 +264,7 @@ static void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_selec
 */
 static void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id)
 {
-    esp_partition_write(otadata_partition, otadata_partition->erase_size * sec_id, &ota_data[sec_id], sizeof(esp_ota_select_entry_t));
+    esp_partition_write(otadata_partition, SPI_FLASH_SEC_SIZE * sec_id, &ota_data[sec_id], sizeof(esp_ota_select_entry_t));
 }

 /* @brief Makes a corrupt of ota_data.
@@ -512,7 +530,7 @@ static void test_flow5(void)
            ESP_LOGI(TAG, "Factory");
            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_FACTORY, cur_app->subtype);
            set_output_pin(CONFIG_BOOTLOADER_NUM_PIN_APP_TEST);
-            esp_partition_copy(esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_TEST, NULL), 0, cur_app, 0, cur_app->size);
+            copy_partition(esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_TEST, NULL), cur_app);
            esp_restart();
            break;
        case 3:
@@ -823,7 +841,8 @@ static void test_flow6(void)
 // 3 Stage: run OTA0    -> check it -> erase OTA_DATA for next tests    -> PASS
 TEST_CASE_MULTIPLE_STAGES("Switching between factory, OTA0 using esp_ota_write_with_offset", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", start_test, test_flow6, test_flow6);

-TEST_CASE("Test bootloader_common_get_sha256_of_partition returns ESP_ERR_IMAGE_INVALID when image is invalid", "[partitions]")
+//IDF-5145
+TEST_CASE("Test bootloader_common_get_sha256_of_partition returns ESP_ERR_IMAGE_INVALID when image is ivalid", "[partitions]")
 {
    const esp_partition_t *cur_app = esp_ota_get_running_partition();
    ESP_LOGI(TAG, "copy current app to next part");
--- a/components/app_update/test_apps/test_app_update/partition_table_unit_test_two_ota.csv
+++ b/components/app_update/test_apps/test_app_update/partition_table_unit_test_two_ota.csv
@@ -7,3 +7,5 @@ factory,    0,    0,       ,        0xB0000
 ota_0,      0,    ota_0,   ,        0xB0000
 ota_1,      0,    ota_1,   ,        0xB0000
 test,       0,    test,    ,        0xB0000
+# flash_test partition used for SPI flash tests, WL FAT tests, and SPIFFS tests
+flash_test, data, fat,     ,        528K
--- a/components/app_update/test_apps/test_app_update/partition_table_unit_test_two_ota_2m.csv
+++ b/components/app_update/test_apps/test_app_update/partition_table_unit_test_two_ota_2m.csv
@@ -7,3 +7,5 @@ factory,    0,    0,       ,        0x70000
 ota_0,      0,    ota_0,   ,        0x70000
 ota_1,      0,    ota_1,   ,        0x70000
 test,       0,    test,    ,        0x70000
+# flash_test partition used for SPI flash tests, WL FAT tests, and SPIFFS tests
+flash_test, data, fat,     ,        128K
--- a/components/app_update/test_apps/pytest_app_update_ut.py
+++ b/components/app_update/test_apps/pytest_app_update_ut.py
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import re
+
+import pytest
+from pytest_embedded import Dut
+
+DEFAULT_TIMEOUT = 20
+TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
+
+
+def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
+    for stage in range(1, stages + 1):
+        dut.write(str(test_case_num))
+        dut.expect(TEST_SUBMENU_PATTERN_PYTEST, timeout=DEFAULT_TIMEOUT)
+        dut.write(str(stage))
+        if stage != stages:
+            dut.expect_exact('Press ENTER to see the list of tests.')
+
+
+@pytest.mark.supported_targets
+@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2'], reason='c6/h2 support TBD')
+@pytest.mark.generic
+def test_app_update(dut: Dut) -> None:
+    extra_data = dut.parse_test_menu()
+    for test_case in extra_data:
+        if test_case.type != 'multi_stage':
+            dut.write(str(test_case.index))
+        else:
+            run_multiple_stages(dut, test_case.index, len(test_case.subcases))
+        dut.expect_unity_test_output(timeout=90)
+        dut.expect_exact("Enter next test, or 'enter' to see menu")
--- a/components/app_update/test_apps/sdkconfig.defaults
+++ b/components/app_update/test_apps/sdkconfig.defaults
@@ -0,0 +1,18 @@
+# General options for additional checks
+CONFIG_HEAP_POISONING_COMPREHENSIVE=y
+CONFIG_COMPILER_WARN_WRITE_STRINGS=y
+CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
+CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
+CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y
+CONFIG_COMPILER_STACK_CHECK=y
+
+CONFIG_ESP_TASK_WDT=n
+
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_two_ota.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_two_ota.csv"
+
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_OFFSET=0x18000
+CONFIG_BOOTLOADER_HOLD_TIME_GPIO=2
+CONFIG_BOOTLOADER_OTA_DATA_ERASE=y
--- a/components/app_update/test_apps/sdkconfig.defaults.esp32
+++ b/components/app_update/test_apps/sdkconfig.defaults.esp32
@@ -0,0 +1,7 @@
+CONFIG_IDF_TARGET="esp32"
+CONFIG_BOOTLOADER_FACTORY_RESET=y
+CONFIG_BOOTLOADER_APP_TEST=y
+CONFIG_BOOTLOADER_DATA_FACTORY_RESET=""
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=32
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
+CONFIG_BOOTLOADER_HOLD_TIME_GPIO=2
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32c2
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32c2
@@ -3,4 +3,3 @@ CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_two_ota_2m.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_two_ota_2m.csv"
 CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/app_update/test_apps/sdkconfig.defaults.esp32c3
+++ b/components/app_update/test_apps/sdkconfig.defaults.esp32c3
@@ -0,0 +1,2 @@
+CONFIG_IDF_TARGET="esp32c3"
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
--- a/components/app_update/test_apps/sdkconfig.defaults.esp32s2
+++ b/components/app_update/test_apps/sdkconfig.defaults.esp32s2
@@ -0,0 +1,2 @@
+CONFIG_IDF_TARGET="esp32s2"
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
--- a/components/app_update/test_apps/test_app_update/.build-test-rules.yml
+++ b/components/app_update/test_apps/test_app_update/.build-test-rules.yml
@@ -1,12 +0,0 @@
-# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
-
-components/app_update/test_apps:
-  enable:
-    - if: CONFIG_NAME == "defaults" and IDF_TARGET != "linux"
-    - if: CONFIG_NAME == "xip_psram" and IDF_TARGET in ["esp32s2", "esp32s3", "esp32p4"]
-    # S2 doesn't have ROM for flash
-    - if: CONFIG_NAME == "xip_psram_with_rom_impl" and IDF_TARGET in ["esp32s3", "esp32p4"]
-  disable:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: target esp32c61 is not supported yet  # TODO: [ESP32C61] IDF-9245
--- a/components/app_update/test_apps/test_app_update/README.md
+++ b/components/app_update/test_apps/test_app_update/README.md
@@ -1,2 +0,0 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/components/app_update/test_apps/test_app_update/main/CMakeLists.txt
+++ b/components/app_update/test_apps/test_app_update/main/CMakeLists.txt
@@ -1,4 +0,0 @@
-idf_component_register(SRC_DIRS "."
-                       PRIV_INCLUDE_DIRS "."
-                       PRIV_REQUIRES cmock test_utils app_update bootloader_support nvs_flash driver spi_flash esp_psram
-                      WHOLE_ARCHIVE)
--- a/components/app_update/test_apps/test_app_update/pytest_app_update_ut.py
+++ b/components/app_update/test_apps/test_app_update/pytest_app_update_ut.py
@@ -1,52 +0,0 @@
-# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: Unlicense OR CC0-1.0
-import re
-
-import pytest
-from pytest_embedded import Dut
-
-DEFAULT_TIMEOUT = 20
-TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
-
-
-@pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep')  # TODO: [ESP32C5] IDF-8640, IDF-10317
-@pytest.mark.generic
-@pytest.mark.parametrize(
-    'config',
-    [
-        'defaults',
-    ],
-    indirect=True,
-)
-def test_app_update(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
-
-
-@pytest.mark.supported_targets
-# TODO: [ESP32C61] IDF-9245, IDF-10983
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
-@pytest.mark.generic
-@pytest.mark.parametrize(
-    'config',
-    [
-        'xip_psram',
-    ],
-    indirect=True,
-)
-def test_app_update_xip_psram(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
-
-
-@pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep')  # TODO: [ESP32C5] IDF-8640, IDF-10317
-@pytest.mark.generic
-@pytest.mark.parametrize(
-    'config',
-    [
-        'xip_psram_with_rom_impl',
-    ],
-    indirect=True,
-)
-def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
--- a/components/app_update/test_apps/test_app_update/sdkconfig.ci.xip_psram
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.ci.xip_psram
@@ -1,2 +0,0 @@
-CONFIG_SPIRAM=y
-CONFIG_SPIRAM_XIP_FROM_PSRAM=y
--- a/components/app_update/test_apps/test_app_update/sdkconfig.ci.xip_psram_with_rom_impl
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.ci.xip_psram_with_rom_impl
@@ -1,3 +0,0 @@
-CONFIG_SPIRAM=y
-CONFIG_SPIRAM_XIP_FROM_PSRAM=y
-CONFIG_SPI_FLASH_ROM_IMPL=y
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults
@@ -1,22 +0,0 @@
-# General options for additional checks
-CONFIG_HEAP_POISONING_COMPREHENSIVE=y
-CONFIG_COMPILER_WARN_WRITE_STRINGS=y
-CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
-CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
-CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y
-CONFIG_COMPILER_STACK_CHECK=y
-
-CONFIG_ESP_TASK_WDT=n
-
-CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
-CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_two_ota.csv"
-CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_two_ota.csv"
-
-CONFIG_PARTITION_TABLE_CUSTOM=y
-CONFIG_PARTITION_TABLE_OFFSET=0x18000
-
-CONFIG_BOOTLOADER_FACTORY_RESET=y
-CONFIG_BOOTLOADER_APP_TEST=y
-CONFIG_BOOTLOADER_DATA_FACTORY_RESET=""
-CONFIG_BOOTLOADER_HOLD_TIME_GPIO=2
-CONFIG_BOOTLOADER_OTA_DATA_ERASE=y
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=32
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32c3
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32c3
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32c3"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32c6
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32c6
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32c6"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32h2
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32h2
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32h2"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=22
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32p4
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32p4
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32p4"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=19
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32s2
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32s2
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32s2"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32s3
+++ b/components/app_update/test_apps/test_app_update/sdkconfig.defaults.esp32s3
@@ -1,3 +0,0 @@
-CONFIG_IDF_TARGET="esp32s3"
-CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
-CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
--- a/components/bootloader/Kconfig.log
+++ b/components/bootloader/Kconfig.log
@@ -1,34 +0,0 @@
-menu "Log"
-
-    choice BOOTLOADER_LOG_LEVEL
-        bool "Bootloader log verbosity"
-        default BOOTLOADER_LOG_LEVEL_INFO
-        help
-            Specify how much output to see in bootloader logs.
-
-        config BOOTLOADER_LOG_LEVEL_NONE
-            bool "No output"
-        config BOOTLOADER_LOG_LEVEL_ERROR
-            bool "Error"
-        config BOOTLOADER_LOG_LEVEL_WARN
-            bool "Warning"
-        config BOOTLOADER_LOG_LEVEL_INFO
-            bool "Info"
-        config BOOTLOADER_LOG_LEVEL_DEBUG
-            bool "Debug"
-        config BOOTLOADER_LOG_LEVEL_VERBOSE
-            bool "Verbose"
-    endchoice
-
-    config BOOTLOADER_LOG_LEVEL
-        int
-        default 0 if BOOTLOADER_LOG_LEVEL_NONE
-        default 1 if BOOTLOADER_LOG_LEVEL_ERROR
-        default 2 if BOOTLOADER_LOG_LEVEL_WARN
-        default 3 if BOOTLOADER_LOG_LEVEL_INFO
-        default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
-        default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
-
-    orsource "Kconfig.log.format"
-
-endmenu
--- a/components/bootloader/Kconfig.log.format
+++ b/components/bootloader/Kconfig.log.format
@@ -1,38 +0,0 @@
-menu "Format"
-
-    config BOOTLOADER_LOG_COLORS
-        bool "Color"
-        default n
-        help
-            Use ANSI terminal colors in log output
-            Enable ANSI terminal color codes.
-            In order to view these, your terminal program must support ANSI color codes.
-
-    choice BOOTLOADER_LOG_TIMESTAMP_SOURCE
-        prompt "Timestamp"
-        default BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS
-        help
-            Choose what sort of timestamp is displayed in the log output:
-
-            - "None" - The log will only contain the actual log messages themselves
-              without any time-related information. Avoiding timestamps can help conserve
-              processing power and memory. It might useful when you
-              perform log analysis or debugging, sometimes it's more straightforward
-              to work with logs that lack timestamps, especially if the time of occurrence
-              is not critical for understanding the issues.
-              "I log_test: info message"
-
-            - "Milliseconds since boot" is calculated from the RTOS tick count multiplied
-              by the tick period. This time will reset after a software reboot.
-              "I (112500) log_test: info message"
-
-        config BOOTLOADER_LOG_TIMESTAMP_SOURCE_NONE
-            bool "None"
-            depends on NO_SYMBOL  # hide it now, turn it on final MR
-
-        config BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS
-            bool "Milliseconds Since Boot"
-
-    endchoice # BOOTLOADER_LOG_TIMESTAMP_SOURCE
-
-endmenu
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -20,14 +20,14 @@ menu "Bootloader config"
            This option sets compiler optimization level (gcc -O argument)
            for the bootloader.

-            - The default "Size" setting will add the -Os (-Oz with clang) flag to CFLAGS.
+            - The default "Size" setting will add the -0s flag to CFLAGS.
            - The "Debug" setting will add the -Og flag to CFLAGS.
            - The "Performance" setting will add the -O2 flag to CFLAGS.

            Note that custom optimization levels may be unsupported.

        config BOOTLOADER_COMPILER_OPTIMIZATION_SIZE
-            bool "Size (-Os with GCC, -Oz with Clang)"
+            bool "Size (-Os)"
        config BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG
            bool "Debug (-Og)"
        config BOOTLOADER_COMPILER_OPTIMIZATION_PERF
@@ -38,7 +38,34 @@ menu "Bootloader config"

    endchoice

-    orsource "Kconfig.log"
+    choice BOOTLOADER_LOG_LEVEL
+        bool "Bootloader log verbosity"
+        default BOOTLOADER_LOG_LEVEL_INFO
+        help
+            Specify how much output to see in bootloader logs.
+
+        config BOOTLOADER_LOG_LEVEL_NONE
+            bool "No output"
+        config BOOTLOADER_LOG_LEVEL_ERROR
+            bool "Error"
+        config BOOTLOADER_LOG_LEVEL_WARN
+            bool "Warning"
+        config BOOTLOADER_LOG_LEVEL_INFO
+            bool "Info"
+        config BOOTLOADER_LOG_LEVEL_DEBUG
+            bool "Debug"
+        config BOOTLOADER_LOG_LEVEL_VERBOSE
+            bool "Verbose"
+    endchoice
+
+    config BOOTLOADER_LOG_LEVEL
+        int
+        default 0 if BOOTLOADER_LOG_LEVEL_NONE
+        default 1 if BOOTLOADER_LOG_LEVEL_ERROR
+        default 2 if BOOTLOADER_LOG_LEVEL_WARN
+        default 3 if BOOTLOADER_LOG_LEVEL_INFO
+        default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
+        default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE

    menu "Serial Flash Configurations"
        config BOOTLOADER_SPI_CUSTOM_WP_PIN
@@ -100,15 +127,9 @@ menu "Bootloader config"
            help
                This is a helper config for 32bits address flash. Invisible for users.

-        config BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH
-            bool
-            default y if BOOTLOADER_FLASH_NEEDS_32BIT_FEAT && SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
-            help
-                This is a helper config for 32bits address quad flash. Invisible for users.
-
        config BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
            bool "Enable cache access to 32-bit-address (over 16MB) range of SPI Flash (READ DOCS FIRST)"
-            depends on BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH && IDF_EXPERIMENTAL_FEATURES
+            depends on BOOTLOADER_FLASH_NEEDS_32BIT_FEAT && IDF_TARGET_ESP32S3 && IDF_EXPERIMENTAL_FEATURES
            default n
            help
                Enabling this option allows the CPU to access 32-bit-address flash beyond 16M range.
@@ -145,7 +166,7 @@ menu "Bootloader config"

    config BOOTLOADER_FACTORY_RESET
        bool "GPIO triggers factory reset"
-        default n
+        default N
        select BOOTLOADER_RESERVE_RTC_MEM if SOC_RTC_FAST_MEM_SUPPORTED
        help
            Allows to reset the device to factory settings:
@@ -158,23 +179,13 @@ menu "Bootloader config"
        int "Number of the GPIO input for factory reset"
        depends on BOOTLOADER_FACTORY_RESET
        range 0 39 if IDF_TARGET_ESP32
-        range 0 46 if IDF_TARGET_ESP32S2
-        range 0 48 if IDF_TARGET_ESP32S3
-        range 0 20 if IDF_TARGET_ESP32C2
-        range 0 21 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C61
-        range 0 28 if IDF_TARGET_ESP32C5
-        range 0 30 if IDF_TARGET_ESP32C6
-        range 0 27 if IDF_TARGET_ESP32H2
-        range 0 54 if IDF_TARGET_ESP32P4
+        range 0 44 if IDF_TARGET_ESP32S2
        default 4
        help
-            The selected GPIO will be configured as an input with internal pull-up enabled. To trigger a factory
+            The selected GPIO will be configured as an input with internal pull-up enabled (note that on some SoCs.
+            not all pins have an internal pull-up, consult the hardware datasheet for details.) To trigger a factory
            reset, this GPIO must be held high or low (as configured) on startup.

-            Note that on some SoCs not all pins have an internal pull-up and certain pins are already
-            used by ROM bootloader as bootstrapping. Refer to the technical reference manual for further
-            details on the selected SoC.
-
    choice BOOTLOADER_FACTORY_RESET_PIN_LEVEL
        bool "Factory reset GPIO level"
        depends on BOOTLOADER_FACTORY_RESET
@@ -210,7 +221,7 @@ menu "Bootloader config"

    config BOOTLOADER_APP_TEST
        bool "GPIO triggers boot from test app partition"
-        default n
+        default N
        depends on !BOOTLOADER_APP_ANTI_ROLLBACK
        help
            Allows to run the test app from "TEST" partition.
@@ -220,25 +231,14 @@ menu "Bootloader config"
    config BOOTLOADER_NUM_PIN_APP_TEST
        int "Number of the GPIO input to boot TEST partition"
        depends on BOOTLOADER_APP_TEST
-        range 0 39 if IDF_TARGET_ESP32
-        range 0 46 if IDF_TARGET_ESP32S2
-        range 0 48 if IDF_TARGET_ESP32S3
-        range 0 20 if IDF_TARGET_ESP32C2
-        range 0 21 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C61
-        range 0 28 if IDF_TARGET_ESP32C5
-        range 0 30 if IDF_TARGET_ESP32C6
-        range 0 27 if IDF_TARGET_ESP32H2
-        range 0 54 if IDF_TARGET_ESP32P4
+        range 0 39
        default 18
        help
            The selected GPIO will be configured as an input with internal pull-up enabled.
            To trigger a test app, this GPIO must be pulled low on reset.
            After the GPIO input is deactivated and the device reboots, the old application will boot.
            (factory or OTA[x]).
-
-            Note that on some SoCs not all pins have an internal pull-up and certain pins are already
-            used by ROM bootloader as bootstrapping. Refer to the technical reference manual for further
-            details on the selected SoC.
+            Note that GPIO34-39 do not have an internal pullup and an external one must be provided.

    choice BOOTLOADER_APP_TEST_PIN_LEVEL
        bool "App test GPIO level"
@@ -269,8 +269,6 @@ menu "Bootloader config"
            Protects the unmapped memory regions of the entire address space from unintended accesses.
            This will ensure that an exception will be triggered whenever the CPU performs a memory
            operation on unmapped regions of the address space.
-            NOTE: Disabling this config on some targets (ESP32-C6, ESP32-H2, ESP32-C5) would not generate
-            an exception when reading from or writing to 0x0.

    config BOOTLOADER_WDT_ENABLE
        bool "Use RTC watchdog in start code"
@@ -383,9 +381,9 @@ menu "Bootloader config"
        # options, allowing to turn on "allow insecure options" and have secure boot with
        # "skip validation when existing deep sleep". Keeping this to avoid a breaking change,
        # but - as noted in help - it invalidates the integrity of Secure Boot checks
-        depends on ((SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT)
+        depends on SOC_RTC_FAST_MEM_SUPPORTED && ((SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT)
        default n
-        select BOOTLOADER_RESERVE_RTC_MEM if SOC_RTC_FAST_MEM_SUPPORTED
+        select BOOTLOADER_RESERVE_RTC_MEM
        help
            This option disables the normal validation of an image coming out of
            deep sleep (checksums, SHA256, and signature). This is a trade-off
@@ -784,7 +782,7 @@ menu "Security features"
    config SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
        bool "Enable Aggressive key revoke strategy"
        depends on SECURE_BOOT && SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
-        default n
+        default N
        help
            If this option is set, ROM bootloader will revoke the public key digest burned in efuse block
            if it fails to verify the signature of software bootloader with it.
@@ -797,37 +795,10 @@ menu "Security features"
            This can lead to permanent bricking of the device, in case all keys are revoked
            because of signature verification failure.

-    config SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
-        bool "Do not disable the ability to further read protect eFuses"
-        depends on SECURE_BOOT_V2_ENABLED
-        default n
-        help
-            If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS
-            efuse when Secure Boot is enabled. This prevents any more efuses from being read protected.
-
-            If this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure
-            Boot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and
-            BLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the secure boot public key digest,
-            causing an immediate denial of service and possibly allowing an additional fault injection attack to
-            bypass the signature protection.
-
-            The option must be set when you need to program any read-protected key type into the efuses,
-            e.g., HMAC, ECDSA etc. after secure boot has already been enabled on the device.
-            Please refer to secure boot V2 documentation guide for more details.
-
-            NOTE: Once a BLOCK is read-protected, the application will read all zeros from that block
-
-            NOTE: If "UART ROM download mode (Permanently disabled (recommended))" or
-            "UART ROM download mode (Permanently switch to Secure mode (recommended))" is set,
-            then it is __NOT__ possible to read/write efuses using espefuse.py utility.
-            However, efuse can be read/written from the application
-
-            Please refer to the Secure Boot V2 documentation guide for more information.
-
    config SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT
        bool "Flash bootloader along with other artifacts when using the default flash command"
        depends on SECURE_BOOT_V2_ENABLED && SECURE_BOOT_BUILD_SIGNED_BINARIES
-        default n
+        default N
        help
            When Secure Boot V2 is enabled, by default the bootloader is not flashed along with other artifacts
            like the application and the partition table images, i.e. bootloader has to be separately flashed
@@ -867,7 +838,7 @@ menu "Security features"
    config SECURE_BOOT_INSECURE
        bool "Allow potentially insecure options"
        depends on SECURE_BOOT
-        default n
+        default N
        help
            You can disable some of the default protections offered by secure boot, in order to enable testing or a
            custom combination of security features.
@@ -878,7 +849,7 @@ menu "Security features"

    config SECURE_FLASH_ENC_ENABLED
        bool "Enable flash encryption on boot (READ DOCS FIRST)"
-        default n
+        default N
        select SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE
        help
            If this option is set, flash contents will be encrypted by the bootloader on first boot.
@@ -965,7 +936,7 @@ menu "Security features"
        config SECURE_BOOT_ALLOW_ROM_BASIC
            bool "Leave ROM BASIC Interpreter available on reset"
            depends on (SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT) && IDF_TARGET_ESP32
-            default n
+            default N
            help
                By default, the BASIC ROM Console starts on reset if no valid bootloader is
                read from the flash.
@@ -980,7 +951,7 @@ menu "Security features"
            bool "Allow JTAG Debugging"
            depends on SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
            select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
-            default n
+            default N
            help
                If not set (default), the bootloader will permanently disable JTAG (across entire chip) on first boot
                when either secure boot or flash encryption is enabled.
@@ -1004,10 +975,30 @@ menu "Security features"
                image to this length. It is generally not recommended to set this option, unless you have a legacy
                partitioning scheme which doesn't support 64KB aligned partition lengths.

+        config SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
+            bool "Allow additional read protecting of efuses"
+            depends on SECURE_BOOT_INSECURE && SECURE_BOOT_V2_ENABLED
+            help
+                If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS
+                efuse when Secure Boot is enabled. This prevents any more efuses from being read protected.
+
+                If this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure
+                Boot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and
+                BLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the public key digest, causing an
+                immediate denial of service and possibly allowing an additional fault injection attack to
+                bypass the signature protection.
+
+                NOTE: Once a BLOCK is read-protected, the application will read all zeros from that block
+
+                NOTE: If "UART ROM download mode (Permanently disabled (recommended))" or
+                "UART ROM download mode (Permanently switch to Secure mode (recommended))" is set,
+                then it is __NOT__ possible to read/write efuses using espefuse.py utility.
+                However, efuse can be read/written from the application
+
        config SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS
            bool "Leave unused digest slots available (not revoke)"
            depends on SECURE_BOOT_INSECURE && SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
-            default n
+            default N
            help
                If not set (default), during startup in the app all unused digest slots will be revoked.
                To revoke unused slot will be called esp_efuse_set_digest_revoke(num_digest) for each digest.
@@ -1026,7 +1017,7 @@ menu "Security features"
            bool "Leave UART bootloader encryption enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
            select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
-            default n
+            default N
            help
                If not set (default), the bootloader will permanently disable UART bootloader encryption access on
                first boot. If set, the UART bootloader will still be able to access hardware encryption.
@@ -1036,7 +1027,7 @@ menu "Security features"
        config SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC
            bool "Leave UART bootloader decryption enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && IDF_TARGET_ESP32
-            default n
+            default N
            help
                If not set (default), the bootloader will permanently disable UART bootloader decryption access on
                first boot. If set, the UART bootloader will still be able to access hardware decryption.
@@ -1048,7 +1039,7 @@ menu "Security features"
            bool "Leave UART bootloader flash cache enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && \
                (IDF_TARGET_ESP32 || SOC_EFUSE_DIS_DOWNLOAD_ICACHE || SOC_EFUSE_DIS_DOWNLOAD_DCACHE) # NOERROR
-            default n
+            default N
            select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
            help
                If not set (default), the bootloader will permanently disable UART bootloader flash cache access on
@@ -1059,7 +1050,7 @@ menu "Security features"
        config SECURE_FLASH_REQUIRE_ALREADY_ENABLED
            bool "Require flash encryption to be already enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
-            default n
+            default N
            help
                If not set (default), and flash encryption is not yet enabled in eFuses, the 2nd stage bootloader
                will enable flash encryption: generate the flash encryption key and program eFuses.
--- a/components/bootloader/project_include.cmake
+++ b/components/bootloader/project_include.cmake
@@ -30,6 +30,12 @@ idf_build_get_property(project_dir PROJECT_DIR)
 if(CONFIG_SECURE_SIGNED_APPS)
    add_custom_target(gen_secure_boot_keys)

+    if(CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
+        set(secure_apps_signing_version "1")
+    elseif(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME)
+        set(secure_apps_signing_version "2")
+    endif()
+
    if(CONFIG_SECURE_BOOT_V1_ENABLED)
        # Check that the configuration is sane
        if((CONFIG_SECURE_BOOTLOADER_REFLASHABLE AND CONFIG_SECURE_BOOTLOADER_ONE_TIME_FLASH) OR
@@ -59,10 +65,11 @@ if(CONFIG_SECURE_SIGNED_APPS)
            # If the signing key is not found, create a phony gen_secure_boot_signing_key target that
            # fails the build. fail_at_build_time causes a cmake run next time
            # (to pick up a new signing key if one exists, etc.)
-            if(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
+            if(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME)
                fail_at_build_time(gen_secure_boot_signing_key
                    "Secure Boot Signing Key ${CONFIG_SECURE_BOOT_SIGNING_KEY} does not exist. Generate using:"
-                    "\tidf.py secure-generate-signing-key ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
+                    "\tespsecure.py generate_signing_key --version ${secure_apps_signing_version} \
+                    ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
            else()
                if(CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_192_BITS)
                    set(scheme "ecdsa192")
@@ -71,7 +78,8 @@ if(CONFIG_SECURE_SIGNED_APPS)
                endif()
                fail_at_build_time(gen_secure_boot_signing_key
                    "Secure Boot Signing Key ${CONFIG_SECURE_BOOT_SIGNING_KEY} does not exist. Generate using:"
-                    "\tidf.py secure-generate-signing-key --scheme ${scheme} ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
+                    "\tespsecure.py generate_signing_key --version ${secure_apps_signing_version} \
+                    --scheme ${scheme} ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
            endif()
        else()
            add_custom_target(gen_secure_boot_signing_key)
@@ -116,7 +124,7 @@ idf_build_get_property(sdkconfig SDKCONFIG)
 idf_build_get_property(python PYTHON)
 idf_build_get_property(extra_cmake_args EXTRA_CMAKE_ARGS)

-# We cannot pass lists are a parameter to the external project without modifying the ';' separator
+# We cannot pass lists are a parameter to the external project without modifying the ';' spearator
 string(REPLACE ";" "|" BOOTLOADER_IGNORE_EXTRA_COMPONENT "${BOOTLOADER_IGNORE_EXTRA_COMPONENT}")

 externalproject_add(bootloader
--- a/components/bootloader/subproject/CMakeLists.txt
+++ b/components/bootloader/subproject/CMakeLists.txt
@@ -58,7 +58,6 @@ foreach(component ${proj_components})
 endforeach()

 set(BOOTLOADER_BUILD 1)
-set(NON_OS_BUILD 1)
 include("${IDF_PATH}/tools/cmake/project.cmake")
 set(common_req log esp_rom esp_common esp_hw_support newlib)
 idf_build_set_property(EXTRA_COMPONENT_EXCLUDE_DIRS "${EXTRA_COMPONENT_EXCLUDE_DIRS}")
@@ -67,7 +66,6 @@ idf_build_set_property(__OUTPUT_SDKCONFIG 0)
 project(bootloader)

 idf_build_set_property(COMPILE_DEFINITIONS "BOOTLOADER_BUILD=1" APPEND)
-idf_build_set_property(COMPILE_DEFINITIONS "NON_OS_BUILD=1" APPEND)
 idf_build_set_property(COMPILE_OPTIONS "-fno-stack-protector" APPEND)

 idf_component_get_property(main_args esptool_py FLASH_ARGS)
@@ -209,7 +207,7 @@ elseif(CONFIG_SECURE_BOOTLOADER_REFLASHABLE)
        COMMAND ${CMAKE_COMMAND} -E echo
            "* After first boot, only re-flashes of this kind (with same key) will be accepted."
        COMMAND ${CMAKE_COMMAND} -E echo
-            "* Not recommended to reuse the same secure boot keyfile on multiple production devices."
+            "* Not recommended to re-use the same secure boot keyfile on multiple production devices."
        DEPENDS gen_secure_bootloader_key gen_bootloader_digest_bin
        VERBATIM)
 elseif(
--- a/components/bootloader/subproject/main/CMakeLists.txt
+++ b/components/bootloader/subproject/main/CMakeLists.txt
@@ -1,7 +1,13 @@
 idf_component_register(SRCS "bootloader_start.c"
                    REQUIRES bootloader bootloader_support)

-set(target_folder "${target}")
+if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    set(target_folder "esp32c5/beta3")
+elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+    set(target_folder "esp32c5/mp")
+else()
+    set(target_folder "${target}")
+endif()

 idf_build_get_property(target IDF_TARGET)
 set(scripts "ld/${target_folder}/bootloader.ld")
--- a/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
@@ -0,0 +1,310 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  TODO: [ESP32C5] IDF-9358 Check this file whether need update for MP ROM
+ *  ESP32-C5 ROM static data usage is as follows:
+ *  - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4087ebc0 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4087cbc0).
+ */
+
+/* We consider 0x4087cbc0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4087cbc0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x5000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2200;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4086EBC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    /* we use either libgcc or compiler-rt, so put similar entries for them here */
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.bootdesc : ALIGN(0x10)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ * 0x4086b2b8 ------------------> _dram0_0_start
+ *            |               |
+ *            |               |
+ *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *            |               |
+ *            |               |
+ * 0x4087cbc0 ------------------> __stack_sentry
+ *            |               |
+ *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *            |               |
+ * 0x4087ebc0 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |
+ *            |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *            |               |      (can be freed when IDF runs)
+ *            |               |
+ *            |               |
+ * 0x4087fb14 ------------------> _dram0_rtos_reserved_start
+ *            |               |
+ *            |               |
+ *            |               |   4. Shared memory used in startup code and when IDF runs
+ *            |               |
+ *            |               |
+ * 0x4087fefc ------------------> _dram0_rtos_reserved_end
+ *            |               |
+ * 0x4087ffb8 ------------------> _data_start_interface
+ *            |               |
+ *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *            |               |
+ * 0x40880000 ------------------> _data_end_interface
+ */
--- a/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld
--- a/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.ld
--- a/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.rom.ld
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-C5 target */
--- a/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld
@@ -7,20 +7,20 @@
 *  Make sure the bootloader can load into main memory without overwriting itself.
 *
 *  ESP32-C61 ROM static data usage is as follows:
- *  - 0x4083ea70 - 0x4084ca70: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4084ca70 - 0x4084ea70: PRO CPU stack, can be reclaimed as heap after RTOS startup
- *  - 0x4084ea70 - 0x40850000: ROM .bss and .data (not easily reclaimable)
+ *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
 *
 *  The 2nd stage bootloader can take space up to the end of ROM shared
- *  buffers area (0x4084ca70).
+ *  buffers area (0x4087c610).
 */

-/* We consider 0x4084ca70 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
 * and work out iram_seg and iram_loader_seg addresses from there, backwards.
 */

 /* These lengths can be adjusted, if necessary: */
-bootloader_usable_dram_end = 0x4084ca70;
+bootloader_usable_dram_end = 0x4084c9f0;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
 bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
@@ -45,7 +45,7 @@ MEMORY
 * 2. Update the value in this assert.
 * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c61/memory.ld.in to the same value.
 */
-ASSERT(bootloader_iram_loader_seg_start == 0x4083ea70, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+ASSERT(bootloader_iram_loader_seg_start == 0x4083E9F0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");

 /* Default entry point: */
 ENTRY(call_start_cpu0);
@@ -273,37 +273,37 @@ SECTIONS
 }


-/**
+/** TODO: [ESP32C61] IDF-9405, update after rom freeze
 *  Appendix: Memory Usage of ROM bootloader
 *
- * 0x4083ea70 ------------------> _dram0_0_start
+ * 0x4086ad08 ------------------> _dram0_0_start
 *            |               |
 *            |               |
 *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
 *            |               |
 *            |               |
- * 0x4084ca70 ------------------> __stack_sentry
+ * 0x4087c610 ------------------> __stack_sentry
 *            |               |
 *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
 *            |               |
- * 0x4084ea70 ------------------> __stack (pro cpu)
+ * 0x4087e610 ------------------> __stack (pro cpu)
 *            |               |
 *            |               |
 *            |               |   3. Shared memory only used in startup code or nonos/early boot*
 *            |               |      (can be freed when IDF runs)
 *            |               |
 *            |               |
- * 0x4084f5d0 ------------------> _dram0_rtos_reserved_start
+ * 0x4087f564 ------------------> _dram0_rtos_reserved_start
 *            |               |
 *            |               |
 *            |               |   4. Shared memory used in startup code and when IDF runs
 *            |               |
 *            |               |
- * 0x4084fc58 ------------------> _dram0_rtos_reserved_end
+ * 0x4087fab0 ------------------> _dram0_rtos_reserved_end
 *            |               |
- * 0x4084fc6c ------------------> _data_start_interface
+ * 0x4087fce8 ------------------> _data_start_interface
 *            |               |
 *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
 *            |               |
- * 0x40850000 ------------------> _data_end_interface
+ * 0x40880000 ------------------> _data_end_interface
 */
--- a/components/bootloader_support/CMakeLists.txt
+++ b/components/bootloader_support/CMakeLists.txt
@@ -15,7 +15,7 @@ set(srcs
    "src/secure_boot.c"
    )

-if(NOT CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING)
+if(NOT CONFIG_IDF_ENV_FPGA)
    # For FPGA ENV, bootloader_random implementation is implemented in `bootloader_random.c`
    list(APPEND srcs "src/bootloader_random_${IDF_TARGET}.c")
 endif()
--- a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
+++ b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
@@ -1,12 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 #pragma once
 #include <stdint.h>
 #include <esp_err.h>
-#include "soc/soc_caps.h"

 #ifdef __cplusplus
 extern "C" {
@@ -28,11 +27,6 @@ esp_err_t bootloader_init_spi_flash(void);
 void bootloader_flash_hardware_init(void);
 #endif

-/**
- * @brief Initialise mspi core clock
- */
-void bootloader_init_mspi_clock(void);
-
 #ifdef __cplusplus
 }
 #endif
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@@ -18,8 +18,19 @@
 #endif
 #include "hal/spi_flash_ll.h"
 #include "rom/spi_flash.h"
-#if !CONFIG_IDF_TARGET_ESP32
-#include "hal/spimem_flash_ll.h"
+#if CONFIG_IDF_TARGET_ESP32
+#   include "soc/spi_struct.h"
+#   include "soc/spi_reg.h"
+    /* SPI flash controller */
+#   define SPIFLASH SPI1
+#   define SPI0     SPI0
+#else
+#   include "hal/spimem_flash_ll.h"
+#   include "soc/spi_mem_struct.h"
+#   include "soc/spi_mem_reg.h"
+    /* SPI flash controller */
+#   define SPIFLASH SPIMEM1
+#   define SPI0     SPIMEM0
 #endif

 // This dependency will be removed in the future.  IDF-5025
@@ -125,8 +136,6 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)

 #if CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/opi_flash.h"
-#elif CONFIG_IDF_TARGET_ESP32P4
-#include "esp32p4/rom/opi_flash.h"
 #endif
 static const char *TAG = "bootloader_flash";

@@ -323,8 +332,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
            ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
 #if CONFIG_IDF_TARGET_ESP32
            //Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
-            // Return value unused if asserts are disabled
-            int e __attribute__((unused)) = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
+            int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
            assert(e == 0);
 #else
            uint32_t actual_mapped_len = 0;
@@ -577,43 +585,61 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
 {
    assert(mosi_len <= 32);
    assert(miso_len <= 32);
-    uint32_t old_ctrl_reg = 0;
-    uint32_t old_user_reg = 0;
-    uint32_t old_user1_reg = 0;
-    uint32_t old_user2_reg = 0;
-    spi_flash_ll_get_common_command_register_info(&SPIMEM_LL_APB, &old_ctrl_reg, &old_user_reg, &old_user1_reg, &old_user2_reg);
-    SPIMEM_LL_APB.ctrl.val = 0;
+    uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
+    uint32_t old_user_reg = SPIFLASH.user.val;
+    uint32_t old_user1_reg = SPIFLASH.user1.val;
+    uint32_t old_user2_reg = SPIFLASH.user2.val;
+    // Clear ctrl regs.
+    SPIFLASH.ctrl.val = 0;
 #if CONFIG_IDF_TARGET_ESP32
-    spi_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
+    spi_flash_ll_set_wp_level(&SPIFLASH, true);
 #else
-    spimem_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
+    spimem_flash_ll_set_wp_level(&SPIFLASH, true);
 #endif
    //command phase
-    spi_flash_ll_set_command(&SPIMEM_LL_APB, command, 8);
+    SPIFLASH.user.usr_command = 1;
+    SPIFLASH.user2.usr_command_bitlen = 7;
+    SPIFLASH.user2.usr_command_value = command;
    //addr phase
-    spi_flash_ll_set_addr_bitlen(&SPIMEM_LL_APB, addr_len);
-    spi_flash_ll_set_usr_address(&SPIMEM_LL_APB, address, addr_len);
+    SPIFLASH.user.usr_addr = addr_len > 0;
+    SPIFLASH.user1.usr_addr_bitlen = addr_len - 1;
+#if CONFIG_IDF_TARGET_ESP32
+    SPIFLASH.addr = (addr_len > 0)? (address << (32-addr_len)) : 0;
+#else
+    SPIFLASH.addr = address;
+#endif
    //dummy phase
    uint32_t total_dummy = dummy_len;
    if (miso_len > 0) {
        total_dummy += g_rom_spiflash_dummy_len_plus[1];
    }
-    spi_flash_ll_set_dummy(&SPIMEM_LL_APB, total_dummy);
+    SPIFLASH.user.usr_dummy = total_dummy > 0;
+    SPIFLASH.user1.usr_dummy_cyclelen = total_dummy - 1;
    //output data
-
-    spi_flash_ll_set_mosi_bitlen(&SPIMEM_LL_APB, mosi_len);
-    spi_flash_ll_set_buffer_data(&SPIMEM_LL_APB, &mosi_data, mosi_len / 8);
+    SPIFLASH.user.usr_mosi = mosi_len > 0;
+#if CONFIG_IDF_TARGET_ESP32
+    SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
+#else
+    SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
+#endif
+    SPIFLASH.data_buf[0] = mosi_data;
    //input data
-    spi_flash_ll_set_miso_bitlen(&SPIMEM_LL_APB, miso_len);
+    SPIFLASH.user.usr_miso = miso_len > 0;
+#if CONFIG_IDF_TARGET_ESP32
+    SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
+#else
+    SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
+#endif

-    spi_flash_ll_user_start(&SPIMEM_LL_APB, false);
-    while(!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
+    SPIFLASH.cmd.usr = 1;
+    while (SPIFLASH.cmd.usr != 0) {
    }
-    spi_flash_ll_set_common_command_register_info(&SPIMEM_LL_APB, old_ctrl_reg, old_user_reg, old_user1_reg, old_user2_reg);
+    SPIFLASH.ctrl.val = old_ctrl_reg;
+    SPIFLASH.user.val = old_user_reg;
+    SPIFLASH.user1.val = old_user1_reg;
+    SPIFLASH.user2.val = old_user2_reg;

-    uint32_t output_data = 0;
-    spi_flash_ll_get_buffer_data(&SPIMEM_LL_APB, &output_data, miso_len / 8);
-    uint32_t ret = output_data;
+    uint32_t ret = SPIFLASH.data_buf[0];
    if (miso_len < 32) {
        //set unused bits to 0
        ret &= ~(UINT32_MAX << miso_len);
@@ -669,7 +695,7 @@ void bootloader_spi_flash_reset(void)
 ******************************************************************************/

 #define XMC_SUPPORT CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT
-#define XMC_VENDOR_ID_1 0x20
+#define XMC_VENDOR_ID 0x20

 #if BOOTLOADER_BUILD
 #define BOOTLOADER_FLASH_LOG(level, ...)    ESP_EARLY_LOG##level(TAG, ##__VA_ARGS__)
@@ -686,7 +712,7 @@ static IRAM_ATTR bool is_xmc_chip_strict(uint32_t rdid)
    uint32_t mfid = BYTESHIFT(rdid, 1);
    uint32_t cpid = BYTESHIFT(rdid, 0);

-    if (vendor_id != XMC_VENDOR_ID_1) {
+    if (vendor_id != XMC_VENDOR_ID) {
        return false;
    }

@@ -719,7 +745,7 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
    // Check the Manufacturer ID in SFDP registers (JEDEC standard). If not XMC chip, no need to run the flow
    const int sfdp_mfid_addr = 0x10;
    uint8_t mf_id = (bootloader_flash_read_sfdp(sfdp_mfid_addr, 1) & 0xff);
-    if (mf_id != XMC_VENDOR_ID_1) {
+    if (mf_id != XMC_VENDOR_ID) {
        BOOTLOADER_FLASH_LOG(D, "non-XMC chip detected by SFDP Read (%02X), skip.", mf_id);
        return ESP_OK;
    }
@@ -751,7 +777,7 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
 static IRAM_ATTR bool is_xmc_chip(uint32_t rdid)
 {
    uint32_t vendor_id = (rdid >> 16) & 0xFF;
-    return (vendor_id == XMC_VENDOR_ID_1);
+    return (vendor_id == XMC_VENDOR_ID);
 }

 esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
@@ -765,9 +791,28 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)

 #endif //XMC_SUPPORT

+FORCE_INLINE_ATTR void bootloader_mspi_reset(void)
+{
+#if CONFIG_IDF_TARGET_ESP32
+    SPI1.slave.sync_reset = 0;
+    SPI0.slave.sync_reset = 0;
+    SPI1.slave.sync_reset = 1;
+    SPI0.slave.sync_reset = 1;
+    SPI1.slave.sync_reset = 0;
+    SPI0.slave.sync_reset = 0;
+#else
+    SPIMEM1.ctrl2.sync_reset = 0;
+    SPIMEM0.ctrl2.sync_reset = 0;
+    SPIMEM1.ctrl2.sync_reset = 1;
+    SPIMEM0.ctrl2.sync_reset = 1;
+    SPIMEM1.ctrl2.sync_reset = 0;
+    SPIMEM0.ctrl2.sync_reset = 0;
+#endif
+}
+
 esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
 {
-    spi_flash_ll_sync_reset();
+    bootloader_mspi_reset();
    // Seems that sync_reset cannot make host totally idle.'
    // Sending an extra(useless) command to make the host idle in order to send reset command.
    bootloader_execute_flash_command(0x05, 0, 0, 0);
@@ -797,7 +842,7 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
 esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
 {
    esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
-    uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPIMEM_LL_CACHE);
+    uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
 #if CONFIG_IDF_TARGET_ESP32
    if (spi_ctrl & SPI_FREAD_QIO) {
        spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -28,12 +28,12 @@
 #include "bootloader_flash_priv.h"
 #include "bootloader_init.h"

-#define FLASH_CLK_IO    MSPI_IOMUX_PIN_NUM_CLK
-#define FLASH_CS_IO     MSPI_IOMUX_PIN_NUM_CS0
-#define FLASH_SPIQ_IO   MSPI_IOMUX_PIN_NUM_MISO
-#define FLASH_SPID_IO   MSPI_IOMUX_PIN_NUM_MOSI
-#define FLASH_SPIWP_IO  MSPI_IOMUX_PIN_NUM_WP
-#define FLASH_SPIHD_IO  MSPI_IOMUX_PIN_NUM_HD
+#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
+#define FLASH_CS_IO SPI_CS0_GPIO_NUM
+#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
+#define FLASH_SPID_IO SPI_D_GPIO_NUM
+#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
+#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM

 void bootloader_flash_update_id(void)
 {
@@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
    } else {
        const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
        if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
-            esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
-            esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
-            esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
-            esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
-            esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
-            esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
-            esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
-            esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
-            esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
+            esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
+            esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
+            esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
+            esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
+            esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
+            esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
+            esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
+            esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
+            esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
            //select pin function gpio
            gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
            gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
@@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
    case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
        return ESP32_PICO_V3_GPIO;
    default:
-        return MSPI_IOMUX_PIN_NUM_WP;
+        return SPI_WP_GPIO_NUM;
    }
 #endif
 }
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
@@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
    // IDF-4066
    const uint32_t spiconfig = 0;
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    if (spiconfig == 0) {

    }
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
@@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    if (spiconfig == 0) {

    } else {
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
@@ -14,8 +14,11 @@
 #include "esp32c5/rom/efuse.h"
 #include "soc/gpio_periph.h"
 #include "soc/io_mux_reg.h"
+// TODO: IDF-9197
+#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
 #include "esp_rom_efuse.h"
 #include "soc/efuse_reg.h"
+#endif
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -28,7 +31,7 @@
 #include "hal/mmu_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
-#include "hal/mspi_timing_tuning_ll.h"
+#include "hal/clk_tree_ll.h"

 void bootloader_flash_update_id()
 {
@@ -48,18 +51,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
 }

-void IRAM_ATTR bootloader_init_mspi_clock(void)
-{
-    // Set source mspi pll clock as 80M in bootloader stage.
-    // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
-    // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
-}
-
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
-    bootloader_init_mspi_clock();
    uint32_t spi_clk_div = 0;
    switch (pfhdr->spi_speed) {
    case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -84,12 +77,12 @@ static const char *TAG = "boot.esp32c5";

 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
@@ -214,7 +207,19 @@ static void bootloader_spi_flash_resume(void)

 esp_err_t bootloader_init_spi_flash(void)
 {
-    bootloader_init_mspi_clock();
+// TODO: IDF-9197
+#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+    // On ESP32C5, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
+    // Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
+    // 80MHz after the switch. PLL = 480MHz, so divider is 6.
+    clk_ll_mspi_fast_set_hs_divider(6);
+#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
+    /* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
+       need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
+       and we need to check flash freq before restart as well */
+    clk_ll_mspi_fast_set_divider(1);
+    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
+#endif

    bootloader_init_flash_configure();
    bootloader_spi_flash_resume();
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
@@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6";

 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
@@ -24,7 +24,6 @@
 #include "hal/mmu_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
-#include "hal/mspi_timing_tuning_ll.h"

 static const char *TAG __attribute__((unused))  = "boot.esp32c61";

@@ -46,19 +45,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
 }

-void IRAM_ATTR bootloader_init_mspi_clock(void)
-{
-    // Set source mspi pll clock as 80M in bootloader stage.
-    // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
-    // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
-}
-
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
-    bootloader_init_mspi_clock();
-
    uint32_t spi_clk_div = 0;
    switch (pfhdr->spi_speed) {
    case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -81,12 +69,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
@@ -209,7 +197,6 @@ static void bootloader_spi_flash_resume(void)

 esp_err_t bootloader_init_spi_flash(void)
 {
-    bootloader_init_mspi_clock();
    bootloader_init_flash_configure();
    bootloader_spi_flash_resume();
    bootloader_flash_unlock();
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
@@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2";

 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
@@ -19,12 +19,10 @@
 #include "bootloader_init.h"
 #include "hal/mmu_hal.h"
 #include "hal/mmu_ll.h"
-#include "hal/spimem_flash_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
-#include "esp_private/bootloader_flash_internal.h"

-void IRAM_ATTR bootloader_flash_update_id(void)
+void IRAM_ATTR bootloader_flash_update_id()
 {
    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
    chip->device_id = bootloader_read_flash_id();
@@ -35,23 +33,15 @@ void bootloader_flash_update_size(uint32_t size)
    rom_spiflash_legacy_data->chip.chip_size = size;
 }

-void IRAM_ATTR bootloader_flash_cs_timing_config(void)
+void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    SET_PERI_REG_MASK(SPI_MEM_C_USER_REG, SPI_MEM_C_CS_HOLD_M | SPI_MEM_C_CS_SETUP_M);
    SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_HOLD_TIME_V, 0, SPI_MEM_C_CS_HOLD_TIME_S);
    SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
 }

-void IRAM_ATTR bootloader_init_mspi_clock(void)
-{
-    _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
-    _spimem_ctrlr_ll_set_core_clock(0, 6);
-}
-
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
-    bootloader_init_mspi_clock();
-
    uint32_t spi_clk_div = 0;
    switch (pfhdr->spi_speed) {
    case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -76,12 +66,12 @@ static const char *TAG = "boot.esp32p4";

 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
@@ -109,15 +99,6 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    case ESP_IMAGE_FLASH_SIZE_16MB:
        size = 16;
        break;
-    case ESP_IMAGE_FLASH_SIZE_32MB:
-        size = 32;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_64MB:
-        size = 64;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_128MB:
-        size = 128;
-        break;
    default:
        size = 2;
    }
@@ -194,15 +175,6 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
    case ESP_IMAGE_FLASH_SIZE_16MB:
        str = "16MB";
        break;
-    case ESP_IMAGE_FLASH_SIZE_32MB:
-        str = "32MB";
-        break;
-    case ESP_IMAGE_FLASH_SIZE_64MB:
-        str = "64MB";
-        break;
-    case ESP_IMAGE_FLASH_SIZE_128MB:
-        str = "128MB";
-        break;
    default:
        str = "2MB";
        break;
@@ -231,9 +203,6 @@ esp_err_t bootloader_init_spi_flash(void)
 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
    bootloader_enable_qio_mode();
 #endif
-#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
-    bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
-#endif

    print_flash_info(&bootloader_image_hdr);

@@ -302,10 +271,6 @@ void bootloader_flash_hardware_init(void)
    bootloader_spi_flash_resume();
    bootloader_flash_unlock();

-#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
-    bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
-#endif
-
    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
    update_flash_config(&hdr);
    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    if (spiconfig == 0) {

    } else {
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
@@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
-    uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
-    uint8_t q_gpio_num   = MSPI_IOMUX_PIN_NUM_MISO;
-    uint8_t d_gpio_num   = MSPI_IOMUX_PIN_NUM_MOSI;
-    uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
-    uint8_t hd_gpio_num  = MSPI_IOMUX_PIN_NUM_HD;
-    uint8_t wp_gpio_num  = MSPI_IOMUX_PIN_NUM_WP;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
    if (spiconfig == 0) {

    } else {
--- a/components/bootloader_support/include/bootloader_common.h
+++ b/components/bootloader_support/include/bootloader_common.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -181,20 +181,6 @@ uint32_t bootloader_common_get_chip_ver_pkg(void);
 */
 esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type);

-#if !CONFIG_IDF_TARGET_ESP32
-/**
- * @brief Check the eFuse block revision
- *
- * @param[in] min_rev_full The required minimum revision of the eFuse block
- * @param[in] max_rev_full The required maximum revision of the eFuse block
- * @return
- *          - ESP_OK: The eFuse block revision is in the required range.
- *          - ESP_OK: DISABLE_BLK_VERSION_MAJOR has been set in the eFuse of the SoC. No requirements shall be checked at this time.
- *          - ESP_FAIL: The eFuse block revision of this chip does not match the requirement of the current image.
- */
-esp_err_t bootloader_common_check_efuse_blk_validity(uint32_t min_rev_full, uint32_t max_rev_full);
-#endif  // !CONFIG_IDF_TARGET_ESP32
-
 /**
 * @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
 */
--- a/components/bootloader_support/include/esp_app_format.h
+++ b/components/bootloader_support/include/esp_app_format.h
@@ -8,9 +8,8 @@
 #include <inttypes.h>
 #include "esp_assert.h"

-#ifdef __cplusplus
-extern "C" {
-#endif
+// TODO: IDF-9197
+#include "sdkconfig.h"

 /**
 * @brief ESP chip ID
@@ -25,7 +24,11 @@ typedef enum {
    ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
    ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
    ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
-    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 */
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
+    ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
+#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
+#endif
    ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;

@@ -117,7 +120,3 @@ typedef struct {
 } esp_image_segment_header_t;

 #define ESP_IMAGE_MAX_SEGMENTS 16           /*!< Max count of segments in the image. */
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/include/esp_flash_encrypt.h
+++ b/components/bootloader_support/include/esp_flash_encrypt.h
@@ -180,19 +180,9 @@ void esp_flash_encryption_init_checks(void);
 /** @brief Set all secure eFuse features related to flash encryption
 *
 * @return
- *  - ESP_OK - On success
+ *  - ESP_OK - Successfully
 */
 esp_err_t esp_flash_encryption_enable_secure_features(void);
-
-#if CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
-/** @brief Enable the key manager for flash encryption
- *
- * @return
- *  - ESP_OK - On success
- */
-esp_err_t esp_flash_encryption_enable_key_mgr(void);
-#endif // CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
-
 #endif /* BOOTLOADER_BUILD && CONFIG_SECURE_FLASH_ENC_ENABLED */

 /** @brief Returns the verification status for all physical security features of flash encryption in release mode
--- a/components/bootloader_support/include/esp_flash_partitions.h
+++ b/components/bootloader_support/include/esp_flash_partitions.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -29,14 +29,6 @@ extern "C" {
 #define PART_SUBTYPE_DATA_NVS_KEYS 0x04
 #define PART_SUBTYPE_DATA_EFUSE_EM 0x05

-#define PART_TYPE_BOOTLOADER 0x02
-#define PART_SUBTYPE_BOOTLOADER_PRIMARY 0x00
-#define PART_SUBTYPE_BOOTLOADER_OTA 0x01
-
-#define PART_TYPE_PARTITION_TABLE 0x03
-#define PART_SUBTYPE_PARTITION_TABLE_PRIMARY 0x00
-#define PART_SUBTYPE_PARTITION_TABLE_OTA 0x01
-
 #define PART_TYPE_END 0xff
 #define PART_SUBTYPE_END 0xff

@@ -49,11 +41,7 @@ extern "C" {
 /* Pre-partition table fixed flash offsets */
 #define ESP_BOOTLOADER_DIGEST_OFFSET 0x0
 #define ESP_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH  /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */
-#define ESP_PRIMARY_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH  /* Offset of Primary bootloader image. */
 #define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/
-#define ESP_PRIMARY_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. */
-#define ESP_PARTITION_TABLE_SIZE (0x1000) /* The partition table occupies 1 sector of flash (SPI_FLASH_SEC_SIZE) */
-#define ESP_BOOTLOADER_SIZE (ESP_PARTITION_TABLE_OFFSET - ESP_BOOTLOADER_OFFSET)

 #define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */
 #define ESP_PARTITION_TABLE_MAX_ENTRIES (ESP_PARTITION_TABLE_MAX_LEN / sizeof(esp_partition_info_t)) /* Maximum length of partition table data, including terminating entry */
--- a/components/bootloader_support/include/esp_secure_boot.h
+++ b/components/bootloader_support/include/esp_secure_boot.h
@@ -31,10 +31,6 @@
 #include "esp32h2/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/secure_boot.h"
-#elif CONFIG_IDF_TARGET_ESP32C5
-#include "esp32c5/rom/secure_boot.h"
-#elif CONFIG_IDF_TARGET_ESP32C61
-#include "esp32c61/rom/secure_boot.h"
 #endif

 #ifdef CONFIG_SECURE_BOOT_V1_ENABLED
@@ -65,42 +61,6 @@ extern "C" {
 #include "esp_efuse_table.h"
 #endif

-/**
- * @brief   Secure Boot Signature Block Version field
- */
-typedef enum {
-    ESP_SECURE_BOOT_V1_ECDSA = 0,           /*!< Secure Boot v1 */
-    ESP_SECURE_BOOT_V2_RSA   = 2,           /*!< Secure Boot v2 with RSA key */
-    ESP_SECURE_BOOT_V2_ECDSA = 3,           /*!< Secure Boot v2 with ECDSA key */
-} esp_secure_boot_sig_scheme_t;
-
-#if CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME
-#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V1_ECDSA
-#elif CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME
-#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V2_RSA
-#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME
-#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V2_ECDSA
-#endif
-
-#if CONFIG_SECURE_BOOT || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT
-/** @brief Get the selected secure boot scheme key type
- *
- * @return key type for the selected secure boot scheme
- */
-static inline const char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme)
-{
-    switch (scheme) {
-        case ESP_SECURE_BOOT_V2_RSA:
-            return "RSA";
-        case ESP_SECURE_BOOT_V1_ECDSA:
-        case ESP_SECURE_BOOT_V2_ECDSA:
-            return "ECDSA";
-        default:
-            return "Unknown";
-    }
-}
-#endif
-
 /** @brief Is secure boot currently enabled in hardware?
 *
 * This means that the ROM bootloader code will only boot
--- a/components/bootloader_support/private_include/bootloader_console.h
+++ b/components/bootloader_support/private_include/bootloader_console.h
@@ -1,15 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #pragma once

-#ifdef __cplusplus
-extern "C" {
-#endif
-
 /**
 * @brief Initialize console output (UART or USB)
 */
@@ -25,7 +21,3 @@ void bootloader_console_deinit(void);
 * Only defined if USB CDC is used for console output.
 */
 void bootloader_console_write_char_usb(char c);
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/private_include/bootloader_init.h
+++ b/components/bootloader_support/private_include/bootloader_init.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -8,10 +8,6 @@
 #include "esp_err.h"
 #include "esp_image_format.h"

-#ifdef __cplusplus
-extern "C" {
-#endif
-
 /**@{*/
 /**
 * @brief labels from bootloader linker script: bootloader.ld
@@ -53,7 +49,3 @@ void bootloader_print_banner(void);
 *          ESP_FAIL - If the setting is not successful.
 */
 esp_err_t bootloader_init(void);
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/private_include/bootloader_sha.h
+++ b/components/bootloader_support/private_include/bootloader_sha.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -16,10 +16,6 @@
 #include <stdlib.h>
 #include "esp_err.h"

-#ifdef __cplusplus
-extern "C" {
-#endif
-
 typedef void *bootloader_sha256_handle_t;

 bootloader_sha256_handle_t bootloader_sha256_start(void);
@@ -27,7 +23,3 @@ bootloader_sha256_handle_t bootloader_sha256_start(void);
 void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len);

 void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest);
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/private_include/bootloader_signature.h
+++ b/components/bootloader_support/private_include/bootloader_signature.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -25,14 +25,6 @@
 #include "esp32h2/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/secure_boot.h"
-#elif CONFIG_IDF_TARGET_ESP32C5
-#include "esp32c5/rom/secure_boot.h"
-#elif CONFIG_IDF_TARGET_ESP32C61
-#include "esp32c61/rom/secure_boot.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
 #endif

 #if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
@@ -53,7 +45,3 @@ esp_err_t esp_secure_boot_verify_rsa_signature_block(const ets_secure_boot_signa
 #endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */

 #endif
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/private_include/bootloader_soc.h
+++ b/components/bootloader_support/private_include/bootloader_soc.h
@@ -1,15 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 #pragma once

-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
 /**
 * @brief Configure analog super WDT reset
 *
@@ -17,21 +12,16 @@ extern "C"
 */
 void bootloader_ana_super_wdt_reset_config(bool enable);

+/**
+ * @brief Configure analog brownout reset
+ *
+ * @param enable Boolean to enable or disable brownout reset
+ */
+void bootloader_ana_bod_reset_config(bool enable);
+
 /**
 * @brief Configure analog clock glitch reset
 *
 * @param enable Boolean to enable or disable clock glitch reset
 */
 void bootloader_ana_clock_glitch_reset_config(bool enable);
-
-/**
- * @brief Configure analog power glitch reset & glitch reset dref
- *
- * @param enable Boolean to enable or disable power glitch reset
- * @param dref voltage threshold
- */
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/private_include/bootloader_utility.h
+++ b/components/bootloader_support/private_include/bootloader_utility.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -9,11 +9,6 @@
 #include "esp_image_format.h"
 #include "bootloader_config.h"

-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
 /**
 * @brief Load partition table.
 *
@@ -21,7 +16,7 @@ extern "C"
 * OTA data partition, factory app partition, and test app partition.
 *
 * @param[out] bs Bootloader state structure used to save read data.
- * @return        Return true if the partition table was successfully loaded and MD5 checksum is valid.
+ * @return        Return true if the partition table was succesfully loaded and MD5 checksum is valid.
 */
 bool bootloader_utility_load_partition_table(bootloader_state_t* bs);

@@ -56,14 +51,9 @@ __attribute__((__noreturn__)) void bootloader_utility_load_boot_image(const boot
 /**
 * @brief Load that application which was worked before we go to the deep sleep.
 *
- * If chip supports the RTC memory:
 * Checks the reboot reason if it is the deep sleep and has a valid partition in the RTC memory
 * then try to load the application which was worked before we go to the deep sleep.
 *
- * If chip does not support the RTC memory:
- * Checks the reboot reason if it is the deep sleep then the partition table is read
- * to select and load an application which was worked before we go to the deep sleep.
- *
 */
 void bootloader_utility_load_boot_image_from_deep_sleep(void);
 #endif
@@ -130,7 +120,3 @@ void bootloader_debug_buffer(const void *buffer, size_t length, const char *labe
 * @return ESP_OK if secure boot digest is generated successfully.
 */
 esp_err_t bootloader_sha256_flash_contents(uint32_t flash_offset, uint32_t len, uint8_t *digest);
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -53,29 +53,32 @@ __attribute__((weak)) void bootloader_clock_configure(void)

        clk_cfg.cpu_freq_mhz = cpu_freq_mhz;

+#if CONFIG_IDF_TARGET_ESP32C5
+        // TODO: [ESP32C5] IDF-9009 Check whether SOC_RTC_SLOW_CLK_SRC_RC_SLOW can be used on C5 MP
+        // RC150K can't do calibrate on ESP32C5MPW so not use it
+        clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
+#else
        // Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
        // RTC_SLOW clock source will be switched according to Kconfig selection at application startup
        clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
        if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
            clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
        }
+#endif

+//TODO: [ESP32C61] IDF-9274, basic rtc support
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+        // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
+        // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
+        clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
+#else
        // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader
        // RTC_FAST clock source will be switched to RC_FAST at application startup
        clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
        if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
        }
-
-#if CONFIG_IDF_TARGET_ESP32C6
-        if (efuse_hal_chip_revision() == 0) {
-            // Some of ESP32C6-ECO0 chip's SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue,
-            // which will cause the chip to be unable to capture the reset reason when it is reset.
-            // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
-            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
-        }
 #endif
-
        rtc_clk_init(clk_cfg);
    }

--- a/Show More
+++ b/Show More