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Merge pull request #195 from dgarske/LPCXpresso

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Adds LPCXpresso IDE support
This commit is contained in:
toddouska
2015-11-23 14:47:20 -08:00
parent 6c1fd13184 6abfaf6df4
commit b9f0243528
11 changed files with 1313 additions and 1 deletions
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&lt;family&gt;Cortex-M&lt;/family&gt;
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>lib_wolfssl</name>
<comment></comment>
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<project>lpc_board_nxp_lpcxpresso_1837</project>
<project>lpc_chip_18xx</project>
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# WolfSSL Example using the OM13076 (LPCXpresso18S37) board
To use, install the NXP LPCXpresso IDE and import the projects in a new workspace.
1. Run LPCXpresso and choose a workspace location.
2. Right click in the project exporer window and choose Inport.
3. Under General choose "Existing Projects into Workspace".
4. Under "Select root directory" click browse and select the wolfSSL root.
5. Check the "Search for nested projects" box.
5. Make sure "wolfssl" and "wolfssl_example" are checked under "Projects:".
6. Click finish.
7. Download the board and chip LPCOpen package for your platform.
8. Import the projects. For example "lpc_board_nxp_lpcxpresso_1837" and "lpc_chip_18xx" are the ones for the LPC18S37.
To setup this example to work with different baords/chips you will need to locate the LPCOpen sources for LPCXpresso on the NXP website and import the board and chip projects. Then you will need to update the "wolfssl_example" project properties to reference these projects (C/C++ General -> Paths and Symbols -> References). See the [LPCOpen v2.xx LPCXpresso quickstart guide for all platforms](https://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-v200-quickstart-guides/lpcopen-1) for additional information.
## WolfSSL example projects:
1. `wolf_example`. It has console options to run the Wolf tests and benchmarks ('t' for the WolfSSL Tests and 'b' for the WolfSSL Benchmarks).
## Static libraries projects:
1. `wolfssl` for WolfSSL. The WolfSSL port for the LPC18XX platform is located in `IDE/LPCXPRESSO/lpc_18xx_port.c`. This has platform specific functions for `current_time` and `rand_gen`. The `WOLF_USER_SETTINGS` define is set which allows all WolfSSL settings to exist in the `user_settings.h` file (see this file for all customizations used).
## Important Files
1. `IDE/LPCXPRESSO/user_settings.h`. This provides a reference for library settings used to optimize for this embedded platform.
2. `IDE/LPCXPRESSO/lpc_18xx_port.c`. This defines the required time and random number functions for the WolfSSL library.
3. `IDE/LPCXPRESSO/wolf_example/wolf_example.c`. This shows use of the WolfSSL tests and benchmarks.

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/* lpc_18xx_port.c
*
* Copyright (C) 2006-2015 wolfSSL Inc.
*
* This file is part of wolfSSL. (formerly known as CyaSSL)
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "board.h"
#include "otp_18xx_43xx.h" /* For RNG */
#include "timer_18xx_43xx.h"
static uint32_t mTimeInit = 0;
#define TIMER_SCALER 1000000
static void init_time(void)
{
if(mTimeInit == 0) {
uint32_t timerFreq;
/* Set current time for RTC 2:00:00PM, 2012-10-05 */
RTC_TIME_T FullTime;
Chip_RTC_Init(LPC_RTC);
FullTime.time[RTC_TIMETYPE_SECOND] = 0;
FullTime.time[RTC_TIMETYPE_MINUTE] = 0;
FullTime.time[RTC_TIMETYPE_HOUR] = 14;
FullTime.time[RTC_TIMETYPE_DAYOFMONTH] = 5;
FullTime.time[RTC_TIMETYPE_DAYOFWEEK] = 5;
FullTime.time[RTC_TIMETYPE_DAYOFYEAR] = 279;
FullTime.time[RTC_TIMETYPE_MONTH] = 10;
FullTime.time[RTC_TIMETYPE_YEAR] = 2012;
Chip_RTC_SetFullTime(LPC_RTC, &FullTime);
/* Enable RTC (starts increase the tick counter and second counter register) */
Chip_RTC_Enable(LPC_RTC, ENABLE);
/* Enable timer 1 clock and reset it */
Chip_TIMER_Init(LPC_TIMER2);
Chip_RGU_TriggerReset(RGU_TIMER2_RST);
while (Chip_RGU_InReset(RGU_TIMER2_RST)) {}
/* Get timer peripheral clock rate */
timerFreq = Chip_Clock_GetRate(CLK_MX_TIMER2);
/* Timer setup */
Chip_TIMER_Reset(LPC_TIMER2);
Chip_TIMER_PrescaleSet(LPC_TIMER2, timerFreq/TIMER_SCALER);
Chip_TIMER_Enable(LPC_TIMER2);
mTimeInit = 1;
}
}
double current_time()
{
//RTC_TIME_T FullTime;
uint32_t timerMs;
init_time();
timerMs = Chip_TIMER_ReadCount(LPC_TIMER2);
//Chip_RTC_GetFullTime(LPC_RTC, &FullTime);
//(double)FullTime.time[RTC_TIMETYPE_SECOND]
return (double)timerMs/TIMER_SCALER;
}
/* Memory location of the generated random numbers (for total of 128 bits) */
static volatile uint32_t* mRandData = (uint32_t*)0x40045050;
static uint32_t mRandInit = 0;
static uint32_t mRandIndex = 0;
uint32_t rand_gen(void)
{
uint32_t rand = 0;
uint32_t status = LPC_OK;
if(mRandIndex == 0) {
if(mRandInit == 0) {
Chip_OTP_Init();
mRandInit = 1;
}
status = Chip_OTP_GenRand();
}
if(status == LPC_OK) {
rand = mRandData[mRandIndex];
}
else {
printf("GenRand Failed 0x%x\n", status);
}
if(++mRandIndex > 4) {
mRandIndex = 0;
}
return rand;
}

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#include <stdint.h>
/* Configuration */
#define WOLFSSL_USER_IO
#define WOLFSSL_GENERAL_ALIGNMENT 4
#define WOLFSSL_SMALL_STACK
#define WOLFSSL_BASE64_ENCODE
#define WOLFSSL_SHA512
#define HAVE_ECC
#define HAVE_AESGCM
#define HAVE_CURVE25519
#define HAVE_HKDF
#define HAVE_HASHDRBG
#define HAVE_CHACHA
#define HAVE_POLY1305
#define HAVE_ONE_TIME_AUTH
#define HAVE_TLS_EXTENSIONS
#define HAVE_SUPPORTED_CURVES
#define HAVE_ERRNO_H
#define HAVE_LWIP_NATIVE
#define FP_LUT 4
#define FP_MAX_BITS 2048 /* 4096 */
#define FP_MAX_BITS_ECC 512
#define ALT_ECC_SIZE
#define USE_FAST_MATH
#define SMALL_SESSION_CACHE
#define CURVED25519_SMALL
#define RSA_LOW_MEM
#define GCM_SMALL
#define ECC_SHAMIR
#define USE_SLOW_SHA2
#define MP_LOW_MEM
#define TFM_TIMING_RESISTANT
//#define TFM_ARM
/* Remove Features */
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_WRITEV
#define NO_MAIN_DRIVER
#define NO_WOLFSSL_MEMORY
#define NO_DEV_RANDOM
#define NO_MD4
#define NO_RABBIT
#define NO_HC128
#define NO_DSA
#define NO_PWDBASED
#define NO_PSK
#define NO_64BIT
#define NO_WOLFSSL_SERVER
#define NO_OLD_TLS
#define ECC_USER_CURVES /* Disables P-112, P-128, P-160, P-192, P-224, P-384, P-521 but leaves P-256 enabled */
#define NO_DES3
#define NO_MD5
#define NO_RC4
#define NO_DH
#define NO_SHA
/* Benchmark / Testing */
#define BENCH_EMBEDDED
#define USE_CERT_BUFFERS_1024
/* Custom functions */
extern uint32_t rand_gen(void);
#define CUSTOM_RAND_GENERATE rand_gen
#define CUSTOM_RAND_TYPE uint32_t
extern double current_time(int reset);
#define WOLFSSL_USER_CURRTIME
/* Debugging - Optional */
#if 0
#define fprintf(file, format, ...) printf(format, ##__VA_ARGS__)
#define DEBUG_WOLFSSL
#endif

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&lt;TargetConfig&gt;
&lt;Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC1837" property_count="5" version="70200"/&gt;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1837" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC1837" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC1837&lt;/name&gt;
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&lt;prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;
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&lt;peripheralInstance derived_from="GPDMA" determined="infoFile" id="GPDMA" location="0x40002000"/&gt;
&lt;peripheralInstance derived_from="SPIFI" determined="infoFile" id="SPIFI" location="0x40003000"/&gt;
&lt;peripheralInstance derived_from="SDMMC" determined="infoFile" id="SDMMC" location="0x40004000"/&gt;
&lt;peripheralInstance derived_from="EMC" determined="infoFile" id="EMC" location="0x40005000"/&gt;
&lt;peripheralInstance derived_from="USB0" determined="infoFile" id="USB0" location="0x40006000"/&gt;
&lt;peripheralInstance derived_from="USB1" determined="infoFile" id="USB1" location="0x40007000"/&gt;
&lt;peripheralInstance derived_from="EEPROM" determined="infoFile" id="EEPROM" location="0x4000e000"/&gt;
&lt;peripheralInstance derived_from="ETHERNET" determined="infoFile" id="ETHERNET" location="0x40010000"/&gt;
&lt;peripheralInstance derived_from="ATIMER" determined="infoFile" id="ATIMER" location="0x40040000"/&gt;
&lt;peripheralInstance derived_from="REGFILE" determined="infoFile" id="REGFILE" location="0x40041000"/&gt;
&lt;peripheralInstance derived_from="PMC" determined="infoFile" id="PMC" location="0x40042000"/&gt;
&lt;peripheralInstance derived_from="CREG" determined="infoFile" id="CREG" location="0x40043000"/&gt;
&lt;peripheralInstance derived_from="EVENTROUTER" determined="infoFile" id="EVENTROUTER" location="0x40044000"/&gt;
&lt;peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40046000"/&gt;
&lt;peripheralInstance derived_from="CGU" determined="infoFile" id="CGU" location="0x40050000"/&gt;
&lt;peripheralInstance derived_from="CCU1" determined="infoFile" id="CCU1" location="0x40051000"/&gt;
&lt;peripheralInstance derived_from="CCU2" determined="infoFile" id="CCU2" location="0x40052000"/&gt;
&lt;peripheralInstance derived_from="RGU" determined="infoFile" id="RGU" location="0x40053000"/&gt;
&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40080000"/&gt;
&lt;peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40081000"/&gt;
&lt;peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x400c1000"/&gt;
&lt;peripheralInstance derived_from="USART3" determined="infoFile" id="USART3" location="0x400c2000"/&gt;
&lt;peripheralInstance derived_from="UART1" determined="infoFile" id="UART1" location="0x40082000"/&gt;
&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40083000"/&gt;
&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x400c5000"/&gt;
&lt;peripheralInstance derived_from="TIMER0" determined="infoFile" id="TIMER0" location="0x40084000"/&gt;
&lt;peripheralInstance derived_from="TIMER1" determined="infoFile" id="TIMER1" location="0x40085000"/&gt;
&lt;peripheralInstance derived_from="TIMER2" determined="infoFile" id="TIMER2" location="0x400c3000"/&gt;
&lt;peripheralInstance derived_from="TIMER3" determined="infoFile" id="TIMER3" location="0x400c4000"/&gt;
&lt;peripheralInstance derived_from="SCU" determined="infoFile" id="SCU" location="0x40086000"/&gt;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x40087000"/&gt;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x40088000"/&gt;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40089000"/&gt;
&lt;peripheralInstance derived_from="MCPWM" determined="infoFile" id="MCPWM" location="0x400a0000"/&gt;
&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x400a1000"/&gt;
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&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x400f4000"/&gt;
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&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;
&lt;family&gt;Cortex-M&lt;/family&gt;
&lt;/processor&gt;
&lt;link href="nxp_lpc18xx_peripheral.xme" show="embed" type="simple"/&gt;
&lt;/info&gt;
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29
IDE/LPCXPRESSO/wolf_example/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>wolf_example</name>
<comment></comment>
<projects>
<project>lpc_chip_18xx</project>
<project>lpc_board_nxp_lpcxpresso_1837</project>
<project>wolfssl</project>
</projects>
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<arguments>
</arguments>
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</natures>
</projectDescription>

7
IDE/LPCXPRESSO/wolf_example/readme.txt Normal file
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wolfSSL example
Target board LPC43S37 Xpresso board
The board communicates to the PC terminal through UART0 at 115200.
This example builds the wolfSSL library, test and benchmark examples.
Use 't' to launch the WolfSSL Test
Use 'b' to launch the WolfSSL Benchmark

352
IDE/LPCXPRESSO/wolf_example/src/lpc_18xx_startup.c Normal file
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/* lpc_18xx_startup.c
*
* Copyright (C) 2006-2015 wolfSSL Inc.
*
* This file is part of wolfSSL. (formerly known as CyaSSL)
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "board.h"
#include <stdint.h>
#include <stdio.h>
/* Top of stack location */
extern void _vStackTop(void);
/* Memory locations */
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
/* Copy memory: src=Source, dst_beg=Destination Begin, dst_end=Destination End */
__attribute__ ((section(".after_vectors")))
void memcpy32(uint32_t* src, uint32_t* dst_beg, uint32_t len)
{
unsigned int i;
for (i = 0; i < len; i += sizeof(uint32_t)) {
*dst_beg++ = *src++;
}
}
/* Zero address in range */
__attribute__ ((section(".after_vectors")))
void meminit32(uint32_t* start, uint32_t len)
{
unsigned int i;
for (i = 0; i < len; i += sizeof(uint32_t)) {
*start++ = 0;
}
}
/* Reset Entry Point */
void ResetISR(void)
{
unsigned int irqPendLoop;
unsigned int *SectionTableAddr;
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
/* Chip cleanup/reset */
__asm volatile ("cpsid i"); /* Disable interrupts */
/* Write to LPC_RGU->RESET_CTRL0 */
*(RESET_CONTROL+0) = 0x10DF0000;
/* GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
* USB1_RST|USB0_RST|LCD_RST */
/* Write to LPC_RGU->RESET_CTRL1 */
*(RESET_CONTROL+1) = 0x00DFF7FF;
/* CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
* I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
* DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
* RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST */
/* Clear all pending interrupts in the NVIC */
for (irqPendLoop = 0; irqPendLoop < 8; irqPendLoop++) {
*(NVIC_ICPR + irqPendLoop) = 0xFFFFFFFF;
}
__asm volatile ("cpsie i"); /* Re-enable interrupts */
/* Init sections */
SectionTableAddr = &__data_section_table;
/* Copy the data sections from flash to SRAM */
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
memcpy32((uint32_t*)LoadAddr, (uint32_t*)ExeAddr, SectionLen);
}
/* Zero fill the bss segment */
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
meminit32((uint32_t*)ExeAddr, SectionLen);
}
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
/* Board specific SystemInit */
Board_SystemInit();
/* Start main */
#if defined (__REDLIB__)
/* Call the Redlib library, which in turn calls main() */
extern void __main(void);
__main() ;
#else
extern void main(void);
main();
#endif
/* Application has ended, so busy wait */
while(1) {};
}
/* Vector Exception/Interrupt Handlers */
__attribute__ ((section(".after_vectors")))
static void Default_Handler(void)
{
/* Loop forever */
while(1);
}
void HardFault_HandlerC( uint32_t *hardfault_args )
{
/* These are volatile to try and prevent the compiler/linker optimizing them
away as the variables never actually get used. If the debugger won't show the
values of the variables, make them global my moving their declaration outside
of this function. */
volatile uint32_t stacked_r0;
volatile uint32_t stacked_r1;
volatile uint32_t stacked_r2;
volatile uint32_t stacked_r3;
volatile uint32_t stacked_r12;
volatile uint32_t stacked_lr;
volatile uint32_t stacked_pc;
volatile uint32_t stacked_psr;
volatile uint32_t _CFSR;
volatile uint32_t _HFSR;
volatile uint32_t _DFSR;
volatile uint32_t _AFSR;
volatile uint32_t _BFAR;
volatile uint32_t _MMAR;
stacked_r0 = ((uint32_t)hardfault_args[0]);
stacked_r1 = ((uint32_t)hardfault_args[1]);
stacked_r2 = ((uint32_t)hardfault_args[2]);
stacked_r3 = ((uint32_t)hardfault_args[3]);
stacked_r12 = ((uint32_t)hardfault_args[4]);
stacked_lr = ((uint32_t)hardfault_args[5]);
stacked_pc = ((uint32_t)hardfault_args[6]);
stacked_psr = ((uint32_t)hardfault_args[7]);
/* Configurable Fault Status Register */
/* Consists of MMSR, BFSR and UFSR */
_CFSR = (*((volatile uint32_t *)(0xE000ED28)));
/* Hard Fault Status Register */
_HFSR = (*((volatile uint32_t *)(0xE000ED2C)));
/* Debug Fault Status Register */
_DFSR = (*((volatile uint32_t *)(0xE000ED30)));
/* Auxiliary Fault Status Register */
_AFSR = (*((volatile uint32_t *)(0xE000ED3C)));
/* Read the Fault Address Registers. These may not contain valid values. */
/* Check BFARVALID/MMARVALID to see if they are valid values */
/* MemManage Fault Address Register */
_MMAR = (*((volatile uint32_t *)(0xE000ED34)));
/* Bus Fault Address Register */
_BFAR = (*((volatile uint32_t *)(0xE000ED38)));
printf ("\n\nHard fault handler (all numbers in hex):\n");
printf ("R0 = %x\n", stacked_r0);
printf ("R1 = %x\n", stacked_r1);
printf ("R2 = %x\n", stacked_r2);
printf ("R3 = %x\n", stacked_r3);
printf ("R12 = %x\n", stacked_r12);
printf ("LR [R14] = %x subroutine call return address\n", stacked_lr);
printf ("PC [R15] = %x program counter\n", stacked_pc);
printf ("PSR = %x\n", stacked_psr);
printf ("CFSR = %x\n", _CFSR);
printf ("HFSR = %x\n", _HFSR);
printf ("DFSR = %x\n", _DFSR);
printf ("AFSR = %x\n", _AFSR);
printf ("MMAR = %x\n", _MMAR);
printf ("BFAR = %x\n", _BFAR);
/* Break into the debugger */
__asm("BKPT #0\n");
}
__attribute__( ( naked, section(".after_vectors") ) )
void HardFault_Handler(void)
{
__asm volatile
(
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
" ldr r1, [r0, #24] \n"
" ldr r2, handler2_address_const \n"
" bx r2 \n"
" handler2_address_const: .word HardFault_HandlerC \n"
);
}
/* Forward declaration of IRQ handlers */
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
void NMI_Handler(void) ALIAS(Default_Handler);
void MemManage_Handler(void) ALIAS(Default_Handler);
void BusFault_Handler(void) ALIAS(Default_Handler);
void UsageFault_Handler(void) ALIAS(Default_Handler);
void SVC_Handler(void) ALIAS(Default_Handler);
void DebugMon_Handler(void) ALIAS(Default_Handler);
void PendSV_Handler(void) ALIAS(Default_Handler);
void SysTick_Handler(void) ALIAS(Default_Handler);
void DAC_IRQHandler(void) ALIAS(Default_Handler);
void DMA_IRQHandler(void) ALIAS(Default_Handler);
void FLASHEEPROM_IRQHandler(void) ALIAS(Default_Handler);
void ETH_IRQHandler(void) ALIAS(Default_Handler);
void SDIO_IRQHandler(void) ALIAS(Default_Handler);
void LCD_IRQHandler(void) ALIAS(Default_Handler);
void USB0_IRQHandler(void) ALIAS(Default_Handler);
void USB1_IRQHandler(void) ALIAS(Default_Handler);
void SCT_IRQHandler(void) ALIAS(Default_Handler);
void RIT_IRQHandler(void) ALIAS(Default_Handler);
void TIMER0_IRQHandler(void) ALIAS(Default_Handler);
void TIMER1_IRQHandler(void) ALIAS(Default_Handler);
void TIMER2_IRQHandler(void) ALIAS(Default_Handler);
void TIMER3_IRQHandler(void) ALIAS(Default_Handler);
void MCPWM_IRQHandler(void) ALIAS(Default_Handler);
void ADC0_IRQHandler(void) ALIAS(Default_Handler);
void I2C0_IRQHandler(void) ALIAS(Default_Handler);
void I2C1_IRQHandler(void) ALIAS(Default_Handler);
void ADC1_IRQHandler(void) ALIAS(Default_Handler);
void SSP0_IRQHandler(void) ALIAS(Default_Handler);
void SSP1_IRQHandler(void) ALIAS(Default_Handler);
void UART0_IRQHandler(void) ALIAS(Default_Handler);
void UART1_IRQHandler(void) ALIAS(Default_Handler);
void UART2_IRQHandler(void) ALIAS(Default_Handler);
void UART3_IRQHandler(void) ALIAS(Default_Handler);
void I2S0_IRQHandler(void) ALIAS(Default_Handler);
void I2S1_IRQHandler(void) ALIAS(Default_Handler);
void SPIFI_IRQHandler(void) ALIAS(Default_Handler);
void SGPIO_IRQHandler(void) ALIAS(Default_Handler);
void GPIO0_IRQHandler(void) ALIAS(Default_Handler);
void GPIO1_IRQHandler(void) ALIAS(Default_Handler);
void GPIO2_IRQHandler(void) ALIAS(Default_Handler);
void GPIO3_IRQHandler(void) ALIAS(Default_Handler);
void GPIO4_IRQHandler(void) ALIAS(Default_Handler);
void GPIO5_IRQHandler(void) ALIAS(Default_Handler);
void GPIO6_IRQHandler(void) ALIAS(Default_Handler);
void GPIO7_IRQHandler(void) ALIAS(Default_Handler);
void GINT0_IRQHandler(void) ALIAS(Default_Handler);
void GINT1_IRQHandler(void) ALIAS(Default_Handler);
void EVRT_IRQHandler(void) ALIAS(Default_Handler);
void CAN1_IRQHandler(void) ALIAS(Default_Handler);
void ATIMER_IRQHandler(void) ALIAS(Default_Handler);
void RTC_IRQHandler(void) ALIAS(Default_Handler);
void WDT_IRQHandler(void) ALIAS(Default_Handler);
void CAN0_IRQHandler(void) ALIAS(Default_Handler);
void QEI_IRQHandler(void) ALIAS(Default_Handler);
/* Vectors */
extern void (* const g_pfnVectors[])(void);
__attribute__ ((used,section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC18
DAC_IRQHandler, // 16
0, // 17
DMA_IRQHandler, // 18
0, // 19
FLASHEEPROM_IRQHandler, // 20
ETH_IRQHandler, // 21
SDIO_IRQHandler, // 22
LCD_IRQHandler, // 23
USB0_IRQHandler, // 24
USB1_IRQHandler, // 25
SCT_IRQHandler, // 26
RIT_IRQHandler, // 27
TIMER0_IRQHandler, // 28
TIMER1_IRQHandler, // 29
TIMER2_IRQHandler, // 30
TIMER3_IRQHandler, // 31
MCPWM_IRQHandler, // 32
ADC0_IRQHandler, // 33
I2C0_IRQHandler, // 34
I2C1_IRQHandler, // 35
0, // 36
ADC1_IRQHandler, // 37
SSP0_IRQHandler, // 38
SSP1_IRQHandler, // 39
UART0_IRQHandler, // 40
UART1_IRQHandler, // 41
UART2_IRQHandler, // 42
UART3_IRQHandler, // 43
I2S0_IRQHandler, // 44
I2S1_IRQHandler, // 45
SPIFI_IRQHandler, // 46
SGPIO_IRQHandler, // 47
GPIO0_IRQHandler, // 48
GPIO1_IRQHandler, // 49
GPIO2_IRQHandler, // 50
GPIO3_IRQHandler, // 51
GPIO4_IRQHandler, // 52
GPIO5_IRQHandler, // 53
GPIO6_IRQHandler, // 54
GPIO7_IRQHandler, // 55
GINT0_IRQHandler, // 56
GINT1_IRQHandler, // 57
EVRT_IRQHandler, // 58
CAN1_IRQHandler, // 59
0, // 60
0, // 61
ATIMER_IRQHandler, // 62
RTC_IRQHandler, // 63
0, // 64
WDT_IRQHandler, // 65
0, // 66
CAN0_IRQHandler, // 67
QEI_IRQHandler, // 68
};

95
IDE/LPCXPRESSO/wolf_example/src/wolfssl_example.c Normal file
View File

@ -0,0 +1,95 @@
#include "board.h"
#include <string.h>
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include <wolfssl/wolfcrypt/settings.h>
#include <wolfssl/ssl.h>
#include <wolfcrypt/test/test.h>
#include <wolfcrypt/benchmark/benchmark.h>
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* UART definitions */
#define LPC_UART LPC_USART0
#define UARTx_IRQn USART0_IRQn
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
typedef struct func_args {
int argc;
char** argv;
int return_code;
} func_args;
const char menu1[] = "\r\n"
"\tt. WolfSSL Test\r\n"
"\tb. WolfSSL Benchmark\r\n";
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
int main(void)
{
int opt = 0;
uint8_t buffer[1];
func_args args;
SystemCoreClockUpdate();
Board_Init();
Board_UART_Init(LPC_UART);
Chip_UART_Init(LPC_UART);
Chip_UART_SetBaud(LPC_UART, 115200);
Chip_UART_ConfigData(LPC_UART, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT); /* Default 8-N-1 */
Chip_UART_TXEnable(LPC_UART);
Chip_UART_SetupFIFOS(LPC_UART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS |
UART_FCR_TX_RS | UART_FCR_DMAMODE_SEL | UART_FCR_TRG_LEV0));
Chip_UART_IntEnable(LPC_UART, (UART_IER_ABEOINT | UART_IER_ABTOINT));
NVIC_SetPriority(UARTx_IRQn, 1);
NVIC_EnableIRQ(UARTx_IRQn);
Chip_OTP_Init();
while (1) {
DEBUGOUT("\r\n\t\t\t\tMENU\r\n");
DEBUGOUT(menu1);
DEBUGOUT("Please select one of the above options: ");
opt = 0;
while (opt == 0) {
opt = Chip_UART_Read(LPC_UART, buffer, sizeof(buffer));
}
switch (buffer[0]) {
case 't':
memset(&args, 0, sizeof(args));
printf("\nCrypt Test\n");
wolfcrypt_test(&args);
printf("Crypt Test: Return code %d\n", args.return_code);
break;
case 'b':
memset(&args, 0, sizeof(args));
printf("\nBenchmark Test\n");
benchmark_test(&args);
printf("Benchmark Test: Return code %d\n", args.return_code);
break;
// All other cases go here
default: DEBUGOUT("\r\nSelection out of range\r\n"); break;
}
}
}

2
IDE/include.am
View File

@ -7,4 +7,4 @@ include IDE/WIN/include.am
include IDE/WORKBENCH/include.am
include IDE/ROWLEY-CROSSWORKS-ARM/include.am
EXTRA_DIST+= IDE/IAR-EWARM IDE/MDK-ARM IDE/MDK5-ARM IDE/MYSQL
EXTRA_DIST+= IDE/IAR-EWARM IDE/MDK-ARM IDE/MDK5-ARM IDE/MYSQL IDE/LPCXPRESSO