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Fix Shift Amount Register

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The least 5 significant bits is 0x1f, not 0xf. Also, don’t AND the SAR
when shifting; it’s already <32.
This commit is contained in:
Sebastian Schmidt
2020-01-05 13:02:34 +01:00
parent c21f1866e7
commit fb39ee087a
1 changed files with 3 additions and 3 deletions
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6
data/languages/xtensaInstructions.sinc
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@@ -1085,7 +1085,7 @@ macro extract_bit(val, bit, result) {
# SLL - Shift Left Logical, pg. 524.
:sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 {
local sa:1 = 32 - (sar & 0xf);
local sa:1 = 32 - sar;
ar = as << sa;
}
@@ -1156,12 +1156,12 @@ macro extract_bit(val, bit, result) {
# SSL - Set Shift Amount for Left Shift, pg. 538.
:ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 {
sar = 32 - (as:1 & 0xf);
sar = 32 - (as:1 & 0x1f);
}
# SSR - Set Shift Amount for Right Shift, pg. 539.
:ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 {
sar = (as:1 & 0xf);
sar = (as:1 & 0x1f);
}
# SSX - Store Singe Indexed, pg. 540.