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Merge branch 'feature/support_i2s_and_etm_on_h4' into 'master'

Browse Source 
feat(i2s & etm): support i2s and etm on esp32-h4

Closes IDF-12385, IDF-12355, and IDF-13396

See merge request espressif/esp-idf!39698
This commit is contained in:
Kevin (Lao Kaiyao)
2025-07-22 20:27:11 +08:00
parent b37a159603 263a056486
commit 1a242d132c
52 changed files with 2647 additions and 1362 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
components/esp_driver_i2s/CMakeLists.txt
View File

@@ -37,4 +37,5 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${include}
PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
LDFRAGMENTS linker.lf
)

7
components/esp_driver_i2s/Kconfig
View File

@@ -8,6 +8,13 @@ menu "ESP-Driver:I2S Configurations"
Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be
executable when the cache is disabled (e.g. SPI Flash write).
config I2S_CTRL_FUNC_IN_IRAM
bool "Place I2S control functions into IRAM"
default n
help
Place I2S control functions into IRAM,
so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
config I2S_ENABLE_DEBUG_LOG
bool "Enable I2S debug log"
default n

52
components/esp_driver_i2s/i2s_common.c
View File

@@ -47,6 +47,7 @@
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_private/i2s_sync.h"
#include "driver/i2s_common.h"
#include "i2s_private.h"
@@ -574,7 +575,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
}
#if SOC_GDMA_SUPPORTED
static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
static bool i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
{
i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
BaseType_t need_yield1 = 0;
@@ -605,7 +606,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
return need_yield1 | need_yield2 | user_need_yield;
}
static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
static bool i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
{
i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
BaseType_t need_yield1 = 0;
@@ -652,7 +653,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
#else
static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
static void i2s_dma_rx_callback(void *arg)
{
BaseType_t need_yield1 = 0;
BaseType_t need_yield2 = 0;
@@ -690,7 +691,7 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
}
}
static void IRAM_ATTR i2s_dma_tx_callback(void *arg)
static void i2s_dma_tx_callback(void *arg)
{
BaseType_t need_yield1 = 0;
BaseType_t need_yield2 = 0;
@@ -1483,3 +1484,46 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle)
i2s_ll_tx_reset_fifo_sync_counter(tx_handle->controller->hal.dev);
}
#endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle)
{
return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev);
}
void i2s_sync_reset_fifo_sync_diff_count(i2s_chan_handle_t tx_handle)
{
i2s_ll_tx_reset_fifo_sync_diff_counter(tx_handle->controller->hal.dev);
}
esp_err_t i2s_sync_enable_hw_fifo_sync(i2s_chan_handle_t tx_handle, bool enable)
{
if (tx_handle->dir == I2S_DIR_RX) {
return ESP_ERR_NOT_SUPPORTED;
}
i2s_ll_tx_enable_hw_fifo_sync(tx_handle->controller->hal.dev, enable);
return ESP_OK;
}
esp_err_t i2s_sync_config_hw_fifo_sync(i2s_chan_handle_t tx_handle, const i2s_sync_fifo_sync_config_t *config)
{
if (!(tx_handle && config)) {
return ESP_ERR_INVALID_ARG;
}
if (tx_handle->dir == I2S_DIR_RX) {
return ESP_ERR_NOT_SUPPORTED;
}
if (config->sw_high_thresh < config->hw_low_thresh) {
return ESP_ERR_INVALID_ARG;
}
i2s_ll_tx_set_etm_sync_ideal_cnt(tx_handle->controller->hal.dev, config->ideal_cnt);
i2s_ll_tx_set_fifo_sync_diff_conter_sw_threshold(tx_handle->controller->hal.dev, config->sw_high_thresh);
i2s_ll_tx_set_fifo_sync_diff_conter_hw_threshold(tx_handle->controller->hal.dev, config->hw_low_thresh);
i2s_ll_tx_set_hw_fifo_sync_suppl_mode(tx_handle->controller->hal.dev, (uint32_t)config->suppl_mode);
if (config->suppl_mode == I2S_SYNC_SUPPL_MODE_STATIC_DATA) {
i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(tx_handle->controller->hal.dev, config->suppl_data);
}
return ESP_OK;
}
#endif

7
components/esp_driver_i2s/i2s_etm.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -84,6 +84,11 @@ esp_err_t i2s_new_etm_task(i2s_chan_handle_t handle, const i2s_etm_task_config_t
{
ESP_RETURN_ON_FALSE(handle && config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(config->task_type < I2S_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type");
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_FIFO || handle->dir == I2S_DIR_TX,
ESP_ERR_NOT_SUPPORTED, TAG, "rx does not support sync check");
#endif
i2s_etm_task_t *task = heap_caps_calloc(1, sizeof(i2s_etm_task_t), ETM_MEM_ALLOC_CAPS);
ESP_RETURN_ON_FALSE(task, ESP_ERR_NO_MEM, TAG, "no memory for ETM task");

77
components/esp_driver_i2s/include/esp_private/i2s_sync.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,7 @@
#include <stdint.h>
#include "driver/i2s_types.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
@@ -31,6 +32,7 @@ extern "C" {
/**
* @brief Get the counter number of BCLK ticks
* @note The BCLK tick count reflects the real data that have sent on line
* @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered
*
* @param[in] tx_handle The I2S tx channel handle
* @return
@@ -43,6 +45,7 @@ uint32_t i2s_sync_get_bclk_count(i2s_chan_handle_t tx_handle);
* @note The FIFO count reflects how many slots have processed
* Normally, fifo_cnt = slot_bit_width * bclk_cnt
* If fifo_cnt < slot_bit_width * bclk_cnt, that means some data are still stuck in the I2S controller
* @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered
*
* @param[in] tx_handle The I2S tx channel handle
* @return
@@ -66,6 +69,78 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle);
#endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
/**
* @brief I2S hardware FIFO synchronization supplement mode
* @note When the FIFO sync difference count is out of threshold, the hardware will supplement data automatically
* This type is to specify which data will be supplemented
*/
typedef enum {
I2S_SYNC_SUPPL_MODE_LAST_DATA = 0, /*!< Supplement with the last transmitted data */
I2S_SYNC_SUPPL_MODE_STATIC_DATA = 1, /*!< Supplement with static data specified in config */
} i2s_sync_suppl_mode_t;
/**
* @brief I2S hardware FIFO synchronization configuration
* @note This configuration is used for multi I2S port synchronization via ETM
*/
typedef struct {
uint32_t hw_low_thresh; /*!< Lower threshold for FIFO sync difference counter
- If difference count < hw_low_thresh, do nothing
- If difference count >= hw_low_thresh, the hardware will supplement data automatically */
uint32_t sw_high_thresh; /*!< Upper threshold for FIFO sync difference counter
- If difference count <= sw_high_thresh, the hardware supplement data automatically
- If difference count > sw_high_thresh, sync interrupt triggered and
the software is responsible to decide how to handle this severe asynchronization */
uint32_t ideal_cnt; /*!< Ideal count for FIFO sync difference counter, it depends on the ETM sync task interval and the data rate */
i2s_sync_suppl_mode_t suppl_mode; /*!< Data supplement mode when FIFO sync difference is out of threshold */
uint32_t suppl_data; /*!< Static supplement data, only valid when suppl_mode is I2S_SYNC_SUPPL_MODE_STATIC_DATA */
} i2s_sync_fifo_sync_config_t;
/**
* @brief Get the counter number of FIFO sync difference
* @note The FIFO sync difference count reflects the difference between current FIFO count and ideal count
*
* @param[in] tx_handle The I2S tx channel handle
* @return
* - FIFO sync difference count
*/
uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle);
/**
* @brief Reset the FIFO sync difference counter
*
* @param[in] tx_handle The I2S tx channel handle
*/
void i2s_sync_reset_fifo_sync_diff_count(i2s_chan_handle_t tx_handle);
/**
* @brief Enable or disable hardware FIFO synchronization
* @note When enabled, hardware will automatically supplement data when FIFO sync difference is greater than hw_low_thresh
*
* @param[in] tx_handle The I2S tx channel handle
* @param[in] enable true to enable, false to disable
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if called on RX channel
*/
esp_err_t i2s_sync_enable_hw_fifo_sync(i2s_chan_handle_t tx_handle, bool enable);
/**
* @brief Configure hardware FIFO synchronization parameters
* @note This function configures the thresholds and supplement mode for hardware FIFO sync
*
* @param[in] tx_handle The I2S tx channel handle
* @param[in] config Configuration for hardware FIFO synchronization
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if invalid arguments
* - ESP_ERR_NOT_SUPPORTED if called on RX channel
*/
esp_err_t i2s_sync_config_hw_fifo_sync(i2s_chan_handle_t tx_handle, const i2s_sync_fifo_sync_config_t *config);
#endif
#ifdef __cplusplus
}
#endif

17
components/esp_driver_i2s/linker.lf Normal file
View File

@@ -0,0 +1,17 @@
[mapping:i2s_driver]
archive: libesp_driver_i2s.a
entries:
if I2S_ISR_IRAM_SAFE = y:
i2s_common: i2s_dma_rx_callback (noflash)
i2s_common: i2s_dma_tx_callback (noflash)
if I2S_CTRL_FUNC_IN_IRAM = y:
if SOC_I2S_SUPPORTS_TX_SYNC_CNT = y:
i2s_common: i2s_sync_get_bclk_count (noflash)
i2s_common: i2s_sync_get_fifo_count (noflash)
i2s_common: i2s_sync_reset_bclk_count (noflash)
i2s_common: i2s_sync_reset_fifo_count (noflash)
if SOC_I2S_SUPPORTS_TX_FIFO_SYNC = y:
i2s_common: i2s_sync_get_fifo_sync_diff_count (noflash)
i2s_common: i2s_sync_reset_fifo_sync_diff_count (noflash)
i2s_common: i2s_sync_enable_hw_fifo_sync (noflash)
i2s_common: i2s_sync_config_hw_fifo_sync (noflash)

4
components/esp_driver_i2s/test_apps/i2s/README.md
View File

@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |

7
components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt
View File

@@ -1,12 +1,15 @@
set(srcs "test_app_main.c"
"test_i2s.c"
"test_i2s_iram.c"
"test_i2s_sleep.c")
"test_i2s_iram.c")
if(CONFIG_SOC_I2S_SUPPORTS_ETM AND CONFIG_SOC_GPIO_SUPPORT_ETM)
set(srcs ${srcs} "test_i2s_etm.c")
endif()
if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED)
list(APPEND srcs "test_i2s_sleep.c")
endif()
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_pcnt spi_flash
esp_driver_gpio esp_driver_i2s esp_driver_uart esp_psram

1
components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe
View File

@@ -1,5 +1,6 @@
CONFIG_COMPILER_DUMP_RTL_FILES=y
CONFIG_I2S_ISR_IRAM_SAFE=y
CONFIG_I2S_CTRL_FUNC_IN_IRAM=y
CONFIG_COMPILER_OPTIMIZATION_NONE=y
# silent the error check, as the error string are stored in rodata, causing RTL check failure
CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y

4
components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md
View File

@@ -1,3 +1,3 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

1
components/esp_hw_support/include/esp_private/etm_interface.h
View File

@@ -29,6 +29,7 @@ typedef enum {
ETM_TRIG_PERIPH_TSENS, /*!< ETM trigger source: Temperature Sensor */
ETM_TRIG_PERIPH_I2S, /*!< ETM trigger source: I2S */
ETM_TRIG_PERIPH_LP_CORE, /*!< ETM trigger source: Low-Power Core */
ETM_TRIG_PERIPH_MODEM, /*!< ETM trigger source: Modem */
} etm_trigger_peripheral_t;
/**

86
components/esp_hw_support/modem/include/modem/modem_etm.h Normal file
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@@ -0,0 +1,86 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Modem ETM event type
*
* @note The event type is used to identify the event type.
*/
typedef enum {
MODEM_ETM_EVENT_G0 = 0, /*!< Modem ETM event group 0 */
MODEM_ETM_EVENT_G1 = 1, /*!< Modem ETM event group 1 */
MODEM_ETM_EVENT_G2 = 2, /*!< Modem ETM event group 2 */
MODEM_ETM_EVENT_G3 = 3, /*!< Modem ETM event group 3 */
MODEM_ETM_EVENT_MAX,
} modem_etm_event_type_t;
/**
* @brief Modem ETM task type
*
* @note The task type is used to identify the task type.
*/
typedef enum {
MODEM_ETM_TASK_G0 = 0, /*!< Modem ETM task group 0 */
MODEM_ETM_TASK_G1 = 1, /*!< Modem ETM task group 1 */
MODEM_ETM_TASK_G2 = 2, /*!< Modem ETM task group 2 */
MODEM_ETM_TASK_G3 = 3, /*!< Modem ETM task group 3 */
MODEM_ETM_TASK_MAX,
} modem_etm_task_type_t;
/**
* @brief Modem ETM event configuration
*
* @note The event configuration is used to configure the event.
*/
typedef struct {
modem_etm_event_type_t event_type; /*!< Modem ETM event type */
} modem_etm_event_config_t;
/**
* @brief Modem ETM task configuration
*
* @note The task configuration is used to configure the task.
*/
typedef struct {
modem_etm_task_type_t task_type; /*!< Modem ETM task type */
} modem_etm_task_config_t;
/**
* @brief Create a new modem ETM event
*
* @param config The modem ETM event configuration
* @param out_event The output modem ETM event handle
* @return
* - ESP_OK: Success
* - ESP_ERR_INVALID_ARG: Invalid argument
* - ESP_ERR_NO_MEM: No memory
*/
esp_err_t modem_new_etm_event(const modem_etm_event_config_t *config, esp_etm_event_handle_t *out_event);
/**
* @brief Create a new modem ETM task
*
* @param config The modem ETM task configuration
* @param out_task The output modem ETM task handle
* @return
* - ESP_OK: Success
* - ESP_ERR_INVALID_ARG: Invalid argument
* - ESP_ERR_NO_MEM: No memory
*/
esp_err_t modem_new_etm_task(const modem_etm_task_config_t *config, esp_etm_task_handle_t *out_task);
#ifdef __cplusplus
}
#endif

69
components/esp_hw_support/modem/modem_etm.c Normal file
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@@ -0,0 +1,69 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include <sys/cdefs.h>
#include "sdkconfig.h"
#include "esp_log.h"
#include "esp_check.h"
#include "esp_heap_caps.h"
#include "modem/modem_etm.h"
#include "hal/modem_ll.h"
#include "esp_private/etm_interface.h"
#define ETM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
static const char *TAG = "modem-etm";
static esp_err_t s_modem_del_etm_event(esp_etm_event_t *event)
{
free(event);
return ESP_OK;
}
static esp_err_t s_modem_del_etm_task(esp_etm_task_t *task)
{
free(task);
return ESP_OK;
}
esp_err_t modem_new_etm_event(const modem_etm_event_config_t *config, esp_etm_event_handle_t *out_event)
{
ESP_RETURN_ON_FALSE(config && out_event, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(config->event_type < MODEM_ETM_EVENT_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid event type");
esp_etm_event_t *event = heap_caps_calloc(1, sizeof(esp_etm_event_t), ETM_MEM_ALLOC_CAPS);
ESP_RETURN_ON_FALSE(event, ESP_ERR_NO_MEM, TAG, "no memory for ETM event");
// Get the event id from the modem ETM event table
uint32_t event_id = MODEM_LL_ETM_EVENT_TABLE((uint32_t)config->event_type);
// fill the ETM event object
event->event_id = event_id;
event->trig_periph = ETM_TRIG_PERIPH_MODEM;
event->del = s_modem_del_etm_event;
*out_event = event;
return ESP_OK;
}
esp_err_t modem_new_etm_task(const modem_etm_task_config_t *config, esp_etm_task_handle_t *out_task)
{
ESP_RETURN_ON_FALSE(config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(config->task_type < MODEM_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type");
esp_etm_task_t *task = heap_caps_calloc(1, sizeof(esp_etm_task_t), ETM_MEM_ALLOC_CAPS);
ESP_RETURN_ON_FALSE(task, ESP_ERR_NO_MEM, TAG, "no memory for ETM task");
// Get the task id from the modem ETM task table
uint32_t task_id = MODEM_LL_ETM_TASK_TABLE((uint32_t)config->task_type);
// fill the ETM task object
task->task_id = task_id;
task->trig_periph = ETM_TRIG_PERIPH_MODEM;
task->del = s_modem_del_etm_task;
*out_task = task;
return ESP_OK;
}

119
components/hal/esp32h4/include/hal/etm_ll.h Normal file
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@@ -0,0 +1,119 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task
/**
* @brief Enable the clock for ETM register
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Reset the ETM register
*
* @param group_id Group ID
*/
static inline void etm_ll_reset_register(int group_id)
{
(void)group_id;
PCR.etm_conf.etm_rst_en = 1;
PCR.etm_conf.etm_rst_en = 0;
}
/**
* @brief Enable ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
*/
static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
hw->etm_ch_ena_ad0_set.val = 1 << chan;
} else {
hw->etm_ch_ena_ad1_set.val = 1 << (chan - 32);
}
}
/**
* @brief Disable ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
*/
static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
hw->etm_ch_ena_ad0_clr.val = 1 << chan;
} else {
hw->etm_ch_ena_ad1_clr.val = 1 << (chan - 32);
}
}
/**
* @brief Check whether the ETM channel is enabled or not
*
* @param hw ETM register base address
* @param chan Channel ID
* @return true if the channel is enabled, false otherwise
*/
static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
return hw->etm_ch_ena_ad0.val & (1 << chan);
} else {
return hw->etm_ch_ena_ad1.val & (1 << (chan - 32));
}
}
/**
* @brief Set the input event for the ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
* @param event Event ID
*/
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, etm_chn_evt_id, event);
}
/**
* @brief Set the output task for the ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
* @param task Task ID
*/
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, etm_chn_task_id, task);
}
#ifdef __cplusplus
}
#endif

136
components/hal/esp32h4/include/hal/gpio_etm_ll.h Normal file
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@@ -0,0 +1,136 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/gpio_ext_struct.h"
#include "soc/soc_etm_source.h"
#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch))
#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch))
#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch))
#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8
#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set which GPIO to be bound to the event channel
*
* @note Different channels can be bound to one GPIO
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @param gpio_num GPIO number
*/
static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
{
dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel = gpio_num;
}
/**
* @brief Whether to enable the event channel
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
{
dev->etm_event_chn_cfg[chan].ext_etm_chn_event_en = enable;
}
/**
* @brief Get which GPIO is bound to the event channel
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @return GPIO number
*/
static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
{
return dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel;
}
/**
* @brief Set which GPIO to be bound to the task channel
*
* @note One channel can be bound to multiple different GPIOs
*
* @param dev Register base address
* @param chan GPIO ETM Task channel number
* @param gpio_num GPIO number
*/
static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x07 << (g_idx * 6));
reg_val |= ((chan & 0x07) << (g_idx * 6));
dev->etm_task_pn_cfg[g_p].val = reg_val;
}
/**
* @brief Whether to enable the GPIO to be managed by the task channel
*
* @param dev Register base address
* @param gpio_num GPIO number
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x01 << (g_idx * 6 + 5));
reg_val |= ((enable & 0x01) << (g_idx * 6 + 5));
dev->etm_task_pn_cfg[g_p].val = reg_val;
}
/**
* @brief Check whether a GPIO has been enabled and managed by a task channel
*
* @param dev Register base address
* @param gpio_num GPIO number
* @return True if enabled, false otherwise
*/
static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5));
}
/**
* @brief Get the channel number that the GPIO is bound to
*
* @param dev Register base address
* @param gpio_num GPIO number
* @return GPIO ETM Task channel number
*/
static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07;
}
#ifdef __cplusplus
}
#endif

1456
components/hal/esp32h4/include/hal/i2s_ll.h Normal file
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File diff suppressed because it is too large Load Diff

83
components/hal/esp32h4/include/hal/modem_etm_ll.h Normal file
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@@ -0,0 +1,83 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "hal/assert.h"
#include "soc/soc_etm_struct.h"
#include "soc/soc_etm_reg.h"
#include "soc/soc_etm_source.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_LL_ETM_EVENT_TABLE(event_type) \
(uint32_t[4]){ \
[0] = MODEM_EVT_G0, \
[1] = MODEM_EVT_G1, \
[2] = MODEM_EVT_G2, \
[3] = MODEM_EVT_G3, \
}[event_type]
#define MODEM_LL_ETM_TASK_TABLE(task_type) \
(uint32_t[4]){ \
[0] = MODEM_TASK_G0, \
[1] = MODEM_TASK_G1, \
[2] = MODEM_TASK_G2, \
[3] = MODEM_TASK_G3, \
}[task_type]
static inline bool modem_etm_ll_get_group_event_status(int group_id)
{
switch (group_id) {
case 0:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g0_st;
case 1:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g1_st;
case 2:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g2_st;
case 3:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g3_st;
default:
HAL_ASSERT(false);
}
return false;
}
static inline bool modem_etm_ll_get_group_task_status(int group_id)
{
switch (group_id) {
case 0:
return SOC_ETM.etm_task_st5.etm_modem_task_g0_st;
case 1:
return SOC_ETM.etm_task_st5.etm_modem_task_g1_st;
case 2:
return SOC_ETM.etm_task_st5.etm_modem_task_g2_st;
case 3:
return SOC_ETM.etm_task_st5.etm_modem_task_g3_st;
default:
HAL_ASSERT(false);
}
return false;
}
static inline void modem_etm_ll_clear_group_event_status(int group_id)
{
SOC_ETM.etm_evt_st6_clr.val = SOC_ETM_MODEM_EVT_G0_ST_CLR << group_id;
}
static inline void modem_etm_ll_clear_group_task_status(int group_id)
{
SOC_ETM.etm_task_st5_clr.val = SOC_ETM_MODEM_TASK_G0_ST_CLR << group_id;
}
#ifdef __cplusplus
}
#endif

3
components/hal/include/hal/i2s_types.h
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@@ -233,6 +233,9 @@ typedef enum {
typedef enum {
I2S_ETM_TASK_START, /*!< Start the I2S channel */
I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */
#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
I2S_ETM_TASK_SYNC_FIFO, /*!< Check the I2S TX channel sync status */
#endif
I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */
} i2s_etm_task_type_t;

17
components/soc/esp32/register/soc/i2s_reg.h
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@@ -1,15 +1,17 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
#ifdef __cplusplus
extern "C" {
#endif
#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008)
/* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */
@@ -1511,7 +1513,6 @@
#define I2S_I2SDATE_V 0xFFFFFFFF
#define I2S_I2SDATE_S 0
#endif /*_SOC_I2S_REG_H_ */
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c3/include/soc/soc.h
View File

@@ -20,7 +20,6 @@
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI

14
components/soc/esp32c3/register/soc/i2s_reg.h
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@@ -1,16 +1,18 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/soc.h"
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
@@ -1037,7 +1039,3 @@ T12_5[2:0]).*/
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */

1
components/soc/esp32c5/include/soc/soc.h
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@@ -18,7 +18,6 @@
#define REG_UHCI_BASE(i) (DR_REG_UHCI_BASE) // only one UHCI on C5
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5

2
components/soc/esp32c5/register/soc/i2s_reg.h
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@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32c6/include/soc/soc.h
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@@ -20,7 +20,6 @@
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6

2
components/soc/esp32c6/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32c61/include/soc/soc.h
View File

@@ -19,7 +19,6 @@
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61

2
components/soc/esp32c61/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32h2/include/soc/soc.h
View File

@@ -20,7 +20,6 @@
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI

2
components/soc/esp32h2/register/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

44
components/soc/esp32h4/etm_periph.c Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};

77
components/soc/esp32h4/i2s_periph.c Normal file
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@@ -0,0 +1,77 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
.m_tx_bck_sig = I2SO_BCK_OUT_IDX,
.m_rx_bck_sig = I2SI_BCK_OUT_IDX,
.m_tx_ws_sig = I2SO_WS_OUT_IDX,
.m_rx_ws_sig = I2SI_WS_OUT_IDX,
.s_tx_bck_sig = I2SO_BCK_IN_IDX,
.s_rx_bck_sig = I2SI_BCK_IN_IDX,
.s_tx_ws_sig = I2SO_WS_IN_IDX,
.s_rx_ws_sig = I2SI_WS_IN_IDX,
.data_out_sig = I2SO_SD_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S_INTR_SOURCE,
}
};
/**
* I2S Registers to be saved during sleep retention
* - I2S_INT_ENA_REG
* - I2S_RX_CONF_REG
* - I2S_TX_CONF_REG
* - I2S_RX_CONF1_REG
* - I2S_TX_CONF1_REG
* - I2S_TX_PCM2PDM_CONF_REG
* - I2S_TX_PCM2PDM_CONF1_REG
* - I2S_RX_TDM_CTRL_REG
* - I2S_TX_TDM_CTRL_REG
* - I2S_RXEOF_NUM_REG
* - I2S_ETM_CONF_REG
* - I2S_IDEAL_CNT_REG
* - I2S_SYNC_SW_THRES_REG
* - I2S_SYNC_HW_THRES_REG
* - I2S_HW_SYNC_CONF_REG
* - I2S_HW_SYNC_DATA_REG
*/
#define I2S_RETENTION_REGS_CNT 16
#define I2S_RETENTION_REGS_BASE(i) (I2S_INT_ENA_REG(i))
static const uint32_t i2s_regs_map[4] = {0xf191b079, 0x0, 0x0, 0x0};
#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) { \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
REGDMA_I2S_LINK(0x00), \
I2S_RETENTION_REGS_BASE(i2s_port), \
I2S_RETENTION_REGS_BASE(i2s_port), \
I2S_RETENTION_REGS_CNT, 0, 0, \
i2s_regs_map[0], i2s_regs_map[1], \
i2s_regs_map[2], i2s_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2) }, \
};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
.array_size = ARRAY_SIZE(i2s0_regs_retention)
},
};

116
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -19,6 +19,10 @@ config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_ETM_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -31,6 +35,10 @@ config SOC_EFUSE_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -207,6 +215,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 5
config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
@@ -215,6 +227,18 @@ config SOC_AHB_GDMA_SUPPORT_PSRAM
bool
default y
config SOC_ETM_GROUPS
int
default 1
config SOC_ETM_CHANNELS_PER_GROUP
int
default 50
config SOC_ETM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_GPIO_PORT
int
default 1
@@ -231,6 +255,18 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 39
config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_ETM_EVENTS_PER_GROUP
int
default 8
config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
@@ -299,6 +335,78 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F96M
bool
default y
config SOC_I2S_SUPPORTS_PLL_F64M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PCM2PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX
bool
default y
config SOC_I2S_SUPPORTS_TX_SYNC_CNT
bool
default y
config SOC_I2S_SUPPORTS_TX_FIFO_SYNC
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
config SOC_I2S_PDM_MAX_RX_LINES
int
default 1
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
@@ -391,6 +499,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_SYSTIMER_SUPPORT_ETM
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
@@ -399,6 +511,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_TIMER_SUPPORT_SLEEP_RETENTION
bool
default y

18
components/soc/esp32h4/include/soc/clk_tree_defs.h
View File

@@ -299,6 +299,24 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_i2c_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
// I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
} soc_periph_i2s_clk_src_t;
#ifdef __cplusplus
}
#endif

48
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -41,7 +41,7 @@
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12338
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12352
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12355
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
@@ -54,7 +54,7 @@
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32H4] IDF-12385
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12402
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12348
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366
@@ -191,13 +191,14 @@
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 5
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
/*-------------------------- ETM CAPS --------------------------------------*/
// #define SOC_ETM_GROUPS 1U // Number of ETM groups
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
#define SOC_ETM_GROUPS 1U // Number of ETM groups
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-H4 has 1 GPIO peripheral
@@ -212,9 +213,9 @@
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 // TODO: [ESP32H4] IDF-12391
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1 // TODO: [ESP32H4] IDF-12394
// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8
#define SOC_GPIO_SUPPORT_ETM 1
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has the full LP IO subsystem
// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
@@ -268,15 +269,25 @@
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// #define SOC_I2S_NUM (1U)
// #define SOC_I2S_HW_VERSION_2 (1)
// #define SOC_I2S_SUPPORTS_XTAL (1)
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
// #define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F96M (1)
#define SOC_I2S_SUPPORTS_PLL_F64M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
#define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter
#define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data
#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
#define SOC_I2S_SUPPORTS_TX_FIFO_SYNC (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
@@ -423,7 +434,7 @@
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
@@ -431,6 +442,7 @@
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
// #define SOC_TIMER_SUPPORT_ETM (1) // TODO: [ESP32H4] IDF-12355
#define SOC_TIMER_SUPPORT_ETM (1)
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/

1
components/soc/esp32h4/ld/esp32h4.peripherals.ld
View File

@@ -43,6 +43,7 @@ PROVIDE ( TIMERG1 = 0x60091000 );
PROVIDE ( IO_MUX = 0x60092000 );
PROVIDE ( GPIO = 0x60093000 );
PROVIDE ( GPIO_EXT = 0x60093E00 );
PROVIDE ( GPIO_ETM = 0x60093F18 );
PROVIDE ( PCR = 0x60094000 );
PROVIDE ( SPIMEM0 = 0x60098000 );
PROVIDE ( SPIMEM1 = 0x60099000 );

622
components/soc/esp32h4/register/soc/gpio_ext_struct.h
View File

@@ -117,7 +117,7 @@ typedef union {
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of ext_etm_task_p0_cfg register
/** Type of ext_etm_task_pn_cfg register
* GPIO selection register 0 for ETM
*/
typedef union {
@@ -200,602 +200,7 @@ typedef union {
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p0_cfg_reg_t;
/** Type of ext_etm_task_p1_cfg register
* GPIO selection register 1 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO5.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio5_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO5 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio5_en:1;
/** ext_etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO6.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio6_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO6 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio6_en:1;
/** ext_etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO7.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio7_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO7 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio7_en:1;
/** ext_etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO8.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio8_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO8 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio8_en:1;
/** ext_etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO9.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio9_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO9 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio9_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p1_cfg_reg_t;
/** Type of ext_etm_task_p2_cfg register
* GPIO selection register 2 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO10.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio10_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO10 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio10_en:1;
/** ext_etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO11.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio11_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO11 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio11_en:1;
/** ext_etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO12.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio12_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO12 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio12_en:1;
/** ext_etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO13.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio13_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO13 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio13_en:1;
/** ext_etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO14.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio14_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO14 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio14_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p2_cfg_reg_t;
/** Type of ext_etm_task_p3_cfg register
* GPIO selection register 3 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO15.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio15_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO15 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio15_en:1;
/** ext_etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO16.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio16_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO16 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio16_en:1;
/** ext_etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO17.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio17_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO17 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio17_en:1;
/** ext_etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO18.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio18_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO18 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio18_en:1;
/** ext_etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO19.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio19_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO19 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio19_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p3_cfg_reg_t;
/** Type of ext_etm_task_p4_cfg register
* GPIO selection register 4 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO20.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio20_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO20 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio20_en:1;
/** ext_etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO21.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio21_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO21 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio21_en:1;
/** ext_etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO22.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio22_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO22 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio22_en:1;
/** ext_etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO23.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio23_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO23 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio23_en:1;
/** ext_etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO24.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio24_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO24 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio24_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p4_cfg_reg_t;
/** Type of ext_etm_task_p5_cfg register
* GPIO selection register 5 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO25.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio25_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO25 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio25_en:1;
/** ext_etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO26.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio26_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO26 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio26_en:1;
/** ext_etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO27.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio27_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO27 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio27_en:1;
/** ext_etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO28.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio28_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO28 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio28_en:1;
/** ext_etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO29.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio29_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio29_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO29 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio29_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p5_cfg_reg_t;
/** Type of ext_etm_task_p6_cfg register
* GPIO selection register 6 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio30_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO30.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio30_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio30_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO30 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio30_en:1;
/** ext_etm_task_gpio31_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO31.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio31_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio31_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO31 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio31_en:1;
/** ext_etm_task_gpio32_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO32.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio32_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio32_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO32 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio32_en:1;
/** ext_etm_task_gpio33_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO33.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio33_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio33_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO33 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio33_en:1;
/** ext_etm_task_gpio34_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO34.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio34_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio34_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO34 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio34_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p6_cfg_reg_t;
/** Type of ext_etm_task_p7_cfg register
* GPIO selection register 7 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio35_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO35.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio35_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio35_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO35 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio35_en:1;
/** ext_etm_task_gpio36_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO36.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio36_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio36_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO36 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio36_en:1;
/** ext_etm_task_gpio37_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO37.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio37_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio37_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO37 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio37_en:1;
/** ext_etm_task_gpio38_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO38.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio38_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio38_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO38 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio38_en:1;
/** ext_etm_task_gpio39_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO39.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio39_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio39_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO39 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio39_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p7_cfg_reg_t;
} gpio_ext_etm_task_pn_cfg_reg_t;
/** Group: Version Register */
@@ -813,6 +218,11 @@ typedef union {
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct gpio_etm_dev_t {
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[8];
} gpio_etm_dev_t;
typedef struct {
uint32_t reserved_000;
@@ -821,24 +231,16 @@ typedef struct {
uint32_t reserved_018[48];
volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8];
uint32_t reserved_0f8[8];
volatile gpio_ext_etm_event_chn_cfg_reg_t ext_etm_event_chn_cfg[8];
uint32_t reserved_138[8];
volatile gpio_ext_etm_task_p0_cfg_reg_t ext_etm_task_p0_cfg;
volatile gpio_ext_etm_task_p1_cfg_reg_t ext_etm_task_p1_cfg;
volatile gpio_ext_etm_task_p2_cfg_reg_t ext_etm_task_p2_cfg;
volatile gpio_ext_etm_task_p3_cfg_reg_t ext_etm_task_p3_cfg;
volatile gpio_ext_etm_task_p4_cfg_reg_t ext_etm_task_p4_cfg;
volatile gpio_ext_etm_task_p5_cfg_reg_t ext_etm_task_p5_cfg;
volatile gpio_ext_etm_task_p6_cfg_reg_t ext_etm_task_p6_cfg;
volatile gpio_ext_etm_task_p7_cfg_reg_t ext_etm_task_p7_cfg;
volatile gpio_etm_dev_t etm;
uint32_t reserved_178[33];
volatile gpio_ext_version_reg_t ext_version;
} gpio_dev_t;
} gpio_ext_dev_t;
extern gpio_dev_t GPIO_EXT;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x200, "Invalid size of gpio_dev_t structure");
_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus

277
components/soc/esp32h4/register/soc/i2s_reg.h
View File

@@ -11,10 +11,12 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S0_BASE) // only one I2S on H4
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/
#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the i2s_rx_done_int interrupt
*/
@@ -54,7 +56,7 @@ extern "C" {
/** I2S_INT_ST_REG register
* I2S interrupt status register.
*/
#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the i2s_rx_done_int interrupt
*/
@@ -94,7 +96,7 @@ extern "C" {
/** I2S_INT_ENA_REG register
* I2S interrupt enable register.
*/
#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the i2s_rx_done_int interrupt
*/
@@ -134,7 +136,7 @@ extern "C" {
/** I2S_INT_CLR_REG register
* I2S interrupt clear register.
*/
#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the i2s_rx_done_int interrupt
*/
@@ -174,7 +176,7 @@ extern "C" {
/** I2S_RX_CONF_REG register
* I2S RX configure register
*/
#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset receiver
*/
@@ -326,7 +328,7 @@ extern "C" {
/** I2S_TX_CONF_REG register
* I2S TX configure register
*/
#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset transmitter
*/
@@ -502,7 +504,7 @@ extern "C" {
/** I2S_RX_CONF1_REG register
* I2S RX configure register 1
*/
#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
* The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
* T_bck
@@ -539,7 +541,7 @@ extern "C" {
/** I2S_TX_CONF1_REG register
* I2S TX configure register 1
*/
#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
* The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
* T_bck
@@ -573,177 +575,10 @@ extern "C" {
#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU
#define I2S_TX_TDM_CHAN_BITS_S 27
/** I2S_RX_RECOMB_CTRL_REG register
* I2S RX configure register 1
*/
#define I2S_RX_RECOMB_CTRL_REG (DR_REG_I2S_BASE + 0x30)
/** I2S_RX_RECOMB_EN : R/W; bitpos: [0]; default: 0;
* Set this bit to enable i2s rx data recombination.
*/
#define I2S_RX_RECOMB_EN (BIT(0))
#define I2S_RX_RECOMB_EN_M (I2S_RX_RECOMB_EN_V << I2S_RX_RECOMB_EN_S)
#define I2S_RX_RECOMB_EN_V 0x00000001U
#define I2S_RX_RECOMB_EN_S 0
/** I2S_RX_RECOMB_EXT_CH_NUM : R/W; bitpos: [2:1]; default: 0;
* The channel number that i2s will extract the data into.
*/
#define I2S_RX_RECOMB_EXT_CH_NUM 0x00000003U
#define I2S_RX_RECOMB_EXT_CH_NUM_M (I2S_RX_RECOMB_EXT_CH_NUM_V << I2S_RX_RECOMB_EXT_CH_NUM_S)
#define I2S_RX_RECOMB_EXT_CH_NUM_V 0x00000003U
#define I2S_RX_RECOMB_EXT_CH_NUM_S 1
/** I2S_RX_RECOMB_UPDATE : WT; bitpos: [31]; default: 0;
* Set this bit to update i2s data recombination configuration, must be performed
* after changing the config of any recombined-dma-channel.
*/
#define I2S_RX_RECOMB_UPDATE (BIT(31))
#define I2S_RX_RECOMB_UPDATE_M (I2S_RX_RECOMB_UPDATE_V << I2S_RX_RECOMB_UPDATE_S)
#define I2S_RX_RECOMB_UPDATE_V 0x00000001U
#define I2S_RX_RECOMB_UPDATE_S 31
/** I2S_RX_RECOMB_DMA_CH0_REG register
* I2S RX recombined-dma-channel configuration register
*/
#define I2S_RX_RECOMB_DMA_CH0_REG (DR_REG_I2S_BASE + 0x34)
/** I2S_RX_RECOMB_DMA_CH0_VALID : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH0_VALID (BIT(0))
#define I2S_RX_RECOMB_DMA_CH0_VALID_M (I2S_RX_RECOMB_DMA_CH0_VALID_V << I2S_RX_RECOMB_DMA_CH0_VALID_S)
#define I2S_RX_RECOMB_DMA_CH0_VALID_V 0x00000001U
#define I2S_RX_RECOMB_DMA_CH0_VALID_S 0
/** I2S_RX_RECOMB_DMA_CH0_STYLE : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
#define I2S_RX_RECOMB_DMA_CH0_STYLE 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH0_STYLE_M (I2S_RX_RECOMB_DMA_CH0_STYLE_V << I2S_RX_RECOMB_DMA_CH0_STYLE_S)
#define I2S_RX_RECOMB_DMA_CH0_STYLE_V 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH0_STYLE_S 1
/** I2S_RX_RECOMB_DMA_CH0_ORDER : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
#define I2S_RX_RECOMB_DMA_CH0_ORDER 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH0_ORDER_M (I2S_RX_RECOMB_DMA_CH0_ORDER_V << I2S_RX_RECOMB_DMA_CH0_ORDER_S)
#define I2S_RX_RECOMB_DMA_CH0_ORDER_V 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH0_ORDER_S 5
/** I2S_RX_RECOMB_DMA_CH0_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S)
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S 13
/** I2S_RX_RECOMB_DMA_CH1_REG register
* I2S RX recombined-dma-channel configuration register
*/
#define I2S_RX_RECOMB_DMA_CH1_REG (DR_REG_I2S_BASE + 0x38)
/** I2S_RX_RECOMB_DMA_CH1_VALID : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH1_VALID (BIT(0))
#define I2S_RX_RECOMB_DMA_CH1_VALID_M (I2S_RX_RECOMB_DMA_CH1_VALID_V << I2S_RX_RECOMB_DMA_CH1_VALID_S)
#define I2S_RX_RECOMB_DMA_CH1_VALID_V 0x00000001U
#define I2S_RX_RECOMB_DMA_CH1_VALID_S 0
/** I2S_RX_RECOMB_DMA_CH1_STYLE : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
#define I2S_RX_RECOMB_DMA_CH1_STYLE 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH1_STYLE_M (I2S_RX_RECOMB_DMA_CH1_STYLE_V << I2S_RX_RECOMB_DMA_CH1_STYLE_S)
#define I2S_RX_RECOMB_DMA_CH1_STYLE_V 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH1_STYLE_S 1
/** I2S_RX_RECOMB_DMA_CH1_ORDER : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
#define I2S_RX_RECOMB_DMA_CH1_ORDER 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH1_ORDER_M (I2S_RX_RECOMB_DMA_CH1_ORDER_V << I2S_RX_RECOMB_DMA_CH1_ORDER_S)
#define I2S_RX_RECOMB_DMA_CH1_ORDER_V 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH1_ORDER_S 5
/** I2S_RX_RECOMB_DMA_CH1_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S)
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S 13
/** I2S_RX_RECOMB_DMA_CH2_REG register
* I2S RX recombined-dma-channel configuration register
*/
#define I2S_RX_RECOMB_DMA_CH2_REG (DR_REG_I2S_BASE + 0x3c)
/** I2S_RX_RECOMB_DMA_CH2_VALID : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH2_VALID (BIT(0))
#define I2S_RX_RECOMB_DMA_CH2_VALID_M (I2S_RX_RECOMB_DMA_CH2_VALID_V << I2S_RX_RECOMB_DMA_CH2_VALID_S)
#define I2S_RX_RECOMB_DMA_CH2_VALID_V 0x00000001U
#define I2S_RX_RECOMB_DMA_CH2_VALID_S 0
/** I2S_RX_RECOMB_DMA_CH2_STYLE : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
#define I2S_RX_RECOMB_DMA_CH2_STYLE 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH2_STYLE_M (I2S_RX_RECOMB_DMA_CH2_STYLE_V << I2S_RX_RECOMB_DMA_CH2_STYLE_S)
#define I2S_RX_RECOMB_DMA_CH2_STYLE_V 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH2_STYLE_S 1
/** I2S_RX_RECOMB_DMA_CH2_ORDER : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
#define I2S_RX_RECOMB_DMA_CH2_ORDER 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH2_ORDER_M (I2S_RX_RECOMB_DMA_CH2_ORDER_V << I2S_RX_RECOMB_DMA_CH2_ORDER_S)
#define I2S_RX_RECOMB_DMA_CH2_ORDER_V 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH2_ORDER_S 5
/** I2S_RX_RECOMB_DMA_CH2_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S)
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S 13
/** I2S_RX_RECOMB_DMA_CH3_REG register
* I2S RX recombined-dma-channel configuration register
*/
#define I2S_RX_RECOMB_DMA_CH3_REG (DR_REG_I2S_BASE + 0x40)
/** I2S_RX_RECOMB_DMA_CH3_VALID : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH3_VALID (BIT(0))
#define I2S_RX_RECOMB_DMA_CH3_VALID_M (I2S_RX_RECOMB_DMA_CH3_VALID_V << I2S_RX_RECOMB_DMA_CH3_VALID_S)
#define I2S_RX_RECOMB_DMA_CH3_VALID_V 0x00000001U
#define I2S_RX_RECOMB_DMA_CH3_VALID_S 0
/** I2S_RX_RECOMB_DMA_CH3_STYLE : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
#define I2S_RX_RECOMB_DMA_CH3_STYLE 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH3_STYLE_M (I2S_RX_RECOMB_DMA_CH3_STYLE_V << I2S_RX_RECOMB_DMA_CH3_STYLE_S)
#define I2S_RX_RECOMB_DMA_CH3_STYLE_V 0x0000000FU
#define I2S_RX_RECOMB_DMA_CH3_STYLE_S 1
/** I2S_RX_RECOMB_DMA_CH3_ORDER : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
#define I2S_RX_RECOMB_DMA_CH3_ORDER 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH3_ORDER_M (I2S_RX_RECOMB_DMA_CH3_ORDER_V << I2S_RX_RECOMB_DMA_CH3_ORDER_S)
#define I2S_RX_RECOMB_DMA_CH3_ORDER_V 0x000000FFU
#define I2S_RX_RECOMB_DMA_CH3_ORDER_S 5
/** I2S_RX_RECOMB_DMA_CH3_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S)
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V 0x0000FFFFU
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S 13
/** I2S_TX_PCM2PDM_CONF_REG register
* I2S TX PCM2PDM configuration register
*/
#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x44)
#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x44)
/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
@@ -825,7 +660,7 @@ extern "C" {
/** I2S_TX_PCM2PDM_CONF1_REG register
* I2S TX PCM2PDM configuration register
*/
#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x48)
#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x48)
/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
@@ -857,60 +692,10 @@ extern "C" {
#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U
#define I2S_TX_IIR_HP_MULT12_0_S 23
/** I2S_RX_PDM2PCM_CONF_REG register
* I2S RX configure register
*/
#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x4c)
/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
* 1: Enable PDM2PCM RX mode. 0: DIsable.
*/
#define I2S_RX_PDM2PCM_EN (BIT(19))
#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
#define I2S_RX_PDM2PCM_EN_V 0x00000001U
#define I2S_RX_PDM2PCM_EN_S 19
/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
* sampling rate is 128. 0: down sampling rate is 64.
*/
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20))
#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U
#define I2S_RX_PDM_SINC_DSR_16_EN_S 20
/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
* Configure PDM RX amplify number.
*/
#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21
/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
* I2S PDM RX bypass hp filter or not.
*/
#define I2S_RX_PDM_HP_BYPASS (BIT(25))
#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U
#define I2S_RX_PDM_HP_BYPASS_S 25
/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
*/
#define I2S_RX_IIR_HP_MULT12_5 0x00000007U
#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U
#define I2S_RX_IIR_HP_MULT12_5_S 26
/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
*/
#define I2S_RX_IIR_HP_MULT12_0 0x00000007U
#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U
#define I2S_RX_IIR_HP_MULT12_0_S 29
/** I2S_RX_TDM_CTRL_REG register
* I2S TX TDM mode control register
*/
#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
* 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
* input 0 in this channel.
@@ -1050,7 +835,7 @@ extern "C" {
/** I2S_TX_TDM_CTRL_REG register
* I2S TX TDM mode control register
*/
#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
* 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
* 0 in this channel.
@@ -1199,7 +984,7 @@ extern "C" {
/** I2S_RX_TIMING_REG register
* I2S RX timing control register
*/
#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
* The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
@@ -1268,7 +1053,7 @@ extern "C" {
/** I2S_TX_TIMING_REG register
* I2S TX timing control register
*/
#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
* The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
* delay by neg edge. 3: not used.
@@ -1321,7 +1106,7 @@ extern "C" {
/** I2S_LC_HUNG_CONF_REG register
* I2S HUNG configure register.
*/
#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
* the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
* when fifo hung counter is equal to this value
@@ -1349,7 +1134,7 @@ extern "C" {
/** I2S_RXEOF_NUM_REG register
* I2S RX data number control register.
*/
#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
/** I2S_RX_EOF_NUM : R/W; bitpos: [15:0]; default: 64;
* The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0])
* . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
@@ -1362,7 +1147,7 @@ extern "C" {
/** I2S_CONF_SIGLE_DATA_REG register
* I2S signal data register
*/
#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
* The configured constant channel data to be sent out.
*/
@@ -1374,7 +1159,7 @@ extern "C" {
/** I2S_STATE_REG register
* I2S TX status register
*/
#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
* 1: i2s_tx is idle state. 0: i2s_tx is working.
*/
@@ -1386,7 +1171,7 @@ extern "C" {
/** I2S_ETM_CONF_REG register
* I2S ETM configure register
*/
#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [13:0]; default: 64;
* I2S ETM send x words event. When sending word number of
* reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event.
@@ -1407,7 +1192,7 @@ extern "C" {
/** I2S_IDEAL_CNT_REG register
* I2S sync counter register
*/
#define I2S_IDEAL_CNT_REG (DR_REG_I2S_BASE + 0x74)
#define I2S_IDEAL_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
/** I2S_TX_IDEAL_CNT : R/W; bitpos: [30:0]; default: 0;
* tx fifo counter ideal value.
*/
@@ -1419,7 +1204,7 @@ extern "C" {
/** I2S_FIFO_CNT_REG register
* I2S sync counter register
*/
#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x78)
#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
* tx fifo counter value.
*/
@@ -1438,7 +1223,7 @@ extern "C" {
/** I2S_BCK_CNT_REG register
* I2S sync counter register
*/
#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x7c)
#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x7c)
/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
* tx bck counter value.
*/
@@ -1457,7 +1242,7 @@ extern "C" {
/** I2S_CNT_DIFF_REG register
* I2S sync counter register
*/
#define I2S_CNT_DIFF_REG (DR_REG_I2S_BASE + 0x80)
#define I2S_CNT_DIFF_REG(i) (REG_I2S_BASE(i) + 0x80)
/** I2S_TX_CNT_DIFF : RO; bitpos: [30:0]; default: 0;
* tx bck counter value.
*/
@@ -1476,7 +1261,7 @@ extern "C" {
/** I2S_SYNC_SW_THRES_REG register
* I2S sync counter register
*/
#define I2S_SYNC_SW_THRES_REG (DR_REG_I2S_BASE + 0x84)
#define I2S_SYNC_SW_THRES_REG(i) (REG_I2S_BASE(i) + 0x84)
/** I2S_TX_CNT_DIFF_SW_THRES : R/W; bitpos: [30:0]; default: 0;
* tx fifo counter difference software threshold value, when difference larger than
* this threshold, interrupt will occur and hardware sync will not be executed.
@@ -1489,7 +1274,7 @@ extern "C" {
/** I2S_SYNC_HW_THRES_REG register
* I2S sync counter register
*/
#define I2S_SYNC_HW_THRES_REG (DR_REG_I2S_BASE + 0x88)
#define I2S_SYNC_HW_THRES_REG(i) (REG_I2S_BASE(i) + 0x88)
/** I2S_TX_CNT_DIFF_HW_THRES : R/W; bitpos: [30:0]; default: 0;
* tx fifo counter difference hardware threshold value, which means that only when
* difference larger than this threshold will hardware start hardware sync.
@@ -1502,7 +1287,7 @@ extern "C" {
/** I2S_HW_SYNC_CONF_REG register
* I2S TX hardware sync function configuration register
*/
#define I2S_HW_SYNC_CONF_REG (DR_REG_I2S_BASE + 0x8c)
#define I2S_HW_SYNC_CONF_REG(i) (REG_I2S_BASE(i) + 0x8c)
/** I2S_TX_HW_SYNC_EN : R/W; bitpos: [0]; default: 0;
* Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable
*/
@@ -1522,7 +1307,7 @@ extern "C" {
/** I2S_HW_SYNC_DATA_REG register
* I2S TX hardware sync function configuration register
*/
#define I2S_HW_SYNC_DATA_REG (DR_REG_I2S_BASE + 0x90)
#define I2S_HW_SYNC_DATA_REG(i) (REG_I2S_BASE(i) + 0x90)
/** I2S_TX_HW_SYNC_SUPPL_DATA : R/W; bitpos: [31:0]; default: 0;
* Configure the i2s tx hardware sync supplementation data when
* I2S_TX_HW_SYNC_SUPPL_MODE is 1.
@@ -1535,7 +1320,7 @@ extern "C" {
/** I2S_CLK_GATE_REG register
* Clock gate register
*/
#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0xf8)
#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0xf8)
/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
* set this bit to enable clock gate
*/
@@ -1547,7 +1332,7 @@ extern "C" {
/** I2S_DATE_REG register
* Version control register
*/
#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc)
#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0xfc)
/** I2S_DATE : R/W; bitpos: [27:0]; default: 37818432;
* I2S version control register
*/

192
components/soc/esp32h4/register/soc/i2s_struct.h
View File

@@ -260,178 +260,6 @@ typedef union {
uint32_t val;
} i2s_rx_conf1_reg_t;
/** Type of rx_recomb_ctrl register
* I2S RX configure register 1
*/
typedef union {
struct {
/** rx_recomb_en : R/W; bitpos: [0]; default: 0;
* Set this bit to enable i2s rx data recombination.
*/
uint32_t rx_recomb_en:1;
/** rx_recomb_ext_ch_num : R/W; bitpos: [2:1]; default: 0;
* The channel number that i2s will extract the data into.
*/
uint32_t rx_recomb_ext_ch_num:2;
uint32_t reserved_3:28;
/** rx_recomb_update : WT; bitpos: [31]; default: 0;
* Set this bit to update i2s data recombination configuration, must be performed
* after changing the config of any recombined-dma-channel.
*/
uint32_t rx_recomb_update:1;
};
uint32_t val;
} i2s_rx_recomb_ctrl_reg_t;
/** Type of rx_recomb_dma_ch0 register
* I2S RX recombined-dma-channel configuration register
*/
typedef union {
struct {
/** rx_recomb_dma_ch0_valid : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
uint32_t rx_recomb_dma_ch0_valid:1;
/** rx_recomb_dma_ch0_style : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
uint32_t rx_recomb_dma_ch0_style:4;
/** rx_recomb_dma_ch0_order : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
uint32_t rx_recomb_dma_ch0_order:8;
/** rx_recomb_dma_ch0_eof_num : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
uint32_t rx_recomb_dma_ch0_eof_num:16;
uint32_t reserved_29:3;
};
uint32_t val;
} i2s_rx_recomb_dma_ch0_reg_t;
/** Type of rx_recomb_dma_ch1 register
* I2S RX recombined-dma-channel configuration register
*/
typedef union {
struct {
/** rx_recomb_dma_ch1_valid : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
uint32_t rx_recomb_dma_ch1_valid:1;
/** rx_recomb_dma_ch1_style : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
uint32_t rx_recomb_dma_ch1_style:4;
/** rx_recomb_dma_ch1_order : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
uint32_t rx_recomb_dma_ch1_order:8;
/** rx_recomb_dma_ch1_eof_num : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
uint32_t rx_recomb_dma_ch1_eof_num:16;
uint32_t reserved_29:3;
};
uint32_t val;
} i2s_rx_recomb_dma_ch1_reg_t;
/** Type of rx_recomb_dma_ch2 register
* I2S RX recombined-dma-channel configuration register
*/
typedef union {
struct {
/** rx_recomb_dma_ch2_valid : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
uint32_t rx_recomb_dma_ch2_valid:1;
/** rx_recomb_dma_ch2_style : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
uint32_t rx_recomb_dma_ch2_style:4;
/** rx_recomb_dma_ch2_order : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
uint32_t rx_recomb_dma_ch2_order:8;
/** rx_recomb_dma_ch2_eof_num : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
uint32_t rx_recomb_dma_ch2_eof_num:16;
uint32_t reserved_29:3;
};
uint32_t val;
} i2s_rx_recomb_dma_ch2_reg_t;
/** Type of rx_recomb_dma_ch3 register
* I2S RX recombined-dma-channel configuration register
*/
typedef union {
struct {
/** rx_recomb_dma_ch3_valid : R/W; bitpos: [0]; default: 0;
* Set this bit to enable the adc-dma-channel.
*/
uint32_t rx_recomb_dma_ch3_valid:1;
/** rx_recomb_dma_ch3_style : R/W; bitpos: [4:1]; default: 0;
* Set this field to set the recombined-dma-channel style. If choose to use i2s
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
*/
uint32_t rx_recomb_dma_ch3_style:4;
/** rx_recomb_dma_ch3_order : R/W; bitpos: [12:5]; default: 0;
* Set this field to set the recombined-dma-channel order. If choose to use the order
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
*/
uint32_t rx_recomb_dma_ch3_order:8;
/** rx_recomb_dma_ch3_eof_num : R/W; bitpos: [28:13]; default: 0;
* Set this field to set the receive eof byte length of the recombined-dma-channel.
*/
uint32_t rx_recomb_dma_ch3_eof_num:16;
uint32_t reserved_29:3;
};
uint32_t val;
} i2s_rx_recomb_dma_ch3_reg_t;
/** Type of rx_pdm2pcm_conf register
* I2S RX configure register
*/
typedef union {
struct {
uint32_t reserved_0:19;
/** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
* 1: Enable PDM2PCM RX mode. 0: DIsable.
*/
uint32_t rx_pdm2pcm_en:1;
/** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
* sampling rate is 128. 0: down sampling rate is 64.
*/
uint32_t rx_pdm_sinc_dsr_16_en:1;
/** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
* Configure PDM RX amplify number.
*/
uint32_t rx_pdm2pcm_amplify_num:4;
/** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
* I2S PDM RX bypass hp filter or not.
*/
uint32_t rx_pdm_hp_bypass:1;
/** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
*/
uint32_t rx_iir_hp_mult12_5:3;
/** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
*/
uint32_t rx_iir_hp_mult12_0:3;
};
uint32_t val;
} i2s_rx_pdm2pcm_conf_reg_t;
/** Type of rx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -526,7 +354,7 @@ typedef union {
uint32_t val;
} i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
/** Type of rx_eof_num register
* I2S RX data number control register.
*/
typedef union {
@@ -539,7 +367,7 @@ typedef union {
uint32_t reserved_16:16;
};
uint32_t val;
} i2s_rxeof_num_reg_t;
} i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */
@@ -1001,7 +829,7 @@ typedef union {
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
* I2S signal data register
* I2S single data register
*/
typedef union {
struct {
@@ -1011,7 +839,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@@ -1225,21 +1053,17 @@ typedef struct {
volatile i2s_tx_conf_reg_t tx_conf;
volatile i2s_rx_conf1_reg_t rx_conf1;
volatile i2s_tx_conf1_reg_t tx_conf1;
volatile i2s_rx_recomb_ctrl_reg_t rx_recomb_ctrl;
volatile i2s_rx_recomb_dma_ch0_reg_t rx_recomb_dma_ch0;
volatile i2s_rx_recomb_dma_ch1_reg_t rx_recomb_dma_ch1;
volatile i2s_rx_recomb_dma_ch2_reg_t rx_recomb_dma_ch2;
volatile i2s_rx_recomb_dma_ch3_reg_t rx_recomb_dma_ch3;
uint32_t reserved_030[5];
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
uint32_t reserved_04c;
volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
volatile i2s_ideal_cnt_reg_t ideal_cnt;

8
components/soc/esp32h4/register/soc/pcr_struct.h
View File

@@ -728,8 +728,8 @@ typedef union {
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S TX.
* 0 (default): XTAL_CLK
* 1: PLL_F240M_CLK
* 2: PLL_F160M_CLK
* 1: PLL_F96M_CLK
* 2: PLL_F64M_CLK
* 3: I2S_MCLK_in
*/
uint32_t i2s_tx_clkm_sel:2;
@@ -785,8 +785,8 @@ typedef union {
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Configures the clock source of I2S RX.
* 0 (default): XTAL_CLK
* 1: PLL_F240M_CLK
* 2: PLL_F160M_CLK
* 1: PLL_F96M_CLK
* 2: PLL_F64M_CLK
* 3: I2S_MCLK_in
*/
uint32_t i2s_rx_clkm_sel:2;

268
components/soc/esp32h4/register/soc/soc_etm_reg.h
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File diff suppressed because it is too large Load Diff

112
components/soc/esp32h4/register/soc/soc_etm_struct.h
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@@ -5985,113 +5985,17 @@ typedef union {
} soc_etm_date_reg_t;
typedef struct {
typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad0_reg_t etm_ch_ena_ad0;
volatile soc_etm_ch_ena_ad0_set_reg_t etm_ch_ena_ad0_set;
volatile soc_etm_ch_ena_ad0_clr_reg_t etm_ch_ena_ad0_clr;
volatile soc_etm_ch_ena_ad1_reg_t etm_ch_ena_ad1;
volatile soc_etm_ch_ena_ad1_set_reg_t etm_ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t etm_ch_ena_ad1_clr;
volatile soc_etm_chn_evt_id_reg_t etm_ch0_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch0_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch1_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch1_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch2_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch2_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch3_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch3_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch4_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch4_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch5_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch5_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch6_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch6_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch7_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch7_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch8_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch8_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch9_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch9_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch10_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch10_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch11_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch11_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch12_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch12_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch13_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch13_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch14_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch14_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch15_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch15_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch16_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch16_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch17_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch17_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch18_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch18_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch19_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch19_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch20_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch20_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch21_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch21_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch22_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch22_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch23_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch23_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch24_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch24_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch25_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch25_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch26_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch26_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch27_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch27_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch28_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch28_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch29_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch29_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch30_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch30_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch31_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch31_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch32_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch32_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch33_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch33_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch34_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch34_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch35_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch35_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch36_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch36_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch37_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch37_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch38_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch38_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch39_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch39_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch40_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch40_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch41_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch41_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch42_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch42_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch43_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch43_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch44_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch44_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch45_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch45_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch46_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch46_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch47_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch47_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch48_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch48_task_id;
volatile soc_etm_chn_evt_id_reg_t etm_ch49_evt_id;
volatile soc_etm_chn_task_id_reg_t etm_ch49_task_id;
volatile struct {
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_evt_st0_reg_t etm_evt_st0;
volatile soc_etm_evt_st0_clr_reg_t etm_evt_st0_clr;
volatile soc_etm_evt_st1_reg_t etm_evt_st1;
@@ -6120,12 +6024,12 @@ typedef struct {
volatile soc_etm_task_st5_clr_reg_t etm_task_st5_clr;
volatile soc_etm_clk_en_reg_t etm_clk_en;
volatile soc_etm_date_reg_t etm_date;
} soc_dev_t;
} soc_etm_dev_t;
extern soc_dev_t SOC_ETM;
extern soc_etm_dev_t SOC_ETM;
#ifndef __cplusplus
_Static_assert(sizeof(soc_dev_t) == 0x218, "Invalid size of soc_dev_t structure");
_Static_assert(sizeof(soc_etm_dev_t) == 0x218, "Invalid size of soc_etm_dev_t structure");
#endif
#ifdef __cplusplus

1
components/soc/esp32p4/include/soc/soc.h
View File

@@ -19,7 +19,6 @@
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
#define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3

2
components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h
View File

@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/

1
components/soc/esp32s2/include/soc/soc.h
View File

@@ -22,7 +22,6 @@
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3

14
components/soc/esp32s2/register/soc/i2s_reg.h
View File

@@ -1,16 +1,18 @@
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/soc.h"
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008)
/* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
@@ -1378,7 +1380,3 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */

1
components/soc/esp32s3/include/soc/soc.h
View File

@@ -30,7 +30,6 @@
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3

13
components/soc/esp32s3/register/soc/i2s_reg.h
View File

@@ -1,17 +1,18 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xC)
/* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/
@@ -1092,7 +1093,3 @@ when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */

4
examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# I2S Basic PDM Mode Example

4
examples/peripherals/i2s/i2s_basic/i2s_std/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
# I2S Basic Standard Mode Example

4
examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# I2S Basic TDM Mode Example

4
examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
# I2S ES8311 Example

4
examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 |
| ----------------- | -------- | -------- | --------- | -------- | -------- | -------- |
# HC-SR04 Example based on GPTimer Capture and ETM