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Merge branch 'change/sync_trm_csv_update_5_23' into 'master'

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change(csv_update): sync the csv update to idf

See merge request espressif/esp-idf!39386
This commit is contained in:
Kevin (Lao Kaiyao)
2025-05-27 12:45:14 +08:00
parent 2b81deaca8 0a93309a89
commit 7e554894ce
17 changed files with 4902 additions and 16428 deletions
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8
components/hal/esp32c61/include/hal/cache_ll.h
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@ -246,11 +246,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
}
@ -268,11 +268,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
}

320
components/soc/esp32c5/register/soc/cpu_apm_reg.h
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140
components/soc/esp32c5/register/soc/cpu_apm_struct.h
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@ -10,16 +10,16 @@
extern "C" {
#endif
/** Group: Region filter enable register */
/** Group: Configuration Registers */
/** Type of region_filter_en register
* Region filter enable register
* Region enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
* Configures bit $n (0-7) to enable region $n (0-7).
* 0: Disable
* 1: Enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
@ -28,7 +28,7 @@ typedef union {
} cpu_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Group: Region Address Registers */
/** Type of regionn_addr_start register
* Region address register
*/
@ -39,7 +39,7 @@ typedef union {
*/
uint32_t regionn_addr_start_l:12;
/** regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
* Configures start address of region n.
* Configures the start address of region n.
*/
uint32_t regionn_addr_start:7;
/** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
@ -60,7 +60,7 @@ typedef union {
*/
uint32_t regionn_addr_end_l:12;
/** regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
* Configures end address of region n.
* Configures the end address of region n.
*/
uint32_t regionn_addr_end:7;
/** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
@ -71,53 +71,55 @@ typedef union {
uint32_t val;
} cpu_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
* Region access permissions configuration register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
* Configures the execution permission in region n in REE0 mode.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
* Configures the write permission in region n in REE0 mode.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
* Configures the read permission in region n in REE0 mode.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
* Configures the execution permission in region n in REE1 mode.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
* Configures the write permission in region n in REE1 mode.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
* Configures the read permission in region n in REE1 mode.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
* Configures the execution permission in region n in REE2 mode.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
* Configures the write permission in region n in REE2 mode.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
* Configures the read permission in region n in REE2 mode.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region n's configuration registers
* (CPU_APM_REGIONn_ADDR_START_REG, CPU_APM_REGIONn_ADDR_END_REG, and
* CPU_APM_REGIONn_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
@ -125,19 +127,21 @@ typedef union {
uint32_t val;
} cpu_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
* APM access path permission management register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
* Configures whether to enable permission management for CPU_APM_CTRL M0.
* 0: Disable
* 1: Enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
* Configures whether to enable permission management for CPU_APM_CTRL M1.
* 0: Disable
* 1: Enable
*/
uint32_t m1_func_en:1;
uint32_t reserved_2:30;
@ -146,16 +150,16 @@ typedef union {
} cpu_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Group: Status Registers */
/** Type of m0_status register
* M0 status register
* CPU_APM_CTRL M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
@ -163,15 +167,13 @@ typedef union {
uint32_t val;
} cpu_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
* CPU_APM_CTRL M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
* Write 1 to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
@ -179,23 +181,21 @@ typedef union {
uint32_t val;
} cpu_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
* CPU_APM_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
@ -203,32 +203,28 @@ typedef union {
uint32_t val;
} cpu_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
* CPU_APM_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} cpu_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
* CPU_APM_CTRL M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
@ -236,15 +232,13 @@ typedef union {
uint32_t val;
} cpu_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
* CPU_APM_CTRL M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
* Write 1 to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
@ -252,23 +246,21 @@ typedef union {
uint32_t val;
} cpu_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
* CPU_APM_CTRL M1 exception information register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
@ -276,15 +268,13 @@ typedef union {
uint32_t val;
} cpu_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
* CPU_APM_CTRL M1 exception information register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m1_exception_addr:32;
};
@ -292,22 +282,22 @@ typedef union {
} cpu_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Group: Interrupt Registers */
/** Type of int_en register
* APM interrupt enable register
* CPU_APM_CTRL M0/1 interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
* Configures whether to enable CPU_APM_CTRL M0 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
* Configures whether to enable CPU_APM_CTRL M1 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
@ -316,7 +306,7 @@ typedef union {
} cpu_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Group: Clock Gating Registers */
/** Type of clock_gate register
* Clock gating register
*/
@ -324,8 +314,8 @@ typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@ -334,7 +324,7 @@ typedef union {
} cpu_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Group: Version Control Registers */
/** Type of date register
* Version control register
*/

650
components/soc/esp32c5/register/soc/hp_apm_reg.h
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254
components/soc/esp32c5/register/soc/hp_apm_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,16 +10,16 @@
extern "C" {
#endif
/** Group: Region filter enable register */
/** Group: Configuration Registers */
/** Type of region_filter_en register
* Region filter enable register
* Region enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [15:0]; default: 1;
* Configure bit $n (0-15) to enable region $n.\\
* 0: disable \\
* 1: enable \\
* Configure bit $n (0-15) to enable region $n (0-15).
* 0: Disable
* 1: Enable
*/
uint32_t region_filter_en:16;
uint32_t reserved_16:16;
@ -27,15 +27,13 @@ typedef union {
uint32_t val;
} hp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n.
* Configures the start address of region n.
*/
uint32_t regionn_addr_start:32;
};
@ -48,60 +46,62 @@ typedef union {
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n.
* Configures the end address of region n.
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} hp_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
* Region access permissions configuration register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
* Configures the execution permission in region n in REE0 mode.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
* Configures the write permission in region n in REE0 mode.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
* Configures the read permission in region n in REE0 mode.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
* Configures the execution permission in region n in REE1 mode.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
* Configures the write permission in region n in REE1 mode.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
* Configures the read permission in region n in REE1 mode.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
* Configures the execution permission in region n in REE2 mode.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
* Configures the write permission in region n in REE2 mode.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
* Configures the read permission in region n in REE2 mode.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region n configuration registers
* (HP_APM_REGIONn_ADDR_START_REG, HP_APM_REGIONn_ADDR_END_REG and
* HP_APM_REGIONn_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
@ -109,31 +109,29 @@ typedef union {
uint32_t val;
} hp_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
* APM access path permission management register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
* Configures to enable permission management for HP_APM_CTRL M0.
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
* Configures to enable permission management for HP_APM_CTRL M1.
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
* Configures to enable permission management for HP_APM_CTRL M2.
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
* Configures to enable permission management for HP_APM_CTRL M3.
*/
uint32_t m3_func_en:1;
/** m4_func_en : R/W; bitpos: [4]; default: 1;
* PMS M4 function enable
* Configures to enable permission management for HP_APM_CTRL M4.
*/
uint32_t m4_func_en:1;
uint32_t reserved_5:27;
@ -142,16 +140,16 @@ typedef union {
} hp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Group: Status Registers */
/** Type of m0_status register
* M0 status register
* HP_APM_CTRL M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
@ -159,10 +157,8 @@ typedef union {
uint32_t val;
} hp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
* HP_APM_CTRL M0 status clear register
*/
typedef union {
struct {
@ -175,23 +171,21 @@ typedef union {
uint32_t val;
} hp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
* HP_APM_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
@ -199,32 +193,28 @@ typedef union {
uint32_t val;
} hp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
* HP_APM_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} hp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
* HP_APM_CTRL M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
@ -232,10 +222,8 @@ typedef union {
uint32_t val;
} hp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
* HP_APM_CTRL M1 status clear register
*/
typedef union {
struct {
@ -248,23 +236,21 @@ typedef union {
uint32_t val;
} hp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
* HP_APM_CTRL M1 exception information register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
@ -272,32 +258,28 @@ typedef union {
uint32_t val;
} hp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
* HP_APM_CTRL M1 exception information register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} hp_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
* HP_APM_CTRL M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
@ -305,10 +287,8 @@ typedef union {
uint32_t val;
} hp_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
* HP_APM_CTRL M2 status clear register
*/
typedef union {
struct {
@ -321,23 +301,21 @@ typedef union {
uint32_t val;
} hp_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
* HP_APM_CTRL M2 exception information register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m2_exception_region:16;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m2_exception_id:5;
uint32_t reserved_23:9;
@ -345,32 +323,28 @@ typedef union {
uint32_t val;
} hp_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
* HP_APM_CTRL M2 exception information register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} hp_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
* HP_APM_CTRL M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
@ -378,10 +352,8 @@ typedef union {
uint32_t val;
} hp_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
* HP_APM_CTRL M3 status clear register
*/
typedef union {
struct {
@ -394,23 +366,21 @@ typedef union {
uint32_t val;
} hp_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
* HP_APM_CTRL M3 exception information register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m3_exception_region:16;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m3_exception_id:5;
uint32_t reserved_23:9;
@ -418,32 +388,28 @@ typedef union {
uint32_t val;
} hp_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
* HP_APM_CTRL M3 exception information register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} hp_apm_m3_exception_info1_reg_t;
/** Group: M4 status register */
/** Type of m4_status register
* M4 status register
* HP_APM_CTRL M4 status register
*/
typedef union {
struct {
/** m4_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
* Represents exception status.
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m4_exception_status:2;
uint32_t reserved_2:30;
@ -451,10 +417,8 @@ typedef union {
uint32_t val;
} hp_apm_m4_status_reg_t;
/** Group: M4 status clear register */
/** Type of m4_status_clr register
* M4 status clear register
* HP_APM_CTRL M4 status clear register
*/
typedef union {
struct {
@ -467,23 +431,21 @@ typedef union {
uint32_t val;
} hp_apm_m4_status_clr_reg_t;
/** Group: M4 exception_info0 register */
/** Type of m4_exception_info0 register
* M4 exception_info0 register
* HP_APM_CTRL M4 exception information register
*/
typedef union {
struct {
/** m4_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m4_exception_region:16;
/** m4_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m4_exception_mode:2;
/** m4_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m4_exception_id:5;
uint32_t reserved_23:9;
@ -491,15 +453,13 @@ typedef union {
uint32_t val;
} hp_apm_m4_exception_info0_reg_t;
/** Group: M4 exception_info1 register */
/** Type of m4_exception_info1 register
* M4 exception_info1 register
* HP_APM_CTRL M4 exception information register
*/
typedef union {
struct {
/** m4_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m4_exception_addr:32;
};
@ -507,40 +467,40 @@ typedef union {
} hp_apm_m4_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Group: Interrupt Registers */
/** Type of int_en register
* APM interrupt enable register
* HP_APM_CTRL M0/1/2/3/4 interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable HP_APM_CTRL M0 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable HP_APM_CTRL M1 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable HP_APM_CTRL M2 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable HP_APM_CTRL M3 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m3_apm_int_en:1;
/** m4_apm_int_en : R/W; bitpos: [4]; default: 0;
* Configures to enable APM M4 interrupt.\\
* 0: disable \\
* 1: enable \\
* Configures to enable HP_APM_CTRL M4 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m4_apm_int_en:1;
uint32_t reserved_5:27;
@ -549,16 +509,16 @@ typedef union {
} hp_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Group: Clock Gating Registers */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@ -567,7 +527,7 @@ typedef union {
} hp_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Group: Version Control Registers */
/** Type of date register
* Version control register
*/

288
components/soc/esp32c5/register/soc/lp_apm0_reg.h
View File

@ -12,13 +12,13 @@ extern "C" {
#endif
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
* Region enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n(0-7) to enable region $n.
* 0: disable
* 1: enable
* Configure bit $n (0-7) to enable region $n (0-7).
* 0: Disable
* 1: Enable
*/
#define LP_APM0_REGION_FILTER_EN 0x000000FFU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
@ -30,7 +30,7 @@ extern "C" {
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 0
* Configures the start address of region 0.
*/
#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
@ -42,7 +42,7 @@ extern "C" {
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 0
* Configures the end address of region 0.
*/
#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
@ -50,74 +50,78 @@ extern "C" {
#define LP_APM0_REGION0_ADDR_END_S 0
/** LP_APM0_REGION0_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION0_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 0.
* Configures the execution permission in region 0 in REE0 mode.
*/
#define LP_APM0_REGION0_R0_X (BIT(0))
#define LP_APM0_REGION0_R0_X_M (LP_APM0_REGION0_R0_X_V << LP_APM0_REGION0_R0_X_S)
#define LP_APM0_REGION0_R0_X_V 0x00000001U
#define LP_APM0_REGION0_R0_X_S 0
/** LP_APM0_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 0.
* Configures the write permission in region 0 in REE0 mode.
*/
#define LP_APM0_REGION0_R0_W (BIT(1))
#define LP_APM0_REGION0_R0_W_M (LP_APM0_REGION0_R0_W_V << LP_APM0_REGION0_R0_W_S)
#define LP_APM0_REGION0_R0_W_V 0x00000001U
#define LP_APM0_REGION0_R0_W_S 1
/** LP_APM0_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 0.
* Configures the read permission in region 0 in REE0 mode.
*/
#define LP_APM0_REGION0_R0_R (BIT(2))
#define LP_APM0_REGION0_R0_R_M (LP_APM0_REGION0_R0_R_V << LP_APM0_REGION0_R0_R_S)
#define LP_APM0_REGION0_R0_R_V 0x00000001U
#define LP_APM0_REGION0_R0_R_S 2
/** LP_APM0_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 0.
* Configures the execution permission in region 0 in REE1 mode.
*/
#define LP_APM0_REGION0_R1_X (BIT(4))
#define LP_APM0_REGION0_R1_X_M (LP_APM0_REGION0_R1_X_V << LP_APM0_REGION0_R1_X_S)
#define LP_APM0_REGION0_R1_X_V 0x00000001U
#define LP_APM0_REGION0_R1_X_S 4
/** LP_APM0_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 0.
* Configures the write permission in region 0 in REE1 mode.
*/
#define LP_APM0_REGION0_R1_W (BIT(5))
#define LP_APM0_REGION0_R1_W_M (LP_APM0_REGION0_R1_W_V << LP_APM0_REGION0_R1_W_S)
#define LP_APM0_REGION0_R1_W_V 0x00000001U
#define LP_APM0_REGION0_R1_W_S 5
/** LP_APM0_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 0.
* Configures the read permission in region 0 in REE1 mode.
*/
#define LP_APM0_REGION0_R1_R (BIT(6))
#define LP_APM0_REGION0_R1_R_M (LP_APM0_REGION0_R1_R_V << LP_APM0_REGION0_R1_R_S)
#define LP_APM0_REGION0_R1_R_V 0x00000001U
#define LP_APM0_REGION0_R1_R_S 6
/** LP_APM0_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 0.
* Configures the execution permission in region 0 in REE2 mode.
*/
#define LP_APM0_REGION0_R2_X (BIT(8))
#define LP_APM0_REGION0_R2_X_M (LP_APM0_REGION0_R2_X_V << LP_APM0_REGION0_R2_X_S)
#define LP_APM0_REGION0_R2_X_V 0x00000001U
#define LP_APM0_REGION0_R2_X_S 8
/** LP_APM0_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 0.
* Configures the write permission in region 0 in REE2 mode.
*/
#define LP_APM0_REGION0_R2_W (BIT(9))
#define LP_APM0_REGION0_R2_W_M (LP_APM0_REGION0_R2_W_V << LP_APM0_REGION0_R2_W_S)
#define LP_APM0_REGION0_R2_W_V 0x00000001U
#define LP_APM0_REGION0_R2_W_S 9
/** LP_APM0_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 0.
* Configures the read permission in region 0 in REE2 mode.
*/
#define LP_APM0_REGION0_R2_R (BIT(10))
#define LP_APM0_REGION0_R2_R_M (LP_APM0_REGION0_R2_R_V << LP_APM0_REGION0_R2_R_S)
#define LP_APM0_REGION0_R2_R_V 0x00000001U
#define LP_APM0_REGION0_R2_R_S 10
/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 0 configuration registers
* (LP_APM0_REGION0_ADDR_START_REG, LP_APM0_REGION0_ADDR_END_REG and
* LP_APM0_REGION0_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION0_LOCK (BIT(11))
#define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S)
@ -129,7 +133,7 @@ extern "C" {
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 1
* Configures the start address of region 1.
*/
#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
@ -141,7 +145,7 @@ extern "C" {
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 1
* Configures the end address of region 1.
*/
#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
@ -149,74 +153,78 @@ extern "C" {
#define LP_APM0_REGION1_ADDR_END_S 0
/** LP_APM0_REGION1_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION1_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 1.
* Configures the execution permission in region 1 in REE0 mode.
*/
#define LP_APM0_REGION1_R0_X (BIT(0))
#define LP_APM0_REGION1_R0_X_M (LP_APM0_REGION1_R0_X_V << LP_APM0_REGION1_R0_X_S)
#define LP_APM0_REGION1_R0_X_V 0x00000001U
#define LP_APM0_REGION1_R0_X_S 0
/** LP_APM0_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 1.
* Configures the write permission in region 1 in REE0 mode.
*/
#define LP_APM0_REGION1_R0_W (BIT(1))
#define LP_APM0_REGION1_R0_W_M (LP_APM0_REGION1_R0_W_V << LP_APM0_REGION1_R0_W_S)
#define LP_APM0_REGION1_R0_W_V 0x00000001U
#define LP_APM0_REGION1_R0_W_S 1
/** LP_APM0_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 1.
* Configures the read permission in region 1 in REE0 mode.
*/
#define LP_APM0_REGION1_R0_R (BIT(2))
#define LP_APM0_REGION1_R0_R_M (LP_APM0_REGION1_R0_R_V << LP_APM0_REGION1_R0_R_S)
#define LP_APM0_REGION1_R0_R_V 0x00000001U
#define LP_APM0_REGION1_R0_R_S 2
/** LP_APM0_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 1.
* Configures the execution permission in region 1 in REE1 mode.
*/
#define LP_APM0_REGION1_R1_X (BIT(4))
#define LP_APM0_REGION1_R1_X_M (LP_APM0_REGION1_R1_X_V << LP_APM0_REGION1_R1_X_S)
#define LP_APM0_REGION1_R1_X_V 0x00000001U
#define LP_APM0_REGION1_R1_X_S 4
/** LP_APM0_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 1.
* Configures the write permission in region 1 in REE1 mode.
*/
#define LP_APM0_REGION1_R1_W (BIT(5))
#define LP_APM0_REGION1_R1_W_M (LP_APM0_REGION1_R1_W_V << LP_APM0_REGION1_R1_W_S)
#define LP_APM0_REGION1_R1_W_V 0x00000001U
#define LP_APM0_REGION1_R1_W_S 5
/** LP_APM0_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 1.
* Configures the read permission in region 1 in REE1 mode.
*/
#define LP_APM0_REGION1_R1_R (BIT(6))
#define LP_APM0_REGION1_R1_R_M (LP_APM0_REGION1_R1_R_V << LP_APM0_REGION1_R1_R_S)
#define LP_APM0_REGION1_R1_R_V 0x00000001U
#define LP_APM0_REGION1_R1_R_S 6
/** LP_APM0_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 1.
* Configures the execution permission in region 1 in REE2 mode.
*/
#define LP_APM0_REGION1_R2_X (BIT(8))
#define LP_APM0_REGION1_R2_X_M (LP_APM0_REGION1_R2_X_V << LP_APM0_REGION1_R2_X_S)
#define LP_APM0_REGION1_R2_X_V 0x00000001U
#define LP_APM0_REGION1_R2_X_S 8
/** LP_APM0_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 1.
* Configures the write permission in region 1 in REE2 mode.
*/
#define LP_APM0_REGION1_R2_W (BIT(9))
#define LP_APM0_REGION1_R2_W_M (LP_APM0_REGION1_R2_W_V << LP_APM0_REGION1_R2_W_S)
#define LP_APM0_REGION1_R2_W_V 0x00000001U
#define LP_APM0_REGION1_R2_W_S 9
/** LP_APM0_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 1.
* Configures the read permission in region 1 in REE2 mode.
*/
#define LP_APM0_REGION1_R2_R (BIT(10))
#define LP_APM0_REGION1_R2_R_M (LP_APM0_REGION1_R2_R_V << LP_APM0_REGION1_R2_R_S)
#define LP_APM0_REGION1_R2_R_V 0x00000001U
#define LP_APM0_REGION1_R2_R_S 10
/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 1 configuration registers
* (LP_APM0_REGION1_ADDR_START_REG, LP_APM0_REGION1_ADDR_END_REG and
* LP_APM0_REGION1_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION1_LOCK (BIT(11))
#define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S)
@ -228,7 +236,7 @@ extern "C" {
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 2
* Configures the start address of region 2.
*/
#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
@ -240,7 +248,7 @@ extern "C" {
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 2
* Configures the end address of region 2.
*/
#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
@ -248,74 +256,78 @@ extern "C" {
#define LP_APM0_REGION2_ADDR_END_S 0
/** LP_APM0_REGION2_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION2_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 2.
* Configures the execution permission in region 2 in REE0 mode.
*/
#define LP_APM0_REGION2_R0_X (BIT(0))
#define LP_APM0_REGION2_R0_X_M (LP_APM0_REGION2_R0_X_V << LP_APM0_REGION2_R0_X_S)
#define LP_APM0_REGION2_R0_X_V 0x00000001U
#define LP_APM0_REGION2_R0_X_S 0
/** LP_APM0_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 2.
* Configures the write permission in region 2 in REE0 mode.
*/
#define LP_APM0_REGION2_R0_W (BIT(1))
#define LP_APM0_REGION2_R0_W_M (LP_APM0_REGION2_R0_W_V << LP_APM0_REGION2_R0_W_S)
#define LP_APM0_REGION2_R0_W_V 0x00000001U
#define LP_APM0_REGION2_R0_W_S 1
/** LP_APM0_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 2.
* Configures the read permission in region 2 in REE0 mode.
*/
#define LP_APM0_REGION2_R0_R (BIT(2))
#define LP_APM0_REGION2_R0_R_M (LP_APM0_REGION2_R0_R_V << LP_APM0_REGION2_R0_R_S)
#define LP_APM0_REGION2_R0_R_V 0x00000001U
#define LP_APM0_REGION2_R0_R_S 2
/** LP_APM0_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 2.
* Configures the execution permission in region 2 in REE1 mode.
*/
#define LP_APM0_REGION2_R1_X (BIT(4))
#define LP_APM0_REGION2_R1_X_M (LP_APM0_REGION2_R1_X_V << LP_APM0_REGION2_R1_X_S)
#define LP_APM0_REGION2_R1_X_V 0x00000001U
#define LP_APM0_REGION2_R1_X_S 4
/** LP_APM0_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 2.
* Configures the write permission in region 2 in REE1 mode.
*/
#define LP_APM0_REGION2_R1_W (BIT(5))
#define LP_APM0_REGION2_R1_W_M (LP_APM0_REGION2_R1_W_V << LP_APM0_REGION2_R1_W_S)
#define LP_APM0_REGION2_R1_W_V 0x00000001U
#define LP_APM0_REGION2_R1_W_S 5
/** LP_APM0_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 2.
* Configures the read permission in region 2 in REE1 mode.
*/
#define LP_APM0_REGION2_R1_R (BIT(6))
#define LP_APM0_REGION2_R1_R_M (LP_APM0_REGION2_R1_R_V << LP_APM0_REGION2_R1_R_S)
#define LP_APM0_REGION2_R1_R_V 0x00000001U
#define LP_APM0_REGION2_R1_R_S 6
/** LP_APM0_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 2.
* Configures the execution permission in region 2 in REE2 mode.
*/
#define LP_APM0_REGION2_R2_X (BIT(8))
#define LP_APM0_REGION2_R2_X_M (LP_APM0_REGION2_R2_X_V << LP_APM0_REGION2_R2_X_S)
#define LP_APM0_REGION2_R2_X_V 0x00000001U
#define LP_APM0_REGION2_R2_X_S 8
/** LP_APM0_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 2.
* Configures the write permission in region 2 in REE2 mode.
*/
#define LP_APM0_REGION2_R2_W (BIT(9))
#define LP_APM0_REGION2_R2_W_M (LP_APM0_REGION2_R2_W_V << LP_APM0_REGION2_R2_W_S)
#define LP_APM0_REGION2_R2_W_V 0x00000001U
#define LP_APM0_REGION2_R2_W_S 9
/** LP_APM0_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 2.
* Configures the read permission in region 2 in REE2 mode.
*/
#define LP_APM0_REGION2_R2_R (BIT(10))
#define LP_APM0_REGION2_R2_R_M (LP_APM0_REGION2_R2_R_V << LP_APM0_REGION2_R2_R_S)
#define LP_APM0_REGION2_R2_R_V 0x00000001U
#define LP_APM0_REGION2_R2_R_S 10
/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 2 configuration registers
* (LP_APM0_REGION2_ADDR_START_REG, LP_APM0_REGION2_ADDR_END_REG and
* LP_APM0_REGION2_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION2_LOCK (BIT(11))
#define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S)
@ -327,7 +339,7 @@ extern "C" {
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 3
* Configures the start address of region 3.
*/
#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
@ -339,7 +351,7 @@ extern "C" {
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 3
* Configures the end address of region 3.
*/
#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
@ -347,74 +359,78 @@ extern "C" {
#define LP_APM0_REGION3_ADDR_END_S 0
/** LP_APM0_REGION3_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION3_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 3.
* Configures the execution permission in region 3 in REE0 mode.
*/
#define LP_APM0_REGION3_R0_X (BIT(0))
#define LP_APM0_REGION3_R0_X_M (LP_APM0_REGION3_R0_X_V << LP_APM0_REGION3_R0_X_S)
#define LP_APM0_REGION3_R0_X_V 0x00000001U
#define LP_APM0_REGION3_R0_X_S 0
/** LP_APM0_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 3.
* Configures the write permission in region 3 in REE0 mode.
*/
#define LP_APM0_REGION3_R0_W (BIT(1))
#define LP_APM0_REGION3_R0_W_M (LP_APM0_REGION3_R0_W_V << LP_APM0_REGION3_R0_W_S)
#define LP_APM0_REGION3_R0_W_V 0x00000001U
#define LP_APM0_REGION3_R0_W_S 1
/** LP_APM0_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 3.
* Configures the read permission in region 3 in REE0 mode.
*/
#define LP_APM0_REGION3_R0_R (BIT(2))
#define LP_APM0_REGION3_R0_R_M (LP_APM0_REGION3_R0_R_V << LP_APM0_REGION3_R0_R_S)
#define LP_APM0_REGION3_R0_R_V 0x00000001U
#define LP_APM0_REGION3_R0_R_S 2
/** LP_APM0_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 3.
* Configures the execution permission in region 3 in REE1 mode.
*/
#define LP_APM0_REGION3_R1_X (BIT(4))
#define LP_APM0_REGION3_R1_X_M (LP_APM0_REGION3_R1_X_V << LP_APM0_REGION3_R1_X_S)
#define LP_APM0_REGION3_R1_X_V 0x00000001U
#define LP_APM0_REGION3_R1_X_S 4
/** LP_APM0_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 3.
* Configures the write permission in region 3 in REE1 mode.
*/
#define LP_APM0_REGION3_R1_W (BIT(5))
#define LP_APM0_REGION3_R1_W_M (LP_APM0_REGION3_R1_W_V << LP_APM0_REGION3_R1_W_S)
#define LP_APM0_REGION3_R1_W_V 0x00000001U
#define LP_APM0_REGION3_R1_W_S 5
/** LP_APM0_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 3.
* Configures the read permission in region 3 in REE1 mode.
*/
#define LP_APM0_REGION3_R1_R (BIT(6))
#define LP_APM0_REGION3_R1_R_M (LP_APM0_REGION3_R1_R_V << LP_APM0_REGION3_R1_R_S)
#define LP_APM0_REGION3_R1_R_V 0x00000001U
#define LP_APM0_REGION3_R1_R_S 6
/** LP_APM0_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 3.
* Configures the execution permission in region 3 in REE2 mode.
*/
#define LP_APM0_REGION3_R2_X (BIT(8))
#define LP_APM0_REGION3_R2_X_M (LP_APM0_REGION3_R2_X_V << LP_APM0_REGION3_R2_X_S)
#define LP_APM0_REGION3_R2_X_V 0x00000001U
#define LP_APM0_REGION3_R2_X_S 8
/** LP_APM0_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 3.
* Configures the write permission in region 3 in REE2 mode.
*/
#define LP_APM0_REGION3_R2_W (BIT(9))
#define LP_APM0_REGION3_R2_W_M (LP_APM0_REGION3_R2_W_V << LP_APM0_REGION3_R2_W_S)
#define LP_APM0_REGION3_R2_W_V 0x00000001U
#define LP_APM0_REGION3_R2_W_S 9
/** LP_APM0_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 3.
* Configures the read permission in region 3 in REE2 mode.
*/
#define LP_APM0_REGION3_R2_R (BIT(10))
#define LP_APM0_REGION3_R2_R_M (LP_APM0_REGION3_R2_R_V << LP_APM0_REGION3_R2_R_S)
#define LP_APM0_REGION3_R2_R_V 0x00000001U
#define LP_APM0_REGION3_R2_R_S 10
/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 3 configuration registers
* (LP_APM0_REGION3_ADDR_START_REG, LP_APM0_REGION3_ADDR_END_REG and
* LP_APM0_REGION3_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION3_LOCK (BIT(11))
#define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S)
@ -426,7 +442,7 @@ extern "C" {
*/
#define LP_APM0_REGION4_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x34)
/** LP_APM0_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 4
* Configures the start address of region 4.
*/
#define LP_APM0_REGION4_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION4_ADDR_START_M (LP_APM0_REGION4_ADDR_START_V << LP_APM0_REGION4_ADDR_START_S)
@ -438,7 +454,7 @@ extern "C" {
*/
#define LP_APM0_REGION4_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x38)
/** LP_APM0_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 4
* Configures the end address of region 4.
*/
#define LP_APM0_REGION4_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION4_ADDR_END_M (LP_APM0_REGION4_ADDR_END_V << LP_APM0_REGION4_ADDR_END_S)
@ -446,74 +462,78 @@ extern "C" {
#define LP_APM0_REGION4_ADDR_END_S 0
/** LP_APM0_REGION4_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION4_ATTR_REG (DR_REG_LP_APM0_BASE + 0x3c)
/** LP_APM0_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 4.
* Configures the execution permission in region 4 in REE0 mode.
*/
#define LP_APM0_REGION4_R0_X (BIT(0))
#define LP_APM0_REGION4_R0_X_M (LP_APM0_REGION4_R0_X_V << LP_APM0_REGION4_R0_X_S)
#define LP_APM0_REGION4_R0_X_V 0x00000001U
#define LP_APM0_REGION4_R0_X_S 0
/** LP_APM0_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 4.
* Configures the write permission in region 4 in REE0 mode.
*/
#define LP_APM0_REGION4_R0_W (BIT(1))
#define LP_APM0_REGION4_R0_W_M (LP_APM0_REGION4_R0_W_V << LP_APM0_REGION4_R0_W_S)
#define LP_APM0_REGION4_R0_W_V 0x00000001U
#define LP_APM0_REGION4_R0_W_S 1
/** LP_APM0_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 4.
* Configures the read permission in region 4 in REE0 mode.
*/
#define LP_APM0_REGION4_R0_R (BIT(2))
#define LP_APM0_REGION4_R0_R_M (LP_APM0_REGION4_R0_R_V << LP_APM0_REGION4_R0_R_S)
#define LP_APM0_REGION4_R0_R_V 0x00000001U
#define LP_APM0_REGION4_R0_R_S 2
/** LP_APM0_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 4.
* Configures the execution permission in region 4 in REE1 mode.
*/
#define LP_APM0_REGION4_R1_X (BIT(4))
#define LP_APM0_REGION4_R1_X_M (LP_APM0_REGION4_R1_X_V << LP_APM0_REGION4_R1_X_S)
#define LP_APM0_REGION4_R1_X_V 0x00000001U
#define LP_APM0_REGION4_R1_X_S 4
/** LP_APM0_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 4.
* Configures the write permission in region 4 in REE1 mode.
*/
#define LP_APM0_REGION4_R1_W (BIT(5))
#define LP_APM0_REGION4_R1_W_M (LP_APM0_REGION4_R1_W_V << LP_APM0_REGION4_R1_W_S)
#define LP_APM0_REGION4_R1_W_V 0x00000001U
#define LP_APM0_REGION4_R1_W_S 5
/** LP_APM0_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 4.
* Configures the read permission in region 4 in REE1 mode.
*/
#define LP_APM0_REGION4_R1_R (BIT(6))
#define LP_APM0_REGION4_R1_R_M (LP_APM0_REGION4_R1_R_V << LP_APM0_REGION4_R1_R_S)
#define LP_APM0_REGION4_R1_R_V 0x00000001U
#define LP_APM0_REGION4_R1_R_S 6
/** LP_APM0_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 4.
* Configures the execution permission in region 4 in REE2 mode.
*/
#define LP_APM0_REGION4_R2_X (BIT(8))
#define LP_APM0_REGION4_R2_X_M (LP_APM0_REGION4_R2_X_V << LP_APM0_REGION4_R2_X_S)
#define LP_APM0_REGION4_R2_X_V 0x00000001U
#define LP_APM0_REGION4_R2_X_S 8
/** LP_APM0_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 4.
* Configures the write permission in region 4 in REE2 mode.
*/
#define LP_APM0_REGION4_R2_W (BIT(9))
#define LP_APM0_REGION4_R2_W_M (LP_APM0_REGION4_R2_W_V << LP_APM0_REGION4_R2_W_S)
#define LP_APM0_REGION4_R2_W_V 0x00000001U
#define LP_APM0_REGION4_R2_W_S 9
/** LP_APM0_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 4.
* Configures the read permission in region 4 in REE2 mode.
*/
#define LP_APM0_REGION4_R2_R (BIT(10))
#define LP_APM0_REGION4_R2_R_M (LP_APM0_REGION4_R2_R_V << LP_APM0_REGION4_R2_R_S)
#define LP_APM0_REGION4_R2_R_V 0x00000001U
#define LP_APM0_REGION4_R2_R_S 10
/** LP_APM0_REGION4_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 4 configuration registers
* (LP_APM0_REGION4_ADDR_START_REG, LP_APM0_REGION4_ADDR_END_REG and
* LP_APM0_REGION4_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION4_LOCK (BIT(11))
#define LP_APM0_REGION4_LOCK_M (LP_APM0_REGION4_LOCK_V << LP_APM0_REGION4_LOCK_S)
@ -525,7 +545,7 @@ extern "C" {
*/
#define LP_APM0_REGION5_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x40)
/** LP_APM0_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 5
* Configures the start address of region 5.
*/
#define LP_APM0_REGION5_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION5_ADDR_START_M (LP_APM0_REGION5_ADDR_START_V << LP_APM0_REGION5_ADDR_START_S)
@ -537,7 +557,7 @@ extern "C" {
*/
#define LP_APM0_REGION5_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x44)
/** LP_APM0_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 5
* Configures the end address of region 5.
*/
#define LP_APM0_REGION5_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION5_ADDR_END_M (LP_APM0_REGION5_ADDR_END_V << LP_APM0_REGION5_ADDR_END_S)
@ -545,74 +565,78 @@ extern "C" {
#define LP_APM0_REGION5_ADDR_END_S 0
/** LP_APM0_REGION5_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION5_ATTR_REG (DR_REG_LP_APM0_BASE + 0x48)
/** LP_APM0_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 5.
* Configures the execution permission in region 5 in REE0 mode.
*/
#define LP_APM0_REGION5_R0_X (BIT(0))
#define LP_APM0_REGION5_R0_X_M (LP_APM0_REGION5_R0_X_V << LP_APM0_REGION5_R0_X_S)
#define LP_APM0_REGION5_R0_X_V 0x00000001U
#define LP_APM0_REGION5_R0_X_S 0
/** LP_APM0_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 5.
* Configures the write permission in region 5 in REE0 mode.
*/
#define LP_APM0_REGION5_R0_W (BIT(1))
#define LP_APM0_REGION5_R0_W_M (LP_APM0_REGION5_R0_W_V << LP_APM0_REGION5_R0_W_S)
#define LP_APM0_REGION5_R0_W_V 0x00000001U
#define LP_APM0_REGION5_R0_W_S 1
/** LP_APM0_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 5.
* Configures the read permission in region 5 in REE0 mode.
*/
#define LP_APM0_REGION5_R0_R (BIT(2))
#define LP_APM0_REGION5_R0_R_M (LP_APM0_REGION5_R0_R_V << LP_APM0_REGION5_R0_R_S)
#define LP_APM0_REGION5_R0_R_V 0x00000001U
#define LP_APM0_REGION5_R0_R_S 2
/** LP_APM0_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 5.
* Configures the execution permission in region 5 in REE1 mode.
*/
#define LP_APM0_REGION5_R1_X (BIT(4))
#define LP_APM0_REGION5_R1_X_M (LP_APM0_REGION5_R1_X_V << LP_APM0_REGION5_R1_X_S)
#define LP_APM0_REGION5_R1_X_V 0x00000001U
#define LP_APM0_REGION5_R1_X_S 4
/** LP_APM0_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 5.
* Configures the write permission in region 5 in REE1 mode.
*/
#define LP_APM0_REGION5_R1_W (BIT(5))
#define LP_APM0_REGION5_R1_W_M (LP_APM0_REGION5_R1_W_V << LP_APM0_REGION5_R1_W_S)
#define LP_APM0_REGION5_R1_W_V 0x00000001U
#define LP_APM0_REGION5_R1_W_S 5
/** LP_APM0_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 5.
* Configures the read permission in region 5 in REE1 mode.
*/
#define LP_APM0_REGION5_R1_R (BIT(6))
#define LP_APM0_REGION5_R1_R_M (LP_APM0_REGION5_R1_R_V << LP_APM0_REGION5_R1_R_S)
#define LP_APM0_REGION5_R1_R_V 0x00000001U
#define LP_APM0_REGION5_R1_R_S 6
/** LP_APM0_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 5.
* Configures the execution permission in region 5 in REE2 mode.
*/
#define LP_APM0_REGION5_R2_X (BIT(8))
#define LP_APM0_REGION5_R2_X_M (LP_APM0_REGION5_R2_X_V << LP_APM0_REGION5_R2_X_S)
#define LP_APM0_REGION5_R2_X_V 0x00000001U
#define LP_APM0_REGION5_R2_X_S 8
/** LP_APM0_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 5.
* Configures the write permission in region 5 in REE2 mode.
*/
#define LP_APM0_REGION5_R2_W (BIT(9))
#define LP_APM0_REGION5_R2_W_M (LP_APM0_REGION5_R2_W_V << LP_APM0_REGION5_R2_W_S)
#define LP_APM0_REGION5_R2_W_V 0x00000001U
#define LP_APM0_REGION5_R2_W_S 9
/** LP_APM0_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 5.
* Configures the read permission in region 5 in REE2 mode.
*/
#define LP_APM0_REGION5_R2_R (BIT(10))
#define LP_APM0_REGION5_R2_R_M (LP_APM0_REGION5_R2_R_V << LP_APM0_REGION5_R2_R_S)
#define LP_APM0_REGION5_R2_R_V 0x00000001U
#define LP_APM0_REGION5_R2_R_S 10
/** LP_APM0_REGION5_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 5 configuration registers
* (LP_APM0_REGION5_ADDR_START_REG, LP_APM0_REGION5_ADDR_END_REG and
* LP_APM0_REGION5_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION5_LOCK (BIT(11))
#define LP_APM0_REGION5_LOCK_M (LP_APM0_REGION5_LOCK_V << LP_APM0_REGION5_LOCK_S)
@ -624,7 +648,7 @@ extern "C" {
*/
#define LP_APM0_REGION6_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4c)
/** LP_APM0_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 6
* Configures the start address of region 6.
*/
#define LP_APM0_REGION6_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION6_ADDR_START_M (LP_APM0_REGION6_ADDR_START_V << LP_APM0_REGION6_ADDR_START_S)
@ -636,7 +660,7 @@ extern "C" {
*/
#define LP_APM0_REGION6_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x50)
/** LP_APM0_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 6
* Configures the end address of region 6.
*/
#define LP_APM0_REGION6_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION6_ADDR_END_M (LP_APM0_REGION6_ADDR_END_V << LP_APM0_REGION6_ADDR_END_S)
@ -644,74 +668,78 @@ extern "C" {
#define LP_APM0_REGION6_ADDR_END_S 0
/** LP_APM0_REGION6_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION6_ATTR_REG (DR_REG_LP_APM0_BASE + 0x54)
/** LP_APM0_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 6.
* Configures the execution permission in region 6 in REE0 mode.
*/
#define LP_APM0_REGION6_R0_X (BIT(0))
#define LP_APM0_REGION6_R0_X_M (LP_APM0_REGION6_R0_X_V << LP_APM0_REGION6_R0_X_S)
#define LP_APM0_REGION6_R0_X_V 0x00000001U
#define LP_APM0_REGION6_R0_X_S 0
/** LP_APM0_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 6.
* Configures the write permission in region 6 in REE0 mode.
*/
#define LP_APM0_REGION6_R0_W (BIT(1))
#define LP_APM0_REGION6_R0_W_M (LP_APM0_REGION6_R0_W_V << LP_APM0_REGION6_R0_W_S)
#define LP_APM0_REGION6_R0_W_V 0x00000001U
#define LP_APM0_REGION6_R0_W_S 1
/** LP_APM0_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 6.
* Configures the read permission in region 6 in REE0 mode.
*/
#define LP_APM0_REGION6_R0_R (BIT(2))
#define LP_APM0_REGION6_R0_R_M (LP_APM0_REGION6_R0_R_V << LP_APM0_REGION6_R0_R_S)
#define LP_APM0_REGION6_R0_R_V 0x00000001U
#define LP_APM0_REGION6_R0_R_S 2
/** LP_APM0_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 6.
* Configures the execution permission in region 6 in REE1 mode.
*/
#define LP_APM0_REGION6_R1_X (BIT(4))
#define LP_APM0_REGION6_R1_X_M (LP_APM0_REGION6_R1_X_V << LP_APM0_REGION6_R1_X_S)
#define LP_APM0_REGION6_R1_X_V 0x00000001U
#define LP_APM0_REGION6_R1_X_S 4
/** LP_APM0_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 6.
* Configures the write permission in region 6 in REE1 mode.
*/
#define LP_APM0_REGION6_R1_W (BIT(5))
#define LP_APM0_REGION6_R1_W_M (LP_APM0_REGION6_R1_W_V << LP_APM0_REGION6_R1_W_S)
#define LP_APM0_REGION6_R1_W_V 0x00000001U
#define LP_APM0_REGION6_R1_W_S 5
/** LP_APM0_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 6.
* Configures the read permission in region 6 in REE1 mode.
*/
#define LP_APM0_REGION6_R1_R (BIT(6))
#define LP_APM0_REGION6_R1_R_M (LP_APM0_REGION6_R1_R_V << LP_APM0_REGION6_R1_R_S)
#define LP_APM0_REGION6_R1_R_V 0x00000001U
#define LP_APM0_REGION6_R1_R_S 6
/** LP_APM0_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 6.
* Configures the execution permission in region 6 in REE2 mode.
*/
#define LP_APM0_REGION6_R2_X (BIT(8))
#define LP_APM0_REGION6_R2_X_M (LP_APM0_REGION6_R2_X_V << LP_APM0_REGION6_R2_X_S)
#define LP_APM0_REGION6_R2_X_V 0x00000001U
#define LP_APM0_REGION6_R2_X_S 8
/** LP_APM0_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 6.
* Configures the write permission in region 6 in REE2 mode.
*/
#define LP_APM0_REGION6_R2_W (BIT(9))
#define LP_APM0_REGION6_R2_W_M (LP_APM0_REGION6_R2_W_V << LP_APM0_REGION6_R2_W_S)
#define LP_APM0_REGION6_R2_W_V 0x00000001U
#define LP_APM0_REGION6_R2_W_S 9
/** LP_APM0_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 6.
* Configures the read permission in region 6 in REE2 mode.
*/
#define LP_APM0_REGION6_R2_R (BIT(10))
#define LP_APM0_REGION6_R2_R_M (LP_APM0_REGION6_R2_R_V << LP_APM0_REGION6_R2_R_S)
#define LP_APM0_REGION6_R2_R_V 0x00000001U
#define LP_APM0_REGION6_R2_R_S 10
/** LP_APM0_REGION6_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 6 configuration registers
* (LP_APM0_REGION6_ADDR_START_REG, LP_APM0_REGION6_ADDR_END_REG and
* LP_APM0_REGION6_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION6_LOCK (BIT(11))
#define LP_APM0_REGION6_LOCK_M (LP_APM0_REGION6_LOCK_V << LP_APM0_REGION6_LOCK_S)
@ -723,7 +751,7 @@ extern "C" {
*/
#define LP_APM0_REGION7_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x58)
/** LP_APM0_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 7
* Configures the start address of region 7.
*/
#define LP_APM0_REGION7_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION7_ADDR_START_M (LP_APM0_REGION7_ADDR_START_V << LP_APM0_REGION7_ADDR_START_S)
@ -735,7 +763,7 @@ extern "C" {
*/
#define LP_APM0_REGION7_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x5c)
/** LP_APM0_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 7
* Configures the end address of region 7.
*/
#define LP_APM0_REGION7_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION7_ADDR_END_M (LP_APM0_REGION7_ADDR_END_V << LP_APM0_REGION7_ADDR_END_S)
@ -743,74 +771,78 @@ extern "C" {
#define LP_APM0_REGION7_ADDR_END_S 0
/** LP_APM0_REGION7_ATTR_REG register
* Region access authority attribute register
* Region access permissions configuration register
*/
#define LP_APM0_REGION7_ATTR_REG (DR_REG_LP_APM0_BASE + 0x60)
/** LP_APM0_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 7.
* Configures the execution permission in region 7 in REE0 mode.
*/
#define LP_APM0_REGION7_R0_X (BIT(0))
#define LP_APM0_REGION7_R0_X_M (LP_APM0_REGION7_R0_X_V << LP_APM0_REGION7_R0_X_S)
#define LP_APM0_REGION7_R0_X_V 0x00000001U
#define LP_APM0_REGION7_R0_X_S 0
/** LP_APM0_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 7.
* Configures the write permission in region 7 in REE0 mode.
*/
#define LP_APM0_REGION7_R0_W (BIT(1))
#define LP_APM0_REGION7_R0_W_M (LP_APM0_REGION7_R0_W_V << LP_APM0_REGION7_R0_W_S)
#define LP_APM0_REGION7_R0_W_V 0x00000001U
#define LP_APM0_REGION7_R0_W_S 1
/** LP_APM0_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 7.
* Configures the read permission in region 7 in REE0 mode.
*/
#define LP_APM0_REGION7_R0_R (BIT(2))
#define LP_APM0_REGION7_R0_R_M (LP_APM0_REGION7_R0_R_V << LP_APM0_REGION7_R0_R_S)
#define LP_APM0_REGION7_R0_R_V 0x00000001U
#define LP_APM0_REGION7_R0_R_S 2
/** LP_APM0_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 7.
* Configures the execution permission in region 7 in REE1 mode.
*/
#define LP_APM0_REGION7_R1_X (BIT(4))
#define LP_APM0_REGION7_R1_X_M (LP_APM0_REGION7_R1_X_V << LP_APM0_REGION7_R1_X_S)
#define LP_APM0_REGION7_R1_X_V 0x00000001U
#define LP_APM0_REGION7_R1_X_S 4
/** LP_APM0_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 7.
* Configures the write permission in region 7 in REE1 mode.
*/
#define LP_APM0_REGION7_R1_W (BIT(5))
#define LP_APM0_REGION7_R1_W_M (LP_APM0_REGION7_R1_W_V << LP_APM0_REGION7_R1_W_S)
#define LP_APM0_REGION7_R1_W_V 0x00000001U
#define LP_APM0_REGION7_R1_W_S 5
/** LP_APM0_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 7.
* Configures the read permission in region 7 in REE1 mode.
*/
#define LP_APM0_REGION7_R1_R (BIT(6))
#define LP_APM0_REGION7_R1_R_M (LP_APM0_REGION7_R1_R_V << LP_APM0_REGION7_R1_R_S)
#define LP_APM0_REGION7_R1_R_V 0x00000001U
#define LP_APM0_REGION7_R1_R_S 6
/** LP_APM0_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 7.
* Configures the execution permission in region 7 in REE2 mode.
*/
#define LP_APM0_REGION7_R2_X (BIT(8))
#define LP_APM0_REGION7_R2_X_M (LP_APM0_REGION7_R2_X_V << LP_APM0_REGION7_R2_X_S)
#define LP_APM0_REGION7_R2_X_V 0x00000001U
#define LP_APM0_REGION7_R2_X_S 8
/** LP_APM0_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 7.
* Configures the write permission in region 7 in REE2 mode.
*/
#define LP_APM0_REGION7_R2_W (BIT(9))
#define LP_APM0_REGION7_R2_W_M (LP_APM0_REGION7_R2_W_V << LP_APM0_REGION7_R2_W_S)
#define LP_APM0_REGION7_R2_W_V 0x00000001U
#define LP_APM0_REGION7_R2_W_S 9
/** LP_APM0_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 7.
* Configures the read permission in region 7 in REE2 mode.
*/
#define LP_APM0_REGION7_R2_R (BIT(10))
#define LP_APM0_REGION7_R2_R_M (LP_APM0_REGION7_R2_R_V << LP_APM0_REGION7_R2_R_S)
#define LP_APM0_REGION7_R2_R_V 0x00000001U
#define LP_APM0_REGION7_R2_R_S 10
/** LP_APM0_REGION7_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region 7 configuration registers
* (LP_APM0_REGION7_ADDR_START_REG, LP_APM0_REGION7_ADDR_END_REG and
* LP_APM0_REGION7_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
#define LP_APM0_REGION7_LOCK (BIT(11))
#define LP_APM0_REGION7_LOCK_M (LP_APM0_REGION7_LOCK_V << LP_APM0_REGION7_LOCK_S)
@ -818,11 +850,11 @@ extern "C" {
#define LP_APM0_REGION7_LOCK_S 11
/** LP_APM0_FUNC_CTRL_REG register
* APM function control register
* APM access path permission management register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
* Configures to enable permission management for LP_APM0_CTRL M0.
*/
#define LP_APM0_M0_FUNC_EN (BIT(0))
#define LP_APM0_M0_FUNC_EN_M (LP_APM0_M0_FUNC_EN_V << LP_APM0_M0_FUNC_EN_S)
@ -830,13 +862,13 @@ extern "C" {
#define LP_APM0_M0_FUNC_EN_S 0
/** LP_APM0_M0_STATUS_REG register
* M0 status register
* LP_APM0_CTRL M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
@ -844,11 +876,11 @@ extern "C" {
#define LP_APM0_M0_EXCEPTION_STATUS_S 0
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
* LP_APM0_CTRL M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status
* Configures to clear exception status.
*/
#define LP_APM0_M0_EXCEPTION_STATUS_CLR (BIT(0))
#define LP_APM0_M0_EXCEPTION_STATUS_CLR_M (LP_APM0_M0_EXCEPTION_STATUS_CLR_V << LP_APM0_M0_EXCEPTION_STATUS_CLR_S)
@ -856,25 +888,25 @@ extern "C" {
#define LP_APM0_M0_EXCEPTION_STATUS_CLR_S 0
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
* LP_APM0_CTRL M0 exception information register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
* Represents exception region
* Represents the region where an exception occurs.
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x000000FFU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x000000FFU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode
* Represents the master's security mode when an exception occurs.
*/
#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_S 16
/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Represents exception id information
* Represents master ID when an exception occurs.
*/
#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
@ -882,11 +914,11 @@ extern "C" {
#define LP_APM0_M0_EXCEPTION_ID_S 18
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
* LP_APM0_CTRL M0 exception information register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr
* Represents the access address when an exception occurs.
*/
#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
@ -894,13 +926,13 @@ extern "C" {
#define LP_APM0_M0_EXCEPTION_ADDR_S 0
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
* LP_APM0_CTRL interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures APM M0 interrupt enable.
* 0: disable
* 1: enable
* Configures to enable LP_APM0_CTRL M0 interrupt.
* 0: Disable
* 1: Enable
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
@ -913,8 +945,8 @@ extern "C" {
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
@ -926,7 +958,7 @@ extern "C" {
*/
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664;
* Version control register
* Version control register.
*/
#define LP_APM0_DATE 0x0FFFFFFFU
#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S)

100
components/soc/esp32c5/register/soc/lp_apm0_struct.h
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@ -10,16 +10,16 @@
extern "C" {
#endif
/** Group: Region filter enable register */
/** Group: Configuration Registers */
/** Type of region_filter_en register
* Region filter enable register
* Region enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n(0-7) to enable region $n.
* 0: disable
* 1: enable
* Configure bit $n (0-7) to enable region $n (0-7).
* 0: Disable
* 1: Enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
@ -27,15 +27,13 @@ typedef union {
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n
* Configures the start address of region n.
*/
uint32_t regionn_addr_start:32;
};
@ -48,60 +46,62 @@ typedef union {
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n
* Configures the end address of region n.
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} lp_apm0_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
* Region access permissions configuration register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
* Configures the execution permission in region n in REE0 mode.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
* Configures the write permission in region n in REE0 mode.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
* Configures the read permission in region n in REE0 mode.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
* Configures the execution permission in region n in REE1 mode.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
* Configures the write permission in region n in REE1 mode.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
* Configures the read permission in region n in REE1 mode.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
* Configures the execution permission in region n in REE2 mode.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
* Configures the write permission in region n in REE2 mode.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
* Configures the read permission in region n in REE2 mode.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region n configuration registers
* (LP_APM0_REGIONn_ADDR_START_REG, LP_APM0_REGIONn_ADDR_END_REG and
* LP_APM0_REGIONn_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
@ -109,15 +109,13 @@ typedef union {
uint32_t val;
} lp_apm0_regionn_attr_reg_t;
/** Group: APM function control register */
/** Type of func_ctrl register
* APM function control register
* APM access path permission management register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
* Configures to enable permission management for LP_APM0_CTRL M0.
*/
uint32_t m0_func_en:1;
uint32_t reserved_1:31;
@ -126,16 +124,16 @@ typedef union {
} lp_apm0_func_ctrl_reg_t;
/** Group: M0 status register */
/** Group: Status Registers */
/** Type of m0_status register
* M0 status register
* LP_APM0_CTRL M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
@ -143,15 +141,13 @@ typedef union {
uint32_t val;
} lp_apm0_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
* LP_APM0_CTRL M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
@ -159,24 +155,22 @@ typedef union {
uint32_t val;
} lp_apm0_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
* LP_APM0_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region
* Represents the region where an exception occurs.
*/
uint32_t m0_exception_region:8;
uint32_t reserved_8:8;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode
* Represents the master's security mode when an exception occurs.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information
* Represents master ID when an exception occurs.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
@ -184,15 +178,13 @@ typedef union {
uint32_t val;
} lp_apm0_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
* LP_APM0_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr
* Represents the access address when an exception occurs.
*/
uint32_t m0_exception_addr:32;
};
@ -200,16 +192,16 @@ typedef union {
} lp_apm0_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Group: Interrupt Registers */
/** Type of int_en register
* APM interrupt enable register
* LP_APM0_CTRL interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures APM M0 interrupt enable.
* 0: disable
* 1: enable
* Configures to enable LP_APM0_CTRL M0 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
@ -218,7 +210,7 @@ typedef union {
} lp_apm0_int_en_reg_t;
/** Group: Clock gating register */
/** Group: Clock Gating Registers */
/** Type of clock_gate register
* Clock gating register
*/
@ -226,8 +218,8 @@ typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@ -236,14 +228,14 @@ typedef union {
} lp_apm0_clock_gate_reg_t;
/** Group: Version control register */
/** Group: Version Control Registers */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* Version control register
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;

314
components/soc/esp32c5/register/soc/lp_apm_reg.h
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134
components/soc/esp32c5/register/soc/lp_apm_struct.h
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@ -10,16 +10,16 @@
extern "C" {
#endif
/** Group: Region filter enable register */
/** Group: Configuration Registers */
/** Type of region_filter_en register
* Region filter enable register
* Region enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
* Configure bit $n (0-7) to enable region $n (0-7).
* 0: Disable
* 1: Enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
@ -27,15 +27,13 @@ typedef union {
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n.
* Configures the start address of region n.
*/
uint32_t regionn_addr_start:32;
};
@ -48,60 +46,62 @@ typedef union {
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n.
* Configures the end address of region n.
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} lp_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
* Region access permissions configuration register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
* Configures the execution permission in region n in REE0 mode.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
* Configures the write permission in region n in REE0 mode.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
* Configures the read permission in region n in REE0 mode.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
* Configures the execution permission in region n in REE1 mode.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
* Configures the write permission in region n in REE1 mode.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
* Configures the read permission in region n in REE1 mode.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
* Configures the execution permission in region n in REE1 mode.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
* Configures the write permission in region n in REE2 mode.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
* Configures the read permission in region n in REE2 mode.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
* Configures to lock the value of region n configuration registers
* (LP_APM_REGIONn_ADDR_START_REG, LP_APM_REGIONn_ADDR_END_REG and
* LP_APM_REGIONn_ATTR_REG).
* 0: Do not lock
* 1: Lock
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
@ -109,19 +109,17 @@ typedef union {
uint32_t val;
} lp_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
* APM access path permission management register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
* Configures to enable permission management for LP_APM_CTRL M0.
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
* Configures to enable permission management for LP_APM_CTRL M1.
*/
uint32_t m1_func_en:1;
uint32_t reserved_2:30;
@ -130,16 +128,16 @@ typedef union {
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Group: Status Registers */
/** Type of m0_status register
* M0 status register
* LP_APM_CTRL M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
@ -147,10 +145,8 @@ typedef union {
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
* LP_APM_CTRL M0 status clear register
*/
typedef union {
struct {
@ -163,24 +159,22 @@ typedef union {
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
* LP_APM_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m0_exception_region:8;
uint32_t reserved_8:8;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
@ -188,32 +182,28 @@ typedef union {
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
* LP_APM_CTRL M0 exception information register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
* LP_APM_CTRL M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
* bit0: 1 represents permission restrictions
* bit1: 1 represents address out of bounds
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
@ -221,10 +211,8 @@ typedef union {
uint32_t val;
} lp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
* LP_APM_CTRL M1 status clear register
*/
typedef union {
struct {
@ -237,24 +225,22 @@ typedef union {
uint32_t val;
} lp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
* LP_APM_CTRL M1 exception information register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
* Represents the region where an exception occurs.
*/
uint32_t m1_exception_region:8;
uint32_t reserved_8:8;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
* Represents the master's security mode when an exception occurs.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
* Represents master ID when an exception occurs.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
@ -262,15 +248,13 @@ typedef union {
uint32_t val;
} lp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
* LP_APM_CTRL M1 exception information register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
* Represents the access address when an exception occurs.
*/
uint32_t m1_exception_addr:32;
};
@ -278,22 +262,22 @@ typedef union {
} lp_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Group: Interrupt Registers */
/** Type of int_en register
* APM interrupt enable register
* LP_APM_CTRL M0/1 interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
* Configures to enable LP_APM_CTRL M0 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
* Configures to enable LP_APM_CTRL M1 interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
@ -302,16 +286,16 @@ typedef union {
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Group: Clock Gating Registers */
/** Type of clock_gate register
* clock gating register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@ -320,7 +304,7 @@ typedef union {
} lp_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Group: Version Control Registers */
/** Type of date register
* Version control register
*/

143
components/soc/esp32c5/register/soc/lp_tee_reg.h
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@ -12,22 +12,24 @@ extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
* TEE mode control register
* Security mode configuration register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
* Configures M0 security level mode.
* 0: tee_mode
* 1: ree_mode0
* 2: ree_mode1
* 3: ree_mode2
* Configures the security mode for LP CPU.
* 0: TEE
* 1: REE0
* 2: REE1
* 3: REE2
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
#define LP_TEE_M0_MODE_V 0x00000003U
#define LP_TEE_M0_MODE_S 0
/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
* Configures to lock the value of LP_TEE_M0_MODE.
* 0: Do not lock
* 1: Lock
*/
#define LP_TEE_M0_LOCK (BIT(2))
#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S)
@ -35,7 +37,7 @@ extern "C" {
#define LP_TEE_M0_LOCK_S 2
/** LP_TEE_EFUSE_CTRL_REG register
* efuse read/write control register
* eFuse read/write control register
*/
#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1;
@ -112,7 +114,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_EFUSE_S 7
/** LP_TEE_PMU_CTRL_REG register
* pmu read/write control register
* PMU read/write control register
*/
#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8)
/** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1;
@ -189,7 +191,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_PMU_S 7
/** LP_TEE_CLKRST_CTRL_REG register
* clkrst read/write control register
* LP_CLKRST read/write control register
*/
#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc)
/** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1;
@ -266,7 +268,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_CLKRST_S 7
/** LP_TEE_LP_AON_CTRL_CTRL_REG register
* lp_aon_ctrl read/write control register
* LP_AON read/write control register
*/
#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10)
/** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1;
@ -343,7 +345,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_AON_CTRL_S 7
/** LP_TEE_LP_TIMER_CTRL_REG register
* lp_timer read/write control register
* LP_TIMER read/write control register
*/
#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14)
/** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1;
@ -420,7 +422,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_TIMER_S 7
/** LP_TEE_LP_WDT_CTRL_REG register
* lp_wdt read/write control register
* LP_WDT read/write control register
*/
#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18)
/** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1;
@ -497,7 +499,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_WDT_S 7
/** LP_TEE_LP_PERI_CTRL_REG register
* lp_peri read/write control register
* LPPERI read/write control register
*/
#define LP_TEE_LP_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c)
/** LP_TEE_READ_TEE_LP_PERI : R/W; bitpos: [0]; default: 1;
@ -574,7 +576,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_PERI_S 7
/** LP_TEE_LP_ANA_PERI_CTRL_REG register
* lp_ana_peri read/write control register
* LP_ANA_PERI read/write control register
*/
#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20)
/** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1;
@ -651,7 +653,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_ANA_PERI_S 7
/** LP_TEE_LP_IO_CTRL_REG register
* lp_io read/write control register
* LP_GPIO and LP_IO_MUX read/write control register
*/
#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c)
/** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1;
@ -728,7 +730,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_IO_S 7
/** LP_TEE_LP_TEE_CTRL_REG register
* lp_tee read/write control register
* LP_TEE read/write control register
*/
#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34)
/** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1;
@ -805,7 +807,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_TEE_S 7
/** LP_TEE_UART_CTRL_REG register
* uart read/write control register
* LP_UART read/write control register
*/
#define LP_TEE_UART_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38)
/** LP_TEE_READ_TEE_UART : R/W; bitpos: [0]; default: 1;
@ -882,7 +884,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_UART_S 7
/** LP_TEE_I2C_EXT_CTRL_REG register
* i2c_ext read/write control register
* LP_I2C read/write control register
*/
#define LP_TEE_I2C_EXT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x40)
/** LP_TEE_READ_TEE_I2C_EXT : R/W; bitpos: [0]; default: 1;
@ -959,7 +961,7 @@ extern "C" {
#define LP_TEE_WRITE_REE2_I2C_EXT_S 7
/** LP_TEE_I2C_ANA_MST_CTRL_REG register
* i2c_ana_mst read/write control register
* I2C_ANA_MST read/write control register
*/
#define LP_TEE_I2C_ANA_MST_CTRL_REG (DR_REG_LP_TEE_BASE + 0x44)
/** LP_TEE_READ_TEE_I2C_ANA_MST : R/W; bitpos: [0]; default: 1;
@ -1035,85 +1037,8 @@ extern "C" {
#define LP_TEE_WRITE_REE2_I2C_ANA_MST_V 0x00000001U
#define LP_TEE_WRITE_REE2_I2C_ANA_MST_S 7
/** LP_TEE_HUK_CTRL_REG register
* huk read/write control register
*/
#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x48)
/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1;
* Configures huk registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
#define LP_TEE_READ_TEE_HUK (BIT(0))
#define LP_TEE_READ_TEE_HUK_M (LP_TEE_READ_TEE_HUK_V << LP_TEE_READ_TEE_HUK_S)
#define LP_TEE_READ_TEE_HUK_V 0x00000001U
#define LP_TEE_READ_TEE_HUK_S 0
/** LP_TEE_READ_REE0_HUK : R/W; bitpos: [1]; default: 0;
* Configures huk registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
#define LP_TEE_READ_REE0_HUK (BIT(1))
#define LP_TEE_READ_REE0_HUK_M (LP_TEE_READ_REE0_HUK_V << LP_TEE_READ_REE0_HUK_S)
#define LP_TEE_READ_REE0_HUK_V 0x00000001U
#define LP_TEE_READ_REE0_HUK_S 1
/** LP_TEE_READ_REE1_HUK : R/W; bitpos: [2]; default: 0;
* Configures huk registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
#define LP_TEE_READ_REE1_HUK (BIT(2))
#define LP_TEE_READ_REE1_HUK_M (LP_TEE_READ_REE1_HUK_V << LP_TEE_READ_REE1_HUK_S)
#define LP_TEE_READ_REE1_HUK_V 0x00000001U
#define LP_TEE_READ_REE1_HUK_S 2
/** LP_TEE_READ_REE2_HUK : R/W; bitpos: [3]; default: 0;
* Configures huk registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
#define LP_TEE_READ_REE2_HUK (BIT(3))
#define LP_TEE_READ_REE2_HUK_M (LP_TEE_READ_REE2_HUK_V << LP_TEE_READ_REE2_HUK_S)
#define LP_TEE_READ_REE2_HUK_V 0x00000001U
#define LP_TEE_READ_REE2_HUK_S 3
/** LP_TEE_WRITE_TEE_HUK : R/W; bitpos: [4]; default: 1;
* Configures huk registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
#define LP_TEE_WRITE_TEE_HUK (BIT(4))
#define LP_TEE_WRITE_TEE_HUK_M (LP_TEE_WRITE_TEE_HUK_V << LP_TEE_WRITE_TEE_HUK_S)
#define LP_TEE_WRITE_TEE_HUK_V 0x00000001U
#define LP_TEE_WRITE_TEE_HUK_S 4
/** LP_TEE_WRITE_REE0_HUK : R/W; bitpos: [5]; default: 0;
* Configures huk registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
#define LP_TEE_WRITE_REE0_HUK (BIT(5))
#define LP_TEE_WRITE_REE0_HUK_M (LP_TEE_WRITE_REE0_HUK_V << LP_TEE_WRITE_REE0_HUK_S)
#define LP_TEE_WRITE_REE0_HUK_V 0x00000001U
#define LP_TEE_WRITE_REE0_HUK_S 5
/** LP_TEE_WRITE_REE1_HUK : R/W; bitpos: [6]; default: 0;
* Configures huk registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
#define LP_TEE_WRITE_REE1_HUK (BIT(6))
#define LP_TEE_WRITE_REE1_HUK_M (LP_TEE_WRITE_REE1_HUK_V << LP_TEE_WRITE_REE1_HUK_S)
#define LP_TEE_WRITE_REE1_HUK_V 0x00000001U
#define LP_TEE_WRITE_REE1_HUK_S 6
/** LP_TEE_WRITE_REE2_HUK : R/W; bitpos: [7]; default: 0;
* Configures huk registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
#define LP_TEE_WRITE_REE2_HUK (BIT(7))
#define LP_TEE_WRITE_REE2_HUK_M (LP_TEE_WRITE_REE2_HUK_V << LP_TEE_WRITE_REE2_HUK_S)
#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U
#define LP_TEE_WRITE_REE2_HUK_S 7
/** LP_TEE_LP_APM_CTRL_REG register
* lp_apm read/write control register
* LP_APM read/write control register
*/
#define LP_TEE_LP_APM_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4c)
/** LP_TEE_READ_TEE_LP_APM : R/W; bitpos: [0]; default: 1;
@ -1190,14 +1115,14 @@ extern "C" {
#define LP_TEE_WRITE_REE2_LP_APM_S 7
/** LP_TEE_FORCE_ACC_HP_REG register
* Force access to hpmem configuration register
* Force access to HP SRAM configuration register
*/
#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
* Configures whether to allow LP CPU to force access to HP_MEM regardless of
* Configures whether to allow LP CPU to forcibly access HP SRAM regardless of
* permission management.
* 0: disable force access HP_MEM
* 1: enable force access HP_MEM
* 0: Disable force access to HP SRAM
* 1: Enable force access to HP SRAM
*/
#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
@ -1205,13 +1130,13 @@ extern "C" {
#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
/** LP_TEE_BUS_ERR_CONF_REG register
* Clock gating register
* Error message return configuration register
*/
#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0)
/** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
* 1: enable error response
* Configures whether to return error message to CPU when access is blocked.
* 0: Disable
* 1: Enable
*/
#define LP_TEE_BUS_ERR_RESP_EN (BIT(0))
#define LP_TEE_BUS_ERR_RESP_EN_M (LP_TEE_BUS_ERR_RESP_EN_V << LP_TEE_BUS_ERR_RESP_EN_S)
@ -1224,8 +1149,8 @@ extern "C" {
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
#define LP_TEE_CLK_EN (BIT(0))
#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
@ -1237,7 +1162,7 @@ extern "C" {
*/
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 2363416;
* Version control register
* Version control register.
*/
#define LP_TEE_DATE 0x0FFFFFFFU
#define LP_TEE_DATE_M (LP_TEE_DATE_V << LP_TEE_DATE_S)

138
components/soc/esp32c5/register/soc/lp_tee_struct.h
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@ -10,22 +10,24 @@
extern "C" {
#endif
/** Group: Tee mode control register */
/** Group: Configuration Registers */
/** Type of m0_mode_ctrl register
* TEE mode control register
* Security mode configuration register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
* Configures M0 security level mode.
* 0: tee_mode
* 1: ree_mode0
* 2: ree_mode1
* 3: ree_mode2
* Configures the security mode for LP CPU.
* 0: TEE
* 1: REE0
* 2: REE1
* 3: REE2
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
* Configures to lock the value of LP_TEE_M0_MODE.
* 0: Do not lock
* 1: Lock
*/
uint32_t m0_lock:1;
uint32_t reserved_3:29;
@ -34,9 +36,9 @@ typedef union {
} lp_tee_m0_mode_ctrl_reg_t;
/** Group: read write control register */
/** Group: Peripheral Read/Write Control Register */
/** Type of efuse_ctrl register
* efuse read/write control register
* eFuse read/write control register
*/
typedef union {
struct {
@ -94,7 +96,7 @@ typedef union {
} lp_tee_efuse_ctrl_reg_t;
/** Type of pmu_ctrl register
* pmu read/write control register
* PMU read/write control register
*/
typedef union {
struct {
@ -152,7 +154,7 @@ typedef union {
} lp_tee_pmu_ctrl_reg_t;
/** Type of clkrst_ctrl register
* clkrst read/write control register
* LP_CLKRST read/write control register
*/
typedef union {
struct {
@ -210,7 +212,7 @@ typedef union {
} lp_tee_clkrst_ctrl_reg_t;
/** Type of lp_aon_ctrl_ctrl register
* lp_aon_ctrl read/write control register
* LP_AON read/write control register
*/
typedef union {
struct {
@ -268,7 +270,7 @@ typedef union {
} lp_tee_lp_aon_ctrl_ctrl_reg_t;
/** Type of lp_timer_ctrl register
* lp_timer read/write control register
* LP_TIMER read/write control register
*/
typedef union {
struct {
@ -326,7 +328,7 @@ typedef union {
} lp_tee_lp_timer_ctrl_reg_t;
/** Type of lp_wdt_ctrl register
* lp_wdt read/write control register
* LP_WDT read/write control register
*/
typedef union {
struct {
@ -384,7 +386,7 @@ typedef union {
} lp_tee_lp_wdt_ctrl_reg_t;
/** Type of lp_peri_ctrl register
* lp_peri read/write control register
* LPPERI read/write control register
*/
typedef union {
struct {
@ -442,7 +444,7 @@ typedef union {
} lp_tee_lp_peri_ctrl_reg_t;
/** Type of lp_ana_peri_ctrl register
* lp_ana_peri read/write control register
* LP_ANA_PERI read/write control register
*/
typedef union {
struct {
@ -500,7 +502,7 @@ typedef union {
} lp_tee_lp_ana_peri_ctrl_reg_t;
/** Type of lp_io_ctrl register
* lp_io read/write control register
* LP_GPIO and LP_IO_MUX read/write control register
*/
typedef union {
struct {
@ -558,7 +560,7 @@ typedef union {
} lp_tee_lp_io_ctrl_reg_t;
/** Type of lp_tee_ctrl register
* lp_tee read/write control register
* LP_TEE read/write control register
*/
typedef union {
struct {
@ -616,7 +618,7 @@ typedef union {
} lp_tee_lp_tee_ctrl_reg_t;
/** Type of uart_ctrl register
* uart read/write control register
* LP_UART read/write control register
*/
typedef union {
struct {
@ -674,7 +676,7 @@ typedef union {
} lp_tee_uart_ctrl_reg_t;
/** Type of i2c_ext_ctrl register
* i2c_ext read/write control register
* LP_I2C read/write control register
*/
typedef union {
struct {
@ -732,7 +734,7 @@ typedef union {
} lp_tee_i2c_ext_ctrl_reg_t;
/** Type of i2c_ana_mst_ctrl register
* i2c_ana_mst read/write control register
* I2C_ANA_MST read/write control register
*/
typedef union {
struct {
@ -789,66 +791,8 @@ typedef union {
uint32_t val;
} lp_tee_i2c_ana_mst_ctrl_reg_t;
/** Type of huk_ctrl register
* huk read/write control register
*/
typedef union {
struct {
/** read_tee_huk : R/W; bitpos: [0]; default: 1;
* Configures huk registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t read_tee_huk:1;
/** read_ree0_huk : R/W; bitpos: [1]; default: 0;
* Configures huk registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t read_ree0_huk:1;
/** read_ree1_huk : R/W; bitpos: [2]; default: 0;
* Configures huk registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t read_ree1_huk:1;
/** read_ree2_huk : R/W; bitpos: [3]; default: 0;
* Configures huk registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t read_ree2_huk:1;
/** write_tee_huk : R/W; bitpos: [4]; default: 1;
* Configures huk registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t write_tee_huk:1;
/** write_ree0_huk : R/W; bitpos: [5]; default: 0;
* Configures huk registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t write_ree0_huk:1;
/** write_ree1_huk : R/W; bitpos: [6]; default: 0;
* Configures huk registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t write_ree1_huk:1;
/** write_ree2_huk : R/W; bitpos: [7]; default: 0;
* Configures huk registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t write_ree2_huk:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_huk_ctrl_reg_t;
/** Type of lp_apm_ctrl register
* lp_apm read/write control register
* LP_APM read/write control register
*/
typedef union {
struct {
@ -905,18 +849,16 @@ typedef union {
uint32_t val;
} lp_tee_lp_apm_ctrl_reg_t;
/** Group: Force access to hpmem configuration register */
/** Type of force_acc_hp register
* Force access to hpmem configuration register
* Force access to HP SRAM configuration register
*/
typedef union {
struct {
/** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
* Configures whether to allow LP CPU to force access to HP_MEM regardless of
* Configures whether to allow LP CPU to forcibly access HP SRAM regardless of
* permission management.
* 0: disable force access HP_MEM
* 1: enable force access HP_MEM
* 0: Disable force access to HP SRAM
* 1: Enable force access to HP SRAM
*/
uint32_t force_acc_hpmem_en:1;
uint32_t reserved_1:31;
@ -924,17 +866,15 @@ typedef union {
uint32_t val;
} lp_tee_force_acc_hp_reg_t;
/** Group: config register */
/** Type of bus_err_conf register
* Clock gating register
* Error message return configuration register
*/
typedef union {
struct {
/** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
* 1: enable error response
* Configures whether to return error message to CPU when access is blocked.
* 0: Disable
* 1: Enable
*/
uint32_t bus_err_resp_en:1;
uint32_t reserved_1:31;
@ -943,7 +883,7 @@ typedef union {
} lp_tee_bus_err_conf_reg_t;
/** Group: clock gating register */
/** Group: Clock Gating Registers */
/** Type of clock_gate register
* Clock gating register
*/
@ -951,8 +891,8 @@ typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@ -961,14 +901,14 @@ typedef union {
} lp_tee_clock_gate_reg_t;
/** Group: Version control register */
/** Group: Version Control Registers */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 2363416;
* Version control register
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
@ -995,7 +935,7 @@ typedef struct {
uint32_t reserved_03c;
volatile lp_tee_i2c_ext_ctrl_reg_t i2c_ext_ctrl;
volatile lp_tee_i2c_ana_mst_ctrl_reg_t i2c_ana_mst_ctrl;
volatile lp_tee_huk_ctrl_reg_t huk_ctrl;
uint32_t reserved_048;
volatile lp_tee_lp_apm_ctrl_reg_t lp_apm_ctrl;
uint32_t reserved_050[16];
volatile lp_tee_force_acc_hp_reg_t force_acc_hp;

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components/soc/esp32c5/register/soc/tee_reg.h
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components/soc/esp32c5/register/soc/tee_struct.h
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components/soc/esp32c61/register/soc/cache_reg.h
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components/soc/esp32c61/register/soc/cache_struct.h
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components/soc/esp32h21/register/soc/soc_etm_reg.h
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components/soc/esp32h21/register/soc/soc_etm_struct.h
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