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408 Commits

Author SHA1 Message Date
4bc762621d Merge branch 'bugfix/fix_bleqabr23_222_v5.1' into 'release/v5.1'
Revert "bluedroid: report disconnect event after BLE link closed" (backport 5.1)

See merge request espressif/esp-idf!24036
2023-06-03 08:43:09 +08:00
42592552b5 Merge branch 'feature/itwt_add_setup_timeout_timer_backport_v5.1' into 'release/v5.1'
esp_wifi: itwt add setup timeout timer to track response frame (backport v5.1)

See merge request espressif/esp-idf!24040
2023-06-03 08:40:41 +08:00
5a21bea309 esp_wifi: itwt add setup timeout timer to track response frame 2023-06-02 19:46:15 +08:00
cb88d20f9e Merge branch 'bugfix/fix_wakeup_failed_if_powerdown_flash_in_lightsleep_v5.1' into 'release/v5.1'
Power Management: fixed flash funcs called in sleep wakeup process (backport v5.1)

See merge request espressif/esp-idf!24009
2023-06-02 19:18:36 +08:00
d28cb4a954 esp_wifi:
1. mesh: layer2 node will scan all channels when fixed root leave
2. show warning info when setting max connection num for softAP
2023-06-02 17:27:28 +08:00
c5e580e522 Revert "bluedroid: report disconnect event after BLE link closed"
This reverts commit d751960b27.
2023-06-02 16:51:07 +08:00
ddc16a47fe Merge branch 'bugfix/wpsreg_ap_assoc_respone_v5.1' into 'release/v5.1'
esp_wifi: Bugfix wpsreg AP not responding to assoc req (v5.1)

See merge request espressif/esp-idf!24027
2023-06-02 13:30:22 +08:00
03832dbd5e bugfix: fix some flash funcs called in sleep wakeup process 2023-06-02 02:53:51 +00:00
ecf46dd5da Merge branch 'docs/update_esp32c6_wifi_api_guides_backport_v5.1' into 'release/v5.1'
docs: update esp32c6 api guides about wifi part (backport v5.1)

See merge request espressif/esp-idf!24020
2023-06-01 19:24:50 +08:00
e8d9104953 esp_wifi: Bugfix wpsreg AP not responding to assoc req
Fixed regression caused by 2b8e40e7
2023-06-01 15:36:54 +05:30
6cd76ba321 docs: update for esp32c6 2023-06-01 14:27:19 +08:00
5a9cff0d34 docs: update esp32c6 api guides about wifi part 2023-06-01 14:26:37 +08:00
aa741b90ad Merge branch 'docs/c6_misc_updates_v5.1' into 'release/v5.1'
Docs: c6 misc updates (v5.1)

See merge request espressif/esp-idf!23999
2023-06-01 11:03:42 +08:00
22adf838c9 Merge branch 'bugfix/c6_h2_decrease_rng_frequency_v5.1' into 'release/v5.1'
esp_hw_support: decrease RNG read frequency for C6 and H2 (v5.1)

See merge request espressif/esp-idf!24001
2023-06-01 00:54:49 +08:00
f4f45345ee esp_hw_support: decrease RNG read frequency on C6 and H2
* The RNG reading frequency of 200 KHz has been too high for
  C6 and H2 since on these chips the RNG output is combined
  with the RTC slow clock which is only 150KHz. Reduced the max
  reading frequency via esp_random() from 200KHz to 62.5KHz,
  which show best results in tests.
  Also updated the bootloader_fill_random() max frequency to the
  same value to be in line, even though it was just 83KHz.
2023-05-31 16:16:25 +00:00
7b09d12c89 Merge branch 'bugfix/efuse_summary_v5.1' into 'release/v5.1'
system-hardware/efuse: fixed efuse summary description containing ; breaking efuse-summary (v5.1)

See merge request espressif/esp-idf!23979
2023-05-31 22:57:37 +08:00
30f8f83d52 Merge branch 'bugfix/add_warning_for_rc_fast_calibration_h2_v5.1' into 'release/v5.1'
clk: Add warning log if RC_FAST clock calibration is needed on esp32h2 (v5.1)

See merge request espressif/esp-idf!23935
2023-05-31 20:21:11 +08:00
5cd24826bb Merge branch 'bugfix/fix_rc_fast_calibration_v5.1' into 'release/v5.1'
rtc_clk: fix esp32c6/esp32h2 eco chip `RC_FAST` bad calibration value (backport v5.1)

See merge request espressif/esp-idf!23940
2023-05-31 17:40:28 +08:00
0d13f6f09d Merge branch 'bugfix/fix_hang_during_sleep_process_v5.1' into 'release/v5.1'
bugfix: fix hang on pd_top sleep process (backport v5.1)

See merge request espressif/esp-idf!23852
2023-05-31 17:40:02 +08:00
871dd9e21a docs: updated misc C6 programming guide docs with minor changes. 2023-05-31 15:47:26 +08:00
273d973489 idocs: updated Storage API reference documents for ESP32H2 2023-05-31 15:46:42 +08:00
8df4a852f5 docs: updated Storage API reference documents for ESP32C6 2023-05-31 15:46:41 +08:00
bb4218285b system-hardware/efuse: fixed efuse summary description containing ; breaking efuse-summary
If the efuse description from esptool contained semi-colons it would be interpretted as
a list delimiter in CMake. Summary is now passed as in quotes to escape this behavior.
2023-05-30 14:07:50 +08:00
ea5e0ff298 Merge branch 'backport/fix_matter_commissioning_ble_disconnect_issue' into 'release/v5.1'
openthread: Add some backports related to openthread(Backport v5.1)

See merge request espressif/esp-idf!23893
2023-05-26 15:37:14 +08:00
125d00c0f7 Merge branch 'feature/c6_bootloader_rng_v5.1' into 'release/v5.1'
Feature/c6 bootloader rng (v5.1)

See merge request espressif/esp-idf!23896
2023-05-26 15:36:45 +08:00
8c714acfb5 bugfix: fix rc_fast bad calibration value 2023-05-26 13:59:25 +08:00
702afbb0f7 clk: Add warning log if RC_FAST clock calibration is needed on esp32h2 2023-05-26 11:45:00 +08:00
b0e2f33082 esp_hw_support/bootloader: made ESP32-C6 and ESP32-H2 RNG available 2023-05-24 09:43:21 +05:30
7eb9af5806 openthread: fix frame counter when re-transmition 2023-05-24 10:43:16 +08:00
2016bddbda openthread: add kconfig for enabling mac filter 2023-05-24 10:42:52 +08:00
d9e289a5fb esp_phy: updating lib phy to adapt the voltage changes 2023-05-24 10:35:39 +08:00
6ad6fb9755 Merge branch 'feature/update_ble_doc_for_esp32c6_esp32h2_v5.1' into 'release/v5.1'
ble docs: Update ble doc for esp32c6 and esp32h2

See merge request espressif/esp-idf!23801
2023-05-23 15:33:51 +08:00
56677dabe8 Merge branch 'add_c6_in_supported_targets_in_prov_example_v5.1' into 'release/v5.1'
Add ESP32-C6 in supported targets (v5.1)

See merge request espressif/esp-idf!23846
2023-05-20 07:41:54 +08:00
9310ed608e Merge branch 'contrib/github_pr_10532_v5.1' into 'release/v5.1'
[SDMMC Mount] fix infinite loop when SD card is not responsive (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23527
2023-05-20 07:35:38 +08:00
057cf2b8ee Merge branch 'bugfix/wifi_backport_v5.1' into 'release/v5.1'
esp_wifi: backport some wifi fixes to v5.1

See merge request espressif/esp-idf!23847
2023-05-20 07:34:41 +08:00
829fdd172c Merge branch 'feature/add_support_for_lp_i2c_v5.1' into 'release/v5.1'
lp-i2c: Added support for LP I2C peripheral to LP core (v5.1)

See merge request espressif/esp-idf!23850
2023-05-20 04:38:59 +08:00
8cecbafe18 Merge branch 'bugfix/close_phy_tsens_before_sleep_v5.1' into 'release/v5.1'
sleep: fix deepsleep current leakage caused by phy_tsens (backport v5.1)

See merge request espressif/esp-idf!23843
2023-05-19 20:29:22 +08:00
786faa3cac Merge branch 'doc/update_efuse_info_v5.1' into 'release/v5.1'
doc: Update all efuse info files (v5.1)

See merge request espressif/esp-idf!23853
2023-05-19 20:28:15 +08:00
6477500cf1 sdmmc: incrementally increase delay of vTaskDelay
Prevents unnecessary slowdown in polling functions
2023-05-19 14:01:43 +02:00
3ef8c77588 esp_dpp: Fix retry with esp_supp_dpp_start_listen after failure
This fixes a subtle bug in which ESP_ERR_DPP_TX_FAILURE errors would
call esp_supp_dpp_stop_listen which sets the s_dpp_stop_listening flag
to true.  Subsequent attempts to restart listening with
esp_supp_dpp_start_listen then only attempt to listen once more for
500ms before reading the s_dpp_stop_listening flag again and giving up.

This contributes greatly to #10615, but the fix here is still largely
a work-around as it sometimes requires manually retrying a couple times
before it works.  Without this fix, any number of retries by
deinit/init again will seemingly not work as the retries for currently
unknown reasons.

Signed-off-by: Shreyas Sheth <shreyas.sheth@espressif.com>

Closes https://github.com/espressif/esp-idf/pull/10865
2023-05-19 17:17:18 +08:00
9aedb4bd83 wpa_supplicant : Fix scan results for GCMP and GCMP-256 cipher.
Add support for recognising GCMP and GCMP-256 ciphers if used by AP.
Update the scan example to show the correct cipher.
2023-05-19 16:58:51 +08:00
576489f8cf wpa_supplicant : Add MBO ie in probe request.
Adds the MBO information element in the probe request frame by resetting
scan_ie after set_config is done.
2023-05-19 16:58:40 +08:00
a32201f6ec Merge branch 'bugfix/fix_compilation_error_optimization_v5.1' into 'release/v5.1'
Nimble: Fix compilation issues seen while enabling -O2 optimization (v5.1)

See merge request espressif/esp-idf!23717
2023-05-19 16:48:18 +08:00
774696285d Merge branch 'bugfix/fix_lp_bod_if_bt_i154_init_phy_before_wifi_v5.1' into 'release/v5.1'
fix(phy): fix lp_bod reset if bt/i154 init phy before wifi

See merge request espressif/esp-idf!23831
2023-05-19 16:25:11 +08:00
d345beb02a Merge branch 'contrib/github_pr_11402_v5.1' into 'release/v5.1'
esp_ds: ignore releasing mutex if not called from same task (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23840
2023-05-19 16:11:15 +08:00
cb6b14a0f8 doc: Update efuse info files 2023-05-19 15:17:16 +08:00
eccb5318f9 Kconfig: add more help info for pm related options help 2023-05-19 13:51:29 +08:00
1df2dcc9fe bugfix: treat too short sleep duration as sleep reject by software 2023-05-19 13:51:24 +08:00
00e777aff9 bugfix: fix pmp retention and add pma retention 2023-05-19 13:51:20 +08:00
267c5e37a2 lp-i2c: Added support for LP I2C peripheral to LP core
This commit adds support for the LP I2C peripheral driver to be used by
the LP core. An example is also added to demonstrate the usage of the LP
I2C peripheral from the LP core.
2023-05-19 07:33:01 +02:00
2220a07ec1 1. Support NAN ifx for API's esp_wifi_internal_set_fix_rate and esp_wifi_set_protocol
2. Remove user configurable flag fsd_reqd from NAN publish config
3. Fix issue wherein NDL of previously cancelled service is obtained in peer record of new service with no NDL
2023-05-19 12:46:39 +08:00
a3ecb8fe93 Add esp32c6 in supported target for ota examples 2023-05-19 10:03:45 +05:30
d9de899ed7 Add ESP32-C6 in supported targets for wifi_prov_mgr example 2023-05-19 10:03:45 +05:30
871bbdcec3 netdb:fixed bug for getaddrinfo returns null when IPV4 mapped address
Closes https://github.com/espressif/esp-idf/issues/9693
2023-05-19 12:26:07 +08:00
050367ea37 esp_wifi: fix softap nvs <ssid,password,pmk> not match issue
Closes FCS-1196
2023-05-19 12:23:20 +08:00
8bfb5c837e esp_wifi: Fix tx_callback issue for ESP32C6 2023-05-19 12:19:54 +08:00
7412d1a1a9 wpa_supplicant: Use 'mbedtls_pk_parse_public_key' to parse compressed EC public key and remove unnecessary code
Support to parse compressed EC public key is added from 'mbedtls-3.4.0'
2023-05-19 12:19:08 +08:00
edf9f9eff7 esp-wifi: add station SAE-PK (Public Key) configuration note 2023-05-19 12:18:49 +08:00
fc5fe1132a bugfix: close phy_tsens before deepsleep 2023-05-19 11:04:17 +08:00
ed32d7a267 Merge branch 'bugfix/move_adc_onshot_power_management_to_shot_read_func_v5.1' into 'release/v5.1'
Sleep: Fixed abnormal deepsleep base current of ULP ADC on esp32s2/esp32s3 chips (backport v5.1)

See merge request espressif/esp-idf!23828
2023-05-19 11:03:54 +08:00
0d12613ab9 ble docs: Update the ble docs for esp32c6 and esp32h2 2023-05-19 11:03:11 +08:00
cc7c851cb2 Merge branch 'feature/use_api_to_enable_modem_on_esp32h2_v5.1' into 'release/v5.1'
ble: use modem_clock api to set clocks on ESP32-H2

See merge request espressif/esp-idf!23806
2023-05-19 11:01:44 +08:00
501c7d1101 esp_ds: ignore releasing mutex if not called from same task 2023-05-19 08:31:34 +05:30
05c98d8b53 Merge branch 'bugfix/sync-contribution-guide_v5.1' into 'release/v5.1'
docs: updated contribution agreement (v5.1)

See merge request espressif/esp-idf!23839
2023-05-19 10:54:51 +08:00
19f300fa24 Merge branch 'bugfix/use_safe_noreturn_attr_v5.1' into 'release/v5.1'
compiler: replaced noreturn by __noreturn__ in header files (v5.1)

See merge request espressif/esp-idf!23811
2023-05-19 09:37:50 +08:00
c58915842e Merge branch 'bugfix/eth-start-spi-initialize-failure-v5.1' into 'release/v5.1'
Fix eth_start initializes spi bus with SPI_DMA_CH_AUTO (backport v5.1)

See merge request espressif/esp-idf!23815
2023-05-19 09:12:22 +08:00
6cc4ab56e4 docs: updated contribution agreement 2023-05-18 16:27:45 +02:00
bd0f9b8512 fix(phy): fix lp_bod reset if bt/i154 init phy before wifi 2023-05-18 20:57:57 +08:00
43a67a5da3 Merge branch 'feature/esp32c2_enable_rf_temp_compensation_v5.1' into 'release/v5.1'
Feature/esp32c2 enable rf temp compensation v5.1

See merge request espressif/esp-idf!23730
2023-05-18 20:34:30 +08:00
ed076c2bc8 bugfix: move adc_oneshot_power_acquire/release to adc_oneshot_read
Closes https://github.com/espressif/esp-idf/issues/10595
Closes https://github.com/espressif/esp-idf/issues/11386
2023-05-18 20:08:47 +08:00
7fcba0fbf8 Merge branch 'bugfix/fix_some_ble_bug_v5.1' into 'release/v5.1'
Fixed some BLE bugs (backport v5.1)

See merge request espressif/esp-idf!23699
2023-05-18 20:08:25 +08:00
8b7cd4dc08 Merge branch 'bugfix/hfp_ag_idx_invalid_v5.1' into 'release/v5.1'
bt: Fixed out of bounds access due to variable length array(v5.1)

See merge request espressif/esp-idf!23665
2023-05-18 20:07:21 +08:00
57b31ed545 Merge branch 'feature/add_bluetooth_nimble_lightsleep_example_v5.1' into 'release/v5.1'
bt: Added an example of Bluetooth using light sleep(v5.1)

See merge request espressif/esp-idf!23686
2023-05-18 20:06:16 +08:00
2010d70892 Merge branch 'bugfix/a2dp_source_app_state_error_v5.1' into 'release/v5.1'
bt: Fixed the issue that the a2dp source would not send the media start command due to the connection initiated by the peer device(v5.1)

See merge request espressif/esp-idf!23557
2023-05-18 20:04:45 +08:00
f503b0f621 Merge branch 'fix/sdcard_example_blocker_v5.1' into 'release/v5.1'
CI: fix sdcard examples timeout (v5.1)

See merge request espressif/esp-idf!23477
2023-05-18 20:03:59 +08:00
5b4c95c50f Merge branch 'bugfix/update_esp32c6eco1_sleep_fosc_cal_cycles_backport_v5.1' into 'release/v5.1'
bugfix: update esp32c6 eco1 fosc calibration cycles during sleep(backport v5.1)

See merge request espressif/esp-idf!23490
2023-05-18 19:52:05 +08:00
79fab2eb92 Merge branch 'backport/fix_ieee802154_typo' into 'release/v5.1'
ieee802154: fix a typo in set_channel API(Backport v5.1)

See merge request espressif/esp-idf!23809
2023-05-18 17:07:06 +08:00
f79088f115 Merge branch 'bugfix/add_len_check_per_spi_master_transaction_v5.1' into 'release/v5.1'
spi master: added transaction length check to refuse longer than hardware supported length (v5.1)

See merge request espressif/esp-idf!23747
2023-05-18 16:47:18 +08:00
38a1cfe59c Nimble: Fix compilation issues seen while enabling -O2 optimization 2023-05-18 14:00:33 +05:30
0814386710 Merge branch 'refactor/driver_ut_to_test_app_v5.1' into 'release/v5.1'
CI: Move all UT in driver to test_app(backport v5.1)

See merge request espressif/esp-idf!23708
2023-05-18 16:18:26 +08:00
431f5b81a2 Merge branch 'bugfix/fix_doc_blufi_eror_v5.1' into 'release/v5.1'
fix blufi doc error (backport v5.1)

See merge request espressif/esp-idf!23724
2023-05-18 15:04:17 +08:00
e8dba711ff Merge branch 'bugfix/fix_iphone_disconnects_immediately_after_connecting_when_BLE_wifi_coexist_v5.1' into 'release/v5.1'
Fix the bug that the iPhone disconnects immediately after connecting when BLE and wifi coexist(backport v5.1)

See merge request espressif/esp-idf!23786
2023-05-18 15:04:14 +08:00
bd5b1008de comm_components: eth_start initializes spi bus with SPI_DMA_CH_AUTO
Close https://github.com/espressif/esp-idf/issues/11083
2023-05-18 14:46:09 +08:00
9f7475dd98 Merge branch 'contrib/github_pr_11215_v5.1' into 'release/v5.1'
improve thread safety in esp_timer (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23539
2023-05-18 13:06:46 +08:00
a6cbf68991 compiler: replaced noreturn by __noreturn__ in header files
* noreturn may be replaced by third-party macros,
  rendering it ineffective

* Closes https://github.com/espressif/esp-idf/issues/11339
2023-05-18 12:49:40 +08:00
6ba1c6c44f ieee802154: fix a typo in set_channel API 2023-05-18 10:39:51 +08:00
82c6c8149c Merge branch 'bug/interactive_hints_v5.1' into 'release/v5.1'
tools: fix hints processing in interactive mode (v5.1)

See merge request espressif/esp-idf!23795
2023-05-18 00:09:16 +08:00
b3bde42d8c Merge branch 'bugfix/update_test_dl_esp_cert_v5.1' into 'release/v5.1'
tests: update Root certificate for the test endpoints (v5.1)

See merge request espressif/esp-idf!23797
2023-05-17 21:39:09 +08:00
83ac726851 ble: use modem_clock api to set clock on ESP32-C6 2023-05-17 20:04:07 +08:00
133e19d6ee tests: update Root certificate for the test endpoints
Use Root certificate (`DigiCert Global Root G2`) for the
`dl.espressif.com` and `espressif.com` test endpoints.

This fixes the test failure introduced due to renewal of
the intermediate certificate.
2023-05-17 15:27:24 +05:30
8702e49057 spi: added an API to get max transaction length and use in spi lcd driver 2023-05-17 09:03:26 +00:00
4943844764 spi: added transaction length check to refuse longer than hardware supported length 2023-05-17 09:03:26 +00:00
b525e273ce tools: fix hints processing in interactive mode
Currently hints are processed only once the process is finished and
exits with non-error exit code. In interactive mode, e.g. for monitor,
we want to process ouput lines for hints right away.

This adds a simple buffer, which keeps the last line and once EOL is
reached, it is processed for hints.

Since the original hints processing was file based, a new helper
function was added to allow processing hints in string.

Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
2023-05-17 10:56:39 +02:00
0ed8499898 Merge branch 'bugfix/a2dp_source_crash_connect_to_Bose_speaker_v5.1' into 'release/v5.1'
Bugfix/a2dp source crash connect to bose speaker (v5.1)

See merge request espressif/esp-idf!23574
2023-05-17 15:10:34 +08:00
0122794a4e Merge branch 'bugfix/deinit_ble_v5.1' into 'release/v5.1'
bugfix: deinit ble for specifies ESP_BT_MODE_BTDM (backport v5.1)

See merge request espressif/esp-idf!23068
2023-05-17 15:09:29 +08:00
c92ddbbf6f Merge branch 'bugfix/reduce_logging_for_SAE' into 'release/v5.1'
Modify log level for SAE (Backport v5.1)

See merge request espressif/esp-idf!23547
2023-05-17 14:02:39 +08:00
5bd2b5bc41 fix blufi doc error 2023-05-17 04:06:11 +00:00
b311a3ffc2 Merge branch 'contrib/github_pr_11388_v5.1' into 'release/v5.1'
Update esp_cpu.h to include esp_attr.h (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23738
2023-05-17 09:24:38 +08:00
8adb48cbfd Merge branch 'fix/console-build-error_v5.1' into 'release/v5.1'
console: Fix building issue when serial JTAG is set (v5.1)

See merge request espressif/esp-idf!23735
2023-05-17 08:39:03 +08:00
e86b8136bd Merge branch 'bugfix/c2_wdt_reset_reason_v5.1' into 'release/v5.1'
wdt: fix IWDT reset reason for esp32c2 (v5.1)

See merge request espressif/esp-idf!23740
2023-05-17 08:38:45 +08:00
9b73003628 Fix the bug that the iPhone disconnects immediately after connecting when BLE and wifi coexist 2023-05-16 17:54:06 +08:00
3bdbad6aa7 Merge branch 'feature/remove_coredump_tests_v5.1' into 'release/v5.1'
coredump: remove tests (moved to esp-coredump repo) (v5.1)

See merge request espressif/esp-idf!23767
2023-05-16 17:40:26 +08:00
df7a27e36d CI: Move all UT in driver to test_app 2023-05-16 16:42:28 +08:00
b62cbebb81 Merge branch 'feature/expose_addr_resolv_out_stack_v5.1' into 'release/v5.1'
Nimble:Added change to expose addr resolution API outside stack (v5.1)

See merge request espressif/esp-idf!23491
2023-05-16 16:34:11 +08:00
zwl
c907f489d6 ble:fixed build error when disable smp 2023-05-16 16:08:54 +08:00
zwl
9b61156746 ble:esp32c2 add rf temperature compensation 2023-05-16 16:08:54 +08:00
b8bd147466 ci: re-enable reset reason tests for all targets except H2. 2023-05-16 05:22:07 +00:00
e0b91b748e esp-system: fixed int WDT reset reason being reported as task WDT on C2 2023-05-16 05:22:07 +00:00
726ed144e4 coredump: remove tests (moved to esp-coredump repo) 2023-05-16 12:43:04 +08:00
accb45f466 Update esp_cpu.h
If esp_attr.h is not included then there are no definitions for the symbol 'FORCE_INLINE_ATTR'.
2023-05-16 04:37:17 +00:00
c5003e6220 console: Fix building issue when serial JTAG is set
Closes https://github.com/espressif/esp-idf/issues/10707
2023-05-16 04:37:09 +00:00
96e1f6e7a2 Merge branch 'openthread/default_dnsserver_address_v5_1' into 'release/v5.1'
openthread: Add menuconfig to set the default dns server address(v5.1)

See merge request espressif/esp-idf!23757
2023-05-16 12:36:20 +08:00
d17ab36645 Merge branch 'feature/c6_ulp_timer_v5.1' into 'release/v5.1'
ulp: lp timer support for lp core (v5.1)

See merge request espressif/esp-idf!23659
2023-05-16 09:19:56 +08:00
a056e655d8 openthread: Add menuconfig to set the default dns server address 2023-05-15 19:30:14 +08:00
aed737b351 Merge branch 'feature/efuse_settings_v5.1' into 'release/v5.1'
hal: Explicit setting of efuse time settings (v5.1)

See merge request espressif/esp-idf!23725
2023-05-15 19:16:30 +08:00
0edb7ee43a Merge branch 'bugfix/ulp_i2c_timeout_config_v5.1' into 'release/v5.1'
ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option (v5.1)

See merge request espressif/esp-idf!23657
2023-05-15 16:03:15 +08:00
689db30956 Merge branch 'contrib/github_pr_11025_v5.1' into 'release/v5.1'
Enable support for C++23 in esp-idf (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23421
2023-05-15 16:02:54 +08:00
59b6634a9a Merge branch 'feature/add_missed_settings_for_bootloader_reserve_rtc_mem_for_c6_h2_v5.1' into 'release/v5.1'
esp_system (C6 & H2): Enables BOOTLOADER_RESERVE_RTC_MEM feature for bootloader (v5.1)

See merge request espressif/esp-idf!23402
2023-05-15 16:02:35 +08:00
24ae831b3d Merge branch 'contrib/github_pr_11394_v5.1' into 'release/v5.1'
docs: Fix typo in Linux/macOS getting started docs (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23732
2023-05-15 10:50:34 +08:00
78d88afbef Merge branch 'bugfix/i2c_timing_wrong_v5.1' into 'release/v5.1'
i2c: fix a bug in sda sample timing (backport v5.1)

See merge request espressif/esp-idf!23379
2023-05-15 10:47:35 +08:00
b8365dced6 Merge branch 'Bugfix/fix_tsen_issue_v5.1' into 'release/v5.1'
Temperature sensor: fix return value issue @low temp on H2(backport v5.1)

See merge request espressif/esp-idf!23719
2023-05-15 10:46:11 +08:00
b7199e88b7 Merge branch 'bugfix/mcpwm_bldc_example_v5.1' into 'release/v5.1'
mcpwm: test generator force level with dead time module (v5.1)

See merge request espressif/esp-idf!23714
2023-05-15 10:00:00 +08:00
2701677eb6 Fix typo in Linux/macOS getting started docs
`hello_word` -> `hello_world`
2023-05-15 09:34:48 +08:00
2165ff386e hal: Explicit setting of efuse time settings
EFUSE_PWR_ON_NUM in C3 has default value = 0x2880, now = 0x3000
2023-05-12 21:42:38 +08:00
zlq
79a2cc224c H2:fix temp sensor issue @low temp 2023-05-12 17:00:58 +08:00
6cfc6f53be Merge branch 'bugfix/enable_i_pdm_example_pytest_on_h2_v5.1' into 'release/v5.1'
i2s_pdm: enable example pytest on h2 (v5.1)

See merge request espressif/esp-idf!23642
2023-05-12 16:47:25 +08:00
e35897db33 Merge branch 'feature/heap-in-flash_v5.1' into 'release/v5.1'
heap: Add a configuration that places all the heap component in flash (v5.1)

See merge request espressif/esp-idf!23377
2023-05-12 15:57:31 +08:00
7e49268933 bugfix: deinit ble for specifies ESP_BT_MODE_BTDM 2023-05-12 14:53:56 +08:00
a7021c3e44 mcpwm: fix bldc example force output level inverted
set_force_level can only set the generator level before the deadtime module.
if the deadtime module enables the inverter, then the real output level is inverted accordingly
2023-05-12 14:40:10 +08:00
190e9e7212 Merge branch 'bugfix/fix_several_bugs_in_i2s_v5.1' into 'release/v5.1'
i2s: fix several bugs in std and tdm mode (v5.1)

See merge request espressif/esp-idf!23669
2023-05-12 11:05:34 +08:00
fc69e53e40 Merge branch 'ci/fix_system_invalid_kconfigs_v5.1' into 'release/v5.1'
ci: fix invalid kconfig options in system test apps (v5.1)

See merge request espressif/esp-idf!23660
2023-05-12 11:04:08 +08:00
6f459d4ea8 Merge branch 'feature/reset_mcpwm_in_restart_v5.1' into 'release/v5.1'
mcpwm: reset peripheral in restart, panic and halt (v5.1)

See merge request espressif/esp-idf!23651
2023-05-12 10:12:58 +08:00
1d89e24199 Merge branch 'bugfix/fix_mspi_octal_psram_timing_tuning_point_fallback_id_v5.1' into 'release/v5.1'
mspi: modified mspi 80mhz octal psram timing tuning point fallback id on s3 (v5.1)

See merge request espressif/esp-idf!23689
2023-05-11 21:24:44 +08:00
2379ee36ab cxx: gnu++23 -> gnu++2b for clang compatibility, added docs and test
* Using -std=gnu++2b now for both gcc and clang as clang
  does not recognize gnu++23 yet
* Added a build test app to check the C++ standard in IDF
* Updated english docs to reflect the change to C++23
2023-05-11 17:48:38 +08:00
58fa57af93 Enable support for C++23 in esp-idf 2023-05-11 17:45:20 +08:00
b1c85cc1d5 Merge branch 'contrib/github_pr_10895_v5.1' into 'release/v5.1'
Fix possible conversion errors by using __builtin_ffsll (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23690
2023-05-11 16:45:44 +08:00
cf5e2c3962 Merge branch 'doc/update_mcpwm_deadtime_v5.1' into 'release/v5.1'
MCPWM: don't allow to apply the same delay module to multiple generators (v5.1)

See merge request espressif/esp-idf!23663
2023-05-11 16:13:23 +08:00
b77479df39 bluedroid: fix ble ext adv rand addr setting for NRPA 2023-05-11 14:36:39 +08:00
ac42a8f2c7 bluedroid: fix ble adv data construct for device name 2023-05-11 14:36:39 +08:00
e6f018a309 bluedroid: fix ble smp key distribution setting 2023-05-11 14:36:39 +08:00
2afb56d189 Update bt lib for ESP32-C3 and ESP32-S3
- Fixed remote mic error during encryption procedure
2023-05-11 14:36:39 +08:00
d751960b27 bluedroid: report disconnect event after BLE link closed 2023-05-11 14:36:39 +08:00
7ddb440384 bt: Deleted some redundant variables in HFP_AG 2023-05-11 06:09:06 +00:00
a891aa7e4d bt: Fixed the problem of out-of-bounds access caused by the variable-length array introduced in 3268075231
Closes https://github.com/espressif/esp-idf/issues/11264
2023-05-11 06:09:06 +00:00
d3d73ed8b2 bt: Fixed codec mode error in ESP_HF_WBS_RESPONSE_EVT 2023-05-11 06:09:06 +00:00
a498871111 Merge branch 'bugfix/fix_wrong_hp_ldo_h2_to_v5.1' into 'release/v5.1'
ESP32H2: Fix too low hp ldo dbias (v5.1)

See merge request espressif/esp-idf!23598
2023-05-11 11:59:26 +08:00
5d6b59109b Merge branch 'ci/newlib_pytest_v5.1' into 'release/v5.1'
ci: move newlib tests to pytest (v5.1)

See merge request espressif/esp-idf!23685
2023-05-11 11:49:48 +08:00
48ab527148 cxx/esp_hw_support: added build test, changed parameter types
Changed rv_utils_intr_edge_ack and esp_cpu_intr_edge_ack to
take uint32_t instead of int to avoid build errors.

The test is to test in particular that __builtin_ffsll, used in
xt_utils.h, which is included via esp_cpu.h, compiles fine
in C++20 with -Wsign-conversion enabled.

Closes https://github.com/espressif/esp-idf/pull/10895
2023-05-11 11:16:45 +08:00
51a9057d9e Fix possible conversion errors by using __builtin_ffsll instead of __builtin_ffs
Signed-off-by: term_est <62337595+term-est@users.noreply.github.com>
2023-05-11 11:16:45 +08:00
6ae2c3c240 mspi: modified mspi 80mhz octal psram timing tuning point fallback id on s3 2023-05-11 11:13:32 +08:00
8b8a6a4450 bt: Added an example of Bluetooth using light sleep 2023-05-11 10:24:00 +08:00
6b0d93efd4 ci: misc fixes for newlib test app
Enabled additional tests for C2, added config for testing with newlib nano
as well as cleaned up old configs
2023-05-11 09:27:09 +08:00
d795abeb03 newlib: move test to pytest 2023-05-11 09:26:39 +08:00
70feed14dd Merge branch 'feature/update-OpenOCD-to-v0.12.0-esp32-20230419_v5.1' into 'release/v5.1'
tools: update OpenOCD version to v0.12.0-esp32-20230419 (v5.1)

See merge request espressif/esp-idf!23677
2023-05-11 01:55:34 +08:00
ae4d1c1f81 Merge branch 'feature/esp32c6_esp32h2_enable_panic_tests_v5.1' into 'release/v5.1'
tests: panic: esp32c6/esp32h2 enable (v5.1)

See merge request espressif/esp-idf!23683
2023-05-11 00:27:22 +08:00
eec03e6a32 Merge branch 'feature/freertos_add_create_task_with_caps_v5.1' into 'release/v5.1'
FreeRTOS: Add xTaskCreateWithCaps() (v5.1)

See merge request espressif/esp-idf!23382
2023-05-10 22:34:17 +08:00
6b31235f3f tests: panic: add esp32c6 esp32h2 2023-05-10 19:19:47 +08:00
2744e6ce07 Merge branch 'feature/refactor_gdbstub_v5.1' into 'release/v5.1'
esp_gdbstub: refactor code (v5.1)

See merge request espressif/esp-idf!23513
2023-05-10 19:11:39 +08:00
b3c5ee767a tools: update OpenOCD version to v0.12.0-esp32-20230419 2023-05-10 13:15:19 +03:00
ad5044c5f6 freertos: Add task creation with caps functions
This commit adds the corresponding CreateWithCaps functions for tasks:

- xTaskCreatePinnedToCoreWithCaps()
- xTaskCreateWithCaps()
- vTaskDeleteWithCaps()

Documentation and migraiton guide have been updated accordingly.

Closes https://github.com/espressif/esp-idf/issues/11216
2023-05-10 17:55:49 +08:00
4a35536244 Merge branch 'feature/freertos_get_static_buffers_v5.1' into 'release/v5.1'
FreeRTOS: Add GetStaticBuffer and CreateWithCaps functions (v5.1)

See merge request espressif/esp-idf!23381
2023-05-10 17:53:26 +08:00
670996f484 Merge branch 'bugfix/make_clean_files_v5.1' into 'release/v5.1'
build-system: replace ADDITIONAL_MAKE_CLEAN_FILES with ADDITIONAL_CLEAN_FILES (v5.1)

See merge request espressif/esp-idf!23661
2023-05-10 13:46:56 +08:00
8bb8c144c7 i2s_doc: fixed the data of stereo left/right state 2023-05-10 12:36:00 +08:00
653ba59b23 i2s_tdm: fixed half sample bit calculation and added check for slot mask 2023-05-10 12:34:14 +08:00
319e0689a5 i2s_std: fixed mclk check for 24-bit data and enable left alignment as default 2023-05-10 12:32:38 +08:00
6b86fc7ad7 Merge branch 'test/enlarge_gptimer_test_threshold_v5.1' into 'release/v5.1'
gptimer: enlarge test threshold (v5.1)

See merge request espressif/esp-idf!23622
2023-05-10 10:39:45 +08:00
f4c5fdbd1a Merge branch 'ci/migrate_peripherals_examples_v5.1' into 'release/v5.1'
ci: migrate peripherals ttfw test scripts (v5.1)

See merge request espressif/esp-idf!23403
2023-05-10 10:25:40 +08:00
7b93cf91aa mcpwm: can't apply the same delay module to multiple generators
This is a hardware limitation, one delay module can only be used by one generator at one time.

Closes https://github.com/espressif/esp-idf/issues/11327
2023-05-10 10:09:48 +08:00
63153794c9 build-system: replace ADDITIONAL_MAKE_CLEAN_FILES with ADDITIONAL_CLEAN_FILES
ADDITIONAL_MAKE_CLEAN_FILES is deprecated and only worked with make.
Replaced with the new ADDITIONAL_CLEAN_FILES (CMake 3.15) which also works with ninja.
2023-05-10 09:53:55 +08:00
19a2e42770 ci: fix invalid kconfig options in system test apps 2023-05-10 09:42:12 +08:00
45fd8feba3 ulp: add support for using lp timer with lp core on C6 2023-05-10 09:39:24 +08:00
f5020d3f1b Merge branch 'bugfix/freertos_nested_sched_suspension_v5.1' into 'release/v5.1'
freertos-idf: Fixed incorrect scheduler suspension check in xTaskRemoveFromEventList() (v5.1)

See merge request espressif/esp-idf!23650
2023-05-10 01:41:34 +08:00
08600cb1a3 ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option
The commit 88e4c06028 introduced a loop timeout for all ULP RISC-V I2C
transactions to avoid getting stuck in a forever loop. The loop timeout
was set to 500 msec by default. This commit improves on the concept by
making the loop timeout configurable via a Kconfig option in terms of
CPU ticks. If the timeout is set to -1 value then the transaction loops
will never timeout, therefore restoring the driver behavior before the
timeout was introduced.

The commit also updates the I2C Fast mode timings for esp32s2 which need
to be adjusted due to bus timing constraints.

Closes https://github.com/espressif/esp-idf/issues/11154
2023-05-09 15:07:50 +02:00
236d601e98 mcpwm: reset peripheral in restart, panic and halt
mcpwm is commonly used in power eletronic area, when restart happens,
make sure the mcpwm generator is not working.

closes https://github.com/espressif/esp-idf/issues/11324
2023-05-09 18:30:46 +08:00
ee18b19b8f freertos-idf: Fixed incorrect scheduler suspension check in xTaskRemoveFromEventList()
This commit fixes a bug in xTaskRemoveFromEvenetList() where in the
check for scheduler suspension did not account for nested suspensions.
Additionally, this commit updates all checks for scheduler
suspension to follow a uniform way.
2023-05-09 12:25:09 +02:00
27f044bd7f i2s_pdm: enable example pytest on h2 (v5.1) 2023-05-09 17:30:40 +08:00
5a353ab1ca Merge branch 'docs/add_cn_trans_i2s_v5.1' into 'release/v5.1'
Docs: add CN translation for i2s.rst (backport v5.1)

See merge request espressif/esp-idf!23625
2023-05-09 15:13:45 +08:00
bac34f23bc Docs: add CN translation for i2s.rst (backport v5.1) 2023-05-09 15:13:44 +08:00
8a08cfe7d1 Merge branch 'bugfix/fix_own_addr_is_rap_random_err_v5.1' into 'release/v5.1'
Fixed no error report when own address type is rpa_random and no random address setting(backport v5.1)

See merge request espressif/esp-idf!23623
2023-05-08 20:20:53 +08:00
242713ceee Merge branch 'bugfix/ana_cmpr_negative_enum_v5.1' into 'release/v5.1'
driver: Fix ana_cmpr negative enum comparison and bad test (v5.1)

See merge request espressif/esp-idf!23630
2023-05-08 19:44:56 +08:00
1d3a08d06f Merge branch 'docs/provide_CN_trans_for_22939_backport_v5.1' into 'release/v5.1'
docs: update links in mdns.rst (backport_v5.1)

See merge request espressif/esp-idf!23633
2023-05-08 19:43:31 +08:00
e6de764ca1 docs: update links in mdns.rst_backport_v5.1 2023-05-08 17:46:58 +08:00
3948949019 driver: Fix ana_cmpr negative enum comparison
The C17 standard (sec 6.7.2.2) indicates that the underlying type of an enum is
implementation defined (i.e., can be signed or unsigned). Thus, comparing
"-1 >= some_enum" where "some_enum" is always 0 or largert can return true if
the compiler uses unsigned for enums.

This commit fixes the following issues with ana_cmpr:

- Fixed incorrect comparison in ana_cmpr_del_unit() that relied on enums being
signed, thus would always return true.
- Fixed incorrect expected argument in the "ana_cmpr_unit_install_uninstall"
test. This was not picked up due to the incorrect enum comparison above.
2023-05-08 17:11:52 +08:00
24cc2d714e Fixed BLE disconnection failure on ESP32 2023-05-08 12:17:09 +08:00
16696d98c1 Fixed battery profile wrong condition 2023-05-08 11:31:22 +08:00
zwj
daf2622a5b Fixed no error report when own address type is rpa_random and no random address setting 2023-05-08 11:31:06 +08:00
864f5532fa gptimer: enlarge test threshold 2023-05-08 10:18:58 +08:00
d4a3427eaf Merge branch 'bugfix/gdma_log_nano_v5.1' into 'release/v5.1'
gdma: fixed crash from logging when using newlib nano (v5.1)

See merge request espressif/esp-idf!23585
2023-05-08 10:13:55 +08:00
94d6614c88 Merge branch 'ci/fix_overwrite_pytest_configs_v5.1' into 'release/v5.1'
ci: fixed test apps overriding pytest configs (v5.1)

See merge request espressif/esp-idf!23495
2023-05-06 17:40:58 +08:00
de5a9ac1f3 Merge branch 'bugfix/check_filter_range_v5.1' into 'release/v5.1'
rmt: check filter and idle threashold (v5.1)

See merge request espressif/esp-idf!23604
2023-05-06 14:00:20 +08:00
46f104b3ae gdma: fixed crash from logging when using newlib nano
Newlib nano printf formatting do not support %z, and will crash if such an identifier
is followed by a %s indentifier.

Closes https://github.com/espressif/esp-idf/issues/9631
2023-05-06 13:47:51 +08:00
dd747bd54d Merge branch 'contrib/github_pr_11326_v5.1' into 'release/v5.1'
correct typo in reference to ESP-IDF repo (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23551
2023-05-06 13:09:33 +08:00
7d96d9e306 Merge branch 'backport/fix_openthread_ci' into 'release/v5.1'
OpenThread CI: add a function for executing commands(backport v5.1)

See merge request espressif/esp-idf!23602
2023-05-06 10:34:06 +08:00
1111fd2630 Merge branch 'contrib/github_pr_11296_v5.1' into 'release/v5.1'
Fix references to IDF_ADD_PATHS_EXTRAS before being assigned (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23599
2023-05-05 21:12:11 +08:00
d12ad17373 rmt: check filter and idle threashold
Closes https://github.com/espressif/esp-idf/issues/11262
2023-05-05 19:07:59 +08:00
4db113a2eb Merge branch 'bugfix/hf_cind_ind_index_v5.1' into 'release/v5.1'
bt: Fixed the inconsistency between the indicator event received by the HF application layer and the actually received indicator(v5.1)

See merge request espressif/esp-idf!23559
2023-05-05 18:47:45 +08:00
bba2581f1a Merge branch 'bugfix/fatfs_open_O_CREAT_fails_v5.1' into 'release/v5.1'
fatfs: fix "open("xx",O_CREAT|O_WRONLY,0666)" call failure (v5.1)

See merge request espressif/esp-idf!23561
2023-05-05 18:13:51 +08:00
938bcc0337 OpenThread CI: add a function for executing commands 2023-05-05 18:05:02 +08:00
845efafc76 Fix references to IDF_ADD_PATHS_EXTRAS before being declared 2023-05-05 11:17:24 +02:00
cje
78b9f5e151 fix too low hp ldo dbias bug for h2 2023-05-05 17:04:18 +08:00
8dbe966d89 fix a2dp source crash when connect to Bose speaker 2023-05-04 19:00:20 +08:00
38570b052b pm: fix invalid trace pins for C6 and H2 2023-05-04 14:42:17 +08:00
4477f3e559 bugfix: fix for fatfs "open("xx",O_CREAT|O_WRONLY,0666)" call failure
fatfs 'open' with only O_CREAT flag fails to creat new file

Closes https://github.com/espressif/esp-idf/issues/1817
2023-05-04 11:45:37 +05:30
25e8069532 bt: Fixed the inconsistency between the indicator event received by the HF application layer and the actually received indicator.
Closes https://github.com/espressif/esp-idf/issues/6486
2023-05-04 14:08:30 +08:00
90e354a723 wpa_supplicant: Reduce logging for SAE 2023-05-04 11:23:55 +05:30
2004bf4e11 Merge branch 'bugfix/rmt_one-wire_v5.1' into 'release/v5.1'
rmt_onewire: refactor example with component registry (v5.1)

See merge request espressif/esp-idf!23509
2023-05-04 13:32:18 +08:00
a0a6e34f4f docs: fix wrong link to esp-adf github issues in migration guide 2023-05-04 12:57:08 +08:00
6b5b7f09f9 i2c: fix a bug in sda sample timing
* Closes https://github.com/espressif/esp-idf/issues/9777

This bug prevented SCL line to work properly after a NACK was received in master mode.
2023-05-04 12:14:43 +08:00
42d5b865dd Fixed the issue that the a2dp source would not send the media start command due to the connection initiated by the peer device
Closes https://github.com/espressif/esp-idf/issues/11170
2023-05-04 12:13:27 +08:00
123da6baa7 bugfix: fix esp32c6eco1 fosc calibration cycles during sleep 2023-05-04 11:47:54 +08:00
2654d29bc5 correct typo in reference to ESP-IDF repo
There's a reference to the ESP-ADF repo that looks like it was intended to be a reference to the ESP-IDF repo. This branch fixes the reference.
2023-05-04 11:43:08 +08:00
b3b85cafb1 Merge branch 'bugfix/fix_ble_hop_sel_v5.1' into 'release/v5.1'
Fixed BLE connection failed to be established when disabled 5.0 feature (backport 5.1)

See merge request espressif/esp-idf!23530
2023-05-04 11:38:06 +08:00
21fd9aaee8 ci: small cleanup for the dependencies.yml 2023-05-04 11:21:40 +08:00
8fd3b342aa ci: add pattern ccs811 2023-05-04 11:21:39 +08:00
1c1c6d59b3 ci: migrate peripherals ttfw test scripts 2023-05-04 11:21:29 +08:00
f2d144166a sdio_example: fix meaningless print in host, make shared reg access more readable in slave 2023-05-04 11:21:10 +08:00
e704f72356 Merge branch 'backport/ble_bugfix_5_1' into 'release/v5.1'
ble: [ESP32C6][ESP32H2][ESP32C2] updata libble

See merge request espressif/esp-idf!23523
2023-05-04 10:52:01 +08:00
4f1fc73fc2 Merge branch 'bugfix/eth_driver_cleanup_v5.1' into 'release/v5.1'
Ethernet driver and documentation clean-up (v5.1)

See merge request espressif/esp-idf!23545
2023-05-04 10:05:25 +08:00
2508350137 Merge branch 'bugfix/eth_l2_test_switch_v5.1' into 'release/v5.1'
LAN8720 & IP101 L2 Test Fix (v5.1)

See merge request espressif/esp-idf!23535
2023-05-04 10:04:46 +08:00
058bb0edd0 docs: update translation for esp_eth 2023-05-03 07:39:24 +00:00
71d19fa9c9 Ethernet driver and documentation clean-up 2023-05-03 07:39:24 +00:00
07d1e19107 improve thread safety in esp_timer
Inadequate locking in the esp_timer component allowed corruption
of the s_timers linked list:

1. timer_armed(timer) returns false
2. another task arms the timer and adds it to s_timers
3. the list is locked
4. the timer is inserted into s_timers again

The last step results in a loop in the s_timers list, which causes
an infinite loop when iterated. This change always locks the
list before checking if the timer is already armed avoiding
the data race.
2023-05-02 20:22:24 +02:00
1042115566 esp_eth pytest: increased robustness of the L2 test
Added filtering frames based on MAC address
2023-05-02 10:25:58 +02:00
b97cf6ca7c Merge branch 'fix/ecdsa_hal_v5.1' into 'release/v5.1'
ecdsa: Support multiple ECDSA keys (v5.1)

See merge request espressif/esp-idf!23444
2023-05-02 11:48:17 +08:00
5775e1d3b7 esp_system (C6 & H2): Enables BOOTLOADER_RESERVE_RTC_MEM feature for bootloader
This option reserves an area in RTC FAST memory for the following features:
- "Skip image validation when exiting deep sleep"
- "Reserve RTC FAST memory for custom purposes"
- "GPIO triggers factory reset"
2023-05-01 06:27:11 +00:00
4a74ae4921 ci: Add patterns and target-tests for ecdsa_efuse runner 2023-04-30 11:48:46 +05:30
5fac5b0191 mbedtls/ecdsa: Add ECDSA signature generation test 2023-04-30 11:47:35 +05:30
abc099ce9f ecdsa: Support multiple ECDSA keys
Add provision to choose which efuse block should be used as ECDSA
private key
2023-04-30 11:47:35 +05:30
174ef6c4a3 ecdsa_hal.c: Add missing configuration for signature generation 2023-04-30 11:47:35 +05:30
89c06b3c51 Update bt lib for ESP32-C3 and ESP32-S3
- Fixed ble hopping selection for connection when disabled 5.0 feature
2023-04-28 19:30:45 +08:00
62a5ad5fc1 sdmmc: add vTaskDelay to loops to prevent potential WDT trigger
Also change timeout to 120 seconds in fatfs sdcard pytest to prevent failing during formatting.
2023-04-28 12:39:08 +02:00
c7ca30e62f [SDMMC] add reasonable timeouts to all while loops
Closes: https://github.com/espressif/esp-idf/pull/10532
2023-04-28 12:39:06 +02:00
6ff1059da7 [SDMMC Mount] fix infinite loop when SD card is not responsive
Closes: https://github.com/espressif/esp-idf/pull/10532
2023-04-28 12:37:27 +02:00
d6a1ccb27f ble: [ESP32C6][ESP32H2][ESP32C2] updata libble
Fixed the occasional mic error caused by wrong tx cnt
Fixed the BLE connection timeout issue
2023-04-28 17:27:36 +08:00
zwl
e575e0b44a Ble: bugfix for packet loss issue during connection on ESP32C6 2023-04-28 17:27:08 +08:00
cbd210b431 Merge branch 'refactor/rename_to_esp_clk_tree_prefix_v5.1' into 'release/v5.1'
esp_clk_tree: Rename clk_tree_xxx to esp_clk_tree_xxx (v5.1)

See merge request espressif/esp-idf!23449
2023-04-28 17:11:46 +08:00
14dac35540 rmt_onewire: refactor example with component manager
Closes https://github.com/espressif/esp-idf/issues/10790
2023-04-28 13:38:33 +08:00
71a19d238c esp_gdbstub: refactor code 2023-04-28 12:38:26 +08:00
961018d882 Merge branch 'bugfix/pmkid_sha256_bug_v5.1' into 'release/v5.1'
wpa_supplicant: Fix PMKID SHA-256 related regression (Backport v5.1)

See merge request espressif/esp-idf!23494
2023-04-28 07:52:52 +08:00
c710a69952 Merge branch 'bugfix/fix_softap_pairwise_cipher_issue_v5.1' into 'release/v5.1'
esp_wifi: update pairwise cipher in softAP(Backport v5.1)

See merge request espressif/esp-idf!23503
2023-04-28 04:45:59 +08:00
eeea0a7ea8 Merge branch 'feature/esp_tls_add_getter_setter_v5.1' into 'release/v5.1'
esp-tls: Added getter/setter function for the conn_state. (v5.1)

See merge request espressif/esp-idf!23408
2023-04-28 04:36:25 +08:00
5fdb9b00c5 CI: fix sdcard examples timeout 2023-04-27 17:47:12 +02:00
310e5e71ed Merge branch 'bugfix/spp_notify_v5.1' into 'release/v5.1'
NimBLE: Removed indicate flag from gatt db and added subscription case in spp_server example (v5.1)

See merge request espressif/esp-idf!23458
2023-04-27 23:36:24 +08:00
9a58988bae Merge branch 'test/removed_emmc_esp32_ut_v5.1' into 'release/v5.1'
emmc: removed esp32 emmc ut_017 (v5.1)

See merge request espressif/esp-idf!23485
2023-04-27 23:34:24 +08:00
d89db7e4a7 Merge branch 'feature/spi_hal_move_out_iram_v5.1' into 'release/v5.1'
spi: change linker file to move spi hal out from iram (v5.1)

See merge request espressif/esp-idf!23448
2023-04-27 23:31:16 +08:00
c0c9227883 Merge branch 'fix/sdio_sd_cards_not_detected_correctly_v5.1' into 'release/v5.1'
sdmmc: sdio combination cards correct setup (v5.1)

See merge request espressif/esp-idf!23478
2023-04-27 23:28:28 +08:00
c49dce48eb Merge branch 'fix/esp32s3_ununsed_dcache_as_dram_v5.1' into 'release/v5.1'
esp_hw_support: Update the memory ptr location/property checks to include the unused DCACHE added to DRAM (v5.1)

See merge request espressif/esp-idf!23303
2023-04-27 22:09:55 +08:00
1a03cb02c2 Merge branch 'feature/support_fosc_calibration_c6_eco1_to_v5.1' into 'release/v5.1'
ESP32C6: Fix fosc calibration fail bug for ECO1 & Above (v5.1)

See merge request espressif/esp-idf!23467
2023-04-27 20:38:31 +08:00
193f581cec esp_wifi: update pairwise cipher in softAP 2023-04-27 20:07:48 +08:00
f03e3c164e esp_supplicant: When the softAP authentication mode is set to WPA2_PSK, WPA2_WPA3_PSK, or WPA3_PSK, the pairwise cipher will be overwritten with WIFI_CIPHER_TYPE_CCMP 2023-04-27 20:07:39 +08:00
8d383980a1 esp_supplicant: wpa pmf should be disabled 2023-04-27 20:07:30 +08:00
202b18b5fa esp_clk_tree: Rename clk_tree_xxx to esp_clk_tree_xxx, add compilation warning to clk_tree.h 2023-04-27 11:11:18 +00:00
3048251be0 Merge branch 'ci/pytest_case_tester_script_fix_v5.1' into 'release/v5.1'
ci: pytest automation script increase timeout time (v5.1)

See merge request espressif/esp-idf!23447
2023-04-27 17:35:51 +08:00
c35f7cad45 Merge branch 'feature/c6_ulp_sleep_v5.1' into 'release/v5.1'
ulp: added sleep support for lp core (v5.1)

See merge request espressif/esp-idf!23484
2023-04-27 17:07:24 +08:00
1b4e46428d Merge branch 'bugfix/reject_tkip_in_owe_v5.1' into 'release/v5.1'
Reject TKIP cipher incase of OWE connection (Backport v5.1)

See merge request espressif/esp-idf!23462
2023-04-27 16:51:15 +08:00
5bba395bc8 Merge branch 'bugfix/wifi_prov_deinit_github_v5.1' into 'release/v5.1'
wifi_prov_mgr: Fixed memory leak after bluetooth stack was stopping. (v5.1)

See merge request espressif/esp-idf!23436
2023-04-27 16:33:53 +08:00
8719a45d97 Merge branch 'ci/fix_no_test_script_corner_case_v5.1' into 'release/v5.1'
ci: fix build script when no test script found (v5.1)

See merge request espressif/esp-idf!23404
2023-04-27 16:10:10 +08:00
0e484e1daa Merge branch 'feature/bt_uses_creationg_with_caps_functions_v5.1' into 'release/v5.1'
BT: Remove "create static" calls from OSI (v5.1)

See merge request espressif/esp-idf!23337
2023-04-27 16:06:10 +08:00
0be6802198 Merge branch 'backport/ieee802154_open_src' into 'release/v5.1'
ieee802154: drive code open source (backport v5.1)

See merge request espressif/esp-idf!23461
2023-04-27 16:02:09 +08:00
9f80af3770 Merge branch 'bugfix/ble_mesh_fix_heartbeat_set_v5.1' into 'release/v5.1'
ble_mesh: stack: Update the heartbeat filter entry add/remove handling (v5.1)

See merge request espressif/esp-idf!23460
2023-04-27 14:38:27 +08:00
411c392d97 Merge branch 'feature/support_fosc_calibration_h2_eco2_to_v5.1' into 'release/v5.1'
ESP32H2: Fix fosc calibration fail bug for ECO2 & Above (v5.1)

See merge request espressif/esp-idf!23469
2023-04-27 14:38:01 +08:00
3724bf6256 ci: fixed test apps overriding pytest configs 2023-04-27 14:29:06 +08:00
a64cbdea10 wpa_supplicant: Fix PMKID SHA-256 related regression
Fixed regression caused by commit 38e9c8b4
2023-04-27 11:35:20 +05:30
728c1ffe59 Merge branch 'backport/openthread_ci_fix' into 'release/v5.1'
Openthread: add delay to ensure that the dut can receive input command(BackportV5.1)

See merge request espressif/esp-idf!23486
2023-04-27 13:56:46 +08:00
2bc721739c Merge branch 'bugfix/i2s_tdm_multi_dev_on_h2_v5.1' into 'release/v5.1'
i2s: fixed tdm multi dev test on h2 (v5.1)

See merge request espressif/esp-idf!23475
2023-04-27 13:20:03 +08:00
34e0ed613a Nimble:Added change to expose addr resolution API outside stack 2023-04-27 10:33:47 +05:30
7492e0a2c7 Merge branch 'support/backport_154_related_feature' into 'release/v5.1'
openthread: backport Thread related fixes (backport v5.1)

See merge request espressif/esp-idf!23427
2023-04-27 11:57:47 +08:00
ea65b1fefb esp_phy: remove esp32h4 phylib 2023-04-27 11:28:12 +08:00
a33c60a36f ieee802154: remove libieee802154.a for target esp32h4 2023-04-27 11:28:12 +08:00
3178718a3d ieee802154: support driver opensrc 2023-04-27 11:27:57 +08:00
deedc51cf1 Merge branch 'ci/chip_support_network_invalid_kconfig_v5.1' into 'release/v5.1'
ci: remove redundent ci configs for chip support and network components (v5.1)

See merge request espressif/esp-idf!23471
2023-04-27 11:10:54 +08:00
f7e3f76899 openthread CI: add delay to ensure that the dut can receive input command 2023-04-27 10:54:19 +08:00
46511c8fd1 Merge branch 'bugfix/fix_wrong_frame_ptr_after_wake_restore_backportv5.1' into 'release/v5.1'
bugfix: fix wrong RvCoreCriticalSleepFrame ptr value after wake restore (backport v5.1)

See merge request espressif/esp-idf!23473
2023-04-27 10:45:04 +08:00
96b3f52c4e emmc: temporarily removed esp32 emmc ut_017 2023-04-27 10:30:38 +08:00
2117b7a1dc Merge branch 'contrib/github_pr_11113_v5.1' into 'release/v5.1'
Fix usb enumeration stage error for some device (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23332
2023-04-27 10:12:12 +08:00
3ae079ac12 Merge branch 'bugfix/fix_duplicate_scan_cycle_refresh_not_accurate_v5.1' into 'release/v5.1'
Fixed duplicate scan refresh cycle is not accurate after restarting scan on ESP32(backport v5.1)

See merge request espressif/esp-idf!23405
2023-04-27 10:02:17 +08:00
0bac174058 ulp: added sleep support for lp core
Added support for running LP core while hp core sleeps, as well
as waking up the hp core.
2023-04-27 09:51:41 +08:00
856cfa4ae2 Merge branch 'refactor/remove_esp32h4_target_v5.1' into 'release/v5.1'
esp32h4: remove esp32h4 target (v5.1)

See merge request espressif/esp-idf!23422
2023-04-27 09:37:51 +08:00
0d13dbbb1f OpenThread border router: support border router to connect with SSED 2023-04-27 09:16:10 +08:00
51c058d80f ieee802154: increase the timeout for ieee802.15.4 CI test 2023-04-27 09:16:10 +08:00
aea120b98b openthread: fix the spi conflict between ot-spinel and ethernet 2023-04-27 09:16:10 +08:00
7909394274 openthread: fix platform udp send rules for OT netif 2023-04-27 09:16:10 +08:00
6bfa2b7078 openthread port: set ipv6 address zone with netif index when udp joining or leaving group 2023-04-27 09:16:10 +08:00
86a673946c openthread: Add check for lock acquire and release 2023-04-27 09:16:10 +08:00
aedcec9be5 Merge branch 'feature/emmc_example_v5.1' into 'release/v5.1'
SDMMC Host: added an example to communicate with an eMMC chip and also a bugfix for Host timing (v5.1)

See merge request espressif/esp-idf!23283
2023-04-26 22:41:15 +08:00
934f0477a4 Merge branch 'bugfix/allow_no_specify_uart_clk_src_v5.1' into 'release/v5.1'
uart: Allow omitting source_clk parameter to uart_param_config (v5.1)

See merge request espressif/esp-idf!23451
2023-04-26 20:32:35 +08:00
81988b0007 Merge branch 'docs/add_Chinese_translation_for_api-reference/error-codes_backport_v5.1' into 'release/v5.1'
docs: provide translation for docs/zh_CN/api-reference/error-codes.rst (backport v5.1)

See merge request espressif/esp-idf!23397
2023-04-26 19:47:13 +08:00
de45fb1c33 docs: provide translation for docs/zh_CN/api-reference/error-codes.rst (backport v5.1) 2023-04-26 19:47:13 +08:00
29be39086f Merge branch 'docs/update_out_of_sync_api-reference_docs_backport_v5.1' into 'release/v5.1'
docs: update out-of-sync api reference docs (backport v5.1)

See merge request espressif/esp-idf!23399
2023-04-26 19:45:23 +08:00
934c2c3a58 sdmmc: sdio combination cards correct setup
Co-authored-by: Mau Abata <mauabata@gmail.com>
Closes https://github.com/espressif/esp-idf/issues/9822
Closes https://github.com/espressif/esp-idf/issues/10280
2023-04-26 13:27:59 +02:00
0aad1efe15 i2s: fixed tdm multi dev test on h2 2023-04-26 18:55:36 +08:00
87328d594f esp32h4: checked all the corner stuffs of the removal 2023-04-26 18:53:12 +08:00
954a6a2cff esp32h4: removed esp32h4 related codes 2023-04-26 18:53:12 +08:00
cae47ce37e esp32h4: removed esp32h4 related files 2023-04-26 18:53:12 +08:00
8f24b34f21 esp32h4: remove esp32h4 target from ci 2023-04-26 18:53:12 +08:00
804a9ea1f6 esp32h4: remove esp32h4 target from peripherals 2023-04-26 18:53:10 +08:00
46deef434f esp_pm: check sleep retention frame integrity in ci UT 2023-04-26 17:36:46 +08:00
5ccf93d788 bugfix: fix wrong RvCoreCriticalSleepFrame ptr value after wake restore 2023-04-26 17:36:42 +08:00
4c3c6b7f99 ci: remove redundent ci configs for chip support and network components
CI would build psram config test apps even for target with no psram.
2023-04-26 17:29:51 +08:00
70fc0bde01 support h2 eco2 fosc calibration for v5.1 2023-04-26 17:08:09 +08:00
1564884cc1 support c6 eco1 fosc calibration for v5.1 2023-04-26 16:32:28 +08:00
86226770b8 esp_wifi: Reject TKIP cipher incase of OWE connection 2023-04-26 12:10:33 +05:30
e121775d6c ble_mesh: stack: Update the heartbeat filter entry add/remove handling 2023-04-26 14:17:11 +08:00
ef3da6b372 NimBLE: Removed indicate flag from gatt db, added subscription case and corrected indentation
in spp_server example.
2023-04-26 11:39:09 +05:30
1b6461b9f8 Merge branch 'bugfix/bod_glitch_reset_c6_v5.1' into 'release/v5.1'
bootloader: fix BOD and glitch reset on C6 and H2 (v5.1)

See merge request espressif/esp-idf!23380
2023-04-26 13:09:32 +08:00
16f3317496 soc/esp32s3: Fix the SOC_MEM_INTERNAL_HIGH value
- As per the memory block diagram for ESP32-S3, the
  internal memory address ranges as follows:
  DRAM: 0x3FC88000 (== SOC_MEM_INTERNAL_LOW) <-> 0x3FCF0000
  IRAM: 0x40378000 <-> 0x403E0000 (== SOC_MEM_INTERNAL_HIGH)
2023-04-26 04:01:38 +00:00
3118120659 esp_hw_support: Update memory ptr location/property checks
- to acknowledge the unused DCACHE added to DRAM for ESP32-S3

- For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is added to
  the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB (from 0x3C000000).
- But, if we try allocating memory from the 16 kB block and run an `esp_ptr_internal`
  check on that memory pointer, it fails as the address block from 0x3C000000
  corresponds to the external memory symbols SOC_DROM_LOW and SOC_EXTRAM_DATA_LOW.
  (E.g. freertos - If the IDLE task stack buffer gets allocated from this region,
  the firmware will abort due to this failure).
- Thus, the checks `esp_ptr_internal`, `esp_ptr_in_drom` and `esp_ptr_byte_accessible`
  have been updated to acknowledge this memory as a part of the DRAM.

Co-authored-by: Mahavir Jain <mahavir@espressif.com>
2023-04-26 04:01:38 +00:00
e1b89eeae0 Merge branch 'feature/s2_ulp_riscv_adc_v5.1' into 'release/v5.1'
ulp-riscv: enable ULP-RISCV ADC example for esp32s2 (v5.1)

See merge request espressif/esp-idf!23371
2023-04-26 11:59:20 +08:00
cfcb57333b Merge branch 'bugfix/fix_chip_broken_bug_in_monitor_mode_S2_v5.1' into 'release/v5.1'
ESP32S2/C3/C2: fixed S2 dangerous power parameters in sleep modes and support S2/C3/C2 different sleep mode (v5.1)

See merge request espressif/esp-idf!23378
2023-04-26 11:41:09 +08:00
24bfb8a8e5 uart: Allow the users to not specify the source_clk in uart_config_t when calling uart_param_config 2023-04-26 11:24:16 +08:00
f61e219667 spi: change linker file let spi hal able to out from iram 2023-04-26 11:15:30 +08:00
40b0dbae10 spi_flash: fix config SPI_FLASH_SHARE_SPI1_BUS dependency 2023-04-26 11:15:30 +08:00
ee4e5c014a sdio: test_sdio add unity sync signals 2023-04-26 11:11:59 +08:00
4dcd055612 ci: pytest automation script increase timeout time 2023-04-26 11:11:59 +08:00
6b28967b64 Merge branch 'bugfix/fix_adc_continuouus_example_pytest_potential_failure_v5.1' into 'release/v5.1'
adc: fix adc_continuous example pytest potential failure (v5.1)

See merge request espressif/esp-idf!23425
2023-04-25 19:59:43 +08:00
f6e0867eb8 wifi_prov_mgr: Fixed memory leak after bluetooth stack was stopping. 2023-04-25 15:48:09 +05:30
30cc0769ac Merge branch 'refactor/remove_esp_mm_kconfig_as_no_kconfig_option_now_v5.1' into 'release/v5.1'
esp_mm: removed empty kconfig files (v5.1)

See merge request espressif/esp-idf!23284
2023-04-25 17:52:35 +08:00
f793584c68 Merge branch 'docs/update_cn_trans_api_guides' into 'release/v5.1'
Docs: Update cn trans api guides (backport v5.1)

See merge request espressif/esp-idf!23384
2023-04-25 17:16:43 +08:00
3a34660d54 Docs: Update cn trans api guides (backport v5.1) 2023-04-25 17:16:43 +08:00
d54af90022 Merge branch 'ci/disable_test_dram_reg2_execute_violation_v5.1' into 'release/v5.1'
ci: disable test_dram_reg2_execute_violation on esp32s2 (v5.1)

See merge request espressif/esp-idf!23420
2023-04-25 14:28:16 +08:00
a0df46d342 Merge branch 'bugfix/wifi_backport_v5.1' into 'release/v5.1'
esp_wifi: backport some wifi fixes to v5.1

See merge request espressif/esp-idf!23389
2023-04-25 13:52:44 +08:00
959f92e744 Merge branch 'docs/esp_protocols_docs_migration_v5.1' into 'release/v5.1'
docs: migrated documentation from github.io to docs.espressif.com (v5.1)

See merge request espressif/esp-idf!23319
2023-04-25 13:49:13 +08:00
e23ce8209d fix adc_continuous example pytest potential failure 2023-04-25 12:26:34 +08:00
92965cd124 Merge branch 'feature/sram1_iram_v5.1' into 'release/v5.1'
system: add kconfig option for using parts of SRAM1 for IRAM (v5.1)

See merge request espressif/esp-idf!23370
2023-04-25 11:35:08 +08:00
8c11edb852 Merge branch 'feature/update_mbedtls_v5.1' into 'release/v5.1'
mbedtls: Update to release/v3.4.0 (v5.1)

See merge request espressif/esp-idf!23398
2023-04-25 11:04:44 +08:00
f67a860cf0 ci: disable test_dram_reg2_execute_violation on esp32s2 2023-04-25 10:02:00 +08:00
9d114e30b5 Merge branch 'feature/esp_sys_iram_cleanup_v5.1' into 'release/v5.1'
esp-system: move uncessary IRAM functions to flash (v5.1)

See merge request espressif/esp-idf!23376
2023-04-25 09:51:25 +08:00
e104fa1904 Merge branch 'bugfix/esp32_pico_v3_2_chip_info_v5.1' into 'release/v5.1'
system: fix esp32 chip info not listing esp32 pico v3-02 as having embedded spiram (v5.1)

See merge request espressif/esp-idf!23393
2023-04-25 09:46:25 +08:00
d7b344c97a heap: Add a configuration that places all the heap component and related functionalities in flash when enabled
Add test configuration to run all tests with heap component in the flash.
Add reference to this new configuration in performance section of the documentation.
2023-04-25 01:12:10 +00:00
5bea8592d9 Merge branch 'ci/run_readme_checks_not_in_parallel' into 'release/v5.1'
ci: run readme check when constants.py or check script updated (v5.1)

See merge request espressif/esp-idf!23386
2023-04-25 09:00:59 +08:00
0f8bf38913 ci: run readme check when constants.py or check script updated 2023-04-25 08:51:22 +08:00
e24e674e2f esp-tls: Added getter/setter function for the conn_state.
* Added the setter function to set the connection sockfd value
Closes https://github.com/espressif/esp-idf/issues/10871
2023-04-24 14:49:26 +05:30
zwj
52ca53746f Fixed disconnection due to consecutive CRC errors in first 6 intervals 2023-04-24 15:49:36 +08:00
zwj
a26449844f Fixed duplicate scan refresh cycle is not accurate after restarting scan on ESP32 2023-04-24 15:49:12 +08:00
d020a58be1 Merge branch 'ci/soc_caps_docs_build_v5.1' into 'release/v5.1'
ci: build all docs if soc_caps.h changed (v5.1)

See merge request espressif/esp-idf!23374
2023-04-24 15:48:15 +08:00
4f40bfd864 ci: fix build script when no test script found 2023-04-24 15:47:58 +08:00
75002dce56 Merge branch 'contrib/github_pr_11163_v5.1' into 'release/v5.1'
Make custom bootloader message match actual output (GitHub PR) (v5.1)

See merge request espressif/esp-idf!23375
2023-04-24 15:46:58 +08:00
b8718506cd mbedtls: fix ci failures for update v3.4.0
- While updating to mbedtls release/v3.4.0, building mbedtls/library/psa_crypto.c,
clang produced an unreachable-code warning, so added `-Wno-unreachable-code` compile option for clang.
- In `mbedtls/v3.4.0`, the ECDSA restartable sign and verify functions (`ecdsa.c`) were made public.
- But the `mbedtls_ecdsa_sign_det_restartable` function prototype was declared in the file `ecdsa.h`,
only when `MBEDTLS_ECDSA_SIGN_ALT` was not defined.
- added a patch in mbedtls library to fix it.
2023-04-24 11:56:56 +05:30
0116dcb578 mbedtls: replace low-level sha apis with md apis in esp_ssl_tls 2023-04-24 11:56:56 +05:30
3152dea192 mbedtls: Update config options as per release/v3.4.0
- Added a Kconfig option for the newly added mbedtls option MBEDTLS_PKCS7_C
2023-04-24 11:56:56 +05:30
31e42e77de mbedtls: Update to release/v3.4.0
- Release Notes: https://github.com/Mbed-TLS/mbedtls/releases/tag/v3.4.0
2023-04-24 11:56:56 +05:30
f0b2bd5c81 docs: update out-of-sync api reference docs 2023-04-24 14:23:35 +08:00
83a682ca1a Merge branch 'monitor_win_color-v5.1' into 'release/v5.1'
bug(idf_monitor): fix color on windows with hints (v5.1)

See merge request espressif/esp-idf!23346
2023-04-24 14:00:05 +08:00
9ddd08c502 system: fix esp32 chip info not listing esp32 pico v3-02 as having embedded spiram
Closes https://github.com/espressif/esp-idf/issues/11233
2023-04-24 13:53:26 +08:00
4e73cb77e5 Merge branch 'esptool_extra-v5.1' into 'release/v5.1'
feat(esptool): allow to set force for write_flash (v5.1)

See merge request espressif/esp-idf!23338
2023-04-24 13:44:41 +08:00
f9ebbdf6ea esp_wifi:Enable wpsreg to initialize in APSTA mode 2023-04-24 12:32:47 +08:00
39caffc592 esp_wifi: espnow support using 11ax rate to send frame 2023-04-24 12:32:27 +08:00
ce5444d349 esp_wifi: Bugfix store authmode security in NVS 2023-04-24 12:32:08 +08:00
79dabf50b0 esp_wifi: Install keys after successful transmission of EAPOL 4/4 Message 2023-04-24 12:31:21 +08:00
a4dbb3a0a1 esp_wifi: Update wifi libs
Fix some NAN issues related to followup and matching filters
2023-04-24 12:30:54 +08:00
8438887cb4 esp_wifi: update phy_init_data.h for c6 mcs 8 9 power issue 2023-04-24 12:30:30 +08:00
7a410499f3 esp_wifi: Validate softap interface when sending beacon frame 2023-04-24 12:30:04 +08:00
c020a68e1e Update the ESP-NOW frame length in docs 2023-04-24 12:29:32 +08:00
55d44e0bee wifi_mesh: fix the heap corrupt issue in MTXON task 2023-04-24 12:29:19 +08:00
5736694dbc Merge branch 'bugfix/adds_iram_attr_for_some_esp_timer_apis_v5.1' into 'release/v5.1'
esp_timer: Adds IRAM_ATTR for esp_timer_restart and esp_timer_is_active (v5.1)

See merge request espressif/esp-idf!23309
2023-04-24 11:48:02 +08:00
6102cfdd27 sdmmc: in/out phase adapted to esp32 and esp32s3 2023-04-24 03:45:29 +00:00
5b18007d92 sdmmc: I/O phase adjustments
1. Fix incorrect meaning of SDMMC.clock bits, synchronize the names
   with the TRM.
2. Choose input and output phases to satisfy typical timing
   requirements.
3. Move use_hold_reg setting into the host driver, since it is related
   to timing.

Closes https://github.com/espressif/esp-idf/issues/8521
Related to https://github.com/espressif/esp-idf/issues/8257
2023-04-24 03:45:29 +00:00
bead0d741b sdmmc: add an example communicating with eMMC chip on S3 2023-04-24 03:45:29 +00:00
a218144f4c esp_mm: removed empty kconfig files
- MMU configuration related kconfig options will be in soc, or
esp_hw_support
- Cache configuration related kconfig options will be in soc, or
esp_hw_support
- mmap driver and msync driver kconfig options will be still in esp_mm.
As there's no kconfig options for them yet, removed kconfig files
2023-04-24 03:45:00 +00:00
46fe70fb46 freertos: Add unit tests for ...WithCaps() functions 2023-04-24 11:44:46 +08:00
c5fe3ec05d freertos: Add wrapper functions to create objects with capabilities
This commit adds various ...WithCaps() functions to create FreeRTOS objects
with specific memory capabilities.
2023-04-24 11:44:46 +08:00
3562cb8051 freertos: Add GetStaticBuffer functions
This commit adds the various ...GetStaticBuffer() functions from upstream
FreeRTOS. See https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/641 for more
details.
2023-04-24 11:44:46 +08:00
7b41d6004a freertos: Fix idf_additions.h include order error
When building for CONFIG_FREERTOS_SMP, "idf_additions.h" was previously
implicitly included by "task.h" so that other ESP-IDF components still have
access to IDF API additions without needing to include "idf_additions.h"
directly.

However, some FreeRTOS headers (e.g., queue.h) will include task.h before
declaring any types (e.g., QueueHandle_t). Thus if any of those types are used
in idf_additions.h, we get a missing type error.

This commit moves the implicity include of idf_additions.h to FreeRTOS.h
2023-04-24 11:44:46 +08:00
5c88e0d801 bootloader: enable super WDT and BOD reset on C2 2023-04-24 11:32:23 +08:00
c6559a9b64 bootloader: cleanup ana reset config code 2023-04-24 11:32:23 +08:00
ca3d871a21 bootloader: fixed super watchdog not enabled issue on C3, S3, H4 2023-04-24 11:32:23 +08:00
113e4dc520 bootloader: removed unavailable rtc features 2023-04-24 11:32:23 +08:00
80315b77a0 bootloader: fix analog reset on C6 and H2 2023-04-24 11:32:23 +08:00
aeabe8d742 Merge branch 'feature/hfp_ag_hints_v5.1' into 'release/v5.1'
tools: Update idf-py hints with Bluedroid HFP AG info[backport 5.1]

See merge request espressif/esp-idf!23289
2023-04-24 10:42:24 +08:00
1644050652 Merge branch 'bugfix/fix_some_ble_bug_v5.1' into 'release/v5.1'
Fixed some BLE bugs (backport v5.1)

See merge request espressif/esp-idf!23324
2023-04-24 10:41:59 +08:00
a12e124410 Merge branch 'bugfix/bt_diable_enbale_crash_v5.1' into 'release/v5.1'
bt:Fixed esp32 controller bug (v5.1)

See merge request espressif/esp-idf!23365
2023-04-24 10:39:58 +08:00
36d6a927d1 Merge branch 'bugfix/fix_some_esp32c3_s3_ble_bugs_230422' into 'release/v5.1'
Fixed some ESP32C3/S3 BLE bugs 23-04-22(backport v5.1)

See merge request espressif/esp-idf!23353
2023-04-24 10:38:34 +08:00
cje
93eeb4265c fix chip broken bug when run in monitor mode of S2 and modify voltage param to fit all sleep mode of S2/C2/C3 2023-04-24 10:37:57 +08:00
f608431421 Merge branch 'bugfix/spi_lcd_max_trans_size_v5.1' into 'release/v5.1'
spi_lcd: maximum transfer size should respect bus configuration (v5.1)

See merge request espressif/esp-idf!23229
2023-04-24 10:31:51 +08:00
21c536c563 Merge branch 'bugfix/lcd_align_before_cache_write_back_v5.1' into 'release/v5.1'
manually align the color buffer before cache write back (v5.1)

See merge request espressif/esp-idf!23243
2023-04-24 10:28:16 +08:00
de33225c31 riscv: moved some interrupt functions from IRAM to flash
These functions dont need to be in IRAM.
2023-04-24 10:27:31 +08:00
b07a534984 esp-system: move uncessary IRAM functions to flash 2023-04-24 10:27:31 +08:00
b0a1c0d045 Make custom bootloader message match actual output
Fixes the custom bootloader README.md so that the example output matches
what will actually be output by default in the custom bootloader.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>
2023-04-24 10:25:22 +08:00
73f895217b ci: build all docs if soc_caps.h changed
soc_caps.h is thightly coupled with the docs build. Should build all docs
after changing it to make sure nothing broke.
2023-04-24 10:18:11 +08:00
0fb6316888 Merge branch 'bugfix/rmt_encode_state_init_v5.1' into 'release/v5.1'
rmt: define RMT_ENCODING_RESET in rmt_encode_state_t (v5.1)

See merge request espressif/esp-idf!23239
2023-04-24 10:18:08 +08:00
be8727cf88 Merge branch 'bugfix/i2s_fix_intr_flag_for_pdm_rx_v5.1' into 'release/v5.1'
i2s: fix interrupt flag of pdm rx mode (v5.1)

See merge request espressif/esp-idf!23125
2023-04-24 10:13:41 +08:00
8b0860ef95 ulp-riscv: enable ULP-RISCV ADC example for esp32s2
ADC can now be used from the ULP-RISCV on S2 after the RTC power parameters were
fixed in a624d8d061

Closes https://github.com/espressif/esp-idf/issues/11052
Closes https://github.com/espressif/esp-idf/issues/11040
2023-04-24 10:12:00 +08:00
6bb4dc35ab docs: update CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM docs to better reflect the limitations 2023-04-24 09:55:00 +08:00
34fea0d38f system: add kconfig option for using parts of SRAM1 for IRAM
Using parts of SRAM1 for IRAM allows apps with more statically allocated IRAM

Closes https://github.com/espressif/esp-idf/issues/9824
2023-04-24 09:54:47 +08:00
a6b1ebce31 Merge branch 'maint/release_v5.1_codeowners' into 'release/v5.1'
gitlab: simplify approvals for backports (v5.1)

See merge request espressif/esp-idf!23285
2023-04-24 05:19:37 +08:00
b5357e8b01 bt:Fixed esp32 controller bug
1. Fixed crash after controller disable and re-enable
2. Fixed the crash caused by processing the HCI_Read_Remote_Extented_Features command in the non-connected state

Closes https://github.com/espressif/esp-idf/issues/11164
Closes https://github.com/espressif/esp-idf/issues/10835
2023-04-23 20:26:56 +08:00
59666637bc Disable controller 5.0 feature bits if host 5.0 feature is not enabled 2023-04-22 20:49:30 +08:00
zwj
48c5f74cbc improve scan performance when scan and sync coexist on ESP32-C3 and ESP32-S3 2023-04-22 20:49:10 +08:00
8e41186ac8 Update bt lib for ESP32-C3 and ESP32-S3
- Fixed non-connectable and non-scannable directed adv can't be scanned
2023-04-22 20:48:38 +08:00
49718b20a5 bug(idf_monitor): fix color on windows with hints
Closes https://github.com/espressif/esp-idf/issues/9610
2023-04-21 14:42:26 +02:00
f1a2bc777e usb_host: Use up-to-date syntax in pytest 2023-04-21 15:45:42 +08:00
0ed6610212 feat(esptool): allow to set force for write_flash 2023-04-21 09:36:18 +02:00
51405fd9d4 bt: Remove FreeRTOS static allocation from OSI functions
Previously, the BT OSI would use various FreeRTOS "create static" functions to
ensure that semaphores and queues were always allocated to internal memory.
However, from commit e21ab0332b onwards, all
dynamic memory allocated by FreeRTOS will default to internal RAM.

Thus, the extra "create static" calls can be removed to simply the code.
2023-04-21 15:19:29 +08:00
71786a7413 usb_host: Update docs and comments regarding first configuration enumeration
This commit updates some comments and documentation regarding changes made in
PR https://github.com/espressif/esp-idf/pull/11113.
2023-04-21 12:49:18 +08:00
4102628a3b Fix usb enumeration stage error for some device 2023-04-21 12:49:18 +08:00
d0011b778a bluedroid: report status after clearing the BLE white list 2023-04-20 18:58:38 +08:00
c2fe7be50e bluedroid: fix GATTC cache address save 2023-04-20 18:57:23 +08:00
13e3480f03 docs: migrated documentetation from github.io to docs.espressif.com 2023-04-20 13:38:16 +04:00
024e201097 esp_timer: Adds IRAM_ATTR for esp_timer_restart and esp_timer_is_active
Closes https://github.com/espressif/esp-idf/issues/10522
Closes https://github.com/espressif/esp-idf/issues/10859
2023-04-20 15:14:52 +08:00
62467fbca5 tools: Update idf-py hints with Bluedroid HFP AG info 2023-04-19 19:10:00 +08:00
84f81437a3 gitlab: simplify approvals for backports (v5.1) 2023-04-19 12:19:55 +02:00
c00759ad34 lcd: test send color buffers in multiple steps 2023-04-18 10:08:38 +08:00
472cc06f6c i80_lcd: align before cache sync 2023-04-18 10:08:38 +08:00
b5572b1db0 rmt: define RMT_ENCODING_RESET in rmt_encode_state_t
Closes https://github.com/espressif/esp-idf/issues/11200
2023-04-17 21:28:45 +08:00
2b461df8a8 spi_lcd: test spi lcd io can transfer color data to a fixed window region
also test the io tx_param and tx_color can skip the command phase
2023-04-17 16:25:14 +08:00
7a716377a3 spi_lcd: maximum transfer size should respect bus configuration
Also this commit added the SPI_TRANS_CS_KEEP_ACTIVE flag for io_tx_color
2023-04-17 16:25:14 +08:00
965e9abd7b i2s: fixed the test case I2S_thread_concurrent_safety_test 2023-04-10 15:29:22 +08:00
a47169f450 i2s: fix interrupt flag of pdm rx mode
Forgot to update in PR https://github.com/espressif/esp-idf/pull/10997
2023-04-10 15:29:22 +08:00
1325 changed files with 22474 additions and 128759 deletions

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#
# https://docs.gitlab.com/ee/user/project/code_owners.html#the-syntax-of-code-owners-files
#
# If more than one rule matches a given file, the latest rule is used.
# The file should be generally kept sorted, except when it is necessary
# to use a different order due to the fact above. In that case, use
# '# sort-order-reset' comment line to reset the sort order.
#
# Recipes for a few common cases:
#
# 1. Specific directory with all its contents:
#
# /components/app_trace/
#
# Note the trailing slash!
#
# 2. File with certain extension in any subdirectory of a certain directory:
#
# /examples/**/*.py
#
# This includes an *.py files in /examples/ directory as well.
#
# 3. Contents of a directory with a certain name, anywhere in the tree:
#
# test_*_host/
#
# Will match everything under components/efuse/test_efuse_host/,
# components/heap/test_multi_heap_host/, components/lwip/test_afl_host/, etc.
#
# 4. Same as above, except limited to a specific place in the tree:
#
# /components/esp32*/
#
# Matches everything under /components/esp32, /components/esp32s2, etc.
# Doesn't match /tools/some-test/components/esp32s5.
#
# 5. Specific file:
#
# /tools/tools.json
#
# 6. File with a certain name anywhere in the tree
#
# .gitignore
#
* @esp-idf-codeowners/other
/.* @esp-idf-codeowners/tools
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/components/json/ @esp-idf-codeowners/app-utilities
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/components/mbedtls/ @esp-idf-codeowners/app-utilities/mbedtls @esp-idf-codeowners/security
/components/mqtt/ @esp-idf-codeowners/network
/components/newlib/ @esp-idf-codeowners/system @esp-idf-codeowners/tools
/components/nvs_flash/ @esp-idf-codeowners/storage
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/components/sdmmc/ @esp-idf-codeowners/storage
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/examples/common_components/ @esp-idf-codeowners/system
/examples/custom_bootloader/ @esp-idf-codeowners/system
/examples/cxx/ @esp-idf-codeowners/system
/examples/ethernet/ @esp-idf-codeowners/network
/examples/get-started/ @esp-idf-codeowners/system
/examples/mesh/ @esp-idf-codeowners/wifi
/examples/network/ @esp-idf-codeowners/network @esp-idf-codeowners/wifi
/examples/openthread/ @esp-idf-codeowners/ieee802154
/examples/peripherals/ @esp-idf-codeowners/peripherals
/examples/peripherals/usb/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
/examples/protocols/ @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
/examples/provisioning/ @esp-idf-codeowners/app-utilities/provisioning
/examples/security/ @esp-idf-codeowners/security
/examples/storage/ @esp-idf-codeowners/storage
/examples/system/ @esp-idf-codeowners/system
/examples/system/ota/ @esp-idf-codeowners/app-utilities
/examples/wifi/ @esp-idf-codeowners/wifi
/examples/zigbee/ @esp-idf-codeowners/ieee802154
/tools/ @esp-idf-codeowners/tools
/tools/ble/ @esp-idf-codeowners/app-utilities
/tools/catch/ @esp-idf-codeowners/ci
/tools/ci/ @esp-idf-codeowners/ci
/tools/cmake/ @esp-idf-codeowners/build-config
/tools/esp_prov/ @esp-idf-codeowners/app-utilities
/tools/kconfig*/ @esp-idf-codeowners/build-config
/tools/ldgen/ @esp-idf-codeowners/build-config
/tools/mass_mfg/ @esp-idf-codeowners/app-utilities
/tools/mocks/ @esp-idf-codeowners/system
/tools/test_apps/README.md @esp-idf-codeowners/docs @esp-idf-codeowners/ci
## Note: owners here should be the same as the owners for the same example subdir, above
/tools/test_apps/build_system/ @esp-idf-codeowners/build-config
/tools/test_apps/protocols/ @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
/tools/test_apps/security/ @esp-idf-codeowners/security
/tools/test_apps/system/ @esp-idf-codeowners/system
/tools/test_apps/**/*.py @esp-idf-codeowners/ci @esp-idf-codeowners/tools
/tools/test_build_system/ @esp-idf-codeowners/tools @esp-idf-codeowners/build-config
/tools/unit-test-app/ @esp-idf-codeowners/system @esp-idf-codeowners/tools
# sort-order-reset
/components/**/test_apps/**/*.py @esp-idf-codeowners/ci @esp-idf-codeowners/tools
# ignore lists
/tools/ci/check_copyright_config.yaml @esp-idf-codeowners/all-maintainers
/tools/ci/check_copyright_ignore.txt @esp-idf-codeowners/all-maintainers
/tools/ci/mypy_ignore_list.txt @esp-idf-codeowners/tools
* @esp-idf-codeowners/all-maintainers

View File

@ -215,14 +215,6 @@ build_pytest_examples_esp32c2:
IDF_TARGET: esp32c2
TEST_DIR: examples
build_pytest_examples_esp32h4:
extends:
- .build_pytest_no_jtag_template
- .rules:build:example_test-esp32h4
variables:
IDF_TARGET: esp32h4
TEST_DIR: examples
build_pytest_examples_jtag: # for all targets
extends:
- .build_pytest_jtag_template
@ -649,14 +641,6 @@ build_examples_cmake_esp32c3:
IDF_TARGET: esp32c3
TEST_DIR: examples
build_examples_cmake_esp32h4:
extends:
- .build_cmake_template
- .rules:build:example_test-esp32h4
variables:
IDF_TARGET: esp32h4
TEST_DIR: examples
build_examples_cmake_esp32c6:
extends:
- .build_cmake_template
@ -729,13 +713,6 @@ build_clang_test_apps_esp32c6:
variables:
IDF_TARGET: esp32c6
build_clang_test_apps_esp32h4:
extends:
- .build_clang_test_apps_riscv
- .rules:build:custom_test-esp32h4
variables:
IDF_TARGET: esp32h4
.test_build_system_template:
stage: host_test
extends:

View File

@ -3,7 +3,6 @@
- esp32s2
- esp32s3
- esp32c3
- esp32h4
- esp32c2
- esp32c6
- esp32h2
@ -133,13 +132,15 @@ build:integration_test:
- *target_test
- *all_targets
- - bt # example_test_005
- wifi # example_test_002, example_test*wifi*
- ethernet # example_test*ethernet*
- sdio # component_ut_pytest_esp32_sdio
- wifi # pytest*wifi*
- ethernet # pytest*ethernet*
- sdio # pytest*sdio*
- usb # USB Device & Host tests
- adc # component_ut_pytest_esp32x_adc
- adc # pytest*adc*
- i154
- flash_multi
- ecdsa
- ccs811 # pytest*ccs811*
patterns:
- "{0}-{1}-{2}"
- "{0}-{2}"
@ -213,31 +214,10 @@ build:integration_test:
#################################
# Triggered Only By Labels Jobs #
#################################
"labels:iperf_stress_test": # example_test
labels:
- iperf_stress_test
included_in:
- build:example_test
- build:example_test-esp32
- build:target_test
"labels:weekend_test": # custom test
labels:
- weekend_test
included_in:
- build:custom_test
- build:custom_test-esp32
- build:target_test
"labels:nvs_coverage": # host_test
labels:
- nvs_coverage
"labels:fuzzer_test-weekend_test": # host test
labels:
- fuzzer_test
- weekend_test
"labels-protected:lan8720": # UT # FIXME: IDFCI-1176 temporary run this on master/release or with label
labels:
- lan8720

View File

@ -3,6 +3,7 @@
- "docs/**/*"
- "**/*.rst"
- "CONTRIBUTING.rst"
- "**/soc_caps.h"
.patterns-docs-partial: &patterns-docs-partial
- "components/**/*.h"
@ -43,6 +44,9 @@
.doc-rules:build:docs-partial:
rules:
- <<: *if-dev-push
changes: *patterns-docs-full
when: never
- <<: *if-dev-push
changes: *patterns-docs-partial

View File

@ -185,30 +185,6 @@ test_efuse_table_on_host_esp32c6:
variables:
IDF_TARGET: esp32c6
test_efuse_table_on_host_esp32h4:
extends: .test_efuse_table_on_host_template
variables:
IDF_TARGET: esp32h4
test_espcoredump:
extends: .host_test_template
artifacts:
when: always
paths:
- components/espcoredump/test/**/.coverage
- components/espcoredump/test/**/output
expire_in: 1 week
variables:
IDF_COREDUMP_ELF_REPO: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/idf/idf-coredump-elf.git"
IDF_COREDUMP_ELF_TAG: idf-20220928
# install CMake version specified in tools.json
SETUP_TOOLS_LIST: "all"
script:
- eval $($IDF_PATH/tools/idf_tools.py export)
- retry_failed git clone ${IDF_COREDUMP_ELF_REPO} -b $IDF_COREDUMP_ELF_TAG
- cd ${IDF_PATH}/components/espcoredump/test/
- ./test_espcoredump.sh ${CI_PROJECT_DIR}/idf-coredump-elf
test_logtrace_proc:
extends: .host_test_template
artifacts:

View File

@ -55,8 +55,6 @@
- "tools/test_build_system/**/*"
.patterns-custom_test: &patterns-custom_test
- "components/espcoredump/**/*"
- "tools/ci/python_packages/gitlab_api.py"
- "tools/ci/python_packages/tiny_test_fw/**/*"
- "tools/ci/python_packages/ttfw_idf/**/*"
@ -246,6 +244,7 @@
- "components/driver/include/driver/sdio*.h"
- "components/driver/include/driver/sdmmc*.h"
- "components/sdmmc/**/*"
- "examples/peripherals/sdio/**/*"
# for jobs: component_ut_pytest_sdio related
.patterns-component_ut-sdio: &patterns-component_ut-sdio
@ -259,6 +258,13 @@
- "components/driver/include/driver/sdmmc*.h"
- "components/sdmmc/**/*"
.patterns-example_test-ccs811: &patterns-example_test-ccs811
# components
- "examples/system/console/advanced/components/**/*"
- "components/driver/i2c/**/*"
# tests
- "examples/peripherals/i2c/i2c_tools/**/*"
# for jobs: UT_xx_SDSPI related
.patterns-unit_test-sdio: &patterns-unit_test-sdio
- "components/hal/sdio*.c"
@ -306,6 +312,11 @@
- "components/efuse/**/*"
- "examples/peripherals/adc/**/*"
.patterns-target_test-ecdsa: &patterns-target_test-ecdsa
- "components/hal/**/*"
- "components/efuse/**/*"
- "components/mbedtls/port/ecdsa/*"
##############
# if anchors #
##############
@ -447,9 +458,6 @@
.if-label-component_ut_esp32h2: &if-label-component_ut_esp32h2
if: '$BOT_LABEL_COMPONENT_UT_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32h4: &if-label-component_ut_esp32h4
if: '$BOT_LABEL_COMPONENT_UT_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-component_ut_esp32s2: &if-label-component_ut_esp32s2
if: '$BOT_LABEL_COMPONENT_UT_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32s2(?:,[^,\n\r]+)*$/i'
@ -474,9 +482,6 @@
.if-label-custom_test_esp32h2: &if-label-custom_test_esp32h2
if: '$BOT_LABEL_CUSTOM_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32h4: &if-label-custom_test_esp32h4
if: '$BOT_LABEL_CUSTOM_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-custom_test_esp32s2: &if-label-custom_test_esp32s2
if: '$BOT_LABEL_CUSTOM_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32s2(?:,[^,\n\r]+)*$/i'
@ -504,18 +509,12 @@
.if-label-example_test_esp32h2: &if-label-example_test_esp32h2
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32h4: &if-label-example_test_esp32h4
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32s2: &if-label-example_test_esp32s2
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32s2(?:,[^,\n\r]+)*$/i'
.if-label-example_test_esp32s3: &if-label-example_test_esp32s3
if: '$BOT_LABEL_EXAMPLE_TEST_ESP32S3 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32s3(?:,[^,\n\r]+)*$/i'
.if-label-fuzzer_test: &if-label-fuzzer_test
if: '$BOT_LABEL_FUZZER_TEST || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*fuzzer_test(?:,[^,\n\r]+)*$/i'
.if-label-host_test: &if-label-host_test
if: '$BOT_LABEL_HOST_TEST || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*host_test(?:,[^,\n\r]+)*$/i'
@ -528,9 +527,6 @@
.if-label-integration_test_wifi: &if-label-integration_test_wifi
if: '$BOT_LABEL_INTEGRATION_TEST_WIFI || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*integration_test_wifi(?:,[^,\n\r]+)*$/i'
.if-label-iperf_stress_test: &if-label-iperf_stress_test
if: '$BOT_LABEL_IPERF_STRESS_TEST || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*iperf_stress_test(?:,[^,\n\r]+)*$/i'
.if-label-lan8720: &if-label-lan8720
if: '$BOT_LABEL_LAN8720 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*lan8720(?:,[^,\n\r]+)*$/i'
@ -567,18 +563,12 @@
.if-label-unit_test_esp32h2: &if-label-unit_test_esp32h2
if: '$BOT_LABEL_UNIT_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h2(?:,[^,\n\r]+)*$/i'
.if-label-unit_test_esp32h4: &if-label-unit_test_esp32h4
if: '$BOT_LABEL_UNIT_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h4(?:,[^,\n\r]+)*$/i'
.if-label-unit_test_esp32s2: &if-label-unit_test_esp32s2
if: '$BOT_LABEL_UNIT_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32s2(?:,[^,\n\r]+)*$/i'
.if-label-unit_test_esp32s3: &if-label-unit_test_esp32s3
if: '$BOT_LABEL_UNIT_TEST_ESP32S3 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32s3(?:,[^,\n\r]+)*$/i'
.if-label-weekend_test: &if-label-weekend_test
if: '$BOT_LABEL_WEEKEND_TEST || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*weekend_test(?:,[^,\n\r]+)*$/i'
.if-label-windows: &if-label-windows
if: '$BOT_LABEL_WINDOWS || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*windows(?:,[^,\n\r]+)*$/i'
@ -607,7 +597,6 @@
- <<: *if-label-component_ut_esp32c3
- <<: *if-label-component_ut_esp32c6
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32h4
- <<: *if-label-component_ut_esp32s2
- <<: *if-label-component_ut_esp32s3
- <<: *if-label-lan8720
@ -618,7 +607,6 @@
- <<: *if-label-unit_test_esp32c3
- <<: *if-label-unit_test_esp32c6
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-label-unit_test_esp32s2
- <<: *if-label-unit_test_esp32s3
- <<: *if-dev-push
@ -637,6 +625,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -670,6 +660,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -702,6 +694,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -734,6 +728,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -766,6 +762,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -798,6 +796,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -830,6 +830,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -862,6 +864,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -879,11 +883,9 @@
- <<: *if-label-custom_test_esp32c3
- <<: *if-label-custom_test_esp32c6
- <<: *if-label-custom_test_esp32h2
- <<: *if-label-custom_test_esp32h4
- <<: *if-label-custom_test_esp32s2
- <<: *if-label-custom_test_esp32s3
- <<: *if-label-target_test
- <<: *if-label-weekend_test
- <<: *if-dev-push
changes: *patterns-build_components
- <<: *if-dev-push
@ -894,6 +896,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -908,7 +912,6 @@
- <<: *if-label-custom_test
- <<: *if-label-custom_test_esp32
- <<: *if-label-target_test
- <<: *if-label-weekend_test
- <<: *if-dev-push
changes: *patterns-build_components
- <<: *if-dev-push
@ -919,6 +922,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -943,6 +948,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -967,6 +974,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -991,6 +1000,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1016,29 +1027,7 @@
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
changes: *patterns-target_test-wifi
.rules:build:custom_test-esp32h4:
rules:
- <<: *if-revert-branch
when: never
- <<: *if-protected
- <<: *if-label-build
- <<: *if-label-custom_test
- <<: *if-label-custom_test_esp32h4
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-build_components
- <<: *if-dev-push
changes: *patterns-build_system
- <<: *if-dev-push
changes: *patterns-custom_test
- <<: *if-dev-push
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1063,6 +1052,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1087,6 +1078,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1121,10 +1114,8 @@
- <<: *if-label-example_test_esp32c3
- <<: *if-label-example_test_esp32c6
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32h4
- <<: *if-label-example_test_esp32s2
- <<: *if-label-example_test_esp32s3
- <<: *if-label-iperf_stress_test
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-build-example_test
@ -1138,6 +1129,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1150,6 +1143,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1164,7 +1159,6 @@
- <<: *if-label-build
- <<: *if-label-example_test
- <<: *if-label-example_test_esp32
- <<: *if-label-iperf_stress_test
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-build-example_test
@ -1178,6 +1172,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1190,6 +1186,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1216,6 +1214,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1228,6 +1228,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1255,6 +1257,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1267,6 +1271,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1293,6 +1299,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1305,6 +1313,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1332,43 +1342,7 @@
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
changes: *patterns-example_test-i154
- <<: *if-dev-push
changes: *patterns-example_test-sdio
- <<: *if-dev-push
changes: *patterns-example_test-usb
- <<: *if-dev-push
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
changes: *patterns-target_test-wifi
.rules:build:example_test-esp32h4:
rules:
- <<: *if-revert-branch
when: never
- <<: *if-protected
- <<: *if-label-build
- <<: *if-label-example_test
- <<: *if-label-example_test_esp32h4
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-build-example_test
- <<: *if-dev-push
changes: *patterns-build_components
- <<: *if-dev-push
changes: *patterns-build_system
- <<: *if-dev-push
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1381,6 +1355,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1407,6 +1383,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1419,6 +1397,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1445,6 +1425,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1457,6 +1439,8 @@
changes: *patterns-example_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1509,7 +1493,6 @@
- <<: *if-label-component_ut_esp32c3
- <<: *if-label-component_ut_esp32c6
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-component_ut_esp32h4
- <<: *if-label-component_ut_esp32s2
- <<: *if-label-component_ut_esp32s3
- <<: *if-label-custom_test
@ -1518,7 +1501,6 @@
- <<: *if-label-custom_test_esp32c3
- <<: *if-label-custom_test_esp32c6
- <<: *if-label-custom_test_esp32h2
- <<: *if-label-custom_test_esp32h4
- <<: *if-label-custom_test_esp32s2
- <<: *if-label-custom_test_esp32s3
- <<: *if-label-example_test
@ -1527,13 +1509,11 @@
- <<: *if-label-example_test_esp32c3
- <<: *if-label-example_test_esp32c6
- <<: *if-label-example_test_esp32h2
- <<: *if-label-example_test_esp32h4
- <<: *if-label-example_test_esp32s2
- <<: *if-label-example_test_esp32s3
- <<: *if-label-integration_test
- <<: *if-label-integration_test_ble
- <<: *if-label-integration_test_wifi
- <<: *if-label-iperf_stress_test
- <<: *if-label-lan8720
- <<: *if-label-target_test
- <<: *if-label-unit_test
@ -1542,10 +1522,8 @@
- <<: *if-label-unit_test_esp32c3
- <<: *if-label-unit_test_esp32c6
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-label-unit_test_esp32s2
- <<: *if-label-unit_test_esp32s3
- <<: *if-label-weekend_test
- <<: *if-dev-push
changes: *patterns-build-example_test
- <<: *if-dev-push
@ -1568,6 +1546,8 @@
changes: *patterns-example_test
- <<: *if-dev-push
changes: *patterns-example_test-bt
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
- <<: *if-dev-push
changes: *patterns-example_test-ethernet
- <<: *if-dev-push
@ -1584,6 +1564,8 @@
changes: *patterns-integration_test-wifi
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1609,7 +1591,6 @@
- <<: *if-label-unit_test_esp32c3
- <<: *if-label-unit_test_esp32c6
- <<: *if-label-unit_test_esp32h2
- <<: *if-label-unit_test_esp32h4
- <<: *if-label-unit_test_esp32s2
- <<: *if-label-unit_test_esp32s3
- <<: *if-dev-push
@ -1620,6 +1601,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1649,6 +1632,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1677,6 +1662,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1705,6 +1692,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1733,6 +1722,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1761,6 +1752,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1789,6 +1782,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -1817,6 +1812,8 @@
changes: *patterns-downloadable-tools
- <<: *if-dev-push
changes: *patterns-target_test-adc
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
- <<: *if-dev-push
changes: *patterns-target_test-i154
- <<: *if-dev-push
@ -2085,6 +2082,19 @@
- <<: *if-dev-push
changes: *patterns-target_test-adc
.rules:test:component_ut-esp32h2-ecdsa:
rules:
- <<: *if-revert-branch
when: never
- <<: *if-protected
- <<: *if-label-build-only
when: never
- <<: *if-label-component_ut
- <<: *if-label-component_ut_esp32h2
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-target_test-ecdsa
.rules:test:component_ut-esp32s2:
rules:
- <<: *if-revert-branch
@ -2338,6 +2348,19 @@
- <<: *if-dev-push
changes: *patterns-example_test-bt
.rules:test:example_test-esp32-ccs811:
rules:
- <<: *if-revert-branch
when: never
- <<: *if-protected
- <<: *if-label-build-only
when: never
- <<: *if-label-example_test
- <<: *if-label-example_test_esp32
- <<: *if-label-target_test
- <<: *if-dev-push
changes: *patterns-example_test-ccs811
.rules:test:example_test-esp32-ethernet:
rules:
- <<: *if-revert-branch

View File

@ -97,6 +97,22 @@ pytest_examples_esp32_jtag:
SETUP_TOOLS: "1" # need gdb openocd
PYTEST_EXTRA_FLAGS: "--log-cli-level DEBUG"
pytest_examples_esp32_ccs811:
extends:
- .pytest_examples_dir_template
- .rules:test:example_test-esp32-ccs811
needs:
- build_pytest_examples_esp32
tags: [ esp32, ccs811 ]
pytest_examples_esp32_sdio:
extends:
- .pytest_examples_dir_template
- .rules:test:example_test-esp32-sdio
needs:
- build_pytest_examples_esp32
tags: [ esp32, sdio_master_slave ]
pytest_examples_esp32s2_generic:
extends:
- .pytest_examples_dir_template
@ -488,6 +504,14 @@ pytest_examples_esp32h2_adc:
- build_pytest_examples_esp32h2
tags: [ esp32h2, adc ]
example_test_pytest_esp32s3_emmc:
extends:
- .pytest_examples_dir_template
- .rules:test:example_test-esp32s3
needs:
- build_pytest_examples_esp32s3
tags: [ esp32s3, emmc ]
.pytest_components_dir_template:
extends: .pytest_template
variables:
@ -884,6 +908,14 @@ pytest_components_esp32h2_adc:
- build_pytest_components_esp32h2
tags: [ esp32h2, adc ]
component_ut_pytest_esp32h2_ecdsa:
extends:
- .pytest_components_dir_template
- .rules:test:component_ut-esp32h2-ecdsa
needs:
- build_pytest_components_esp32h2
tags: [ esp32h2, ecdsa_efuse ]
pytest_components_esp32c6_generic_multi_device:
extends:
- .pytest_components_dir_template
@ -1090,12 +1122,6 @@ example_test_001C:
- ESP32
- Example_GENERIC
.example_test_003:
extends: .example_test_esp32_template
tags:
- ESP32
- Example_SDIO
example_test_005:
extends:
- .example_test_esp32_template
@ -1104,12 +1130,6 @@ example_test_005:
- ESP32
- Example_WIFI_BT
example_test_007:
extends: .example_test_esp32_template
tags:
- ESP32
- Example_I2C_CCS811_SENSOR
example_test_C3_GENERIC:
extends: .example_test_esp32c3_template
tags:
@ -1203,19 +1223,12 @@ UT_006:
- UT_T1_SPIMODE
- psram
UT_017:
.UT_017:
extends: .unit_test_esp32_template
tags:
- ESP32_IDF
- EMMC
UT_022:
extends: .unit_test_esp32_template
tags:
- ESP32_IDF
- UT_T2_I2C
- psram
UT_028:
extends: .unit_test_esp32_template
tags:
@ -1288,12 +1301,6 @@ UT_C3_FLASH:
- ESP32C3_IDF
- UT_T1_ESP_FLASH
UT_C3_I2C:
extends: .unit_test_esp32c3_template
tags:
- ESP32C3_IDF
- UT_T2_I2C
UT_C3_SDSPI:
extends:
- .unit_test_esp32c3_template

View File

@ -139,7 +139,8 @@ repos:
name: Check if all apps readme files match given .build-test-rules.yml files. Modify the supported target tables
entry: tools/ci/check_build_test_rules.py check-readmes
language: python
files: 'tools/test_apps/.+|examples/.+|components/.+'
files: 'tools/test_apps/.+|examples/.+|components/.+|tools/idf_py_actions/constants.py|tools/ci/check_build_test_rules.py'
require_serial: true
additional_dependencies:
- PyYAML == 5.3.1
- idf_build_apps

24
Kconfig
View File

@ -66,28 +66,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
config IDF_TARGET_ESP32H4
bool
default "y" if IDF_TARGET="esp32h4"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
choice IDF_TARGET_ESP32H4_BETA_VERSION
prompt "ESP32-H4 beta version"
depends on IDF_TARGET_ESP32H4
default IDF_TARGET_ESP32H4_BETA_VERSION_2
help
Currently ESP32-H4 has several beta versions for internal use only.
Select the one that matches your chip model.
config IDF_TARGET_ESP32H4_BETA_VERSION_1
bool
prompt "ESP32-H4 beta1"
config IDF_TARGET_ESP32H4_BETA_VERSION_2
bool
prompt "ESP32-H4 beta2"
endchoice
config IDF_TARGET_ESP32C2
bool
default "y" if IDF_TARGET="esp32c2"
@ -116,10 +94,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
default 0x0002 if IDF_TARGET_ESP32S2
default 0x0005 if IDF_TARGET_ESP32C3
default 0x0009 if IDF_TARGET_ESP32S3
default 0x000A if IDF_TARGET_ESP32H4_BETA_VERSION_1
default 0x000C if IDF_TARGET_ESP32C2
default 0x000D if IDF_TARGET_ESP32C6
default 0x000E if IDF_TARGET_ESP32H4_BETA_VERSION_2 # ESP32-TODO: IDF-3475
default 0x0010 if IDF_TARGET_ESP32H2
default 0xFFFF

View File

@ -8,7 +8,7 @@
#define HEAP_TRACE_SRCFILE /* don't warn on inclusion here */
#include "esp_heap_trace.h"
#undef HEAP_TRACE_SRCFILE
#include "esp_heap_caps.h"
#if CONFIG_APPTRACE_SV_ENABLE
#include "esp_app_trace.h"
#include "esp_sysview_trace.h"
@ -85,7 +85,7 @@ void heap_trace_dump_caps(__attribute__((unused)) const uint32_t caps)
}
/* Add a new allocation to the heap trace records */
static IRAM_ATTR void record_allocation(const heap_trace_record_t *record)
static HEAP_IRAM_ATTR void record_allocation(const heap_trace_record_t *record)
{
if (!s_tracing) {
return;
@ -100,7 +100,7 @@ static IRAM_ATTR void record_allocation(const heap_trace_record_t *record)
For HEAP_TRACE_ALL, this means filling in the freed_by pointer.
For HEAP_TRACE_LEAKS, this means removing the record from the log.
*/
static IRAM_ATTR void record_free(void *p, void **callers)
static HEAP_IRAM_ATTR void record_free(void *p, void **callers)
{
if (!s_tracing) {
return;

View File

@ -37,8 +37,6 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C6

View File

@ -334,7 +334,7 @@ typedef enum {
/**
* @brief Revokes the old signature digest. To be called in the application after the rollback logic.
*
* Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-H4 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1).
* Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6, ESP32-H2 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1).
* When key \#N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key \#N-1 & Key \#N.
* After successfully booting the OTA app should call this function to revoke Key \#N-1.
*

View File

@ -148,5 +148,5 @@ endif()
#
# So for now we just have the top-level build remove the final build products...
set_property(DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" APPEND PROPERTY
ADDITIONAL_MAKE_CLEAN_FILES
ADDITIONAL_CLEAN_FILES
${bootloader_binary_files})

View File

@ -25,7 +25,7 @@ MEMORY
*/
iram_seg (RWX) : org = 0x40080400, len = 0xfc00
/* 64k at the end of DRAM, after ROM bootloader stack */
dram_seg (RW) : org = 0x3FFF0000, len = 0x10000
dram_seg (RW) : org = 0x3FFF0000, len = 0x6000
}
/* Default entry point: */

View File

@ -1,240 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-H4 ROM static data usage is as follows:
* - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only
* - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700).
*/
/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
iram_dram_offset = 0x700000;
/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x3fcdd120;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
bootloader_iram_seg_len = 0x2000;
/* Start of the lower region is determined by region size and the end of the higher region */
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
MEMORY
{
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* Default entry point: */
ENTRY(call_start_cpu0);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*liblog.a:(.literal .text .literal.* .text.*)
*libgcc.a:(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
*libefuse.a:*.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} > dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
*(.sdata2 .sdata2.* .srodata .srodata.*)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} > dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x3fccb81c ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x3fcdd120 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x3fcdf120 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x3fcdfa6c ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x3fcdfe40 ------------------> _dram0_rtos_reserved_end
* | |
* 0x3fcdfe4c ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |
* 0x3fce0000 ------------------> _data_end_interface
*/

View File

@ -1,6 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* No definition for ESP32-H4 target */

View File

@ -164,7 +164,7 @@ if(CONFIG_SECURE_SIGNED_APPS AND (CONFIG_SECURE_BOOT_V1_ENABLED OR CONFIG_SECURE
target_add_binary_data(${COMPONENT_LIB} "${secure_boot_verification_key}" "BINARY"
RENAME_TO signature_verification_key_bin)
set_property(DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}"
APPEND PROPERTY ADDITIONAL_MAKE_CLEAN_FILES
APPEND PROPERTY ADDITIONAL_CLEAN_FILES
"${secure_boot_verification_key}")
endif()

View File

@ -1,250 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <assert.h>
#include "string.h"
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp32h4/rom/gpio.h"
#include "esp32h4/rom/spi_flash.h"
#include "esp32h4/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/soc_caps.h"
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
#include "hal/mmu_ll.h"
#define FLASH_IO_MATRIX_DUMMY_40M 0
#define FLASH_IO_MATRIX_DUMMY_80M 0
void bootloader_flash_update_id()
{
esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
chip->device_id = bootloader_read_flash_id();
}
void IRAM_ATTR bootloader_flash_cs_timing_config()
{
SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_1:
spi_clk_div = 1;
break;
case ESP_IMAGE_SPI_SPEED_DIV_2:
spi_clk_div = 2;
break;
case ESP_IMAGE_SPI_SPEED_DIV_3:
spi_clk_div = 3;
break;
case ESP_IMAGE_SPI_SPEED_DIV_4:
spi_clk_div = 4;
break;
default:
break;
}
esp_rom_spiflash_config_clk(spi_clk_div, 0);
}
void IRAM_ATTR bootloader_flash_set_dummy_out(void)
{
REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
}
void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
{
bootloader_configure_spi_pins(1);
bootloader_flash_set_dummy_out();
}
static const char *TAG = "boot.esp32h4";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
if (spiconfig == 0) {
} else {
clk_gpio_num = spiconfig & 0x3f;
q_gpio_num = (spiconfig >> 6) & 0x3f;
d_gpio_num = (spiconfig >> 12) & 0x3f;
cs0_gpio_num = (spiconfig >> 18) & 0x3f;
hd_gpio_num = (spiconfig >> 24) & 0x3f;
wp_gpio_num = wp_pin;
}
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
}
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
}
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
{
uint32_t size;
switch (bootloader_hdr->spi_size) {
case ESP_IMAGE_FLASH_SIZE_1MB:
size = 1;
break;
case ESP_IMAGE_FLASH_SIZE_2MB:
size = 2;
break;
case ESP_IMAGE_FLASH_SIZE_4MB:
size = 4;
break;
case ESP_IMAGE_FLASH_SIZE_8MB:
size = 8;
break;
case ESP_IMAGE_FLASH_SIZE_16MB:
size = 16;
break;
default:
size = 2;
}
cache_hal_disable(CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
cache_hal_enable(CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
{
ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
const char *str;
switch (bootloader_hdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_2:
str = "24MHz";
break;
case ESP_IMAGE_SPI_SPEED_DIV_3:
str = "16MHz";
break;
case ESP_IMAGE_SPI_SPEED_DIV_4:
str = "12MHz";
break;
case ESP_IMAGE_SPI_SPEED_DIV_1:
str = "48MHz";
break;
default:
str = "12MHz";
break;
}
ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
/* SPI mode could have been set to QIO during boot already,
so test the SPI registers not the flash header */
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
str = "QIO";
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
str = "QOUT";
} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
str = "DIO";
} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
str = "DOUT";
} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
str = "FAST READ";
} else {
str = "SLOW READ";
}
ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
switch (bootloader_hdr->spi_size) {
case ESP_IMAGE_FLASH_SIZE_1MB:
str = "1MB";
break;
case ESP_IMAGE_FLASH_SIZE_2MB:
str = "2MB";
break;
case ESP_IMAGE_FLASH_SIZE_4MB:
str = "4MB";
break;
case ESP_IMAGE_FLASH_SIZE_8MB:
str = "8MB";
break;
case ESP_IMAGE_FLASH_SIZE_16MB:
str = "16MB";
break;
default:
str = "2MB";
break;
}
ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
}
static void IRAM_ATTR bootloader_init_flash_configure(void)
{
bootloader_flash_dummy_config(&bootloader_image_hdr);
bootloader_flash_cs_timing_config();
}
static void bootloader_spi_flash_resume(void)
{
bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
}
esp_err_t bootloader_init_spi_flash(void)
{
bootloader_init_flash_configure();
#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
return ESP_FAIL;
}
#endif
bootloader_spi_flash_resume();
bootloader_flash_unlock();
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
bootloader_enable_qio_mode();
#endif
print_flash_info(&bootloader_image_hdr);
update_flash_config(&bootloader_image_hdr);
//ensure the flash is write-protected
bootloader_enable_wp();
return ESP_OK;
}

View File

@ -18,11 +18,6 @@ typedef enum {
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
ESP_CHIP_ID_ESP32H4 = 0x000E, /*!< chip ID: ESP32-H4 Beta2*/ // ESP32H4-TODO: IDF-3475
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
ESP_CHIP_ID_ESP32H4 = 0x000A, /*!< chip ID: ESP32-H4 Beta1 */
#endif
ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;

View File

@ -17,8 +17,6 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C6

View File

@ -45,7 +45,7 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs)
* @param[in] bs Bootloader state structure.
* @param[in] start_index The index from which the search for images begins.
*/
__attribute__((noreturn)) void bootloader_utility_load_boot_image(const bootloader_state_t *bs, int start_index);
__attribute__((__noreturn__)) void bootloader_utility_load_boot_image(const bootloader_state_t *bs, int start_index);
#ifdef CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP
/**
@ -65,7 +65,7 @@ void bootloader_utility_load_boot_image_from_deep_sleep(void);
*
* It is not recommended to call this function from an app (if called, the app will abort).
*/
__attribute__((noreturn)) void bootloader_reset(void);
__attribute__((__noreturn__)) void bootloader_reset(void);
/**
* @brief Do any cleanup before exiting the bootloader, before starting the app or resetting

View File

@ -27,9 +27,6 @@ int bootloader_clock_get_rated_freq_mhz(void)
#elif CONFIG_IDF_TARGET_ESP32C3
return 160;
#elif CONFIG_IDF_TARGET_ESP32H4
return 96;
#elif CONFIG_IDF_TARGET_ESP32C6
return 160;

View File

@ -8,6 +8,10 @@
#include "esp_cpu.h"
#include "soc/wdev_reg.h"
#if defined CONFIG_IDF_TARGET_ESP32C6
#include "hal/lp_timer_hal.h"
#endif
#ifndef BOOTLOADER_BUILD
#include "esp_random.h"
#include "esp_private/periph_ctrl.h"
@ -20,9 +24,28 @@
#else
#if !defined CONFIG_IDF_TARGET_ESP32S3
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
#if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
// tested.
#else
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
#endif
#else
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 23) /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 23) /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
#endif
#if defined CONFIG_IDF_TARGET_ESP32H2
// TODO: temporary definition until IDF-6270 is implemented
#include "soc/lp_timer_reg.h"
static inline uint32_t lp_timer_hal_get_cycle_count(void)
{
REG_SET_BIT(LP_TIMER_UPDATE_REG, LP_TIMER_MAIN_TIMER_UPDATE);
uint32_t lo = REG_GET_FIELD(LP_TIMER_MAIN_BUF0_LOW_REG, LP_TIMER_MAIN_TIMER_BUF0_LOW);
return lo;
}
#endif
__attribute__((weak)) void bootloader_fill_random(void *buffer, size_t length)
@ -34,6 +57,21 @@
assert(buffer != NULL);
for (size_t i = 0; i < length; i++) {
#if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
random = REG_READ(WDEV_RND_REG);
start = esp_cpu_get_cycle_count();
do {
random ^= REG_READ(WDEV_RND_REG);
now = esp_cpu_get_cycle_count();
} while (now - start < RNG_CPU_WAIT_CYCLE_NUM);
// XOR the RT slow clock, which is asynchronous, to add some entropy and improve
// the distribution
uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
random = random ^ current_rtc_timer_counter;
buffer_bytes[i] = random & 0xFF;
#else
if (i == 0 || i % 4 == 0) { /* redundant check is for a compiler warning */
/* in bootloader with ADC feeding HWRNG, we accumulate 1
bit of entropy per 40 APB cycles (==80 CPU cycles.)
@ -50,6 +88,7 @@
} while (now - start < RNG_CPU_WAIT_CYCLE_NUM);
}
buffer_bytes[i] = random >> ((i % 4) * 8);
#endif
}
}

View File

@ -1,22 +1,99 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "esp_log.h"
static const char *TAG = "bootloader_random";
static const uint32_t SAR2_CHANNEL = 9;
static const uint32_t PATTERN_BIT_WIDTH = 6;
static const uint32_t SAR1_ATTEN = 1;
static const uint32_t SAR2_ATTEN = 1;
void bootloader_random_enable(void)
{
// TODO: IDF-5352
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
// pull SAR ADC out of reset
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
// enable SAR ADC APB clock
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
// enable ADC_CTRL_CLK (SAR ADC function clock)
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
// create patterns and set them in pattern table
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
// Same as in C3
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
// set timer expiry (timer is ADC_CTRL_CLK)
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
// enable timer
REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
}
void bootloader_random_disable(void)
{
// TODO: IDF-5352
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
// disable timer
REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
// Write reset value of this register
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
// Revert ADC I2C configuration and initial voltage source setting
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
// Revert PMU_RF_PWC_REG to it's initial value
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
// Set PCR_SARADC_CONF_REG to initial state
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
}

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@ -1,21 +1,88 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "esp_log.h"
static const char *TAG = "bootloader_random";
static const uint32_t SAR2_CHANNEL = 9;
static const uint32_t PATTERN_BIT_WIDTH = 6;
static const uint32_t SAR1_ATTEN = 1;
static const uint32_t SAR2_ATTEN = 1;
void bootloader_random_enable(void)
{
// ESP32H2-TODO: IDF-6274
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0X08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0X66);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0X08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0X66);
// create patterns and set them in pattern table
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN;
uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 0);
// Same as in C3
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
// set timer expiry (timer is ADC_CTRL_CLK)
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
// ENABLE_TIMER
REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
}
void bootloader_random_disable(void)
{
// ESP32H2-TODO: IDF-6274
ESP_EARLY_LOGW(TAG, "bootloader_random_disable() has not been implemented yet");
// disable timer
REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
// Write reset value of this register
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
// Revert ADC I2C configuration and initial voltage source setting
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
// Set PCR_SARADC_CONF_REG to initial state
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
}

View File

@ -1,24 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "esp_log.h"
#include "soc/syscon_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/system_reg.h"
#include "esp_private/regi2c_ctrl.h"
// ESP32H4-TODO: IDF-3381
void bootloader_random_enable(void)
{
}
void bootloader_random_disable(void)
{
}

View File

@ -28,12 +28,6 @@
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h"
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/efuse.h"
#include "esp32h4/rom/crc.h"
#include "esp32h4/rom/uart.h"
#include "esp32h4/rom/gpio.h"
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/efuse.h"
#include "esp32c2/rom/crc.h"

View File

@ -3,18 +3,10 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable;
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable;
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;

View File

@ -34,6 +34,7 @@
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
@ -78,10 +79,19 @@ static void bootloader_super_wdt_auto_feed(void)
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
}
static inline void bootloader_ana_reset_config(void)
{
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)
{
esp_err_t ret = ESP_OK;
bootloader_ana_reset_config();
bootloader_super_wdt_auto_feed();
// In RAM_APP, memory will be initialized in `call_start_cpu0`

View File

@ -3,19 +3,34 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/rtc_cntl_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
} else {
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
(void)enable;
}

View File

@ -96,29 +96,29 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
/*
For origin chip & ECO1: only support swt reset;
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
For origin chip & ECO1: brownout & clock glitch reset not available
For ECO2: fix brownout reset bug
For ECO3: fix clock glitch reset bug
*/
switch (efuse_hal_chip_revision()) {
case 0:
case 1:
//Enable WDT reset. Disable BOR and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
//Disable BOD and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable WDT and BOR reset. Disable GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable WDT, BOR, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;

View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

View File

@ -103,33 +103,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
// TODO: IDF-5990 copied from C3, need update
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
/*
For origin chip & ECO1: only support swt reset;
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:
//Disable BOR and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOR reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOR, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)

View File

@ -1,15 +1,24 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
//C6 doesn't support bypass super WDT reset
assert(enable);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
} else {
@ -17,12 +26,8 @@ void bootloader_ana_bod_reset_config(bool enable)
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
} else {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
}
(void)enable;
}

View File

@ -93,33 +93,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
// TODO: IDF-5990 copied from C6, need update
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
/*
For origin chip & ECO1: only support swt reset;
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:
//Disable BOR and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOR reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOR, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)

View File

@ -1,20 +1,22 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
// ESP32H2 has removed the super wdt
//H2 doesn't support bypass super WDT reset
assert(enable);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
} else {
@ -22,12 +24,8 @@ void bootloader_ana_bod_reset_config(bool enable)
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
} else {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
}
(void)enable;
}

View File

@ -1,155 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "sdkconfig.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_image_format.h"
#include "flash_qio_mode.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "soc/efuse_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "soc/assist_debug_reg.h"
#include "esp_cpu.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/spi_periph.h"
#include "soc/extmem_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32h4/rom/efuse.h"
#include "esp32h4/rom/ets_sys.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "bootloader_clock.h"
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
static const char *TAG = "boot.esp32h4";
static void wdt_reset_cpu0_info_enable(void)
{
REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
}
static void wdt_reset_info_dump(int cpu)
{
(void) cpu;
// saved PC was already printed by the ROM bootloader.
// nothing to do here.
}
static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
}
if (wdt_rst) {
// if reset by WDT dump info from trace port
wdt_reset_info_dump(0);
}
wdt_reset_cpu0_info_enable();
}
static void bootloader_super_wdt_auto_feed(void)
{
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
}
static inline void bootloader_hardware_init(void)
{
}
static inline void bootloader_ana_reset_config(void)
{
//Enable WDT, BOR, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
}
esp_err_t bootloader_init(void)
{
esp_err_t ret = ESP_OK;
bootloader_hardware_init();
bootloader_ana_reset_config();
bootloader_super_wdt_auto_feed();
// In RAM_APP, memory will be initialized in `call_start_cpu0`
#if !CONFIG_APP_BUILD_TYPE_RAM
// protect memory region
bootloader_init_mem();
/* check that static RAM is after the stack */
assert(&_bss_start <= &_bss_end);
assert(&_data_start <= &_data_end);
// clear bss section
bootloader_clear_bss_section();
#endif // !CONFIG_APP_BUILD_TYPE_RAM
// config clock
bootloader_clock_configure();
// initialize console, from now on, we can use esp_log
bootloader_console_init();
/* print 2nd bootloader banner */
bootloader_print_banner();
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
//init cache hal
cache_hal_init(); //TODO IDF-4649
//init mmu
mmu_hal_init();
// update flash ID
bootloader_flash_update_id();
// Check and run XMC startup flow
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
return ret;
}
#if !CONFIG_APP_BUILD_TYPE_RAM
// read bootloader header
if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
return ret;
}
// read chip revision and check if it's compatible to bootloader
if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
return ret;
}
#endif // !CONFIG_APP_BUILD_TYPE_RAM
// initialize spi flash
if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
return ret;
}
#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
// check whether a WDT reset happend
bootloader_check_wdt_reset();
// config WDT
bootloader_config_wdt();
// enable RNG early entropy source
bootloader_enable_random();
return ret;
}

View File

@ -1,40 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "bootloader_sha.h"
#include <stdbool.h>
#include <string.h>
#include <assert.h>
#include <sys/param.h>
#include "esp32h4/rom/sha.h"
static SHA_CTX ctx;
bootloader_sha256_handle_t bootloader_sha256_start()
{
// Enable SHA hardware
ets_sha_enable();
ets_sha_init(&ctx, SHA2_256);
return &ctx; // Meaningless non-NULL value
}
void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
{
assert(handle != NULL);
assert(data_len % 4 == 0);
ets_sha_update(&ctx, data, data_len, false);
}
void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
{
assert(handle != NULL);
if (digest == NULL) {
bzero(&ctx, sizeof(ctx));
return;
}
ets_sha_finish(&ctx, digest);
}

View File

@ -1,41 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
} else {
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
}
}
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
} else {
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
}
}

View File

@ -1,59 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <strings.h>
#include "esp_flash_encrypt.h"
#include "esp_secure_boot.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_log.h"
#include "sdkconfig.h"
static __attribute__((unused)) const char *TAG = "flash_encrypt";
esp_err_t esp_flash_encryption_enable_secure_features(void)
{
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
ESP_LOGI(TAG, "Disable UART bootloader encryption...");
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
#else
ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
#endif
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
ESP_LOGI(TAG, "Disable UART bootloader cache...");
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
#else
ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
#endif
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
ESP_LOGI(TAG, "Disable JTAG...");
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
#else
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
#endif
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
// This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
// otherwise the Flash Encryption key cannot be read protected
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
#endif
#ifndef CONFIG_SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE
// Set write-protection for DIS_ICACHE to prevent bricking chip in case it will be set accidentally.
// esp32h4 has DIS_ICACHE. Write-protection bit = 2.
// List of eFuses with the same write protection bit:
// DIS_ICACHE, DIS_USB_JTAG, POWERGLITCH_EN, DIS_FORCE_DOWNLOAD, SPI_DOWNLOAD_MSPI_DIS,
// DIS_TWAI, JTAG_SEL_ENABLE, DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_ICACHE);
#endif
return ESP_OK;
}

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@ -1,70 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <strings.h>
#include "esp_flash_encrypt.h"
#include "esp_secure_boot.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_log.h"
#include "sdkconfig.h"
static __attribute__((unused)) const char *TAG = "secure_boot";
esp_err_t esp_secure_boot_enable_secure_features(void)
{
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
ESP_LOGI(TAG, "Enabling Security download mode...");
esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
if (err != ESP_OK) {
ESP_LOGE(TAG, "Could not enable Security download mode...");
return err;
}
#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
ESP_LOGI(TAG, "Disable ROM Download mode...");
esp_err_t err = esp_efuse_disable_rom_download_mode();
if (err != ESP_OK) {
ESP_LOGE(TAG, "Could not disable ROM Download mode...");
return err;
}
#else
ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
#endif
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
ESP_LOGI(TAG, "Disable hardware & software JTAG...");
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
#else
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
#endif
#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
#endif
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
bool rd_dis_now = true;
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
when Flash Encryption is being enabled */
rd_dis_now = esp_flash_encryption_enabled();
#endif
if (rd_dis_now) {
ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
}
#else
ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
#endif
return ESP_OK;
}

View File

@ -3,18 +3,10 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable;
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable;
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;

View File

@ -130,7 +130,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_ana_reset_config(void)
{
//Enable WDT, BOR, and GLITCH reset
//Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);

View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

View File

@ -29,8 +29,6 @@
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/rtc.h"
#include "esp32c2/rom/secure_boot.h"

View File

@ -13,8 +13,6 @@
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C6

View File

@ -4,8 +4,7 @@ cmake_minimum_required(VERSION 3.16)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers")
list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
list(PREPEND SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers" "sdkconfig.defaults")
# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
set(COMPONENTS main)

View File

@ -4,8 +4,7 @@ cmake_minimum_required(VERSION 3.16)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers")
list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
list(PREPEND SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers" "sdkconfig.defaults")
# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
set(COMPONENTS main)

View File

@ -17,10 +17,6 @@ if(CONFIG_BT_ENABLED)
list(APPEND srcs "controller/esp32c3/bt.c")
list(APPEND include_dirs include/esp32c3/include)
elseif(CONFIG_IDF_TARGET_ESP32H4)
list(APPEND srcs "controller/esp32h4/bt.c")
list(APPEND include_dirs include/esp32h4/include)
elseif(CONFIG_IDF_TARGET_ESP32C2)
list(APPEND srcs "controller/esp32c2/bt.c")
list(APPEND include_dirs include/esp32c2/include)
@ -716,15 +712,6 @@ if(CONFIG_BT_ENABLED)
target_link_directories(${COMPONENT_LIB} INTERFACE
"${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
elseif(CONFIG_IDF_TARGET_ESP32H4)
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1)
# TODO: rename esp32h2 to esp32h4 [BT-2875]
add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta1/libble_app.a")
elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2)
# TODO: rename esp32h2 to esp32h4 [BT-2875]
add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta2/libble_app.a")
endif()
target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
elseif(CONFIG_IDF_TARGET_ESP32C2)
add_prebuilt_library(libble_app "controller/lib_esp32c2/esp32c2-bt-lib/libble_app.a")
target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)

View File

@ -111,7 +111,6 @@ typedef struct {
typedef struct {
void *handle;
void *storage;
} btdm_queue_item_t;
/* OSI function */
@ -555,17 +554,8 @@ static void *semphr_create_wrapper(uint32_t max, uint32_t init)
void *handle = NULL;
#if !CONFIG_SPIRAM_USE_MALLOC
/* IDF FreeRTOS guarantees that all dynamic memory allocation goes to internal RAM. */
handle = (void *)xSemaphoreCreateCounting(max, init);
#else
StaticQueue_t *queue_buffer = NULL;
queue_buffer = heap_caps_malloc(sizeof(StaticQueue_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
assert(queue_buffer);
semphr->storage = queue_buffer;
handle = (void *)xSemaphoreCreateCountingStatic(max, init, queue_buffer);
#endif
assert(handle);
#if CONFIG_BTDM_CTRL_HLI
@ -601,11 +591,6 @@ static void semphr_delete_wrapper(void *semphr)
if (handle) {
vSemaphoreDelete(handle);
}
#ifdef CONFIG_SPIRAM_USE_MALLOC
if (semphr_item->storage) {
free(semphr_item->storage);
}
#endif
free(semphr);
}
@ -691,18 +676,9 @@ static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
queue = (btdm_queue_item_t*)heap_caps_malloc(sizeof(btdm_queue_item_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
assert(queue);
#if CONFIG_SPIRAM_USE_MALLOC
queue->storage = heap_caps_calloc(1, sizeof(StaticQueue_t) + (queue_len*item_size), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
assert(queue->storage);
queue->handle = xQueueCreateStatic( queue_len, item_size, ((uint8_t*)(queue->storage)) + sizeof(StaticQueue_t), (StaticQueue_t*)(queue->storage));
assert(queue->handle);
#else
/* IDF FreeRTOS guarantees that all dynamic memory allocation goes to internal RAM. */
queue->handle = xQueueCreate( queue_len, item_size);
assert(queue->handle);
#endif
return queue;
}
@ -714,13 +690,6 @@ static void queue_delete_wrapper(void *queue)
if(queue_item->handle){
vQueueDelete(queue_item->handle);
}
#if CONFIG_SPIRAM_USE_MALLOC
if (queue_item->storage) {
free(queue_item->storage);
}
#endif
free(queue_item);
}
}

View File

@ -139,6 +139,7 @@ extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv);
extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level);
extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info);
extern void bt_track_pll_cap(void);
extern uint32_t _bt_bss_start;
extern uint32_t _bt_bss_end;
extern uint32_t _nimble_bss_start;
@ -170,7 +171,9 @@ static int esp_intr_free_wrapper(void **ret_handle);
static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
static uint32_t osi_random_wrapper(void);
static void esp_reset_rpa_moudle(void);
static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
const uint8_t *our_priv_key, uint8_t *out_dhkey);
/* Local variable definition
***************************************************************************
*/
@ -223,9 +226,10 @@ struct ext_funcs_t ext_funcs_ro = {
._task_delete = task_delete_wrapper,
._osi_assert = osi_assert_wrapper,
._os_random = osi_random_wrapper,
._ecc_gen_key_pair = ble_sm_alg_gen_key_pair,
._ecc_gen_dh_key = ble_sm_alg_gen_dhkey,
._ecc_gen_key_pair = esp_ecc_gen_key_pair,
._ecc_gen_dh_key = esp_ecc_gen_dh_key,
._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
._esp_bt_track_pll_cap = bt_track_pll_cap,
.magic = EXT_FUNC_MAGIC_VALUE,
};
@ -348,6 +352,25 @@ static void task_delete_wrapper(void *task_handle)
vTaskDelete(task_handle);
}
static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv)
{
int rc = -1;
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
rc = ble_sm_alg_gen_key_pair(pub, priv);
#endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
return rc;
}
static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
const uint8_t *our_priv_key, uint8_t *out_dhkey)
{
int rc = -1;
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
rc = ble_sm_alg_gen_dhkey(peer_pub_key_x, peer_pub_key_y, our_priv_key, out_dhkey);
#endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
return rc;
}
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no)
{
@ -815,8 +838,8 @@ esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
{
intptr_t mem_start, mem_end;
if (mode == ESP_BT_MODE_BLE) {
mem_start = (intptr_t)&_bt_bss_start;
if (mode & ESP_BT_MODE_BLE) {
mem_start = (intptr_t)&_bt_bss_start;
mem_end = (intptr_t)&_bt_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
@ -831,18 +854,18 @@ esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
}
mem_start = (intptr_t)&_nimble_bss_start;
mem_end = (intptr_t)&_nimble_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
mem_end = (intptr_t)&_nimble_bss_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
mem_start = (intptr_t)&_nimble_data_start;
mem_end = (intptr_t)&_nimble_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
mem_start = (intptr_t)&_nimble_data_start;
mem_end = (intptr_t)&_nimble_data_end;
if (mem_start != mem_end) {
ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end);
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
}
}
return ESP_OK;

View File

@ -135,7 +135,6 @@ typedef struct vhci_host_callback {
typedef struct {
void *handle;
void *storage;
} btdm_queue_item_t;
typedef void (* osi_intr_handler)(void);
@ -511,16 +510,10 @@ static void *semphr_create_wrapper(uint32_t max, uint32_t init)
btdm_queue_item_t *semphr = heap_caps_calloc(1, sizeof(btdm_queue_item_t), MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
assert(semphr);
#if !CONFIG_SPIRAM_USE_MALLOC
/* IDF FreeRTOS guarantees that all dynamic memory allocation goes to internal RAM. */
semphr->handle = (void *)xSemaphoreCreateCounting(max, init);
#else
semphr->storage = heap_caps_malloc(sizeof(StaticQueue_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
assert(semphr->storage);
semphr->handle = (void *)xSemaphoreCreateCountingStatic(max, init, semphr->storage);
#endif
assert(semphr->handle);
return semphr;
}
@ -535,11 +528,6 @@ static void semphr_delete_wrapper(void *semphr)
if (semphr_item->handle) {
vSemaphoreDelete(semphr_item->handle);
}
#ifdef CONFIG_SPIRAM_USE_MALLOC
if (semphr_item->storage) {
free(semphr_item->storage);
}
#endif
free(semphr);
}
@ -595,18 +583,9 @@ static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
queue = (btdm_queue_item_t*)heap_caps_malloc(sizeof(btdm_queue_item_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
assert(queue);
#if CONFIG_SPIRAM_USE_MALLOC
queue->storage = heap_caps_calloc(1, sizeof(StaticQueue_t) + (queue_len*item_size), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
assert(queue->storage);
queue->handle = xQueueCreateStatic( queue_len, item_size, ((uint8_t*)(queue->storage)) + sizeof(StaticQueue_t), (StaticQueue_t*)(queue->storage));
assert(queue->handle);
#else
/* IDF FreeRTOS guarantees that all dynamic memory allocation goes to internal RAM. */
queue->handle = xQueueCreate( queue_len, item_size);
assert(queue->handle);
#endif
return queue;
}
@ -618,13 +597,6 @@ static void queue_delete_wrapper(void *queue)
if(queue_item->handle){
vQueueDelete(queue_item->handle);
}
#if CONFIG_SPIRAM_USE_MALLOC
if (queue_item->storage) {
free(queue_item->storage);
}
#endif
free(queue_item);
}
}

View File

@ -167,7 +167,9 @@ static int esp_intr_free_wrapper(void **ret_handle);
static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
static uint32_t osi_random_wrapper(void);
static void esp_reset_rpa_moudle(void);
static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
const uint8_t *our_priv_key, uint8_t *out_dhkey);
/* Local variable definition
***************************************************************************
*/
@ -218,8 +220,8 @@ struct ext_funcs_t ext_funcs_ro = {
._task_delete = task_delete_wrapper,
._osi_assert = osi_assert_wrapper,
._os_random = osi_random_wrapper,
._ecc_gen_key_pair = ble_sm_alg_gen_key_pair,
._ecc_gen_dh_key = ble_sm_alg_gen_dhkey,
._ecc_gen_key_pair = esp_ecc_gen_key_pair,
._ecc_gen_dh_key = esp_ecc_gen_dh_key,
._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
.magic = EXT_FUNC_MAGIC_VALUE,
};
@ -335,6 +337,25 @@ static void task_delete_wrapper(void *task_handle)
vTaskDelete(task_handle);
}
static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv)
{
int rc = -1;
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
rc = ble_sm_alg_gen_key_pair(pub, priv);
#endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
return rc;
}
static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
const uint8_t *our_priv_key, uint8_t *out_dhkey)
{
int rc = -1;
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
rc = ble_sm_alg_gen_dhkey(peer_pub_key_x, peer_pub_key_y, our_priv_key, out_dhkey);
#endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
return rc;
}
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no)
{

View File

@ -167,7 +167,9 @@ static int esp_intr_free_wrapper(void **ret_handle);
static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
static uint32_t osi_random_wrapper(void);
static void esp_reset_rpa_moudle(void);
static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
const uint8_t *our_priv_key, uint8_t *out_dhkey);
/* Local variable definition
***************************************************************************
*/
@ -218,8 +220,8 @@ struct ext_funcs_t ext_funcs_ro = {
._task_delete = task_delete_wrapper,
._osi_assert = osi_assert_wrapper,
._os_random = osi_random_wrapper,
._ecc_gen_key_pair = ble_sm_alg_gen_key_pair,
._ecc_gen_dh_key = ble_sm_alg_gen_dhkey,
._ecc_gen_key_pair = esp_ecc_gen_key_pair,
._ecc_gen_dh_key = esp_ecc_gen_dh_key,
._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
.magic = EXT_FUNC_MAGIC_VALUE,
};
@ -335,6 +337,25 @@ static void task_delete_wrapper(void *task_handle)
vTaskDelete(task_handle);
}
static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv)
{
int rc = -1;
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
rc = ble_sm_alg_gen_key_pair(pub, priv);
#endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
return rc;
}
static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
const uint8_t *our_priv_key, uint8_t *out_dhkey)
{
int rc = -1;
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
rc = ble_sm_alg_gen_dhkey(peer_pub_key_x, peer_pub_key_y, our_priv_key, out_dhkey);
#endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
return rc;
}
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no)
{
@ -562,32 +583,6 @@ void controller_sleep_deinit(void)
#endif //CONFIG_PM_ENABLE
}
#define REG_MODEM_SYSCON_BASE 0x600A5400
#define REG_MODEM_LPCON_BASE 0x600AD000
#define DR_REG_MODEM_SYSCON_BASE REG_MODEM_SYSCON_BASE
#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
#define MODEM_LPCON_CLK_CONF_REG (REG_MODEM_LPCON_BASE + 0x0008)
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (REG_MODEM_LPCON_BASE + 0x000C)
#include "hal/clk_tree_ll.h"
static void enable_chip_clk(void)
{
WRITE_PERI_REG(MODEM_SYSCON_CLK_CONF_REG,0xFFFFFFFF);
WRITE_PERI_REG(MODEM_SYSCON_CLK_CONF1_REG,0xFFFFFFFF);
WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_REG ,0xFFFFFFFF);
// SET BIT for BLE RTC clk
SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG,PMU_HP_SLEEP_XPD_XTAL32K);
// REG_SET_FIELD(LP_CLKRST_LPPERI_REG,LP_CLKRST_LP_SEL_XTAL32K,1);
// REG_SET_FIELD(LP_CLKRST_LPPERI_REG,LP_CLKRST_LP_BLETIMER_DIV_NUM,0);
/* For chip */
WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_REG ,0xFFFFFFFF);
WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_FORCE_ON_REG ,0xFFFFFFFF);
}
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
{
uint8_t mac[6];
@ -612,8 +607,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
return ret;
}
enable_chip_clk();
/* Initialize the function pointers for OS porting */
npl_freertos_funcs_init();
struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
@ -653,9 +646,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
#endif // CONFIG_BT_NIMBLE_ENABLED
/* Enable BT-related clocks */
// modem_clock_module_enable(PERIPH_BT_MODULE);
// modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
// esp_phy_modem_init();
modem_clock_module_enable(PERIPH_BT_MODULE);
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
esp_phy_enable();
esp_btbb_enable();
s_ble_active = true;
@ -697,9 +689,8 @@ free_controller:
ble_controller_deinit();
esp_btbb_disable();
esp_phy_disable();
// esp_phy_modem_deinit();
// modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
// modem_clock_module_disable(PERIPH_BT_MODULE);
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
modem_clock_module_disable(PERIPH_BT_MODULE);
#if CONFIG_BT_NIMBLE_ENABLED
ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
#endif // CONFIG_BT_NIMBLE_ENABLED
@ -728,9 +719,8 @@ esp_err_t esp_bt_controller_deinit(void)
esp_phy_disable();
s_ble_active = false;
}
// esp_phy_modem_deinit();
// modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
// modem_clock_module_disable(PERIPH_BT_MODULE);
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
modem_clock_module_disable(PERIPH_BT_MODULE);
ble_controller_deinit();

View File

@ -1,392 +0,0 @@
menu "HCI Config"
choice BT_LE_HCI_INTERFACE
prompt "Select HCI interface"
default BT_LE_HCI_INTERFACE_USE_RAM
config BT_LE_HCI_INTERFACE_USE_RAM
bool "ram"
help
Use RAM as HCI interface
config BT_LE_HCI_INTERFACE_USE_UART
bool "uart"
help
Use UART as HCI interface
endchoice
config BT_LE_HCI_UART_PORT
int "HCI UART port"
depends on BT_LE_HCI_INTERFACE_USE_UART
default 1
help
Set the port number of HCI UART
config BT_LE_HCI_UART_FLOWCTRL
bool "HCI uart Hardware Flow ctrl"
depends on BT_LE_HCI_INTERFACE_USE_UART
default n
config BT_LE_HCI_UART_TX_PIN
int "HCI uart Tx gpio"
depends on BT_LE_HCI_INTERFACE_USE_UART
default 19
config BT_LE_HCI_UART_RX_PIN
int "HCI uart Rx gpio"
depends on BT_LE_HCI_INTERFACE_USE_UART
default 10
config BT_LE_HCI_UART_RTS_PIN
int "HCI uart RTS gpio"
depends on BT_LE_HCI_UART_FLOWCTRL
default 4
config BT_LE_HCI_UART_CTS_PIN
int "HCI uart CTS gpio"
depends on BT_LE_HCI_UART_FLOWCTRL
default 5
config BT_LE_HCI_UART_BAUD
int "HCI uart baudrate"
depends on BT_LE_HCI_INTERFACE_USE_UART
default 921600
help
HCI uart baud rate 115200 ~ 1000000
choice BT_LE_HCI_UART_PARITY
prompt "select uart parity"
depends on BT_LE_HCI_INTERFACE_USE_UART
default BT_LE_HCI_UART_UART_PARITY_DISABLE
config BT_LE_HCI_UART_UART_PARITY_DISABLE
bool "PARITY_DISABLE"
help
UART_PARITY_DISABLE
config BT_LE_HCI_UART_UART_PARITY_EVEN
bool "PARITY_EVEN"
help
UART_PARITY_EVEN
config BT_LE_HCI_UART_UART_PARITY_ODD
bool "PARITY_ODD"
help
UART_PARITY_ODD
endchoice
config BT_LE_HCI_UART_TASK_STACK_SIZE
int "HCI uart task stack size"
depends on BT_LE_HCI_INTERFACE_USE_UART
default 1000
help
Set the size of uart task stack
endmenu
config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT
bool
default y
help
Enable NPL porting for controller.
menuconfig BT_LE_50_FEATURE_SUPPORT
bool "Enable BLE 5 feature"
depends on !BT_NIMBLE_ENABLED
default y
help
Enable BLE 5 feature
config BT_LE_LL_CFG_FEAT_LE_2M_PHY
bool "Enable 2M Phy"
depends on BT_LE_50_FEATURE_SUPPORT
default y
help
Enable 2M-PHY
config BT_LE_LL_CFG_FEAT_LE_CODED_PHY
bool "Enable coded Phy"
depends on BT_LE_50_FEATURE_SUPPORT
default y
help
Enable coded-PHY
config BT_LE_EXT_ADV
bool "Enable extended advertising"
depends on BT_LE_50_FEATURE_SUPPORT
default y
help
Enable this option to do extended advertising. Extended advertising
will be supported from BLE 5.0 onwards.
if BT_LE_EXT_ADV
config BT_LE_MAX_EXT_ADV_INSTANCES
int "Maximum number of extended advertising instances."
range 0 4
default 1
depends on BT_LE_EXT_ADV
help
Change this option to set maximum number of extended advertising
instances. Minimum there is always one instance of
advertising. Enter how many more advertising instances you
want.
Each extended advertising instance will take about 0.5k DRAM.
config BT_LE_EXT_ADV_MAX_SIZE
int "Maximum length of the advertising data."
range 0 1650
default 1650
depends on BT_LE_EXT_ADV
help
Defines the length of the extended adv data. The value should not
exceed 1650.
config BT_LE_ENABLE_PERIODIC_ADV
bool "Enable periodic advertisement."
default y
depends on BT_LE_EXT_ADV
help
Enable this option to start periodic advertisement.
config BT_LE_PERIODIC_ADV_SYNC_TRANSFER
bool "Enable Transer Sync Events"
depends on BT_LE_ENABLE_PERIODIC_ADV
default y
help
This enables controller transfer periodic sync events to host
endif
config BT_LE_MAX_PERIODIC_SYNCS
int "Maximum number of periodic advertising syncs"
depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED
range 0 8
default 1 if BT_LE_ENABLE_PERIODIC_ADV
default 0
help
Set this option to set the upper limit for number of periodic sync
connections. This should be less than maximum connections allowed by
controller.
config BT_LE_MAX_PERIODIC_ADVERTISER_LIST
int "Maximum number of periodic advertiser list"
depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED
range 1 5
default 5
help
Set this option to set the upper limit for number of periodic advertiser list.
menu "Memory Settings"
depends on !BT_NIMBLE_ENABLED
config BT_LE_MSYS_1_BLOCK_COUNT
int "MSYS_1 Block Count"
default 12
help
MSYS is a system level mbuf registry. For prepare write & prepare
responses MBUFs are allocated out of msys_1 pool. For NIMBLE_MESH
enabled cases, this block count is increased by 8 than user defined
count.
config BT_LE_MSYS_1_BLOCK_SIZE
int "MSYS_1 Block Size"
default 256
help
Dynamic memory size of block 1
config BT_LE_MSYS_2_BLOCK_COUNT
int "MSYS_2 Block Count"
default 24
help
Dynamic memory count
config BT_LE_MSYS_2_BLOCK_SIZE
int "MSYS_2 Block Size"
default 320
help
Dynamic memory size of block 2
config BT_LE_ACL_BUF_COUNT
int "ACL Buffer count"
default 10
help
The number of ACL data buffers.
config BT_LE_ACL_BUF_SIZE
int "ACL Buffer size"
default 517
help
This is the maximum size of the data portion of HCI ACL data packets.
It does not include the HCI data header (of 4 bytes)
config BT_LE_HCI_EVT_BUF_SIZE
int "HCI Event Buffer size"
default 257 if BT_LE_EXT_ADV
default 70
help
This is the size of each HCI event buffer in bytes. In case of
extended advertising, packets can be fragmented. 257 bytes is the
maximum size of a packet.
config BT_LE_HCI_EVT_HI_BUF_COUNT
int "High Priority HCI Event Buffer count"
default 30
help
This is the high priority HCI events' buffer size. High-priority
event buffers are for everything except advertising reports. If there
are no free high-priority event buffers then host will try to allocate a
low-priority buffer instead
config BT_LE_HCI_EVT_LO_BUF_COUNT
int "Low Priority HCI Event Buffer count"
default 8
help
This is the low priority HCI events' buffer size. Low-priority event
buffers are only used for advertising reports. If there are no free
low-priority event buffers, then an incoming advertising report will
get dropped
endmenu
config BT_LE_CONTROLLER_TASK_STACK_SIZE
int "Controller task stack size"
default 5120 if BLE_MESH
default 4096
help
This configures stack size of NimBLE controller task
config BT_LE_LL_RESOLV_LIST_SIZE
int "BLE LL Resolving list size"
range 1 5
default 4
help
Configure the size of resolving list used in link layer.
menuconfig BT_LE_SECURITY_ENABLE
bool "Enable BLE SM feature"
depends on !BT_NIMBLE_ENABLED
default y
help
Enable BLE sm feature
config BT_LE_SM_LEGACY
bool "Security manager legacy pairing"
depends on BT_LE_SECURITY_ENABLE
default y
help
Enable security manager legacy pairing
config BT_LE_SM_SC
bool "Security manager secure connections (4.2)"
depends on BT_LE_SECURITY_ENABLE
default y
help
Enable security manager secure connections
config BT_LE_SM_SC_DEBUG_KEYS
bool "Use predefined public-private key pair"
default n
depends on BT_LE_SECURITY_ENABLE && BT_LE_SM_SC
help
If this option is enabled, SM uses predefined DH key pair as described
in Core Specification, Vol. 3, Part H, 2.3.5.6.1. This allows to
decrypt air traffic easily and thus should only be used for debugging.
config BT_LE_LL_CFG_FEAT_LE_ENCRYPTION
bool "Enable LE encryption"
depends on BT_LE_SECURITY_ENABLE
default y
help
Enable encryption connection
config BT_LE_CRYPTO_STACK_MBEDTLS
bool "Override TinyCrypt with mbedTLS for crypto computations"
default y
depends on !BT_NIMBLE_ENABLED
select MBEDTLS_ECP_RESTARTABLE
select MBEDTLS_CMAC_C
help
Enable this option to choose mbedTLS instead of TinyCrypt for crypto
computations.
config BT_LE_WHITELIST_SIZE
int "BLE white list size"
range 1 15
default 12
depends on !BT_NIMBLE_ENABLED
help
BLE list size
config BT_LE_LL_DUP_SCAN_LIST_COUNT
int "BLE duplicate scan list count"
range 1 100
default 20
help
config the max count of duplicate scan list
config BT_LE_LL_SCA
int "BLE Sleep clock accuracy"
range 0 500
default 60
help
Sleep clock accuracy of our device (in ppm)
config BT_LE_MAX_CONNECTIONS
int "Maximum number of concurrent connections"
depends on !BT_NIMBLE_ENABLED
range 1 9
default 3
help
Defines maximum number of concurrent BLE connections. For ESP32, user
is expected to configure BTDM_CTRL_BLE_MAX_CONN from controller menu
along with this option. Similarly for ESP32-C3 or ESP32-S3, user is expected to
configure BT_CTRL_BLE_MAX_ACT from controller menu.
Each connection will take about 1k DRAM.
choice BT_LE_COEX_PHY_CODED_TX_RX_TLIM
prompt "Coexistence: limit on MAX Tx/Rx time for coded-PHY connection"
default BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS
depends on !BT_NIMBLE_ENABLED
help
When using PHY-Coded in BLE connection, limitation on max tx/rx time can be applied to
better avoid dramatic performance deterioration of Wi-Fi.
config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN
bool "Force Enable"
help
Always enable the limitation on max tx/rx time for Coded-PHY connection
config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS
bool "Force Disable"
help
Disable the limitation on max tx/rx time for Coded-PHY connection
endchoice
config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF
int
depends on !BT_NIMBLE_ENABLED
default 1 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN
default 0 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS
config BT_LE_SLEEP_ENABLE
bool "Enable BLE sleep"
default n
help
Enable BLE sleep
choice BT_LE_WAKEUP_SOURCE
prompt "BLE light sleep wakeup source"
depends on BT_LE_SLEEP_ENABLE
default BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
config BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
bool "Use ESP timer to wakeup CPU"
help
Use esp timer to wakeup CPU
endchoice
config BT_LE_USE_ESP_TIMER
bool "Use Esp Timer for callout"
depends on !BT_NIMBLE_ENABLED
default y
help
Set this option to use Esp Timer which has higher priority timer
instead of FreeRTOS timer

File diff suppressed because it is too large Load Diff

View File

@ -502,7 +502,7 @@ int bt_le_update_white_list(struct bt_mesh_white_list *wl)
}
if (BTM_BleUpdateAdvWhitelist(wl->add_remove, wl->remote_bda,
wl->addr_type, (tBTM_ADD_WHITELIST_CBACK *)wl->update_wl_comp_cb) == false) {
wl->addr_type, (tBTM_UPDATE_WHITELIST_CBACK *)wl->update_wl_comp_cb) == false) {
return -EIO;
}

View File

@ -1547,13 +1547,8 @@ int bt_mesh_provisioner_store_node_info(struct bt_mesh_node *node)
#define HEARTBEAT_FILTER_ADD 0x00
#define HEARTBEAT_FILTER_REMOVE 0x01
#define HEARTBEAT_FILTER_WITH_SRC BIT(0)
#define HEARTBEAT_FILTER_WITH_DST BIT(1)
#define HEARTBEAT_FILTER_WITH_BOTH (BIT(1) | BIT(0))
static struct heartbeat_recv {
struct heartbeat_filter {
uint8_t type; /* Indicate if using src or dst or both to filter heartbeat messages */
uint16_t src; /* Heartbeat source address (unicast address) */
uint16_t dst; /* Heartbeat destination address (unicast address or group address) */
} filter[CONFIG_BLE_MESH_PROVISIONER_RECV_HB_FILTER_SIZE];
@ -1590,19 +1585,6 @@ int bt_mesh_provisioner_set_heartbeat_filter_type(uint8_t type)
return 0;
}
static inline uint8_t get_filter_addr_type(uint16_t src, uint16_t dst)
{
if (BLE_MESH_ADDR_IS_UNICAST(src)) {
if (BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)) {
return HEARTBEAT_FILTER_WITH_BOTH;
} else {
return HEARTBEAT_FILTER_WITH_SRC;
}
} else {
return HEARTBEAT_FILTER_WITH_DST;
}
}
static int hb_filter_alloc(uint16_t src, uint16_t dst)
{
int i;
@ -1612,7 +1594,6 @@ static int hb_filter_alloc(uint16_t src, uint16_t dst)
if (filter->src == BLE_MESH_ADDR_UNASSIGNED &&
filter->dst == BLE_MESH_ADDR_UNASSIGNED) {
filter->type = get_filter_addr_type(src, dst);
filter->src = src;
filter->dst = dst;
return 0;
@ -1627,8 +1608,8 @@ static int hb_filter_add(uint16_t src, uint16_t dst)
{
int i;
if (!BLE_MESH_ADDR_IS_UNICAST(src) &&
!BLE_MESH_ADDR_IS_UNICAST(dst) && !BLE_MESH_ADDR_IS_GROUP(dst)) {
if (!(BLE_MESH_ADDR_IS_UNICAST(src) &&
(BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)))) {
BT_ERR("Invalid filter address, src 0x%04x, dst 0x%04x", src, dst);
return -EINVAL;
}
@ -1637,10 +1618,9 @@ static int hb_filter_add(uint16_t src, uint16_t dst)
for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) {
struct heartbeat_filter *filter = &hb_rx.filter[i];
if ((BLE_MESH_ADDR_IS_UNICAST(src) && filter->src == src) ||
((BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)) &&
filter->dst == dst)) {
memset(filter, 0, sizeof(struct heartbeat_filter));
if (filter->src == src && filter->dst == dst) {
BT_WARN("Filter already exists, src 0x%04x dst 0x%04x", filter->src, filter->dst);
return 0;
}
}
@ -1651,8 +1631,8 @@ static int hb_filter_remove(uint16_t src, uint16_t dst)
{
int i;
if (!BLE_MESH_ADDR_IS_UNICAST(src) &&
!BLE_MESH_ADDR_IS_UNICAST(dst) && !BLE_MESH_ADDR_IS_GROUP(dst)) {
if (!(BLE_MESH_ADDR_IS_UNICAST(src) &&
(BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)))) {
BT_ERR("Invalid filter address, src 0x%04x, dst 0x%04x", src, dst);
return -EINVAL;
}
@ -1660,9 +1640,7 @@ static int hb_filter_remove(uint16_t src, uint16_t dst)
for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) {
struct heartbeat_filter *filter = &hb_rx.filter[i];
if ((BLE_MESH_ADDR_IS_UNICAST(src) && filter->src == src) ||
((BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)) &&
filter->dst == dst)) {
if (filter->src == src && filter->dst == dst) {
memset(filter, 0, sizeof(struct heartbeat_filter));
}
}
@ -1689,26 +1667,8 @@ static bool filter_with_rejectlist(uint16_t hb_src, uint16_t hb_dst)
for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) {
struct heartbeat_filter *filter = &hb_rx.filter[i];
switch (filter->type) {
case HEARTBEAT_FILTER_WITH_SRC:
if (hb_src == filter->src) {
return true;
}
break;
case HEARTBEAT_FILTER_WITH_DST:
if (hb_dst == filter->dst) {
return true;
}
break;
case HEARTBEAT_FILTER_WITH_BOTH:
if (hb_src == filter->src && hb_dst == filter->dst) {
return true;
}
break;
default:
BT_DBG("Unknown filter addr type 0x%02x", filter->type);
break;
if (hb_src == filter->src && hb_dst == filter->dst) {
return true;
}
}
@ -1721,26 +1681,8 @@ static bool filter_with_acceptlist(uint16_t hb_src, uint16_t hb_dst)
for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) {
struct heartbeat_filter *filter = &hb_rx.filter[i];
switch (filter->type) {
case HEARTBEAT_FILTER_WITH_SRC:
if (hb_src == filter->src) {
return false;
}
break;
case HEARTBEAT_FILTER_WITH_DST:
if (hb_dst == filter->dst) {
return false;
}
break;
case HEARTBEAT_FILTER_WITH_BOTH:
if (hb_src == filter->src && hb_dst == filter->dst) {
return false;
}
break;
default:
BT_DBG("Unknown filter addr type 0x%02x", filter->type);
break;
if (hb_src == filter->src && hb_dst == filter->dst) {
return false;
}
}

View File

@ -650,6 +650,7 @@ typedef enum {
typedef enum{
ESP_BLE_WHITELIST_REMOVE = 0X00, /*!< remove mac from whitelist */
ESP_BLE_WHITELIST_ADD = 0X01, /*!< add address to whitelist */
ESP_BLE_WHITELIST_CLEAR = 0x02, /*!< clear all device in whitelist */
} esp_ble_wl_operation_t;
#if (BLE_42_FEATURE_SUPPORT == TRUE)
typedef enum {

View File

@ -1299,11 +1299,11 @@ void bta_av_setconfig_rsp (tBTA_AV_SCB *p_scb, tBTA_AV_DATA *p_data)
if (p_scb->codec_type == BTA_AV_CODEC_SBC || num > 1) {
/* if SBC is used by the SNK as INT, discover req is not sent in bta_av_config_ind.
* call disc_res now */
* call cfg_res now */
/* this is called in A2DP SRC path only, In case of SINK we don't need it */
if (local_sep == AVDT_TSEP_SRC) {
p_scb->p_cos->disc_res(p_scb->hndl, num, num, 0, p_scb->peer_addr,
UUID_SERVCLASS_AUDIO_SOURCE);
p_scb->p_cos->cfg_res(p_scb->hndl, num, num, 0, p_scb->peer_addr,
UUID_SERVCLASS_AUDIO_SOURCE);
}
} else {
/* we do not know the peer device and it is using non-SBC codec

View File

@ -845,14 +845,14 @@ void bta_dm_ble_set_channels (tBTA_DM_MSG *p_data)
void bta_dm_update_white_list(tBTA_DM_MSG *p_data)
{
#if (BLE_INCLUDED == TRUE)
BTM_BleUpdateAdvWhitelist(p_data->white_list.add_remove, p_data->white_list.remote_addr, p_data->white_list.addr_type, p_data->white_list.add_wl_cb);
BTM_BleUpdateAdvWhitelist(p_data->white_list.add_remove, p_data->white_list.remote_addr, p_data->white_list.addr_type, p_data->white_list.update_wl_cb);
#endif ///BLE_INCLUDED == TRUE
}
void bta_dm_clear_white_list(tBTA_DM_MSG *p_data)
{
#if (BLE_INCLUDED == TRUE)
BTM_BleClearWhitelist();
BTM_BleClearWhitelist(p_data->white_list.update_wl_cb);
#endif
}

View File

@ -324,26 +324,26 @@ void BTA_DmBleSetChannels(const uint8_t *channels, tBTA_CMPL_CB *set_channels_c
}
void BTA_DmUpdateWhiteList(BOOLEAN add_remove, BD_ADDR remote_addr, tBLE_ADDR_TYPE addr_type, tBTA_ADD_WHITELIST_CBACK *add_wl_cb)
void BTA_DmUpdateWhiteList(BOOLEAN add_remove, BD_ADDR remote_addr, tBLE_ADDR_TYPE addr_type, tBTA_UPDATE_WHITELIST_CBACK *update_wl_cb)
{
tBTA_DM_API_UPDATE_WHITE_LIST *p_msg;
if ((p_msg = (tBTA_DM_API_UPDATE_WHITE_LIST *)osi_malloc(sizeof(tBTA_DM_API_UPDATE_WHITE_LIST))) != NULL) {
p_msg->hdr.event = BTA_DM_API_UPDATE_WHITE_LIST_EVT;
p_msg->add_remove = add_remove;
p_msg->addr_type = addr_type;
p_msg->add_wl_cb = add_wl_cb;
p_msg->update_wl_cb = update_wl_cb;
memcpy(p_msg->remote_addr, remote_addr, sizeof(BD_ADDR));
bta_sys_sendmsg(p_msg);
}
}
void BTA_DmClearWhiteList(void)
void BTA_DmClearWhiteList(tBTA_UPDATE_WHITELIST_CBACK *update_wl_cb)
{
tBTA_DM_API_ENABLE *p_msg;
if ((p_msg = (tBTA_DM_API_ENABLE *)osi_malloc(sizeof(tBTA_DM_API_ENABLE))) != NULL) {
tBTA_DM_API_UPDATE_WHITE_LIST *p_msg;
if ((p_msg = (tBTA_DM_API_UPDATE_WHITE_LIST *)osi_malloc(sizeof(tBTA_DM_API_UPDATE_WHITE_LIST))) != NULL) {
p_msg->hdr.event = BTA_DM_API_CLEAR_WHITE_LIST_EVT;
p_msg->p_sec_cback = NULL;
p_msg->update_wl_cb = update_wl_cb;
bta_sys_sendmsg(p_msg);
}

View File

@ -389,7 +389,7 @@ void bta_dm_co_ble_set_init_key_req(UINT8 init_key)
{
#if (SMP_INCLUDED == TRUE)
init_key &= 0x0f; // 4~7bit reservd, only used the 0~3bit
bte_appl_cfg.ble_init_key &= init_key;
bte_appl_cfg.ble_init_key = init_key;
#endif ///SMP_INCLUDED == TRUE
}
@ -397,7 +397,7 @@ void bta_dm_co_ble_set_rsp_key_req(UINT8 rsp_key)
{
#if (SMP_INCLUDED == TRUE)
rsp_key &= 0x0f; // 4~7bit reservd, only used the 0~3bit
bte_appl_cfg.ble_resp_key &= rsp_key;
bte_appl_cfg.ble_resp_key = rsp_key;
#endif ///SMP_INCLUDED == TRUE
}

View File

@ -279,7 +279,7 @@ typedef struct {
BOOLEAN add_remove;
BD_ADDR remote_addr;
tBLE_ADDR_TYPE addr_type;
tBTA_ADD_WHITELIST_CBACK *add_wl_cb;
tBTA_UPDATE_WHITELIST_CBACK *update_wl_cb;
}tBTA_DM_API_UPDATE_WHITE_LIST;
typedef struct {

View File

@ -517,8 +517,8 @@ void bta_gattc_co_get_addr_list(BD_ADDR *addr_list)
void bta_gattc_co_cache_addr_save(BD_ADDR bd_addr, hash_key_t hash_key)
{
esp_err_t err_code;
UINT8 num = ++cache_env->num_addr;
UINT8 index = 0;
UINT8 new_index = cache_env->num_addr;
UINT8 *p_buf = osi_malloc(MAX_ADDR_LIST_CACHE_BUF);
// check the address list has the same hash key or not
if (bta_gattc_co_find_hash_in_cache(hash_key) != INVALID_ADDR_NUM) {
@ -530,20 +530,22 @@ void bta_gattc_co_cache_addr_save(BD_ADDR bd_addr, hash_key_t hash_key)
memcpy(cache_env->cache_addr[index].hash_key, hash_key, sizeof(hash_key_t));
} else {
//if the bd_addr didn't in the address list, added the bd_addr to the last of the address list.
memcpy(cache_env->cache_addr[num - 1].hash_key, hash_key, sizeof(hash_key_t));
memcpy(cache_env->cache_addr[num - 1].addr, bd_addr, sizeof(BD_ADDR));
memcpy(cache_env->cache_addr[new_index].hash_key, hash_key, sizeof(hash_key_t));
memcpy(cache_env->cache_addr[new_index].addr, bd_addr, sizeof(BD_ADDR));
cache_env->num_addr++;
}
} else {
APPL_TRACE_DEBUG("%s(), num = %d", __func__, num);
memcpy(cache_env->cache_addr[num - 1].addr, bd_addr, sizeof(BD_ADDR));
memcpy(cache_env->cache_addr[num - 1].hash_key, hash_key, sizeof(hash_key_t));
APPL_TRACE_DEBUG("%s(), num = %d", __func__, new_index + 1);
memcpy(cache_env->cache_addr[new_index].addr, bd_addr, sizeof(BD_ADDR));
memcpy(cache_env->cache_addr[new_index].hash_key, hash_key, sizeof(hash_key_t));
cache_env->num_addr++;
}
nvs_handle_t *fp = &cache_env->addr_fp;
UINT16 length = num*(sizeof(BD_ADDR) + sizeof(hash_key_t));
UINT16 length = cache_env->num_addr * (sizeof(BD_ADDR) + sizeof(hash_key_t));
for (UINT8 i = 0; i < num; i++) {
for (UINT8 i = 0; i < cache_env->num_addr; i++) {
//copy the address to the buffer.
memcpy(p_buf + i*(sizeof(BD_ADDR) + sizeof(hash_key_t)), cache_env->cache_addr[i].addr, sizeof(BD_ADDR));
//copy the hash key to the buffer.

View File

@ -94,7 +94,7 @@ static void bta_ag_cback_open(tBTA_AG_SCB *p_scb, tBTA_AG_DATA *p_data, tBTA_AG_
/* call app callback with open event */
open.hdr.handle = bta_ag_scb_to_idx(p_scb);
open.hdr.app_id = p_scb->app_id;
open.status = status;
open.hdr.status = status;
open.service_id = bta_ag_svc_id[p_scb->conn_service];
if (p_data) {
/* if p_data is provided then we need to pick the bd address from the open api structure */
@ -131,7 +131,7 @@ void bta_ag_register(tBTA_AG_SCB *p_scb, tBTA_AG_DATA *p_data)
/* call app callback with register event */
reg.hdr.handle = bta_ag_scb_to_idx(p_scb);
reg.hdr.app_id = p_scb->app_id;
reg.status = BTA_AG_SUCCESS;
reg.hdr.status = BTA_AG_SUCCESS;
(*bta_ag_cb.p_cback)(BTA_AG_REGISTER_EVT, (tBTA_AG *) &reg);
}

View File

@ -831,7 +831,7 @@ static void bta_ag_api_register(tBTA_AG_DATA *p_data)
APPL_TRACE_DEBUG("bta_ag_api_register: p_scb 0x%08x ", (unsigned int)p_scb);
bta_ag_sm_execute(p_scb, p_data->hdr.event, p_data);
} else {
reg.status = BTA_AG_FAIL_RESOURCES;
reg.hdr.status = BTA_AG_FAIL_RESOURCES;
(*bta_ag_cb.p_cback)(BTA_AG_REGISTER_EVT, (tBTA_AG *) &reg);
}
}

View File

@ -427,7 +427,8 @@ static void bta_hf_client_handle_ciev(UINT32 index, UINT32 value)
APPL_TRACE_DEBUG("%s index: %u value: %u", __FUNCTION__, index, value);
if (index >= BTA_HF_CLIENT_AT_INDICATOR_COUNT) {
if (index == 0 || index > BTA_HF_CLIENT_AT_INDICATOR_COUNT) {
APPL_TRACE_WARNING("%s: Invalid index %d", __FUNCTION__, index);
return;
}
@ -435,7 +436,7 @@ static void bta_hf_client_handle_ciev(UINT32 index, UINT32 value)
service_availability = value == 0 ? FALSE : TRUE;
}
realind = bta_hf_client_cb.scb.at_cb.indicator_lookup[index];
realind = bta_hf_client_cb.scb.at_cb.indicator_lookup[index - 1];
if (realind >= 0 && realind < BTA_HF_CLIENT_AT_SUPPORTED_INDICATOR_COUNT) {
/* get the real in-array index from lookup table by index it comes at */

View File

@ -333,8 +333,6 @@ typedef struct
typedef struct
{
tBTA_AG_HDR hdr;
UINT16 handle;
tBTA_AG_STATUS status;
} tBTA_AG_REGISTER;
/* data associated with BTA_AG_OPEN_EVT */
@ -343,7 +341,6 @@ typedef struct
tBTA_AG_HDR hdr;
BD_ADDR bd_addr;
tBTA_SERVICE_ID service_id;
tBTA_AG_STATUS status;
} tBTA_AG_OPEN;
/* data associated with BTA_AG_CLOSE_EVT */

View File

@ -420,7 +420,7 @@ typedef tBTM_START_ADV_CMPL_CBACK tBTA_START_ADV_CMPL_CBACK;
typedef tBTM_START_STOP_ADV_CMPL_CBACK tBTA_START_STOP_ADV_CMPL_CBACK;
typedef tBTM_ADD_WHITELIST_CBACK tBTA_ADD_WHITELIST_CBACK;
typedef tBTM_UPDATE_WHITELIST_CBACK tBTA_UPDATE_WHITELIST_CBACK;
typedef tBTM_SET_PKT_DATA_LENGTH_CBACK tBTA_SET_PKT_DATA_LENGTH_CBACK;
@ -1756,9 +1756,9 @@ void BTA_DmSetQos(BD_ADDR bd_addr, UINT32 t_poll, tBTM_CMPL_CB *p_cb);
*******************************************************************************/
void BTA_DmBleSetChannels(const uint8_t *channels, tBTA_CMPL_CB *set_channels_cb);
extern void BTA_DmUpdateWhiteList(BOOLEAN add_remove, BD_ADDR remote_addr, tBLE_ADDR_TYPE addr_type, tBTA_ADD_WHITELIST_CBACK *add_wl_cb);
extern void BTA_DmUpdateWhiteList(BOOLEAN add_remove, BD_ADDR remote_addr, tBLE_ADDR_TYPE addr_type, tBTA_UPDATE_WHITELIST_CBACK *update_wl_cb);
extern void BTA_DmClearWhiteList(void);
extern void BTA_DmClearWhiteList(tBTA_UPDATE_WHITELIST_CBACK *update_wl_cb);
extern void BTA_DmBleReadAdvTxPower(tBTA_CMPL_CB *cmpl_cb);
#endif ///BLE_INCLUDED == TRUE

View File

@ -262,6 +262,8 @@ typedef BOOLEAN (*tBTA_AV_CO_INIT) (UINT8 *p_codec_type, UINT8 *p_codec_info,
UINT8 *p_num_protect, UINT8 *p_protect_info, UINT8 tsep);
typedef void (*tBTA_AV_CO_DISC_RES) (tBTA_AV_HNDL hndl, UINT8 num_seps,
UINT8 num_snk, UINT8 num_src, BD_ADDR addr, UINT16 uuid_local);
typedef void (*tBTA_AV_CO_CFG_RES) (tBTA_AV_HNDL hndl, UINT8 num_seps,
UINT8 num_snk, UINT8 num_src, BD_ADDR addr, UINT16 uuid_local);
typedef UINT8 (*tBTA_AV_CO_GETCFG) (tBTA_AV_HNDL hndl, tBTA_AV_CODEC codec_type,
UINT8 *p_codec_info, UINT8 *p_sep_info_idx, UINT8 seid,
UINT8 *p_num_protect, UINT8 *p_protect_info);
@ -291,6 +293,7 @@ typedef BOOLEAN (*tBTA_AVRC_CO_RN_EVT_SUPPORTED) (UINT8 event_id);
typedef struct {
tBTA_AV_CO_INIT init;
tBTA_AV_CO_DISC_RES disc_res;
tBTA_AV_CO_CFG_RES cfg_res;
tBTA_AV_CO_GETCFG getcfg;
tBTA_AV_CO_SETCFG setcfg;
tBTA_AV_CO_OPEN open;

View File

@ -312,6 +312,58 @@ void bta_av_co_audio_disc_res(tBTA_AV_HNDL hndl, UINT8 num_seps, UINT8 num_snk,
} else if (uuid_local == UUID_SERVCLASS_AUDIO_SOURCE) {
p_peer->uuid_to_connect = UUID_SERVCLASS_AUDIO_SINK;
}
p_peer->got_disc_res = TRUE;
}
/*******************************************************************************
**
** Function bta_av_co_audio_cfg_res
**
** Description This callout function is executed by AV to report the
** number of stream end points (SEP) were found during the
** incoming AVDT stream config request process.
**
**
** Returns void.
**
*******************************************************************************/
void bta_av_co_audio_cfg_res(tBTA_AV_HNDL hndl, UINT8 num_seps, UINT8 num_snk,
UINT8 num_src, BD_ADDR addr, UINT16 uuid_local)
{
tBTA_AV_CO_PEER *p_peer;
FUNC_TRACE();
APPL_TRACE_DEBUG("bta_av_co_audio_cfg_res h:x%x num_seps:%d num_snk:%d num_src:%d",
hndl, num_seps, num_snk, num_src);
/* Find the peer info */
p_peer = bta_av_co_get_peer(hndl);
if (p_peer == NULL) {
APPL_TRACE_ERROR("bta_av_co_audio_cfg_res could not find peer entry");
return;
}
/* Sanity check : this should never happen */
if (p_peer->opened) {
APPL_TRACE_ERROR("bta_av_co_audio_cfg_res peer already opened");
}
/* Copy the discovery results */
bdcpy(p_peer->addr, addr);
if (!p_peer->got_disc_res) {
p_peer->num_snks = num_snk;
p_peer->num_srcs = num_src;
p_peer->num_seps = num_seps;
p_peer->num_rx_snks = 0;
p_peer->num_rx_srcs = 0;
p_peer->num_sup_snks = 0;
}
if (uuid_local == UUID_SERVCLASS_AUDIO_SINK) {
p_peer->uuid_to_connect = UUID_SERVCLASS_AUDIO_SOURCE;
} else if (uuid_local == UUID_SERVCLASS_AUDIO_SOURCE) {
p_peer->uuid_to_connect = UUID_SERVCLASS_AUDIO_SINK;
}
}
/*******************************************************************************
@ -1698,6 +1750,7 @@ BOOLEAN bta_av_co_get_remote_bitpool_pref(UINT8 *min, UINT8 *max)
const tBTA_AV_CO_FUNCTS bta_av_a2d_cos = {
bta_av_co_audio_init,
bta_av_co_audio_disc_res,
bta_av_co_audio_cfg_res,
bta_av_co_audio_getconfig,
bta_av_co_audio_setconfig,
bta_av_co_audio_open,

View File

@ -53,6 +53,7 @@ typedef struct {
BOOLEAN opened; /* opened */
UINT16 mtu; /* maximum transmit unit size */
UINT16 uuid_to_connect; /* uuid of peer device */
BOOLEAN got_disc_res; /* got the results of initiating discovery */
} tBTA_AV_CO_PEER;
typedef struct {

View File

@ -104,12 +104,13 @@ static void bas_gatts_callback(esp_gatts_evt_t event, tBTA_GATTS *p_data)
p_data->add_result.char_uuid.uu.uuid16);
UINT16 char_uuid = p_data->add_result.char_uuid.uu.uuid16;
UINT16 service_id = p_data->add_result.service_id;
if (char_uuid == GATT_UUID_BATTERY_LEVEL) {
bas_AddCharDescr(service_id, p_data->add_result.attr_id);
}
if (char_uuid == GATT_UUID_SYSTEM_ID | GATT_UUID_MODEL_NUMBER_STR | GATT_UUID_PNP_ID |
GATT_UUID_SERIAL_NUMBER_STR | GATT_UUID_FW_VERSION_STR | GATT_UUID_HW_VERSION_STR |
GATT_UUID_SW_VERSION_STR | GATT_UUID_MANU_NAME | GATT_UUID_IEEE_DATA) {
UINT16 uuid_len = p_data->add_result.char_uuid.len;
if (uuid_len == ESP_UUID_LEN_16) {
if (char_uuid == GATT_UUID_BATTERY_LEVEL) {
bas_AddCharDescr(service_id, p_data->add_result.attr_id);
}
switch (char_uuid) {
case GATT_UUID_SYSTEM_ID:
dis_cb.dis_attr[0].handle = service_id; break;
@ -130,6 +131,8 @@ static void bas_gatts_callback(esp_gatts_evt_t event, tBTA_GATTS *p_data)
case GATT_UUID_PNP_ID:
dis_cb.dis_attr[8].handle = service_id; break;
}
default:
break;
}
}
break;

View File

@ -811,7 +811,7 @@ static void btc_gap_ble_set_channels_cmpl_callback(void *p_data)
}
static void btc_add_whitelist_complete_callback(UINT8 status, tBTM_WL_OPERATION wl_opration)
static void btc_update_whitelist_complete_callback(UINT8 status, tBTM_WL_OPERATION wl_opration)
{
esp_ble_gap_cb_param_t param;
bt_status_t ret;
@ -1607,10 +1607,10 @@ void btc_gap_ble_call_handler(btc_msg_t *msg)
btc_ble_config_local_icon(arg->cfg_local_icon.icon);
break;
case BTC_GAP_BLE_ACT_UPDATE_WHITE_LIST:
BTA_DmUpdateWhiteList(arg->update_white_list.add_remove, arg->update_white_list.remote_bda, arg->update_white_list.wl_addr_type, btc_add_whitelist_complete_callback);
BTA_DmUpdateWhiteList(arg->update_white_list.add_remove, arg->update_white_list.remote_bda, arg->update_white_list.wl_addr_type, btc_update_whitelist_complete_callback);
break;
case BTC_GAP_BLE_ACT_CLEAR_WHITE_LIST:
BTA_DmClearWhiteList();
BTA_DmClearWhiteList(btc_update_whitelist_complete_callback);
break;
case BTC_GAP_BLE_ACT_READ_RSSI:
BTA_DmReadRSSI(arg->read_rssi.remote_addr, BTA_TRANSPORT_LE, btc_read_ble_rssi_cmpl_callback);

View File

@ -134,6 +134,14 @@ do {
hf_local_param[idx].btc_hf_cb.num_active = 0; \
hf_local_param[idx].btc_hf_cb.num_held = 0;
#define CHECK_HF_IDX(idx) \
do { \
if ((idx < 0) || (idx >= BTC_HF_NUM_CB)) { \
BTC_TRACE_ERROR("%s: Invalid index %d", __FUNCTION__, idx); \
return; \
} \
} while (0)
/************************************************************************************
** Static Function
************************************************************************************/
@ -1213,19 +1221,9 @@ void btc_hf_cb_handler(btc_msg_t *msg)
tBTA_AG *p_data = (tBTA_AG *)msg->arg;
esp_hf_cb_param_t param;
bdstr_t bdstr;
int idx;
if (p_data == NULL) {
idx = BTC_HF_INVALID_IDX;
} else {
idx = p_data->hdr.handle - 1;
}
int idx = BTC_HF_INVALID_IDX;
BTC_TRACE_DEBUG("%s: event = %s", __FUNCTION__, dump_hf_event(event));
if ((idx < 0) || (idx >= BTC_HF_NUM_CB)) {
BTC_TRACE_ERROR("%s: Invalid index %d", __FUNCTION__, idx);
return;
}
switch (event) {
case BTA_AG_ENABLE_EVT:
@ -1234,6 +1232,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_REGISTER_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
hf_local_param[idx].btc_hf_cb.handle = p_data->reg.hdr.handle;
BTC_TRACE_DEBUG("%s: BTA_AG_REGISTER_EVT," "hf_local_param[%d].btc_hf_cb.handle = %d",
__FUNCTION__, idx, hf_local_param[idx].btc_hf_cb.handle);
@ -1242,7 +1242,9 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_OPEN_EVT:
{
if (p_data->open.status == BTA_AG_SUCCESS)
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
if (p_data->open.hdr.status == BTA_AG_SUCCESS)
{
bdcpy(hf_local_param[idx].btc_hf_cb.connected_bda.address, p_data->open.bd_addr);
hf_local_param[idx].btc_hf_cb.connection_state = ESP_HF_CONNECTION_STATE_CONNECTED;
@ -1253,7 +1255,7 @@ void btc_hf_cb_handler(btc_msg_t *msg)
hf_local_param[idx].btc_hf_cb.connection_state = ESP_HF_CONNECTION_STATE_DISCONNECTED;
} else {
BTC_TRACE_WARNING("%s: AG open failed, but another device connected. status=%d state=%d connected device=%s", __FUNCTION__,
p_data->open.status, hf_local_param[idx].btc_hf_cb.connection_state,
p_data->open.hdr.status, hf_local_param[idx].btc_hf_cb.connection_state,
bdaddr_to_string(&hf_local_param[idx].btc_hf_cb.connected_bda, bdstr, sizeof(bdstr)));
break;
}
@ -1270,13 +1272,15 @@ void btc_hf_cb_handler(btc_msg_t *msg)
if (hf_local_param[idx].btc_hf_cb.connection_state == ESP_HF_CONNECTION_STATE_DISCONNECTED)
bdsetany(hf_local_param[idx].btc_hf_cb.connected_bda.address);
if (p_data->open.status != BTA_AG_SUCCESS)
if (p_data->open.hdr.status != BTA_AG_SUCCESS)
btc_queue_advance();
break;
}
case BTA_AG_CONN_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
clock_gettime(CLOCK_MONOTONIC, &(hf_local_param[idx].btc_hf_cb.connected_timestamp));
BTC_TRACE_DEBUG("%s: BTA_AG_CONN_EVT, idx = %d ", __FUNCTION__, idx);
hf_local_param[idx].btc_hf_cb.peer_feat = p_data->conn.peer_feat;
@ -1298,6 +1302,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_CLOSE_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
hf_local_param[idx].btc_hf_cb.connected_timestamp.tv_sec = 0;
hf_local_param[idx].btc_hf_cb.connection_state = ESP_HF_CONNECTION_STATE_DISCONNECTED;
BTC_TRACE_DEBUG("%s: BTA_AG_CLOSE_EVT," "hf_local_param[%d].btc_hf_cb.handle = %d", __FUNCTION__,
@ -1319,6 +1325,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_AUDIO_OPEN_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
do {
memset(&param, 0, sizeof(esp_hf_cb_param_t));
param.audio_stat.state = ESP_HF_AUDIO_STATE_CONNECTED;
@ -1330,6 +1338,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_AUDIO_MSBC_OPEN_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
do {
memset(&param, 0, sizeof(esp_hf_cb_param_t));
param.audio_stat.state = ESP_HF_AUDIO_STATE_CONNECTED_MSBC;
@ -1340,6 +1350,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
}
case BTA_AG_AUDIO_CLOSE_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
do {
memset(&param, 0, sizeof(esp_hf_cb_param_t));
param.audio_stat.state = ESP_HF_AUDIO_STATE_DISCONNECTED;
@ -1351,6 +1363,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_AT_BVRA_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
do {
memset(&param, 0, sizeof(esp_hf_cb_param_t));
param.vra_rep.value = p_data->val.num;
@ -1468,6 +1482,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_AT_BINP_EVT:
case BTA_AG_AT_BTRH_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
tBTA_AG_RES_DATA ag_res;
memset(&ag_res, 0, sizeof(ag_res));
ag_res.ok_flag = BTA_AG_OK_ERROR;
@ -1478,6 +1494,8 @@ void btc_hf_cb_handler(btc_msg_t *msg)
case BTA_AG_AT_BAC_EVT:
{
idx = p_data->hdr.handle - 1;
CHECK_HF_IDX(idx);
BTC_TRACE_DEBUG("AG Bitmap of peer-codecs %d", p_data->val.num);
#if (BTM_WBS_INCLUDED == TRUE)
/* If the peer supports mSBC and the BTC prefferred codec is also mSBC, then
@ -1497,9 +1515,9 @@ void btc_hf_cb_handler(btc_msg_t *msg)
#if (BTM_WBS_INCLUDED == TRUE)
case BTA_AG_WBS_EVT:
{
BTC_TRACE_DEBUG("Set codec status %d codec %d 1=CVSD 2=MSBC", p_data->val.hdr.status, p_data->val.value);
BTC_TRACE_DEBUG("Set codec status %d codec %d 1=CVSD 2=MSBC", p_data->val.hdr.status, p_data->val.num);
memset(&param, 0, sizeof(esp_hf_cb_param_t));
param.wbs_rep.codec = p_data->val.value;
param.wbs_rep.codec = p_data->val.num;
btc_hf_cb_to_app(ESP_HF_WBS_RESPONSE_EVT, &param);
break;
}

View File

@ -302,21 +302,19 @@ tBTM_STATUS BTM_BleSetExtendedAdvRandaddr(UINT8 instance, BD_ADDR rand_addr)
BD_ADDR invalid_rand_addr_a, invalid_rand_addr_b;
memset(invalid_rand_addr_a, 0xff, sizeof(BD_ADDR));
memset(invalid_rand_addr_b, 0x00, sizeof(BD_ADDR));
invalid_rand_addr_b[0] = invalid_rand_addr_b[0] | BT_STATIC_RAND_ADDR_MASK;
if((rand_addr[0] & BT_STATIC_RAND_ADDR_MASK) == BT_STATIC_RAND_ADDR_MASK
&& memcmp(invalid_rand_addr_a, rand_addr, BD_ADDR_LEN) != 0
&& memcmp(invalid_rand_addr_b, rand_addr, BD_ADDR_LEN) != 0){
// set random address
if((err = btsnd_hcic_ble_set_extend_rand_address(instance, rand_addr)) != HCI_SUCCESS) {
BTM_TRACE_ERROR("%s, fail to send the hci command, the error code = %s(0x%x)",
__func__, btm_ble_hci_status_to_str(err), err);
if((rand_addr[0] & BT_STATIC_RAND_ADDR_MASK) == BT_STATIC_RAND_ADDR_MASK) {
invalid_rand_addr_b[0] = invalid_rand_addr_b[0] | BT_STATIC_RAND_ADDR_MASK;
if (memcmp(invalid_rand_addr_a, rand_addr, BD_ADDR_LEN) == 0
|| memcmp(invalid_rand_addr_b, rand_addr, BD_ADDR_LEN) == 0) {
status = BTM_ILLEGAL_VALUE;
} else {
// set random address success, update address infor
if(extend_adv_cb.inst[instance].configured && extend_adv_cb.inst[instance].connetable) {
BTM_BleSetStaticAddr(rand_addr);
BTM_UpdateAddrInfor(BLE_ADDR_RANDOM, rand_addr);
}
goto end;
}
} else if ((rand_addr[0] | BT_NON_RPA_MASK) == BT_NON_RPA_MASK) {
invalid_rand_addr_a[0] = invalid_rand_addr_a[0] & BT_NON_RPA_MASK;
if (memcmp(invalid_rand_addr_a, rand_addr, BD_ADDR_LEN) == 0
|| memcmp(invalid_rand_addr_b, rand_addr, BD_ADDR_LEN) == 0) {
status = BTM_ILLEGAL_VALUE;
goto end;
}
} else {
BTM_TRACE_ERROR("%s invalid random address", __func__);
@ -324,6 +322,19 @@ tBTM_STATUS BTM_BleSetExtendedAdvRandaddr(UINT8 instance, BD_ADDR rand_addr)
goto end;
}
// set random address
if((err = btsnd_hcic_ble_set_extend_rand_address(instance, rand_addr)) != HCI_SUCCESS) {
BTM_TRACE_ERROR("%s, fail to send the hci command, the error code = %s(0x%x)",
__func__, btm_ble_hci_status_to_str(err), err);
status = BTM_ILLEGAL_VALUE;
} else {
// set random address success, update address infor
if(extend_adv_cb.inst[instance].configured && extend_adv_cb.inst[instance].connetable) {
BTM_BleSetStaticAddr(rand_addr);
BTM_UpdateAddrInfor(BLE_ADDR_RANDOM, rand_addr);
}
}
end:
cb_params.status = status;

View File

@ -276,12 +276,12 @@ void btm_enq_wl_dev_operation(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_TYPE ad
** the white list.
**
*******************************************************************************/
BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_TYPE addr_type, tBTM_ADD_WHITELIST_CBACK *add_wl_cb)
BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_TYPE addr_type, tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb)
{
if(addr_type > BLE_ADDR_RANDOM) {
BTM_TRACE_ERROR("%s address type is error, unable to add device", __func__);
if (add_wl_cb){
add_wl_cb(HCI_ERR_ILLEGAL_PARAMETER_FMT,to_add);
if (update_wl_cb){
update_wl_cb(HCI_ERR_ILLEGAL_PARAMETER_FMT,to_add);
}
return FALSE;
}
@ -313,8 +313,8 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_
// do nothing
} else {
BTC_TRACE_ERROR(" controller not support resolvable address");
if (add_wl_cb){
add_wl_cb(HCI_ERR_ILLEGAL_PARAMETER_FMT,to_add);
if (update_wl_cb){
update_wl_cb(HCI_ERR_ILLEGAL_PARAMETER_FMT,to_add);
}
return FALSE;
}
@ -325,8 +325,8 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_
if (to_add && p_cb->white_list_avail_size == 0) {
BTM_TRACE_ERROR("%s Whitelist full, unable to add device", __func__);
if (add_wl_cb){
add_wl_cb(HCI_ERR_MEMORY_FULL,to_add);
if (update_wl_cb){
update_wl_cb(HCI_ERR_MEMORY_FULL,to_add);
}
return FALSE;
}
@ -335,8 +335,8 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_
/* added the bd_addr to the connection hash map queue */
if(!background_connection_add((bt_bdaddr_t *)bd_addr)) {
/* if the bd_addr already exist in whitelist, just callback return TRUE */
if (add_wl_cb){
add_wl_cb(HCI_SUCCESS,to_add);
if (update_wl_cb){
update_wl_cb(HCI_SUCCESS,to_add);
}
return TRUE;
}
@ -344,16 +344,16 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_
/* remove the bd_addr to the connection hash map queue */
if(!background_connection_remove((bt_bdaddr_t *)bd_addr)){
/* if the bd_addr don't exist in whitelist, just callback return TRUE */
if (add_wl_cb){
add_wl_cb(HCI_SUCCESS,to_add);
if (update_wl_cb){
update_wl_cb(HCI_SUCCESS,to_add);
}
return TRUE;
}
}
if (add_wl_cb){
if (update_wl_cb){
//save add whitelist complete callback
p_cb->add_wl_cb = add_wl_cb;
p_cb->update_wl_cb = update_wl_cb;
}
/* stop the auto connect */
btm_suspend_wl_activity(p_cb->wl_state);
@ -371,11 +371,17 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_
** Description This function clears the white list.
**
*******************************************************************************/
void btm_ble_clear_white_list (void)
void btm_ble_clear_white_list (tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb)
{
tBTM_BLE_CB *p_cb = &btm_cb.ble_ctr_cb;
BTM_TRACE_EVENT ("btm_ble_clear_white_list");
btsnd_hcic_ble_clear_white_list();
background_connections_clear();
if (update_wl_cb) {
p_cb->update_wl_cb = update_wl_cb;
}
}
/*******************************************************************************
@ -399,6 +405,10 @@ void btm_ble_clear_white_list_complete(UINT8 *p_data, UINT16 evt_len)
} else {
BTM_TRACE_ERROR ("%s failed, status 0x%x\n", __func__, status);
}
if (p_cb->update_wl_cb) {
(*p_cb->update_wl_cb)(status, BTM_WHITELIST_CLEAR);
}
}
/*******************************************************************************
@ -429,9 +439,9 @@ void btm_ble_add_2_white_list_complete(UINT8 status)
--btm_cb.ble_ctr_cb.white_list_avail_size;
}
// add whitelist complete callback
if (p_cb->add_wl_cb)
if (p_cb->update_wl_cb)
{
(*p_cb->add_wl_cb)(status, BTM_WHITELIST_ADD);
(*p_cb->update_wl_cb)(status, BTM_WHITELIST_ADD);
}
}
@ -451,9 +461,9 @@ void btm_ble_remove_from_white_list_complete(UINT8 *p, UINT16 evt_len)
if (*p == HCI_SUCCESS) {
++btm_cb.ble_ctr_cb.white_list_avail_size;
}
if (p_cb->add_wl_cb)
if (p_cb->update_wl_cb)
{
(*p_cb->add_wl_cb)(*p, BTM_WHITELIST_REMOVE);
(*p_cb->update_wl_cb)(*p, BTM_WHITELIST_REMOVE);
}
}

View File

@ -321,9 +321,9 @@ void BTM_BleRegiseterConnParamCallback(tBTM_UPDATE_CONN_PARAM_CBACK *update_conn
** Returns void
**
*******************************************************************************/
BOOLEAN BTM_BleUpdateAdvWhitelist(BOOLEAN add_remove, BD_ADDR remote_bda, tBLE_ADDR_TYPE addr_type, tBTM_ADD_WHITELIST_CBACK *add_wl_cb)
BOOLEAN BTM_BleUpdateAdvWhitelist(BOOLEAN add_remove, BD_ADDR remote_bda, tBLE_ADDR_TYPE addr_type, tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb)
{
return btm_update_dev_to_white_list(add_remove, remote_bda, addr_type, add_wl_cb);
return btm_update_dev_to_white_list(add_remove, remote_bda, addr_type, update_wl_cb);
}
/*******************************************************************************
@ -335,9 +335,9 @@ BOOLEAN BTM_BleUpdateAdvWhitelist(BOOLEAN add_remove, BD_ADDR remote_bda, tBLE_A
** Returns void
**
*******************************************************************************/
void BTM_BleClearWhitelist(void)
void BTM_BleClearWhitelist(tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb)
{
btm_ble_clear_white_list();
btm_ble_clear_white_list(update_wl_cb);
}
/*******************************************************************************
@ -1068,7 +1068,18 @@ uint32_t BTM_BleUpdateOwnType(uint8_t *own_bda_type, tBTM_START_ADV_CMPL_CBACK *
#else
uint32_t BTM_BleUpdateOwnType(uint8_t *own_bda_type, tBTM_START_ADV_CMPL_CBACK *cb)
{
if((*own_bda_type == BLE_ADDR_RANDOM) || (*own_bda_type == BLE_ADDR_RANDOM_ID)) {
if((btm_cb.ble_ctr_cb.addr_mgnt_cb.exist_addr_bit & BTM_BLE_GAP_ADDR_BIT_RANDOM) != BTM_BLE_GAP_ADDR_BIT_RANDOM) {
BTM_TRACE_ERROR("No random address yet, please set random address and try\n");
if(cb) {
(* cb)(HCI_ERR_ESP_VENDOR_FAIL);
}
return BTM_ILLEGAL_VALUE;
}
}
btm_cb.ble_ctr_cb.addr_mgnt_cb.own_addr_type = *own_bda_type;
return BTM_SUCCESS;
}
#endif
@ -1273,7 +1284,7 @@ BOOLEAN BTM_BleSetBgConnType(tBTM_BLE_CONN_TYPE bg_conn_type,
void BTM_BleClearBgConnDev(void)
{
btm_ble_start_auto_conn(FALSE);
btm_ble_clear_white_list();
btm_ble_clear_white_list(NULL);
gatt_reset_bgdev_list();
}
@ -2226,9 +2237,10 @@ UINT8 *btm_ble_build_adv_data(tBTM_BLE_AD_MASK *p_data_mask, UINT8 **p_dst,
#if BTM_MAX_LOC_BD_NAME_LEN > 0
if (len > MIN_ADV_LENGTH && data_mask & BTM_BLE_AD_BIT_DEV_NAME) {
if (strlen(btm_cb.cfg.bd_name) > (UINT16)(len - MIN_ADV_LENGTH)) {
*p++ = len - MIN_ADV_LENGTH + 1;
cp_len = (UINT16)(len - MIN_ADV_LENGTH);
*p++ = cp_len + 1;
*p++ = BTM_BLE_AD_TYPE_NAME_SHORT;
ARRAY_TO_STREAM(p, btm_cb.cfg.bd_name, len - MIN_ADV_LENGTH);
ARRAY_TO_STREAM(p, btm_cb.cfg.bd_name, cp_len);
} else {
cp_len = (UINT16)strlen(btm_cb.cfg.bd_name);
*p++ = cp_len + 1;

View File

@ -347,7 +347,7 @@ typedef struct {
tBTM_BLE_SEL_CBACK *p_select_cback;
/* white list information */
UINT8 white_list_avail_size;
tBTM_ADD_WHITELIST_CBACK *add_wl_cb;
tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb;
tBTM_BLE_WL_STATE wl_state;
fixed_queue_t *conn_pending_q;
@ -442,10 +442,10 @@ void btm_ble_update_sec_key_size(BD_ADDR bd_addr, UINT8 enc_key_size);
UINT8 btm_ble_read_sec_key_size(BD_ADDR bd_addr);
/* white list function */
BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_TYPE addr_type, tBTM_ADD_WHITELIST_CBACK *add_wl_cb);
BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_TYPE addr_type, tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb);
void btm_update_scanner_filter_policy(tBTM_BLE_SFP scan_policy);
void btm_update_adv_filter_policy(tBTM_BLE_AFP adv_policy);
void btm_ble_clear_white_list (void);
void btm_ble_clear_white_list (tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb);
void btm_read_white_list_size_complete(UINT8 *p, UINT16 evt_len);
void btm_ble_add_2_white_list_complete(UINT8 status);
void btm_ble_remove_from_white_list_complete(UINT8 *p, UINT16 evt_len);

View File

@ -152,6 +152,7 @@ typedef struct {
typedef enum{
BTM_WHITELIST_REMOVE = 0X00,
BTM_WHITELIST_ADD = 0X01,
BTM_WHITELIST_CLEAR = 0x02,
}tBTM_WL_OPERATION;
@ -190,7 +191,7 @@ typedef void (tBTM_SET_PKT_DATA_LENGTH_CBACK) (UINT8 status, tBTM_LE_SET_PKT_DAT
typedef void (tBTM_SET_RAND_ADDR_CBACK) (UINT8 status);
typedef void (tBTM_ADD_WHITELIST_CBACK) (UINT8 status, tBTM_WL_OPERATION wl_opration);
typedef void (tBTM_UPDATE_WHITELIST_CBACK) (UINT8 status, tBTM_WL_OPERATION wl_opration);
typedef void (tBTM_SET_LOCAL_PRIVACY_CBACK) (UINT8 status);

View File

@ -2270,7 +2270,7 @@ void BTM_BleTurnOnPrivacyOnRemote(BD_ADDR bd_addr,
**
*******************************************************************************/
//extern
BOOLEAN BTM_BleUpdateAdvWhitelist(BOOLEAN add_remove, BD_ADDR emote_bda, tBLE_ADDR_TYPE addr_type, tBTM_ADD_WHITELIST_CBACK *add_wl_cb);
BOOLEAN BTM_BleUpdateAdvWhitelist(BOOLEAN add_remove, BD_ADDR emote_bda, tBLE_ADDR_TYPE addr_type, tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb);
/*******************************************************************************
**
@ -2281,7 +2281,7 @@ BOOLEAN BTM_BleUpdateAdvWhitelist(BOOLEAN add_remove, BD_ADDR emote_bda, tBLE_AD
** Returns void
**
*******************************************************************************/
void BTM_BleClearWhitelist(void);
void BTM_BleClearWhitelist(tBTM_UPDATE_WHITELIST_CBACK *update_wl_cb);
/*******************************************************************************
**

View File

@ -157,13 +157,17 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
#if defined (CONFIG_BT_BLE_50_FEATURES_SUPPORTED) || defined (CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT)
#ifdef CONFIG_BT_BLE_50_FEATURES_SUPPORTED
#define BT_CTRL_50_FEATURE_SUPPORT (CONFIG_BT_BLE_50_FEATURES_SUPPORTED)
#endif
#endif // CONFIG_BT_BLE_50_FEATURES_SUPPORTED
#ifdef CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT
#define BT_CTRL_50_FEATURE_SUPPORT (CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT)
#endif
#endif // CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT
#else
#if defined (CONFIG_BT_BLUEDROID_ENABLED) || defined (CONFIG_BT_NIMBLE_ENABLED)
#define BT_CTRL_50_FEATURE_SUPPORT (0)
#else
#define BT_CTRL_50_FEATURE_SUPPORT (1)
#endif
#endif // (CONFIG_BT_BLUEDROID_ENABLED) || (CONFIG_BT_NIMBLE_ENABLED)
#endif // (CONFIG_BT_BLE_50_FEATURES_SUPPORTED) || (CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT)
#define AGC_RECORRECT_EN ((BT_CTRL_AGC_RECORRECT_EN << 0) | (BT_CTRL_CODED_AGC_RECORRECT <<1))

View File

@ -65,6 +65,7 @@ typedef struct {
.max_cmdline_length = 0, \
}
#if CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
/**
* @brief Parameters for console device: UART
*
@ -76,7 +77,7 @@ typedef struct {
int rx_gpio_num; //!< GPIO number for RX path, -1 means using default one
} esp_console_dev_uart_config_t;
#ifdef CONFIG_ESP_CONSOLE_UART_CUSTOM
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \
{ \
.channel = CONFIG_ESP_CONSOLE_UART_NUM, \
@ -92,8 +93,10 @@ typedef struct {
.tx_gpio_num = -1, \
.rx_gpio_num = -1, \
}
#endif
#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
#endif // CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
#if CONFIG_ESP_CONSOLE_USB_CDC || (defined __DOXYGEN__ && SOC_USB_OTG_SUPPORTED)
/**
* @brief Parameters for console device: USB CDC
*
@ -104,11 +107,10 @@ typedef struct {
} esp_console_dev_usb_cdc_config_t;
#define ESP_CONSOLE_DEV_CDC_CONFIG_DEFAULT() \
{ \
}
#define ESP_CONSOLE_DEV_CDC_CONFIG_DEFAULT() {}
#endif // CONFIG_ESP_CONSOLE_USB_CDC || (defined __DOXYGEN__ && SOC_USB_OTG_SUPPORTED)
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || (defined __DOXYGEN__ && SOC_USB_SERIAL_JTAG_SUPPORTED)
/**
* @brief Parameters for console device: USB-SERIAL-JTAG
*
@ -120,8 +122,7 @@ typedef struct {
} esp_console_dev_usb_serial_jtag_config_t;
#define ESP_CONSOLE_DEV_USB_SERIAL_JTAG_CONFIG_DEFAULT() {}
#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || (defined __DOXYGEN__ && SOC_USB_SERIAL_JTAG_SUPPORTED)
/**
* @brief initialize console module
@ -304,6 +305,7 @@ struct esp_console_repl_s {
esp_err_t (*del)(esp_console_repl_t *repl);
};
#if CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
/**
* @brief Establish a console REPL environment over UART driver
*
@ -326,7 +328,9 @@ struct esp_console_repl_s {
* - ESP_FAIL Parameter error
*/
esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl);
#endif // CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
#if CONFIG_ESP_CONSOLE_USB_CDC || (defined __DOXYGEN__ && SOC_USB_OTG_SUPPORTED)
/**
* @brief Establish a console REPL environment over USB CDC
*
@ -347,8 +351,9 @@ esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_con
* - ESP_FAIL Parameter error
*/
esp_err_t esp_console_new_repl_usb_cdc(const esp_console_dev_usb_cdc_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl);
#endif // CONFIG_ESP_CONSOLE_USB_CDC || (defined __DOXYGEN__ && SOC_USB_OTG_SUPPORTED)
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || (defined __DOXYGEN__ && SOC_USB_SERIAL_JTAG_SUPPORTED)
/**
* @brief Establish a console REPL (Read-eval-print loop) environment over USB-SERIAL-JTAG
*
@ -369,7 +374,7 @@ esp_err_t esp_console_new_repl_usb_cdc(const esp_console_dev_usb_cdc_config_t *d
* - ESP_FAIL Parameter error
*/
esp_err_t esp_console_new_repl_usb_serial_jtag(const esp_console_dev_usb_serial_jtag_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl);
#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || (defined __DOXYGEN__ && SOC_USB_SERIAL_JTAG_SUPPORTED)
/**
* @brief Start REPL environment

View File

@ -47,8 +47,12 @@ typedef struct {
} esp_console_repl_universal_t;
static void esp_console_repl_task(void *args);
#if CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
static esp_err_t esp_console_repl_uart_delete(esp_console_repl_t *repl);
#endif // CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
#if CONFIG_ESP_CONSOLE_USB_CDC
static esp_err_t esp_console_repl_usb_cdc_delete(esp_console_repl_t *repl);
#endif // CONFIG_ESP_CONSOLE_USB_CDC
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
static esp_err_t esp_console_repl_usb_serial_jtag_delete(esp_console_repl_t *repl);
#endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
@ -56,6 +60,7 @@ static esp_err_t esp_console_common_init(size_t max_cmdline_length, esp_console_
static esp_err_t esp_console_setup_prompt(const char *prompt, esp_console_repl_com_t *repl_com);
static esp_err_t esp_console_setup_history(const char *history_path, uint32_t max_history_len, esp_console_repl_com_t *repl_com);
#if CONFIG_ESP_CONSOLE_USB_CDC
esp_err_t esp_console_new_repl_usb_cdc(const esp_console_dev_usb_cdc_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl)
{
esp_err_t ret = ESP_OK;
@ -119,6 +124,7 @@ _exit:
}
return ret;
}
#endif // CONFIG_ESP_CONSOLE_USB_CDC
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
esp_err_t esp_console_new_repl_usb_serial_jtag(const esp_console_dev_usb_serial_jtag_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl)
@ -200,6 +206,7 @@ _exit:
}
#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#if CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl)
{
esp_err_t ret = ESP_OK;
@ -300,6 +307,7 @@ _exit:
}
return ret;
}
#endif // CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
esp_err_t esp_console_start_repl(esp_console_repl_t *repl)
{
@ -404,6 +412,7 @@ _exit:
return ret;
}
#if CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
static esp_err_t esp_console_repl_uart_delete(esp_console_repl_t *repl)
{
esp_err_t ret = ESP_OK;
@ -423,7 +432,9 @@ static esp_err_t esp_console_repl_uart_delete(esp_console_repl_t *repl)
_exit:
return ret;
}
#endif // CONFIG_ESP_CONSOLE_UART_DEFAULT || CONFIG_ESP_CONSOLE_UART_CUSTOM
#if CONFIG_ESP_CONSOLE_USB_CDC
static esp_err_t esp_console_repl_usb_cdc_delete(esp_console_repl_t *repl)
{
esp_err_t ret = ESP_OK;
@ -441,6 +452,7 @@ static esp_err_t esp_console_repl_usb_cdc_delete(esp_console_repl_t *repl)
_exit:
return ret;
}
#endif // CONFIG_ESP_CONSOLE_USB_CDC
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
static esp_err_t esp_console_repl_usb_serial_jtag_delete(esp_console_repl_t *repl)

View File

@ -1046,7 +1046,7 @@ int linenoiseProbe(void) {
flushWrite();
/* Try to read response */
int timeout_ms = 300;
int timeout_ms = 500;
const int retry_ms = 10;
size_t read_bytes = 0;
while (timeout_ms > 0 && read_bytes < 4) { // response is ESC[0n or ESC[3n

View File

@ -4,8 +4,7 @@ cmake_minimum_required(VERSION 3.16)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers")
list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
list(PREPEND SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers" "sdkconfig.defaults")
# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
set(COMPONENTS main)

View File

@ -85,10 +85,16 @@ menu "Driver Configurations"
config SPI_MASTER_ISR_IN_IRAM
bool "Place SPI master ISR function into IRAM"
default y
depends on !HEAP_PLACE_FUNCTION_INTO_FLASH
select PERIPH_CTRL_FUNC_IN_IRAM
select HAL_SPI_MASTER_FUNC_IN_IRAM
help
Place the SPI master ISR in to IRAM to avoid possible cache miss.
Enabling this configuration is possible only when HEAP_PLACE_FUNCTION_INTO_FLASH
is disabled since the spi master uses can allocate transactions buffers into DMA
memory section using the heap component API that ipso facto has to be placed in IRAM.
Also you can forbid the ISR being disabled during flash writing
access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
@ -109,6 +115,7 @@ menu "Driver Configurations"
bool "Place SPI slave ISR function into IRAM"
default y
select PERIPH_CTRL_FUNC_IN_IRAM
select HAL_SPI_SLAVE_FUNC_IN_IRAM
help
Place the SPI slave ISR in to IRAM to avoid possible cache miss.

View File

@ -13,7 +13,7 @@
#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
#endif
#include "freertos/FreeRTOS.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_check.h"
@ -116,8 +116,8 @@ esp_err_t ana_cmpr_new_unit(const ana_cmpr_config_t *config, ana_cmpr_handle_t *
#endif
/* Analog clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well */
ESP_GOTO_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
CLK_TREE_SRC_FREQ_PRECISION_CACHED,
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&s_ana_cmpr[unit]->src_clk_freq_hz),
err, TAG, "get source clock frequency failed");
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(config->clk_src)), err, TAG,
@ -155,14 +155,14 @@ esp_err_t ana_cmpr_del_unit(ana_cmpr_handle_t cmpr)
{
ANA_CMPR_NULL_POINTER_CHECK(cmpr);
/* Search the global object array to check if the input handle is valid */
ana_cmpr_unit_t unit = -1;
int unit = -1;
for (int i = 0; i < SOC_ANA_CMPR_NUM; i++) {
if (s_ana_cmpr[i] == cmpr) {
unit = i;
break;
}
}
ESP_RETURN_ON_FALSE(unit >= ANA_CMPR_UNIT_0, ESP_ERR_INVALID_ARG, TAG, "wrong analog comparator handle");
ESP_RETURN_ON_FALSE(unit != -1, ESP_ERR_INVALID_ARG, TAG, "wrong analog comparator handle");
ESP_RETURN_ON_FALSE(!cmpr->is_enabled, ESP_ERR_INVALID_STATE, TAG, "this analog comparator unit not disabled yet");
/* Delete the pm lock if the unit has */

View File

@ -27,7 +27,7 @@
#include "hal/adc_hal_common.h"
#include "esp_private/periph_ctrl.h"
#include "driver/adc_types_legacy.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#if SOC_DAC_SUPPORTED
#include "hal/dac_types.h"
@ -281,7 +281,7 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -440,7 +440,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -753,7 +753,7 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -823,7 +823,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
if (!clk_src_freq_hz) {
//should never fail
clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
}
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED

View File

@ -61,7 +61,7 @@ typedef enum {
ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */
ADC1_CHANNEL_MAX,
} adc1_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
typedef enum {
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
@ -97,7 +97,7 @@ typedef enum {
ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */
ADC2_CHANNEL_MAX,
} adc2_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
// ESP32C6 has no ADC2
typedef enum {
ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */

View File

@ -19,7 +19,7 @@
#include "driver/mcpwm_types_legacy.h"
#include "driver/gpio.h"
#include "esp_private/periph_ctrl.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "esp_private/esp_clk.h"
static const char *TAG = "mcpwm(legacy)";
@ -225,7 +225,7 @@ esp_err_t mcpwm_group_set_resolution(mcpwm_unit_t mcpwm_num, uint32_t resolution
{
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
uint32_t clk_src_hz = 0;
clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
int pre_scale_temp = clk_src_hz / resolution;
ESP_RETURN_ON_FALSE(pre_scale_temp >= 1, ESP_ERR_INVALID_ARG, TAG, "invalid resolution");
@ -415,7 +415,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
mcpwm_hal_init(hal, &config);
uint32_t clk_src_hz = 0;
clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num);
uint32_t timer_resolution = mcpwm_timer_get_resolution(mcpwm_num, timer_num);
uint32_t group_pre_scale = clk_src_hz / group_resolution;
@ -812,7 +812,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
mcpwm_hal_init(hal, &init_config);
uint32_t clk_src_hz = 0;
clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz);
uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num);
uint32_t group_pre_scale = clk_src_hz / group_resolution;

View File

@ -21,7 +21,7 @@
#include "soc/soc_memory_layout.h"
#include "soc/rmt_periph.h"
#include "soc/rmt_struct.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#include "hal/gpio_hal.h"
@ -567,18 +567,18 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
#if SOC_RMT_SUPPORT_XTAL
// clock src: XTAL_CLK
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_XTAL, 1, 0, 0);
#elif SOC_RMT_SUPPORT_REF_TICK
// clock src: REF_CLK
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_REF, 1, 0, 0);
#else
#error "No clock source is aware of DFS"
#endif
} else {
// fallback to use default clock source
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_DEFAULT, 1, 0, 0);
}
RMT_EXIT_CRITICAL();

View File

@ -15,7 +15,7 @@
#include "hal/timer_ll.h"
#include "hal/check.h"
#include "soc/timer_periph.h"
#include "clk_tree.h"
#include "esp_clk_tree.h"
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
@ -78,8 +78,8 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
uint32_t div = p_timer_obj[group_num][timer_num]->divider;
// get clock source frequency
uint32_t counter_src_hz = 0;
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
TIMER_TAG, "get clock source frequency failed");
*time = (double)timer_val * div / counter_src_hz;
return ESP_OK;

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