set_server_config() set ssl authmode to OPTIONAL

add function to start spi transaction from isr
fix(esp-tls): Remove useless const from size paramter
2025-03-20 19:34:44 +01:00 · 2025-01-27 15:53:27 +01:00 · 2024-11-19 14:11:07 +01:00 · 2024-07-16 11:20:15 +02:00 · 2024-06-17 13:05:52 +02:00 · 2024-06-17 11:35:51 +02:00
4772 changed files with 448717 additions and 70475 deletions
--- a/.codespellrc
+++ b/.codespellrc
@@ -0,0 +1,4 @@
+[codespell]
+skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart
+write-changes = true
--- a/.gitignore
+++ b/.gitignore
@@ -24,18 +24,6 @@ GPATH
 # cache dir
 .cache/

-# Components Unit Test Apps files
-components/**/build/
-components/**/build_*_*/
-components/**/sdkconfig
-components/**/sdkconfig.old
-
-# Example project files
-examples/**/build/
-examples/**/build_esp*_*/
-examples/**/sdkconfig
-examples/**/sdkconfig.old
-
 # Doc build artifacts
 docs/_build/
 docs/doxygen_sqlite3.db
@@ -44,16 +32,23 @@ docs/doxygen_sqlite3.db
 docs/_static/DejaVuSans.ttf
 docs/_static/NotoSansSC-Regular.otf

+# Components Unit Test Apps files
+components/**/build/
+components/**/build_*_*/
+components/**/sdkconfig
+components/**/sdkconfig.old
+
+# Example project files
+examples/**/build/
+examples/**/build_*_*/
+examples/**/sdkconfig
+examples/**/sdkconfig.old
+
 # Unit test app files
-tools/unit-test-app/sdkconfig
-tools/unit-test-app/sdkconfig.old
 tools/unit-test-app/build
 tools/unit-test-app/build_*_*/
-tools/unit-test-app/output
-tools/unit-test-app/test_configs
-
-# Unit Test CMake compile log folder
-log_ut_cmake
+tools/unit-test-app/sdkconfig
+tools/unit-test-app/sdkconfig.old

 # test application build files
 tools/test_apps/**/build/
@@ -61,7 +56,8 @@ tools/test_apps/**/build_*_*/
 tools/test_apps/**/sdkconfig
 tools/test_apps/**/sdkconfig.old

-TEST_LOGS
+TEST_LOGS/
+build_summary_*.xml

 # gcov coverage reports
 *.gcda
@@ -101,8 +97,9 @@ managed_components

 # pytest log
 pytest_embedded_log/
-list_job_*.txt
-size_info.txt
+list_job*.txt
+size_info*.txt
+XUNIT_RESULT*.xml

 # clang config (for LSP)
 .clangd
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -24,9 +24,10 @@ include:
  - '.gitlab/ci/upload_cache.yml'
  - '.gitlab/ci/docs.yml'
  - '.gitlab/ci/static-code-analysis.yml'
+  - '.gitlab/ci/pre_commit.yml'
  - '.gitlab/ci/pre_check.yml'
  - '.gitlab/ci/build.yml'
  - '.gitlab/ci/integration_test.yml'
  - '.gitlab/ci/host-test.yml'
-  - '.gitlab/ci/target-test.yml'
  - '.gitlab/ci/deploy.yml'
+  - '.gitlab/ci/test-win.yml'
--- a/.gitlab/CODEOWNERS
+++ b/.gitlab/CODEOWNERS
@@ -47,6 +47,7 @@
 * @esp-idf-codeowners/other

 /.*                                   @esp-idf-codeowners/tools
+/.codespellrc                         @esp-idf-codeowners/ci
 /.github/workflows/                   @esp-idf-codeowners/ci
 /.gitlab-ci.yml                       @esp-idf-codeowners/ci
 /.gitlab/ci/                          @esp-idf-codeowners/ci
@@ -95,6 +96,7 @@
 /components/esp_https_ota/            @esp-idf-codeowners/app-utilities
 /components/esp_https_server/         @esp-idf-codeowners/app-utilities
 /components/esp_hw_support/           @esp-idf-codeowners/system @esp-idf-codeowners/peripherals
+/components/esp_hw_support/lowpower/  @esp-idf-codeowners/power-management
 /components/esp_lcd/                  @esp-idf-codeowners/peripherals
 /components/esp_local_ctrl/           @esp-idf-codeowners/app-utilities
 /components/esp_mm/                   @esp-idf-codeowners/peripherals
@@ -109,11 +111,12 @@
 /components/esp_system/               @esp-idf-codeowners/system
 /components/esp_timer/                @esp-idf-codeowners/system
 /components/esp-tls/                  @esp-idf-codeowners/app-utilities
+/components/esp_vfs_*/                @esp-idf-codeowners/storage
+/components/esp_vfs_console/          @esp-idf-codeowners/storage @esp-idf-codeowners/system
 /components/esp_wifi/                 @esp-idf-codeowners/wifi
 /components/espcoredump/              @esp-idf-codeowners/debugging
 /components/esptool_py/               @esp-idf-codeowners/tools
 /components/fatfs/                    @esp-idf-codeowners/storage
-/components/fatfs/**/*.py             @esp-idf-codeowners/tools
 /components/freertos/                 @esp-idf-codeowners/system
 /components/hal/                      @esp-idf-codeowners/peripherals
 /components/heap/                     @esp-idf-codeowners/system
@@ -152,6 +155,7 @@
 /components/xtensa/                   @esp-idf-codeowners/system

 /docs/                                   @esp-idf-codeowners/docs
+/docs/**/api-guides/tools/               @esp-idf-codeowners/tools
 /docs/en/api-guides/jtag-debugging/      @esp-idf-codeowners/debugging
 /docs/**/api-reference/bluetooth/        @esp-idf-codeowners/bluetooth
 /docs/**/api-reference/network/          @esp-idf-codeowners/network @esp-idf-codeowners/wifi
--- a/.gitlab/ci/build.yml
+++ b/.gitlab/ci/build.yml
@@ -1,7 +1,7 @@
 .build_template:
  stage: build
  extends:
-    - .after_script:build:ccache
+    - .after_script:build:ccache:upload-when-fail
  image: $ESP_ENV_IMAGE
  tags:
    - build
@@ -32,8 +32,8 @@
      # keep the size info to help track the binary size
      - size_info.txt
      - "**/build*/size.json"
+    expire_in: 1 week
    when: always
-    expire_in: 4 days
  script:
    # CI specific options start from "--parallel-count xxx". could ignore when running locally
    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
@@ -45,8 +45,8 @@
        examples/bluetooth/esp_ble_mesh/ble_mesh_console
        examples/bluetooth/hci/controller_hci_uart_esp32
        examples/wifi/iperf
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
+      --modified-components ${MR_MODIFIED_COMPONENTS}
+      --modified-files ${MR_MODIFIED_FILES}
    # for detailed documents, please refer to .gitlab/ci/README.md#uploaddownload-artifacts-to-internal-minio-server
    - python tools/ci/artifacts_handler.py upload

@@ -64,307 +64,14 @@
      --copy-sdkconfig
      --parallel-count ${CI_NODE_TOTAL:-1}
      --parallel-index ${CI_NODE_INDEX:-1}
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
+      --modified-components ${MR_MODIFIED_COMPONENTS}
+      --modified-files ${MR_MODIFIED_FILES}
      $TEST_BUILD_OPTS_EXTRA
    - python tools/ci/artifacts_handler.py upload

-.build_pytest_template:
-  extends:
-    - .build_cmake_template
-  script:
-    # CI specific options start from "--parallel-count xxx". could ignore when running locally
-    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
-      -t $IDF_TARGET
-      -m \"not host_test\"
-      --pytest-apps
-      --parallel-count ${CI_NODE_TOTAL:-1}
-      --parallel-index ${CI_NODE_INDEX:-1}
-      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - python tools/ci/artifacts_handler.py upload
-
-.build_pytest_no_jtag_template:
-  extends:
-    - .build_cmake_template
-  script:
-    # CI specific options start from "--parallel-count xxx". could ignore when running locally
-    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
-      -t $IDF_TARGET
-      -m \"not host_test and not jtag\"
-      --pytest-apps
-      --parallel-count ${CI_NODE_TOTAL:-1}
-      --parallel-index ${CI_NODE_INDEX:-1}
-      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - python tools/ci/artifacts_handler.py upload
-
-.build_pytest_jtag_template:
-  extends:
-    - .build_cmake_template
-  script:
-    # CI specific options start from "--parallel-count xxx". could ignore when running locally
-    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
-      -t $IDF_TARGET
-      -m \"not host_test and jtag\"
-      --pytest-apps
-      --parallel-count ${CI_NODE_TOTAL:-1}
-      --parallel-index ${CI_NODE_INDEX:-1}
-      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - python tools/ci/artifacts_handler.py upload
-
-build_pytest_examples_esp32:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32
-  parallel: 6
-  variables:
-    IDF_TARGET: esp32
-    TEST_DIR: examples
-
-build_pytest_examples_esp32s2:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32s2
-  parallel: 3
-  variables:
-    IDF_TARGET: esp32s2
-    TEST_DIR: examples
-
-build_pytest_examples_esp32s3:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32s3
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32s3
-    TEST_DIR: examples
-
-build_pytest_examples_esp32c3:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32c3
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32c3
-    TEST_DIR: examples
-
-build_pytest_examples_esp32c2:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32c2
-  parallel: 2
-  variables:
-    IDF_TARGET: esp32c2
-    TEST_DIR: examples
-
-build_pytest_examples_esp32c6:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32c6
-  parallel: 2
-  variables:
-    IDF_TARGET: esp32c6
-    TEST_DIR: examples
-
-build_pytest_examples_esp32h2:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32h2
-  parallel: 2
-  variables:
-    IDF_TARGET: esp32h2
-    TEST_DIR: examples
-
-build_pytest_examples_esp32p4:
-  extends:
-    - .build_pytest_no_jtag_template
-    - .rules:build:example_test-esp32p4
-  parallel: 2
-  variables:
-    IDF_TARGET: esp32p4
-    TEST_DIR: examples
-
-build_pytest_examples_jtag:  # for all targets
-  extends:
-    - .build_pytest_jtag_template
-    - .rules:build:example_test
-  variables:
-    IDF_TARGET: all
-    TEST_DIR: examples
-
-build_pytest_components_esp32:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32
-  parallel: 5
-  variables:
-    IDF_TARGET: esp32
-    TEST_DIR: components
-
-build_pytest_components_esp32s2:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32s2
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32s2
-    TEST_DIR: components
-
-build_pytest_components_esp32s3:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32s3
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32s3
-    TEST_DIR: components
-
-build_pytest_components_esp32c3:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32c3
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32c3
-    TEST_DIR: components
-
-build_pytest_components_esp32c2:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32c2
-  parallel: 3
-  variables:
-    IDF_TARGET: esp32c2
-    TEST_DIR: components
-
-build_pytest_components_esp32c6:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32c6
-  parallel: 3
-  variables:
-    IDF_TARGET: esp32c6
-    TEST_DIR: components
-
-build_pytest_components_esp32h2:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32h2
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32h2
-    TEST_DIR: components
-
-build_pytest_components_esp32p4:
-  extends:
-    - .build_pytest_template
-    - .rules:build:component_ut-esp32p4
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32p4
-    TEST_DIR: components
-
-build_only_components_apps:
-  extends:
-    - .build_cmake_template
-    - .rules:build:component_ut
-  parallel: 5
-  script:
-    - set_component_ut_vars
-    # CI specific options start from "--parallel-count xxx". could ignore when running locally
-    - run_cmd python tools/ci/ci_build_apps.py $COMPONENT_UT_DIRS -v
-      -t all
-      --parallel-count ${CI_NODE_TOTAL:-1}
-      --parallel-index ${CI_NODE_INDEX:-1}
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - python tools/ci/artifacts_handler.py upload
-
-build_pytest_test_apps_esp32:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32
-  variables:
-    IDF_TARGET: esp32
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32s2:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32s2
-  variables:
-    IDF_TARGET: esp32s2
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32s3:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32s3
-  parallel: 2
-  variables:
-    IDF_TARGET: esp32s3
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32c3:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32c3
-  variables:
-    IDF_TARGET: esp32c3
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32c2:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32c2
-  variables:
-    IDF_TARGET: esp32c2
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32c6:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32c6
-  variables:
-    IDF_TARGET: esp32c6
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32h2:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32h2
-  variables:
-    IDF_TARGET: esp32h2
-    TEST_DIR: tools/test_apps
-
-build_pytest_test_apps_esp32p4:
-  extends:
-    - .build_pytest_template
-    - .rules:build:custom_test-esp32p4
-  variables:
-    IDF_TARGET: esp32p4
-    TEST_DIR: tools/test_apps
-
-build_only_tools_test_apps:
-  extends:
-    - .build_cmake_template
-    - .rules:build:custom_test
-  parallel: 9
-  script:
-    # CI specific options start from "--parallel-count xxx". could ignore when running locally
-    - run_cmd python tools/ci/ci_build_apps.py tools/test_apps -v
-      -t all
-      --parallel-count ${CI_NODE_TOTAL:-1}
-      --parallel-index ${CI_NODE_INDEX:-1}
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - python tools/ci/artifacts_handler.py upload
-
+######################
+# build_template_app #
+######################
 .build_template_app_template:
  extends:
    - .build_template
@@ -376,12 +83,12 @@ build_only_tools_test_apps:
    BUILD_LOG_CMAKE: "${LOG_PATH}/cmake_@t_@w.txt"
    BUILD_COMMAND_ARGS: ""
  artifacts:
-    when: always
    paths:
      - log_template_app/*
      - size_info.txt
      - build_template_app/**/size.json
    expire_in: 1 week
+    when: always
  script:
    # Set the variable for 'esp-idf-template' testing
    - ESP_IDF_TEMPLATE_GIT=${ESP_IDF_TEMPLATE_GIT:-"https://github.com/espressif/esp-idf-template.git"}
@@ -400,100 +107,32 @@ fast_template_app:
    - .build_template_app_template
    - .rules:build:target_test
  stage: pre_check
+  tags: [fast_run, shiny]
  variables:
    BUILD_COMMAND_ARGS: "-p"
 #------------------------------------------------------------------------------

-build_examples_cmake_esp32:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32
-  parallel: 8
-  variables:
-    IDF_TARGET: esp32
-    TEST_DIR: examples
-
-build_examples_cmake_esp32s2:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32s2
-  parallel: 7
-  variables:
-    IDF_TARGET: esp32s2
-    TEST_DIR: examples
-
-build_examples_cmake_esp32s3:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32s3
-  parallel: 11
-  variables:
-    IDF_TARGET: esp32s3
-    TEST_DIR: examples
-
-build_examples_cmake_esp32c2:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32c2
-  parallel: 7
-  variables:
-    IDF_TARGET: esp32c2
-    TEST_DIR: examples
-
-build_examples_cmake_esp32c3:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32c3
-  parallel: 9
-  variables:
-    IDF_TARGET: esp32c3
-    TEST_DIR: examples
-
-build_examples_cmake_esp32c6:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32c6
-  parallel: 11
-  variables:
-    IDF_TARGET: esp32c6
-    TEST_DIR: examples
-
-build_examples_cmake_esp32h2:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32h2
-  parallel: 9
-  variables:
-    IDF_TARGET: esp32h2
-    TEST_DIR: examples
-
-build_examples_cmake_esp32p4:
-  extends:
-    - .build_cmake_template
-    - .rules:build:example_test-esp32p4
-  parallel: 4
-  variables:
-    IDF_TARGET: esp32p4
-    TEST_DIR: examples
-
+########################################
+# Clang Build Apps Without Tests Cases #
+########################################
 build_clang_test_apps_esp32:
  extends:
    - .build_cmake_clang_template
-    - .rules:build:custom_test-esp32
+    - .rules:build
  variables:
    IDF_TARGET: esp32

 build_clang_test_apps_esp32s2:
  extends:
    - .build_cmake_clang_template
-    - .rules:build:custom_test-esp32s2
+    - .rules:build
  variables:
    IDF_TARGET: esp32s2

 build_clang_test_apps_esp32s3:
  extends:
    - .build_cmake_clang_template
-    - .rules:build:custom_test-esp32s3
+    - .rules:build
  variables:
    IDF_TARGET: esp32s3

@@ -510,54 +149,58 @@ build_clang_test_apps_esp32s3:
 build_clang_test_apps_esp32c3:
  extends:
    - .build_clang_test_apps_riscv
-    - .rules:build:custom_test-esp32c3
+    - .rules:build
  variables:
    IDF_TARGET: esp32c3

 build_clang_test_apps_esp32c2:
  extends:
    - .build_clang_test_apps_riscv
-    - .rules:build:custom_test-esp32c2
+    - .rules:build
  variables:
    IDF_TARGET: esp32c2

 build_clang_test_apps_esp32c6:
  extends:
    - .build_clang_test_apps_riscv
-    - .rules:build:custom_test-esp32c6
+    - .rules:build
  # TODO: c6 builds fail in master due to missing headers
  allow_failure: true
  variables:
    IDF_TARGET: esp32c6

+######################
+# Build System Tests #
+######################
 .test_build_system_template:
  stage: host_test
  extends:
    - .build_template
    - .rules:build:check
+  dependencies: # set dependencies to null to avoid missing artifacts issue
  needs:
    - job: fast_template_app
      artifacts: false
      optional: true
+  artifacts:
+    reports:
+      junit: XUNIT_RESULT.xml
+    paths:
+      - XUNIT_RESULT.xml
+      - test_build_system
+    expire_in: 1 week
+    when: always
  script:
    - ${IDF_PATH}/tools/ci/test_configure_ci_environment.sh
    - cd ${IDF_PATH}/tools/test_build_system
-    - retry_failed git clone $KNOWN_FAILURE_CASES_REPO known_failure_cases
+    - python ${IDF_PATH}/tools/ci/get_known_failure_cases_file.py
    - pytest --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1}
      --work-dir ${CI_PROJECT_DIR}/test_build_system --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
-      --ignore-result-files known_failure_cases/known_failure_cases.txt
+      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}

 pytest_build_system:
  extends: .test_build_system_template
  parallel: 3
-  artifacts:
-    paths:
-      - XUNIT_RESULT.xml
-      - test_build_system
-    when: always
-    expire_in: 2 days
-    reports:
-      junit: XUNIT_RESULT.xml

 pytest_build_system_macos:
  extends:
@@ -567,46 +210,7 @@ pytest_build_system_macos:
  tags:
    - macos_shell
  parallel: 3
-  artifacts:
-    paths:
-      - XUNIT_RESULT.xml
-      - test_build_system
-    when: always
-    expire_in: 2 days
-    reports:
-      junit: XUNIT_RESULT.xml
-
-.test_build_system_template_win:
-  stage: host_test
-  variables:
-  # Enable ccache for all build jobs. See configure_ci_environment.sh for more ccache related settings.
-    IDF_CCACHE_ENABLE: "1"
-    PYTHONPATH: "$PYTHONPATH;$IDF_PATH\\tools;$IDF_PATH\\tools\\esp_app_trace;$IDF_PATH\\components\\partition_table;$IDF_PATH\\tools\\ci\\python_packages"
-  before_script: []
-  after_script: []
-  timeout: 4 hours
-  script:
-    - .\install.ps1 --enable-ci --enable-pytest
-    - . .\export.ps1
-    - python "${SUBMODULE_FETCH_TOOL}" -s "all"
-    - cd ${IDF_PATH}\tools\test_build_system
-    - pytest --junitxml=${CI_PROJECT_DIR}\XUNIT_RESULT.xml
-
-pytest_build_system_win:
-  extends:
-    - .test_build_system_template_win
-    - .rules:labels:windows_pytest_build_system
-  needs: []
-  tags:
-    - windows-target
-  artifacts:
-    paths:
-      - XUNIT_RESULT.xml
-      - test_build_system
-    when: always
-    expire_in: 2 days
-    reports:
-      junit: XUNIT_RESULT.xml
+  allow_failure: true  # IDFCI-2107

 build_docker:
  extends:
@@ -638,6 +242,51 @@ build_template_app:
    - .build_template_app_template
    - .rules:build
  stage: host_test
+  dependencies: # set dependencies to null to avoid missing artifacts issue
  needs:
    - job: fast_template_app
      artifacts: false
+
+####################
+# Dynamic Pipeline #
+####################
+generate_build_child_pipeline:
+  extends:
+    - .build_template
+  tags: [fast_run, shiny]
+  dependencies: # set dependencies to null to avoid missing artifacts issue
+  needs:
+    - pipeline_variables
+    - check_test_cases_env_markers_and_required_runners
+  artifacts:
+    paths:
+      - build_child_pipeline.yml
+      - test_related_apps.txt
+      - non_test_related_apps.txt
+    expire_in: 1 week
+    when: always
+  script:
+    - run_cmd python tools/ci/dynamic_pipelines/scripts/generate_build_child_pipeline.py
+
+build_child_pipeline:
+  stage: build
+  needs:
+    - job: fast_template_app
+      optional: true
+      artifacts: false
+    - pipeline_variables
+    - generate_build_child_pipeline
+  variables:
+    IS_MR_PIPELINE: $IS_MR_PIPELINE
+    MR_MODIFIED_COMPONENTS: $MR_MODIFIED_COMPONENTS
+    MR_MODIFIED_FILES: $MR_MODIFIED_FILES
+    PARENT_PIPELINE_ID: $CI_PIPELINE_ID
+    BUILD_AND_TEST_ALL_APPS: $BUILD_AND_TEST_ALL_APPS
+  # https://gitlab.com/gitlab-org/gitlab/-/issues/214340
+  inherit:
+    variables: false
+  trigger:
+    include:
+      - artifact: build_child_pipeline.yml
+        job: generate_build_child_pipeline
+    strategy: depend
--- a/.gitlab/ci/common.yml
+++ b/.gitlab/ci/common.yml
@@ -20,8 +20,14 @@ variables:
  MAKEFLAGS: "-j5 --no-keep-going"

 # GitLab-CI environment
-
-  # now we have pack-objects cache, so clone strategy is faster than fetch
+  # Thanks to pack-objects cache, clone strategy should behave faster than fetch
+  #   so we pick "clone" as default git strategy
+  # Shiny runners by default remove the CI_PROJECT_DIR every time at the beginning of one job
+  #   and clone with a --depth=1
+  # Brew runners will fetch from locally mirror first, and cache the local CI_PROJECT_DIR
+  # In conclusion
+  # - set GIT_STRATEGY: "clone" to shiny runners
+  # - set GIT_STRATEGY: "fetch" to brew runners
  GIT_STRATEGY: clone
  # we will download archive for each submodule instead of clone.
  # we don't do "recursive" when fetch submodule as they're not used in CI now.
@@ -78,13 +84,25 @@ variables:
  # This is used only if CI_PYTHON_TOOL_REPO is not empty.
  CI_PYTHON_TOOL_BRANCH: ""

+  # Set this variable to specify the file name for the known failure cases.
+  KNOWN_FAILURE_CASES_FILE_NAME: "master.txt"
+
  IDF_CI_BUILD: 1

+  # ccache settings
+  # some settings need to set in .gitlab-ci.yml as it takes effect while start-up the job
+  # https://ccache.dev/manual/latest.html#_configuring_ccache
+
+  # host mapping volume to share ccache between runner concurrent jobs
+  CCACHE_DIR: "/cache/idf_ccache"
+  CCACHE_MAXSIZE: "50G"
+
 ################################################
 # `before_script` and `after_script` Templates #
 ################################################
 .common_before_scripts: &common-before_scripts |
  source tools/ci/utils.sh
+
  is_based_on_commits $REQUIRED_ANCESTOR_COMMITS

  if [[ -n "$IDF_DONT_USE_MIRRORS" ]]; then
@@ -177,7 +195,7 @@ variables:

 .show_ccache_statistics: &show_ccache_statistics |
  # Show ccache statistics if enabled globally
-  test "$CI_CCACHE_STATS" == 1 && test -n "$(which ccache)" && ccache --show-stats || true
+  test "$CI_CCACHE_STATS" == 1 && test -n "$(which ccache)" && ccache --show-stats -vv || true

 .upload_failed_job_log_artifacts: &upload_failed_job_log_artifacts |
  if [ $CI_JOB_STATUS = "failed" ]; then
@@ -208,6 +226,10 @@ variables:
    - export EXTRA_CXXFLAGS=${PEDANTIC_CXXFLAGS}

 .after_script:build:ccache:
+  after_script:
+    - *show_ccache_statistics
+
+.after_script:build:ccache:upload-when-fail:
  after_script:
    - *show_ccache_statistics
    - *upload_failed_job_log_artifacts
@@ -291,22 +313,6 @@ variables:
    - *setup_tools_and_idf_python_venv
    - add_gitlab_ssh_keys

-# git describe requires commit history until the latest tag
-.before_script:fetch:git_describe:
-  variables:
-    GIT_STRAEGY: none
-  before_script:
-    - *git_init
-    - *git_fetch_from_mirror_url_if_exists
-    - |
-      git fetch origin refs/tags/"${LATEST_GIT_TAG}":refs/tags/"${LATEST_GIT_TAG}" --depth=1
-      git repack -d
-      git fetch origin $CI_COMMIT_SHA --shallow-since=$(git log -1 --format=%as "${LATEST_GIT_TAG}")
-    - *git_checkout_fetch_head
-    - *common-before_scripts
-    - *setup_tools_and_idf_python_venv
-    - add_gitlab_ssh_keys
-
 # target test runners may locate in different places
 # for runners set git mirror, we fetch from the mirror first, then fetch the HEAD commit
 .before_script:fetch:target_test:
@@ -346,6 +352,12 @@ default:
    - *setup_tools_and_idf_python_venv
    - add_gitlab_ssh_keys
    - fetch_submodules
+# gitlab bug, setting them here doesn't work
+# - expire_in: https://gitlab.com/gitlab-org/gitlab/-/issues/404563
+# - when: https://gitlab.com/gitlab-org/gitlab/-/issues/440672
+#  artifacts:
+#    expire_in: 1 week
+#    when: always
  retry:
    max: 2
    when:
--- a/.gitlab/ci/default-build-test-rules.yml
+++ b/.gitlab/ci/default-build-test-rules.yml
@@ -7,10 +7,12 @@
 #
 # This file should ONLY be used during bringup. Should be reset to empty after the bringup process
 extra_default_build_targets:
- - esp32p4
+  - esp32p4
+  - esp32c5

-# bypass_check_test_targets:
-#  - esp32p4
+bypass_check_test_targets:
+  - esp32c5
+  - esp32c61
 #
 # These lines would
 # - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
--- a/.gitlab/ci/dependencies/dependencies.yml
+++ b/.gitlab/ci/dependencies/dependencies.yml
@@ -5,6 +5,7 @@
  - esp32c3
  - esp32c2
  - esp32c6
+  - esp32c5
  - esp32h2
  - esp32p4

@@ -65,104 +66,6 @@
  included_in:
    - build:check

-# ---------------
-# Build Test Jobs
-# ---------------
-"build:{0}-{1}":
-  matrix:
-    - *target_test
-    - *all_targets
-  labels:
-    - build
-  patterns:
-    - build_components
-    - build_system
-    - build_target_test
-    - downloadable-tools
-  included_in:
-    - "build:{0}"
-    - build:target_test
-
-####################
-# Target Test Jobs #
-####################
-"test:{0}-{1}":
-  matrix:
-    - *target_test
-    - *all_targets
-  labels: # For each rule, use labels <test_type> and <test_type>-<target>
-    - "{0}"
-    - "{0}_{1}"
-    - target_test
-  patterns: # For each rule, use patterns <test_type> and build-<test_type>
-    - "{0}"
-    - "build-{0}"
-  included_in: # Parent rules
-    - "build:{0}"
-    - "build:{0}-{1}"
-    - build:target_test
-
-# -------------
-# Special Cases
-# -------------
-
-# To reduce the specific runners' usage.
-# Do not create these jobs by default patterns on development branches
-# Can be triggered by labels or related changes
-"test:{0}-{1}-{2}":
-  matrix:
-    - *target_test
-    - *all_targets
-    - - wifi      # pytest*wifi*
-      - ethernet  # pytest*ethernet*
-      - sdio      # pytest*sdio*
-      - usb       # USB Device & Host tests
-      - adc       # pytest*adc*
-      - i154
-      - flash_multi
-      - ecdsa
-      - nvs_encr_hmac
-  patterns:
-    - "{0}-{1}-{2}"
-    - "{0}-{2}"
-    - "target_test-{2}"
-  labels:
-    - "{0}_{1}"
-    - "{0}"
-    - target_test
-  included_in:
-    - "build:{0}-{1}"
-    - "build:{0}"
-    - build:target_test
-
-# For example_test*flash_encryption_wifi_high_traffic jobs
-# set `INCLUDE_NIGHTLY_RUN` variable when triggered on development branches
-"test:example_test-{0}-include_nightly_run-rule":
-  matrix:
-    - - esp32
-      - esp32c3
-  specific_rules:
-    - "if-example_test-ota-include_nightly_run-rule"
-  included_in:
-    - "build:example_test-{0}"
-    - "build:example_test"
-    - build:target_test
-
-# For i154 runners
-"test:example_test-i154":
-  patterns:
-    - "example_test-i154"
-    - "target_test-i154"
-  labels:
-    - target_test
-    - example_test
-  included_in:
-    - "build:example_test-esp32s3"
-    - "build:example_test-esp32c6"
-    - "build:example_test-esp32h2"
-    - "build:example_test"
-    - build:target_test
-
 "test:host_test":
  labels:
    - host_test
--- a/.gitlab/ci/docs.yml
+++ b/.gitlab/ci/docs.yml
@@ -96,6 +96,9 @@ check_docs_lang_sync:
    - if [ -n "${BREATHE_ALT_INSTALL_URL}" ]; then pip uninstall -y breathe && pip install -U ${BREATHE_ALT_INSTALL_URL}; fi
    - cd docs
    - build-docs -t $DOCTGT -bs $DOC_BUILDERS -l $DOCLANG build
+  artifacts:
+    expire_in: 4 days
+    when: always
  parallel:
    matrix:
      - DOCLANG: ["en", "zh_CN"]
@@ -121,11 +124,9 @@ build_docs_html_full:
      artifacts: false
      optional: true
  artifacts:
-    when: always
    paths:
      - docs/_build/*/*/*.txt
      - docs/_build/*/*/html/*
-    expire_in: 4 days
  variables:
    DOC_BUILDERS: "html"

@@ -135,11 +136,9 @@ build_docs_html_full_prod:
    - .doc-rules:build:docs-full-prod
  dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts
  artifacts:
-    when: always
    paths:
      - docs/_build/*/*/*.txt
      - docs/_build/*/*/html/*
-    expire_in: 4 days
  variables:
    DOC_BUILDERS: "html"

@@ -152,11 +151,9 @@ build_docs_html_partial:
      artifacts: false
      optional: true
  artifacts:
-    when: always
    paths:
      - docs/_build/*/*/*.txt
      - docs/_build/*/*/html/*
-    expire_in: 4 days
  variables:
    DOC_BUILDERS: "html"
  parallel:
@@ -175,10 +172,8 @@ build_docs_pdf:
      artifacts: false
      optional: true
  artifacts:
-    when: always
    paths:
      - docs/_build/*/*/latex/*
-    expire_in: 4 days
  variables:
    DOC_BUILDERS: "latex"

@@ -188,10 +183,8 @@ build_docs_pdf_prod:
    - .doc-rules:build:docs-full-prod
  dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts
  artifacts:
-    when: always
    paths:
      - docs/_build/*/*/latex/*
-    expire_in: 4 days
  variables:
    DOC_BUILDERS: "latex"

@@ -266,11 +259,9 @@ check_doc_links:
      artifacts: false
  tags: ["build", "amd64", "internet"]
  artifacts:
-    when: always
    paths:
      - docs/_build/*/*/*.txt
      - docs/_build/*/*/linkcheck/*.txt
-    expire_in: 1 week
  allow_failure: true
  script:
    - cd docs
--- a/.gitlab/ci/host-test.yml
+++ b/.gitlab/ci/host-test.yml
@@ -14,6 +14,25 @@
      optional: true
      artifacts: false
    - pipeline_variables
+  artifacts:
+    expire_in: 1 week
+    when: always
+
+check_public_headers:
+  extends:
+    - .host_test_template
+    - .rules:build:check
+  script:
+    - IDF_TARGET=esp32 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32-elf-
+    - IDF_TARGET=esp32s2 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32s2-elf-
+    - IDF_TARGET=esp32s3 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32s3-elf-
+    - IDF_TARGET=esp32c3 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32c2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32c6 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32c5 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32h2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32p4 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32c61 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-

 test_nvs_on_host:
  extends: .host_test_template
@@ -28,7 +47,6 @@ test_nvs_coverage:
  artifacts:
    paths:
      - components/nvs_flash/test_nvs_host/coverage_report
-    expire_in: 1 week
  script:
    - cd components/nvs_flash/test_nvs_host
    - make coverage_report
@@ -65,7 +83,6 @@ test_reproducible_build:
      - "**/build*/*.bin"
      - "**/build*/bootloader/*.bin"
      - "**/build*/partition_table/*.bin"
-    expire_in: 1 week

 test_spiffs_on_host:
  extends: .host_test_template
@@ -110,17 +127,19 @@ test_cli_installer:
    paths:
      - tools/tools.new.json
      - tools/test_idf_tools/test_python_env_logs.txt
-    expire_in: 1 week
  image:
    name: $ESP_ENV_IMAGE
    entrypoint: [""]  # use system python3. no extra pip package installed
  script:
    # Tools must be downloaded for testing
+    # We could use "idf_tools.py download all", but we don't want to install clang because of its huge size
    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa
    - cd ${IDF_PATH}/tools/test_idf_tools
    - python3 -m pip install jsonschema
    - python3 ./test_idf_tools.py -v
    - python3 ./test_idf_tools_python_env.py
+    # It runs at the end because it modifies dependencies
+    - IDF_TEST_MAY_BREAK_DEPENDENCIES=1 python3 ./test_idf_tools.py -v TestSystemDependencies.test_commands_when_nodeps

 .test_efuse_table_on_host_template:
  extends: .host_test_template
@@ -130,7 +149,6 @@ test_cli_installer:
    when: on_failure
    paths:
      - components/efuse/${IDF_TARGET}/esp_efuse_table.c
-    expire_in: 1 week
  script:
    - cd ${IDF_PATH}/components/efuse/
    - ./efuse_table_gen.py -t "${IDF_TARGET}" ${IDF_PATH}/components/efuse/${IDF_TARGET}/esp_efuse_table.csv
@@ -173,7 +191,6 @@ test_logtrace_proc:
    paths:
      - tools/esp_app_trace/test/logtrace/output
      - tools/esp_app_trace/test/logtrace/.coverage
-    expire_in: 1 week
  script:
    - cd ${IDF_PATH}/tools/esp_app_trace/test/logtrace
    - ./test.sh
@@ -185,7 +202,6 @@ test_sysviewtrace_proc:
    paths:
      - tools/esp_app_trace/test/sysview/output
      - tools/esp_app_trace/test/sysview/.coverage
-    expire_in: 1 week
  script:
    - cd ${IDF_PATH}/tools/esp_app_trace/test/sysview
    - ./test.sh
@@ -194,13 +210,11 @@ test_tools:
  extends:
    - .host_test_template
  artifacts:
-    when: always
    paths:
      - ${IDF_PATH}/*.out
      - ${IDF_PATH}/XUNIT_*.xml
    reports:
      junit: ${IDF_PATH}/XUNIT_*.xml
-    expire_in: 1 week
  variables:
    LC_ALL: C.UTF-8
    INSTALL_QEMU: 1  # for test_idf_qemu.py
@@ -280,13 +294,11 @@ test_pytest_qemu:
    - .host_test_template
    - .before_script:build
  artifacts:
-    when: always
    paths:
      - XUNIT_RESULT.xml
      - pytest_embedded_log/
    reports:
      junit: XUNIT_RESULT.xml
-    expire_in: 1 week
  allow_failure: true # IDFCI-1752
  parallel:
    matrix:
@@ -299,15 +311,15 @@ test_pytest_qemu:
      --pytest-apps
      -m qemu
      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - retry_failed git clone $KNOWN_FAILURE_CASES_REPO known_failure_cases
+      --modified-components ${MR_MODIFIED_COMPONENTS}
+      --modified-files ${MR_MODIFIED_FILES}
+    - python tools/ci/get_known_failure_cases_file.py
    - run_cmd pytest
      --target $IDF_TARGET
      -m qemu
      --embedded-services idf,qemu
      --junitxml=XUNIT_RESULT.xml
-      --ignore-result-files known_failure_cases/known_failure_cases.txt
+      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
      --app-info-filepattern \"list_job_*.txt\"
      --qemu-extra-args \"-global driver=timer.$IDF_TARGET.timg,property=wdt_disable,value=true\"

@@ -316,26 +328,37 @@ test_pytest_linux:
    - .host_test_template
    - .before_script:build
  artifacts:
-    when: always
    paths:
      - XUNIT_RESULT.xml
      - pytest_embedded_log/
      - "**/build*/build_log.txt"
    reports:
      junit: XUNIT_RESULT.xml
-    expire_in: 1 week
  script:
    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -vv
      --target linux
      --pytest-apps
      -m host_test
      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
-      --modified-components ${MODIFIED_COMPONENTS}
-      --modified-files ${MODIFIED_FILES}
-    - retry_failed git clone $KNOWN_FAILURE_CASES_REPO known_failure_cases
+      --modified-components ${MR_MODIFIED_COMPONENTS}
+      --modified-files ${MR_MODIFIED_FILES}
+    - python tools/ci/get_known_failure_cases_file.py
    - run_cmd pytest
      --target linux
      -m host_test
      --junitxml=XUNIT_RESULT.xml
-      --ignore-result-files known_failure_cases/known_failure_cases.txt
+      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
      --app-info-filepattern \"list_job_*.txt\"
+
+test_idf_pytest_plugin:
+  extends:
+    - .host_test_template
+    - .rules:patterns:idf-pytest-plugin
+  variables:
+    SUBMODULES_TO_FETCH: "none"
+  artifacts:
+    reports:
+      junit: XUNIT_RESULT.xml
+  script:
+    - cd tools/ci/idf_pytest
+    - pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
--- a/.gitlab/ci/integration_test.yml
+++ b/.gitlab/ci/integration_test.yml
@@ -34,8 +34,7 @@ gen_integration_pipeline:
  image: ${CI_INTEGRATION_ASSIGN_ENV}
  stage: assign_test
  cache: []
-  tags:
-    - assign_test
+  tags: [fast_run, shiny]
  variables:
    SUBMODULES_TO_FETCH: "none"
    GIT_LFS_SKIP_SMUDGE: 1
@@ -47,6 +46,7 @@ gen_integration_pipeline:
    paths:
      - idf-integration-ci/child_pipeline/
    expire_in: 2 weeks
+    when: always
  script:
    - add_gitlab_ssh_keys
    - retry_failed git clone ${CI_GEN_INTEGRATION_PIPELINE_REPO} idf-integration-ci
--- a/.gitlab/ci/pre_check.yml
+++ b/.gitlab/ci/pre_check.yml
@@ -3,19 +3,7 @@
  image: $ESP_ENV_IMAGE
  tags:
    - host_test
-  dependencies: []
-
-check_pre_commit:
-  extends:
-    - .pre_check_template
-    - .before_script:minimal
-  image: $PRE_COMMIT_IMAGE
-  needs:
-    - pipeline_variables
-  script:
-    - fetch_submodules
-    - pre-commit run --files $MODIFIED_FILES
-    - pre-commit run --hook-stage post-commit validate-sbom-manifest
+  dependencies: # set dependencies to null to avoid missing artifacts issue

 check_version:
  # Don't run this for feature/bugfix branches, so that it is possible to modify
@@ -23,7 +11,13 @@ check_version:
  extends:
    - .pre_check_template
    - .rules:protected
-    - .before_script:fetch:git_describe
+  tags: [ brew, github_sync ]
+  variables:
+    # need a full clone to get the latest tag
+    # the --shallow-since=$(git log -1 --format=%as $LATEST_GIT_TAG) option is not accurate
+    GIT_STRATEGY: fetch
+    SUBMODULES_TO_FETCH: "none"
+    GIT_DEPTH: 0
  script:
    - export IDF_PATH=$PWD
    - tools/ci/check_idf_version.sh
@@ -31,7 +25,8 @@ check_version:
 check_api_usage:
  extends: .pre_check_template
  script:
-    - tools/ci/check_examples_rom_header.sh
+    - python -m pip install ast-grep-cli # use ast-grep to describe customized lint rules
+    - ast-grep scan
    - tools/ci/check_api_violation.sh
    - tools/ci/check_examples_extra_component_dirs.sh

@@ -60,20 +55,6 @@ check_blobs:
    # Check if Wi-Fi, PHY, BT blobs contain references to specific symbols
    - bash $IDF_PATH/tools/ci/check_blobs.sh

-check_public_headers:
-  extends:
-    - .pre_check_template
-    - .rules:build:check
-  script:
-    - IDF_TARGET=esp32 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32-elf-
-    - IDF_TARGET=esp32s2 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32s2-elf-
-    - IDF_TARGET=esp32s3 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32s3-elf-
-    - IDF_TARGET=esp32c3 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
-    - IDF_TARGET=esp32c2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
-    - IDF_TARGET=esp32c6 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
-    - IDF_TARGET=esp32h2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
-    - IDF_TARGET=esp32p4 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
-
 check_chip_support_components:
  extends:
    - .pre_check_template
@@ -86,7 +67,7 @@ check_chip_support_components:
    expire_in: 1 week
  script:
    - python tools/ci/check_soc_headers_leak.py
-    - find ${IDF_PATH}/components/soc/*/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py
+    - find ${IDF_PATH}/components/soc/**/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py
    - tools/ci/check_esp_memory_utils_headers.sh

 check_esp_err_to_name:
@@ -117,16 +98,16 @@ check_version_tag:
  extends:
    - .pre_check_template
    - .rules:tag:release
-    - .before_script:fetch:git_describe
+  tags: [ brew, github_sync ]
+  variables:
+    # need a full clone to get the latest tag
+    # the --shallow-since=$(git log -1 --format=%as $LATEST_GIT_TAG) option is not accurate
+    GIT_STRATEGY: fetch
+    SUBMODULES_TO_FETCH: "none"
+    GIT_DEPTH: 0
  script:
    - (git cat-file -t $CI_COMMIT_REF_NAME | grep tag) || (echo "ESP-IDF versions must be annotated tags." && exit 1)

-check_artifacts_expire_time:
-  extends: .pre_check_template
-  script:
-    # check if we have set expire time for all artifacts
-    - python tools/ci/check_artifacts_expire_time.py
-
 check_test_scripts_build_test_rules:
  extends:
    - .pre_check_template
@@ -149,19 +130,46 @@ pipeline_variables:
  extends:
    - .pre_check_template
    - .before_script:fetch:git_diff
-  tags:
-    - build
+  tags: [fast_run, shiny]
  script:
-    - MODIFIED_FILES=$(echo $GIT_DIFF_OUTPUT | xargs)
+    # MODIFIED_FILES is a list of files that changed, could be used everywhere
+    - MODIFIED_FILES=$(echo "$GIT_DIFF_OUTPUT" | xargs)
    - echo "MODIFIED_FILES=$MODIFIED_FILES" >> pipeline.env
-    - echo "MODIFIED_COMPONENTS=$(run_cmd python tools/ci/ci_get_mr_info.py components --modified-files $MODIFIED_FILES | xargs)" >> pipeline.env
+    # MR_MODIFIED_FILES and MR_MODIFIED_COMPONENTS are semicolon separated lists that is used in MR only
+    # for non MR pipeline, these are empty lists
+    - |
+      if [ $IS_MR_PIPELINE == "0" ]; then
+        echo "MR_MODIFIED_FILES=\"\"" >> pipeline.env
+        echo "MR_MODIFIED_COMPONENTS=\"\"" >> pipeline.env
+      else
+        MR_MODIFIED_FILES=$(echo "$GIT_DIFF_OUTPUT" | tr '\n' ';')
+        echo "MR_MODIFIED_FILES=\"$MR_MODIFIED_FILES\"" >> pipeline.env
+
+        MR_MODIFIED_COMPONENTS=$(run_cmd python tools/ci/ci_get_mr_info.py components --modified-files $MODIFIED_FILES | tr '\n' ';')
+        echo "MR_MODIFIED_COMPONENTS=\"$MR_MODIFIED_COMPONENTS\"" >> pipeline.env
+      fi
    - |
      if echo "$CI_MERGE_REQUEST_LABELS" | egrep "(^|,)BUILD_AND_TEST_ALL_APPS(,|$)"; then
        echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
      fi
+    # run full pipeline if testing constraint branch
+    - |
+      if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
+        echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
+      fi
    - cat pipeline.env
    - python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report
  artifacts:
    reports:
      dotenv: pipeline.env
-    expire_in: 4 days
+    paths:
+      - pipeline.env
+    expire_in: 1 week
+    when: always
+
+check_test_cases_env_markers_and_required_runners:
+  extends:
+    - .pre_check_template
+  tags: [fast_run, shiny]
+  script:
+    - python tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py --check
--- a/.gitlab/ci/pre_commit.yml
+++ b/.gitlab/ci/pre_commit.yml
@@ -0,0 +1,47 @@
+.check_pre_commit_template:
+  extends:
+    - .before_script:minimal
+  stage: pre_check
+  image: $PRE_COMMIT_IMAGE
+  tags: [cache, shiny]
+  needs:
+    - pipeline_variables
+  variables:
+    # cache pre_commit
+    PRE_COMMIT_HOME: "$CI_PROJECT_DIR/.cache/pre-commit"
+  script:
+    - fetch_submodules
+    - pre-commit run --files $MODIFIED_FILES
+    - pre-commit run --hook-stage post-commit validate-sbom-manifest
+
+check_pre_commit_upload_cache:
+  extends:
+    - .check_pre_commit_template
+  rules:
+    - if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/) && $CI_PIPELINE_SOURCE == "push"'
+  cache:
+    - key: pre_commit-cache-${LATEST_GIT_TAG}
+      paths:
+        - .cache/pre-commit
+      policy: pull-push
+    - key: submodule-cache-${LATEST_GIT_TAG}
+      paths:
+        - .cache/submodule_archives
+      policy: pull
+
+check_pre_commit:
+  extends:
+    - .check_pre_commit_template
+  rules:
+    - if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/) && $CI_PIPELINE_SOURCE == "push"'
+      when: never
+    - when: on_success
+  cache:
+    - key: pre_commit-cache-${LATEST_GIT_TAG}
+      paths:
+        - .cache/pre-commit
+      policy: pull
+    - key: submodule-cache-${LATEST_GIT_TAG}
+      paths:
+        - .cache/submodule_archives
+      policy: pull
--- a/.gitlab/ci/rules.yml
+++ b/.gitlab/ci/rules.yml
--- a/.gitlab/ci/static-code-analysis.yml
+++ b/.gitlab/ci/static-code-analysis.yml
@@ -6,8 +6,8 @@ clang_tidy_check:
  artifacts:
    paths:
      - clang_tidy_reports/
+    expire_in: 1 week
    when: always
-    expire_in: 1 day
  variables:
    IDF_TOOLCHAIN: clang
  script:
@@ -23,14 +23,16 @@ check_pylint:
  needs:
    - pipeline_variables
  artifacts:
-    when: always
    reports:
      codequality: pylint.json
+    paths:
+      - pylint.json
    expire_in: 1 week
+    when: always
  script:
    - |
      if [ -n "$CI_MERGE_REQUEST_IID" ]; then
-        export files=$(echo $GIT_DIFF_OUTPUT | grep ".py$" | xargs);
+        export files=$(echo "$GIT_DIFF_OUTPUT" | grep ".py$" | xargs);
      else
        export files=$(git ls-files "*.py" | xargs);
      fi
@@ -53,8 +55,10 @@ check_pylint:
 .sonar_scan_template:
  stage: build
  extends: .pre_check_template
-  image:
-    name: $SONARQUBE_SCANNER_IMAGE
+  # full clone since this image does not support fetch --shallow-since-cutoff
+  # shiny runners are used for full clone
+  tags: [build, shiny]
+  image: $SONARQUBE_SCANNER_IMAGE
  before_script:
    - source tools/ci/utils.sh
    - export PYTHONPATH="$CI_PROJECT_DIR/tools:$CI_PROJECT_DIR/tools/ci/python_packages:$PYTHONPATH"
@@ -68,12 +72,12 @@ check_pylint:
    - export SONAR_SCANNER_OPTS="-Xmx2048m"
  variables:
    GIT_DEPTH: 0
-    REPORT_PATTERN: clang_tidy_reports/*.txt
+    REPORT_PATTERN: clang_tidy_reports/**/*.txt
  artifacts:
-    when: always
    paths:
      - $REPORT_PATTERN
    expire_in: 1 week
+    when: always
  dependencies:  # Here is not a hard dependency relationship, could be skipped when only python files changed. so we do not use "needs" here.
    - clang_tidy_check

@@ -81,7 +85,7 @@ code_quality_check:
  extends:
    - .sonar_scan_template
    - .rules:patterns:static-code-analysis-preview
-  allow_failure: true  # since now it's using exit code to indicate the code analysis result,
+  allow_failure: true  # it's using exit code to indicate the code analysis result,
                       # we don't want to block ci when critical issues founded
  script:
    - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits --src-branch ${CI_COMMIT_REF_NAME} | tr '\n' ',')
@@ -104,7 +108,7 @@ code_quality_report:
  extends:
    - .sonar_scan_template
    - .rules:protected
-  allow_failure: true  # since now it's using exit code to indicate the code analysis result,
+  allow_failure: true  # it's using exit code to indicate the code analysis result,
                       # we don't want to block ci when critical issues founded
  script:
    - sonar-scanner
--- a/.gitlab/ci/target-test.yml
+++ b/.gitlab/ci/target-test.yml
--- a/.gitlab/ci/test-win.yml
+++ b/.gitlab/ci/test-win.yml
@@ -0,0 +1,96 @@
+# Host tests
+.host_test_win_template:
+  extends: .rules:test:host_test
+  stage: host_test
+  image: $ESP_ENV_IMAGE
+  tags:
+    - windows-build
+  dependencies: # set dependencies to null to avoid missing artifacts issue
+  # run host_test jobs immediately, only after upload cache
+  needs:
+    - job: upload-pip-cache
+      optional: true
+      artifacts: false
+    - job: upload-submodules-cache
+      optional: true
+      artifacts: false
+  before_script: []
+  after_script: []
+
+test_cli_installer_win:
+  extends:
+    - .host_test_win_template
+    - .rules:labels:windows_pytest_build_system
+  artifacts:
+    when: on_failure
+    paths:
+      - tools/tools.new.json
+      - tools/test_idf_tools/test_python_env_logs.txt
+    expire_in: 1 week
+  variables:
+    IDF_PATH: "$CI_PROJECT_DIR"
+  script:
+    # Tools must be downloaded for testing
+    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa
+    - cd ${IDF_PATH}\tools\test_idf_tools
+    - python -m pip install jsonschema
+    - python .\test_idf_tools.py
+    - python .\test_idf_tools_python_env.py
+
+test_tools_win:
+  extends:
+    - .host_test_win_template
+    - .rules:labels:windows_pytest_build_system
+  artifacts:
+    paths:
+      - ${IDF_PATH}/*.out
+      - ${IDF_PATH}/XUNIT_*.xml
+    reports:
+      junit: ${IDF_PATH}/XUNIT_*.xml
+    expire_in: 1 week
+    when: always
+  variables:
+    LC_ALL: C.UTF-8
+    PYTHONPATH: "$PYTHONPATH;$IDF_PATH\\tools;$IDF_PATH\\tools\\esp_app_trace;$IDF_PATH\\components\\partition_table;$IDF_PATH\\tools\\ci\\python_packages"
+  script:
+    - python -m pip install jsonschema
+    - .\install.ps1 --enable-ci --enable-pytest
+    - .\export.ps1
+    - python "${SUBMODULE_FETCH_TOOL}" -s "all"
+    - cd ${IDF_PATH}/tools/test_idf_py
+    - pytest --noconftest test_idf_py.py       --junitxml=${IDF_PATH}/XUNIT_IDF_PY.xml
+    - pytest --noconftest test_hints.py        --junitxml=${IDF_PATH}/XUNIT_HINTS.xml
+
+# Build tests
+.test_build_system_template_win:
+  stage: host_test
+  variables:
+  # Enable ccache for all build jobs. See configure_ci_environment.sh for more ccache related settings.
+    IDF_CCACHE_ENABLE: "1"
+    PYTHONPATH: "$PYTHONPATH;$IDF_PATH\\tools;$IDF_PATH\\tools\\esp_app_trace;$IDF_PATH\\components\\partition_table;$IDF_PATH\\tools\\ci\\python_packages"
+  before_script: []
+  after_script: []
+  timeout: 4 hours
+  script:
+    - .\install.ps1 --enable-ci --enable-pytest
+    - . .\export.ps1
+    - python "${SUBMODULE_FETCH_TOOL}" -s "all"
+    - cd ${IDF_PATH}\tools\test_build_system
+    - pytest --parallel-count ${CI_NODE_TOTAL} --parallel-index ${CI_NODE_INDEX} --junitxml=${CI_PROJECT_DIR}\XUNIT_RESULT.xml
+
+pytest_build_system_win:
+  extends:
+    - .test_build_system_template_win
+    - .rules:labels:windows_pytest_build_system
+  parallel: 2
+  needs: []
+  tags:
+    - windows-build
+  artifacts:
+    paths:
+      - XUNIT_RESULT.xml
+      - test_build_system
+    expire_in: 2 days
+    reports:
+      junit: XUNIT_RESULT.xml
+    when: always
--- a/.gitlab/merge_request_templates/Mixed
+++ b/.gitlab/merge_request_templates/Mixed
@@ -10,8 +10,7 @@ _This entire section can be deleted if all items are checked._
 * [ ] All related links, including JIRA, backport, submodule MR, are mentioned in the `Related` subsection.
 * [ ] Any GitHub issues are linked inside the git commit message and corresponding release notes
 * [ ] Add label for the area this MR is part of
-* [ ] For documentation updates, check if label `Docs` and `needs translation:CN` or `needs translation:EN`  have been added when the other language version still needs the update. Skip adding the label if the document is not yet translated.
-* [ ] Check if documents requiring translation fall under get-started section. If yes, add the labels mentioned above. Then the documentation team will assign a translator for you. Please inform the translator to prepare translation once your MR is ready to merge. The translation should be included in your MR to get it merged. For more information, see documentation workflow in Wiki.
+* [ ] For documentation updates, check if label `needs translation:CN` or `needs translation:EN` have been added when the other language version still needs the update. Don't add such labels if the document updated has never been translated before and requires translation from scratch.
 * [ ] Any necessary "needs backport" labels are added
 * [ ] Check if this is a breaking change. If it is, add notes to the `Breaking change notes` subsection below
 * [ ] Release note entry if this is a new public feature, or a fix for an issue introduced in the previous release.
--- a/.gitmodules
+++ b/.gitmodules
@@ -49,12 +49,12 @@
 [submodule "components/json/cJSON"]
 	path = components/json/cJSON
 	url = ../../DaveGamble/cJSON.git
-	sbom-version = 1.7.16
+	sbom-version = 1.7.17
 	sbom-cpe = cpe:2.3:a:cjson_project:cjson:{}:*:*:*:*:*:*:*
 	sbom-supplier = Person: Dave Gamble
 	sbom-url = https://github.com/DaveGamble/cJSON
 	sbom-description = Ultralightweight JSON parser in ANSI C
-	sbom-hash = cb8693b058ba302f4829ec6d03f609ac6f848546
+	sbom-hash = 87d8f0961a01bf09bef98ff89bae9fdec42181ee

 [submodule "components/mbedtls/mbedtls"]
 	path = components/mbedtls/mbedtls
@@ -120,10 +120,6 @@
 	path = components/openthread/lib
 	url = ../../espressif/esp-thread-lib.git

-[submodule "components/ieee802154/lib"]
-	path = components/ieee802154/lib
-	url = ../../espressif/esp-ieee802154-lib.git
-
 [submodule "components/bt/controller/lib_esp32h2/esp32h2-bt-lib"]
 	path = components/bt/controller/lib_esp32h2/esp32h2-bt-lib
 	url = ../../espressif/esp32h2-bt-lib.git
@@ -136,6 +132,10 @@
 	path = components/bt/controller/lib_esp32c6/esp32c6-bt-lib
 	url = ../../espressif/esp32c6-bt-lib.git

+[submodule "components/bt/controller/lib_esp32c5/esp32c5-bt-lib"]
+	path = components/bt/controller/lib_esp32c5/esp32c5-bt-lib
+	url = ../../espressif/esp32c5-bt-lib.git
+
 [submodule "components/heap/tlsf"]
 	path = components/heap/tlsf
 	url = ../../espressif/tlsf.git
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -5,7 +5,7 @@ default_stages: [commit]

 repos:
  - repo: https://github.com/pre-commit/pre-commit-hooks
-    rev: v4.0.1
+    rev: v4.5.0
    hooks:
      - id: trailing-whitespace
        # note: whitespace exclusions use multiline regex, see https://pre-commit.com/#regular-expressions
@@ -22,7 +22,8 @@ repos:
            .*_pb2.py|
            .*.pb-c.h|
            .*.pb-c.c|
-            .*.yuv
+            .*.yuv|
+            .*.rgb
          )$
      - id: end-of-file-fixer
        exclude: *whitespace_excludes
@@ -41,15 +42,20 @@ repos:
    hooks:
      - id: flake8
        args: ['--config=.flake8', '--tee', '--benchmark']
-  - repo: https://github.com/pycqa/isort
-    rev: 5.12.0  # python 3.8 compatible
+  - repo: https://github.com/asottile/reorder-python-imports
+    rev: v3.12.0
    hooks:
-      - id: isort
-        name: isort (python)
+      - id: reorder-python-imports
+        name: Reorder Python imports
+        args: [--py38-plus]
        exclude: >
          (?x)^(
              .*_pb2.py
          )$
+  - repo: https://github.com/codespell-project/codespell
+    rev: v2.2.6
+    hooks:
+      - id: codespell
  - repo: local
    hooks:
      - id: check-executables
@@ -64,13 +70,6 @@ repos:
        language: python
        pass_filenames: false
        always_run: true
-      - id: check-kconfigs
-        name: Validate Kconfig files
-        entry: tools/ci/check_kconfigs.py
-        language: python
-        additional_dependencies:
-          - esp-idf-kconfig
-        files: '^Kconfig$|Kconfig.*$'
      - id: check-deprecated-kconfigs-options
        name: Check if any Kconfig Options Deprecated
        entry: tools/ci/check_deprecated_kconfigs.py
@@ -91,20 +90,13 @@ repos:
        always_run: true
        files: '\.gitlab/CODEOWNERS'
        pass_filenames: false
-      - id: check-rules-yml
-        name: Check rules.yml all rules have at lease one job applied, all rules needed exist
-        entry: tools/ci/check_rules_yml.py
-        language: python
-        files: '\.gitlab/ci/.+\.yml|\.gitlab-ci.yml|\.gitmodules'
-        pass_filenames: false
-        additional_dependencies:
-          - PyYAML == 5.3.1
      - id: check-generated-rules
        name: Check rules are generated (based on .gitlab/ci/dependencies/dependencies.yml)
        entry: tools/ci/generate_rules.py
        language: python
-        files: '\.gitlab/ci/dependencies/.+|\.gitlab/ci/.*\.yml'
+        files: '\.gitlab/ci/dependencies/.+|\.gitlab/ci/.*\.yml|.gitlab-ci.yml'
        pass_filenames: false
+        require_serial: true
        additional_dependencies:
          - PyYAML == 5.3.1
      - id: mypy-check
@@ -115,6 +107,7 @@ repos:
          - 'mypy-extensions==0.4.3'
          - 'types-setuptools==57.4.14'
          - 'types-PyYAML==0.1.9'
+          - 'types-requests'
        exclude: >
          (?x)^(
              .*_pb2.py
@@ -161,14 +154,20 @@ repos:
        require_serial: true
        additional_dependencies:
          - PyYAML == 5.3.1
-          - idf_build_apps~=1.0
-      - id: sort-build-test-rules-ymls
-        name: sort .build-test-rules.yml files
-        entry: tools/ci/check_build_test_rules.py sort-yaml
+          - idf-build-apps~=2.0
+      - id: sort-yaml-files
+        name: sort yaml files
+        entry: tools/ci/sort_yaml.py
        language: python
-        files: '\.build-test-rules\.yml'
+        files: '\.build-test-rules\.yml$|known_generate_test_child_pipeline_warnings\.yml$'
+        additional_dependencies:
+          - ruamel.yaml
+      - id: sort-yaml-test
+        name: sort yaml test
+        entry: python -m unittest tools/ci/sort_yaml.py
+        language: python
+        files: 'tools/ci/sort_yaml\.py$'
        additional_dependencies:
-          - PyYAML == 5.3.1
          - ruamel.yaml
      - id: check-build-test-rules-path-exists
        name: check path in .build-test-rules.yml exists
@@ -185,6 +184,14 @@ repos:
        language: python
        always_run: true
        require_serial: true
+      - id: gitlab-yaml-linter
+        name: Check gitlab yaml files
+        entry: tools/ci/gitlab_yaml_linter.py
+        language: python
+        files: '\.gitlab-ci\.yml|\.gitlab/ci/.+\.yml|\.gitmodules'
+        pass_filenames: false
+        additional_dependencies:
+          - PyYAML == 5.3.1
  - repo: https://github.com/pre-commit/pre-commit-hooks
    rev: v4.0.1
    hooks:
@@ -222,3 +229,13 @@ repos:
    hooks:
      - id: validate-sbom-manifest
        stages: [post-commit]
+  - repo: https://github.com/sphinx-contrib/sphinx-lint
+    rev: v0.9.1
+    hooks:
+      - id: 'sphinx-lint'
+        name: Lint rST files in docs folder using Sphinx Lint
+        files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$
+  - repo: https://github.com/espressif/esp-idf-kconfig.git
+    rev: v2.1.0
+    hooks:
+      - id: check-kconfig-files
--- a/.readthedocs.yml
+++ b/.readthedocs.yml
@@ -15,7 +15,7 @@ python:
  install:
    - requirements: docs/requirements.txt

-# We need to list all the submodules included in documenation build by DOxygen
+# We need to list all the submodules included in documenation build by Doxygen
 submodules:
  include:
    - components/mqtt/esp-mqtt
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -223,9 +223,9 @@ else()
 endif()

 # SMP FreeRTOS user provided minimal idle hook. This allows the user to provide
-# their own copy of vApplicationMinimalIdleHook()
-if(CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK)
-    list(APPEND link_options "-Wl,--wrap=vApplicationMinimalIdleHook")
+# their own copy of vApplicationPassiveIdleHook()
+if(CONFIG_FREERTOS_USE_PASSIVE_IDLE_HOOK)
+    list(APPEND link_options "-Wl,--wrap=vApplicationPassiveIdleHook")
 endif()

 # Placing jump tables in flash would cause issues with code that required
@@ -245,15 +245,6 @@ if(COMPILER_RT_LIB_NAME)
    list(APPEND link_options "-rtlib=${CONFIG_COMPILER_RT_LIB_NAME}")
 endif()

-# For the transition period from 32-bit time_t to 64-bit time_t,
-# auto-detect the size of this type and set corresponding variable.
-include(CheckTypeSize)
-check_type_size("time_t" TIME_T_SIZE)
-if(TIME_T_SIZE)
-    idf_build_set_property(TIME_T_SIZE ${TIME_T_SIZE})
-else()
-    message(FATAL_ERROR "Failed to determine sizeof(time_t)")
-endif()

 idf_build_set_property(COMPILE_OPTIONS "${compile_options}" APPEND)
 idf_build_set_property(C_COMPILE_OPTIONS "${c_compile_options}" APPEND)
--- a/COMPATIBILITY.md
+++ b/COMPATIBILITY.md
@@ -52,12 +52,12 @@ Supported since ESP-IDF v4.2.

 | Release branch         | Recommended | Required |
 |------------------------|-------------|----------|
-| release/v4.2           | v4.2.3      | v4.2     |
-| release/v4.3           | v4.3.3      | v4.3     |
-| release/v4.4           | v4.4.6      | v4.4     |
-| release/v5.0           | v5.0.4      | v5.0     |
-| release/v5.1           | v5.1.2      | v5.1     |
-| release/v5.2 and above | v5.2        | v5.2     |
+| release/v4.2           | v4.2.3+     | v4.2     |
+| release/v4.3           | v4.3.3+     | v4.3     |
+| release/v4.4           | v4.4.6+     | v4.4     |
+| release/v5.0           | v5.0.4+     | v5.0     |
+| release/v5.1           | v5.1.2+     | v5.1     |
+| release/v5.2 and above | v5.2+       | v5.2     |

 ### ESP32-C3

@@ -69,16 +69,23 @@ Supported since ESP-IDF v4.3.

 To be added.

+#### v1.1
+
+| Release branch         | Recommended | Required |
+|------------------------|-------------|----------|
+| release/v4.2           | EOL         | EOL      |
+| release/v4.3           | v4.3.7+     | v4.3.7   |
+| release/v4.4           | v4.4.7+     | v4.4.7   |
+| release/v5.0           | v5.0.5+     | v5.0.5   |
+| release/v5.1           | v5.1.3+     | v5.1.3   |
+| release/v5.2 and above | v5.2+       | v5.2     |
+
 ### ESP32-S3

-#### v0.1
+#### v0.1, v0.2

 Supported since ESP-IDF v4.4.

-#### v0.2
-
-To be added.
-
 ### ESP32-C2 & ESP8684

 #### v1.0
@@ -93,6 +100,17 @@ To be added.

 To be added.

+### ESP32-C6
+
+#### v0.0, v0.1
+
+Supported since ESP-IDF v5.1.
+
+### ESP32-H2
+
+#### v0.1, v0.2
+
+Supported since ESP-IDF v5.1.

 ## What If the ESP-IDF Version Is Lower than the `Required` Version?

--- a/COMPATIBILITY_CN.md
+++ b/COMPATIBILITY_CN.md
@@ -50,14 +50,14 @@

 #### v1.0

-| 发布分支               | 推荐版本    | 需求版本 |
+| 发布分支                | 推荐版本     | 需求版本 |
 |------------------------|-------------|----------|
-| release/v4.2           | v4.2.3      | v4.2     |
-| release/v4.3           | v4.3.3      | v4.3     |
-| release/v4.4           | v4.4.6      | v4.4     |
-| release/v5.0           | v5.0.4      | v5.0     |
-| release/v5.1           | v5.1.2      | v5.1     |
-| release/v5.2 及以上     | v5.2        | v5.2     |
+| release/v4.2           | v4.2.3+     | v4.2     |
+| release/v4.3           | v4.3.3+     | v4.3     |
+| release/v4.4           | v4.4.6+     | v4.4     |
+| release/v5.0           | v5.0.4+     | v5.0     |
+| release/v5.1           | v5.1.2+     | v5.1     |
+| release/v5.2 及以上     | v5.2+       | v5.2     |

 ### ESP32-C3

@@ -69,16 +69,23 @@

 待更新。

+#### v1.1
+
+| 发布分支                | 推荐版本      | 需求版本  |
+|------------------------|-------------|----------|
+| release/v4.2           | EOL         | EOL      |
+| release/v4.3           | v4.3.7+     | v4.3.7   |
+| release/v4.4           | v4.4.7+     | v4.4.7   |
+| release/v5.0           | v5.0.5+     | v5.0.5   |
+| release/v5.1           | v5.1.3+     | v5.1.3   |
+| release/v5.2 及以上     | v5.2+       | v5.2     |
+
 ### ESP32-S3

-#### v0.1
+#### v0.1, v0.2

 从 ESP-IDF v4.4 开始支持。

-#### v0.2
-
-待更新。
-
 ### ESP32-C2 & ESP8684

 #### v1.0
@@ -93,6 +100,18 @@

 待更新。

+### ESP32-C6
+
+#### v0.0, v0.1
+
+从 ESP-IDF v5.1 开始支持。
+
+### ESP32-H2
+
+#### v0.1, v0.2
+
+从 ESP-IDF v5.1 开始支持。
+

 ## 如果 ESP-IDF 版本低于 `需求版本` 会出现什么情况？

--- a/36
+++ b/36
@@ -118,7 +118,28 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default "y" if IDF_TARGET="esp32c5"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_BRINGUP
+
+    # TODO: IDF-9197
+    choice IDF_TARGET_ESP32C5_VERSION
+        prompt "ESP32-C5 version"
+        depends on IDF_TARGET_ESP32C5
+        default IDF_TARGET_ESP32C5_MP_VERSION
+        help
+            ESP32-C5 will support two versions for a period.
+            This option is for internal use only.
+            Select the one that matches your chip model.
+
+        config IDF_TARGET_ESP32C5_BETA3_VERSION
+            bool
+            prompt "ESP32-C5 beta3"
+            select ESPTOOLPY_NO_STUB
+
+        config IDF_TARGET_ESP32C5_MP_VERSION
+            bool
+            prompt "ESP32-C5 MP"
+            select ESPTOOLPY_NO_STUB
+            select IDF_ENV_FPGA
+    endchoice

    config IDF_TARGET_ESP32P4
        bool
@@ -131,6 +152,13 @@ mainmenu "Espressif IoT Development Framework Configuration"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV

+    config IDF_TARGET_ESP32C61
+        bool
+        default "y" if IDF_TARGET="esp32c61"
+        select FREERTOS_UNICORE
+        select IDF_TARGET_ARCH_RISCV
+        select IDF_ENV_FPGA
+
    config IDF_TARGET_LINUX
        bool
        default "y" if IDF_TARGET="linux"
@@ -145,7 +173,9 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default 0x000D if IDF_TARGET_ESP32C6
        default 0x0010 if IDF_TARGET_ESP32H2
        default 0x0012 if IDF_TARGET_ESP32P4
-        default 0x0013 if IDF_TARGET_ESP32C5
+        default 0x0011 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_BETA3_VERSION  # TODO: IDF-9197
+        default 0x0017 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_MP_VERSION     # TODO: IDF-9197
+        default 0x0014 if IDF_TARGET_ESP32C61
        default 0xFFFF


@@ -598,3 +628,5 @@ mainmenu "Espressif IoT Development Framework Configuration"
            - CONFIG_SPIRAM_SPEED_120M && CONFIG_SPIRAM_MODE_OCT
            - CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
            - CONFIG_MBEDTLS_USE_CRYPTO_ROM_IMPL
+            - CONFIG_ESP_WIFI_EAP_TLS1_3
+            - CONFIG_ESP_WIFI_ENABLE_ROAMING_APP
--- a/README.md
+++ b/README.md
@@ -15,16 +15,17 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li

 The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.

-|Chip         |         v4.3           |          v4.4          |          v5.0          |         v5.1           |         v5.2           |                                                            |
-|:----------- | :---------------------:| :---------------------:| :---------------------:| :--------------------: | :--------------------: | :----------------------------------------------------------|
+|Chip         |          v4.4          |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
+|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
 |ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
 |ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
 |ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S3     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
-|ESP32-C2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
-|ESP32-C6     |                        |                        |                        | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
-|ESP32-H2     |                        |                        |                        | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
+|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
+|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
+|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
+|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |

 [supported]: https://img.shields.io/badge/-supported-green "supported"
 [preview]: https://img.shields.io/badge/-preview-orange "preview"
--- a/README_CN.md
+++ b/README_CN.md
@@ -15,16 +15,17 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux

 下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。

-|芯片         |         v4.3           |          v4.4          |          v5.0          |          v5.1          |          v5.2          |                                                                 |
-|:----------- | :---------------------:| :---------------------:| :---------------------:| :--------------------: | :--------------------: | :-------------------------------------------------------------- |
+|芯片         |          v4.4          |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
+|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
 |ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
 |ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
 |ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S3     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
-|ESP32-C2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
-|ESP32-C6     |                        |                        |                        | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
-|ESP32-H2     |                        |                        |                        | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/en/news/ESP32-P4)      |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
+|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
+|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
+|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/en/news/ESP32-P4)      |
+|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |

 [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
 [preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
--- a/components/app_trace/CMakeLists.txt
+++ b/components/app_trace/CMakeLists.txt
@@ -9,6 +9,11 @@ set(srcs
    "app_trace_util.c"
    "host_file_io.c")

+if(CONFIG_ESP_DEBUG_STUBS_ENABLE)
+    list(APPEND srcs
+        "debug_stubs.c")
+endif()
+
 if(CONFIG_APPTRACE_GCOV_ENABLE)
    if("${CMAKE_C_COMPILER_ID}" STREQUAL "GNU")
        list(APPEND srcs
--- a/components/app_trace/app_trace.c
+++ b/components/app_trace/app_trace.c
@@ -1,7 +1,7 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
 *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
 */

 #include <string.h>
@@ -196,7 +196,7 @@ esp_err_t esp_apptrace_read(esp_apptrace_dest_t dest, void *buf, uint32_t *size,
    *size = 0;
    uint8_t *ptr = ch->hw->get_down_buffer(ch->hw_data, &act_sz, &tmo);
    if (ptr && act_sz > 0) {
-        ESP_APPTRACE_LOGD("Read %d bytes from host", act_sz);
+        ESP_APPTRACE_LOGD("Read %" PRIu32 " bytes from host", act_sz);
        memcpy(buf, ptr, act_sz);
        res = ch->hw->put_down_buffer(ch->hw_data, ptr, &tmo);
        *size = act_sz;
@@ -329,7 +329,7 @@ int esp_apptrace_vprintf_to(esp_apptrace_dest_t dest, uint32_t user_tmo, const c
    }

    esp_apptrace_tmo_init(&tmo, user_tmo);
-    ESP_APPTRACE_LOGD("fmt %x", fmt);
+    ESP_APPTRACE_LOGD("fmt %p", fmt);
    while ((p = (uint8_t *)strchr((char *)p, '%')) && nargs < ESP_APPTRACE_MAX_VPRINTF_ARGS) {
        p++;
        if (*p != '%' && *p != 0) {
@@ -355,7 +355,7 @@ int esp_apptrace_vprintf_to(esp_apptrace_dest_t dest, uint32_t user_tmo, const c
        uint32_t arg = va_arg(ap, uint32_t);
        *(uint32_t *)pout = arg;
        pout += sizeof(uint32_t);
-        ESP_APPTRACE_LOGD("arg %x", arg);
+        ESP_APPTRACE_LOGD("arg %" PRIx32, arg);
    }

    int ret = ch->hw->put_up_buffer(ch->hw_data, p, &tmo);
--- a/components/app_trace/app_trace_membufs_proto.c
+++ b/components/app_trace/app_trace_membufs_proto.c
@@ -1,7 +1,7 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
 */

 #include <sys/param.h>
@@ -100,7 +100,7 @@ static esp_err_t esp_apptrace_membufs_swap(esp_apptrace_membufs_proto_data_t *pr
    if (proto->hw->host_data_pending() && hdr->block_sz > 0) {
        // TODO: add support for multiple blocks from host, currently there is no need for that
        uint8_t *p = proto->blocks[new_block_num].start + proto->blocks[new_block_num].sz;
-        ESP_APPTRACE_LOGD("Recvd %d bytes from host (@ 0x%x) [%x %x %x %x %x %x %x %x .. %x %x %x %x %x %x %x %x]",
+        ESP_APPTRACE_LOGD("Recvd %" PRIu16 " bytes from host (@ %p) [%x %x %x %x %x %x %x %x .. %x %x %x %x %x %x %x %x]",
            hdr->block_sz, proto->blocks[new_block_num].start,
            *(proto->blocks[new_block_num].start+0), *(proto->blocks[new_block_num].start+1),
            *(proto->blocks[new_block_num].start+2), *(proto->blocks[new_block_num].start+3),
@@ -109,7 +109,7 @@ static esp_err_t esp_apptrace_membufs_swap(esp_apptrace_membufs_proto_data_t *pr
            *(p-8), *(p-7), *(p-6), *(p-5), *(p-4), *(p-3), *(p-2), *(p-1));
        uint32_t sz = esp_apptrace_membufs_down_buffer_write_nolock(proto, (uint8_t *)(hdr+1), hdr->block_sz);
        if (sz != hdr->block_sz) {
-            ESP_APPTRACE_LOGE("Failed to write %d bytes to down buffer (%d %d)!", hdr->block_sz - sz, hdr->block_sz, sz);
+            ESP_APPTRACE_LOGE("Failed to write %" PRIu32 " bytes to down buffer (%" PRIu16 " %" PRIu32 ")!", hdr->block_sz - sz, hdr->block_sz, sz);
        }
        hdr->block_sz = 0;
    }
@@ -196,7 +196,7 @@ static uint32_t esp_apptrace_membufs_down_buffer_write_nolock(esp_apptrace_membu
    uint32_t total_sz = 0;

    while (total_sz < size) {
-        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock WRS %d-%d-%d %d", proto->rb_down.wr, proto->rb_down.rd,
+        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock WRS %" PRIu32 "-%" PRIu32 "-%" PRIu32 " %" PRIu32, proto->rb_down.wr, proto->rb_down.rd,
            proto->rb_down.cur_size, size);
        uint32_t wr_sz = esp_apptrace_rb_write_size_get(&proto->rb_down);
        if (wr_sz == 0) {
@@ -206,15 +206,15 @@ static uint32_t esp_apptrace_membufs_down_buffer_write_nolock(esp_apptrace_membu
        if (wr_sz > size - total_sz) {
            wr_sz = size - total_sz;
        }
-        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %d", wr_sz);
+        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %" PRIu32, wr_sz);
        uint8_t *ptr = esp_apptrace_rb_produce(&proto->rb_down, wr_sz);
        if (!ptr) {
            assert(false && "Failed to produce bytes to down buffer!");
        }
-        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %d to 0x%x from 0x%x", wr_sz, ptr, data + total_sz + wr_sz);
+        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %" PRIu32 " to %p from %p", wr_sz, ptr, data + total_sz + wr_sz);
        memcpy(ptr, data + total_sz, wr_sz);
        total_sz += wr_sz;
-        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %d/%d", wr_sz, total_sz);
+        ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %" PRIu32 "/%" PRIu32 "", wr_sz, total_sz);
    }
    return total_sz;
 }
@@ -278,7 +278,7 @@ uint8_t *esp_apptrace_membufs_up_buffer_get(esp_apptrace_membufs_proto_data_t *p
    uint8_t *buf_ptr = NULL;

    if (size > ESP_APPTRACE_USR_DATA_LEN_MAX(proto)) {
-        ESP_APPTRACE_LOGE("Too large user data size %d!", size);
+        ESP_APPTRACE_LOGE("Too large user data size %" PRIu32 "!", size);
        return NULL;
    }

@@ -308,21 +308,21 @@ uint8_t *esp_apptrace_membufs_up_buffer_get(esp_apptrace_membufs_proto_data_t *p
 #endif
        if (ESP_APPTRACE_INBLOCK_MARKER(proto) + ESP_APPTRACE_USR_BLOCK_RAW_SZ(size) > ESP_APPTRACE_INBLOCK(proto)->sz) {
            #if CONFIG_APPTRACE_PENDING_DATA_SIZE_MAX > 0
-            ESP_APPTRACE_LOGD("Block full. Get %d bytes from PEND buffer", size);
+            ESP_APPTRACE_LOGD("Block full. Get %" PRIu32 " bytes from PEND buffer", size);
            buf_ptr = esp_apptrace_rb_produce(&proto->rb_pend, ESP_APPTRACE_USR_BLOCK_RAW_SZ(size));
            #endif
            if (buf_ptr == NULL) {
                int pended_buf;
-                ESP_APPTRACE_LOGD(" full. Get %d bytes from pend buffer", size);
+                ESP_APPTRACE_LOGD(" full. Get %" PRIu32 " bytes from pend buffer", size);
                buf_ptr = esp_apptrace_membufs_wait4buf(proto, ESP_APPTRACE_USR_BLOCK_RAW_SZ(size), tmo, &pended_buf);
                if (buf_ptr && !pended_buf) {
-                    ESP_APPTRACE_LOGD("Got %d bytes from block", size);
+                    ESP_APPTRACE_LOGD("Got %" PRIu32 " bytes from block", size);
                    // update cur block marker
                    ESP_APPTRACE_INBLOCK_MARKER_UPD(proto, ESP_APPTRACE_USR_BLOCK_RAW_SZ(size));
                }
            }
        } else {
-            ESP_APPTRACE_LOGD("Get %d bytes from  buffer", size);
+            ESP_APPTRACE_LOGD("Get %" PRIu32 " bytes from  buffer", size);
            // fit to curr  nlock
            buf_ptr = ESP_APPTRACE_INBLOCK(proto)->start + ESP_APPTRACE_INBLOCK_MARKER(proto);
            // update cur block marker
@@ -352,12 +352,12 @@ esp_err_t esp_apptrace_membufs_flush_nolock(esp_apptrace_membufs_proto_data_t *p
    int res = ESP_OK;

    if (ESP_APPTRACE_INBLOCK_MARKER(proto) < min_sz) {
-        ESP_APPTRACE_LOGI("Ignore flush request for min %d bytes. Bytes in  block: %d.", min_sz, ESP_APPTRACE_INBLOCK_MARKER(proto));
+        ESP_APPTRACE_LOGI("Ignore flush request for min %" PRIu32 " bytes. Bytes in  block: %" PRIu32, min_sz, ESP_APPTRACE_INBLOCK_MARKER(proto));
        return ESP_OK;
    }
    // switch  block while size of data (including that in pending buffer) is more than min size
    while (ESP_APPTRACE_INBLOCK_MARKER(proto) > min_sz) {
-        ESP_APPTRACE_LOGD("Try to flush %d bytes. Wait until block switch for %lld us", ESP_APPTRACE_INBLOCK_MARKER(proto), tmo->tmo);
+        ESP_APPTRACE_LOGD("Try to flush %" PRIu32 " bytes. Wait until block switch for %" PRIi64 " us", ESP_APPTRACE_INBLOCK_MARKER(proto), tmo->tmo);
        res = esp_apptrace_membufs_swap_waitus(proto, tmo);
        if (res != ESP_OK) {
            if (tmo->tmo != ESP_APPTRACE_TMO_INFINITE)
--- a/components/app_trace/app_trace_util.c
+++ b/components/app_trace/app_trace_util.c
@@ -1,7 +1,7 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
 *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
 */
 //
 #include "freertos/FreeRTOS.h"
--- a/components/esp_system/debug_stubs.c
+++ b/components/esp_system/debug_stubs.c
@@ -8,7 +8,8 @@
 // Currently one stub is used for GCOV functionality
 //

-#include "esp_private/dbg_stubs.h"
+#include "esp_private/startup_internal.h"
+#include "dbg_stubs.h"
 #include "esp_attr.h"

 /*
@@ -27,7 +28,7 @@ const static char *TAG = "esp_dbg_stubs";
 #define ESP_DBG_STUBS_CODE_BUF_SIZE         32
 #define ESP_DBG_STUBS_STACK_MIN_SIZE        2048

-#define DBG_STUB_TRAMP_ATTR					IRAM_ATTR
+#define DBG_STUB_TRAMP_ATTR                 IRAM_ATTR

 static struct {
    uint32_t    tramp_addr;
@@ -46,7 +47,7 @@ extern void esp_dbg_stubs_ll_init(void *stub_table_addr);
 static void * esp_dbg_stubs_data_alloc(uint32_t size)
 {
    ESP_LOGV(TAG, "%s %"PRIu32, __func__, size);
-	void *p = malloc(size);
+    void *p = malloc(size);
    ESP_LOGV(TAG, "%s EXIT %p", __func__, p);
    return p;
 }
@@ -92,3 +93,9 @@ esp_err_t esp_dbg_stub_entry_get(esp_dbg_stub_id_t id, uint32_t *entry)

    return ESP_OK;
 }
+
+ESP_SYSTEM_INIT_FN(init_dbg_stubs, SECONDARY, BIT(0), 140)
+{
+    esp_dbg_stubs_init();
+    return ESP_OK;
+}
--- a/components/app_trace/gcov/gcov_rtio.c
+++ b/components/app_trace/gcov/gcov_rtio.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -14,14 +14,10 @@
 #include "soc/timer_periph.h"
 #include "esp_app_trace.h"
 #include "esp_freertos_hooks.h"
-#include "esp_private/dbg_stubs.h"
-#include "esp_ipc.h"
+#include "dbg_stubs.h"
+#include "esp_private/esp_ipc.h"
+#include "esp_attr.h"
 #include "hal/wdt_hal.h"
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/libc_stubs.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/libc_stubs.h"
-#endif

 #if CONFIG_APPTRACE_GCOV_ENABLE

@@ -80,11 +76,11 @@ void gcov_create_task(void *arg)
 		(void *)&s_gcov_task_running, configMAX_PRIORITIES - 1, NULL, 0);
 }

+static IRAM_ATTR
 void gcov_create_task_tick_hook(void)
 {
-    extern esp_err_t esp_ipc_start_gcov_from_isr(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
    if (s_create_gcov_task) {
-        if (esp_ipc_start_gcov_from_isr(xPortGetCoreID(), &gcov_create_task, NULL) == ESP_OK) {
+        if (esp_ipc_call_nonblocking(xPortGetCoreID(), &gcov_create_task, NULL) == ESP_OK) {
            s_create_gcov_task = false;
        }
    }
@@ -106,12 +102,16 @@ static int esp_dbg_stub_gcov_entry(void)

 void gcov_rtio_init(void)
 {
-    uint32_t capabilities = 0;
+    uint32_t stub_entry = 0;
    ESP_EARLY_LOGV(TAG, "%s", __FUNCTION__);
-    esp_dbg_stub_entry_set(ESP_DBG_STUB_ENTRY_GCOV, (uint32_t)&esp_dbg_stub_gcov_entry);
-    if (esp_dbg_stub_entry_get(ESP_DBG_STUB_ENTRY_CAPABILITIES, &capabilities) == ESP_OK) {
-        esp_dbg_stub_entry_set(ESP_DBG_STUB_ENTRY_CAPABILITIES, capabilities | ESP_DBG_STUB_CAP_GCOV_TASK);
+    assert(esp_dbg_stub_entry_get(ESP_DBG_STUB_ENTRY_GCOV, &stub_entry) == ESP_OK);
+    if (stub_entry != 0) {
+        /* "__gcov_init()" can be called several times. We must avoid multiple tick hook registration */
+        return;
    }
+    esp_dbg_stub_entry_set(ESP_DBG_STUB_ENTRY_GCOV, (uint32_t)&esp_dbg_stub_gcov_entry);
+    assert(esp_dbg_stub_entry_get(ESP_DBG_STUB_ENTRY_CAPABILITIES, &stub_entry) == ESP_OK);
+    esp_dbg_stub_entry_set(ESP_DBG_STUB_ENTRY_CAPABILITIES, stub_entry | ESP_DBG_STUB_CAP_GCOV_TASK);
    esp_register_freertos_tick_hook(gcov_create_task_tick_hook);
 }

--- a/components/app_trace/host_file_io.c
+++ b/components/app_trace/host_file_io.c
@@ -122,7 +122,7 @@ static esp_err_t esp_apptrace_file_rsp_recv(esp_apptrace_dest_t dest, uint8_t *b
            ESP_EARLY_LOGE(TAG, "Failed to read (%d)!", ret);
            return ret;
        }
-        ESP_EARLY_LOGV(TAG, "%s read %d bytes", __FUNCTION__, rd_size);
+        ESP_EARLY_LOGV(TAG, "%s read %" PRIu32 " bytes", __FUNCTION__, rd_size);
        tot_rd += rd_size;
    }

--- a/components/app_trace/include/esp_app_trace_util.h
+++ b/components/app_trace/include/esp_app_trace_util.h
@@ -174,7 +174,7 @@ void esp_apptrace_log_unlock(void);
 #define ESP_APPTRACE_LOG_LEV( _L_, level, format, ... )   \
    do { \
        if (LOG_LOCAL_LEVEL >= level) { \
-            ESP_APPTRACE_LOG(LOG_FORMAT(_L_, format), esp_log_early_timestamp(), TAG, ##__VA_ARGS__); \
+            ESP_APPTRACE_LOG(LOG_FORMAT(_L_, format), esp_log_early_timestamp(), TAG, LOG_ADDITIONAL_ARGS, ##__VA_ARGS__); \
        } \
    } while(0)

--- a/components/app_trace/port/riscv/port.c
+++ b/components/app_trace/port/riscv/port.c
@@ -1,9 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
 */

+#include "sdkconfig.h"
 #include "esp_cpu.h"
 #include "esp_log.h"
 #include "esp_app_trace_membufs_proto.h"
@@ -56,7 +57,7 @@ static bool esp_apptrace_riscv_host_data_pending(void);

 const static char *TAG = "esp_apptrace";

-static esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[portNUM_PROCESSORS];
+static esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES];

 esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data)
 {
@@ -158,7 +159,7 @@ static esp_err_t esp_apptrace_riscv_init(esp_apptrace_riscv_data_t *hw_data)
    ESP_APPTRACE_LOGI("Apptrace initialized on CPU%d. Tracing control block @ %p.", core_id, &s_tracing_ctrl[core_id]);
    s_tracing_ctrl[core_id].mem_blocks = hw_data->membufs.blocks;
    for (int i = 0; i < 2; i++) {
-        ESP_APPTRACE_LOGD("Mem buf[%d] %d bytes @ %p (%p/%p)", i,
+        ESP_APPTRACE_LOGD("Mem buf[%d] %" PRIu32 " bytes @ %p (%p/%p)", i,
            s_tracing_ctrl[core_id].mem_blocks[i].sz, s_tracing_ctrl[core_id].mem_blocks[i].start,
            &(s_tracing_ctrl[core_id].mem_blocks[i].start), &(s_tracing_ctrl[core_id].mem_blocks[i].sz));
    }
@@ -324,7 +325,7 @@ static esp_err_t esp_apptrace_riscv_buffer_swap_start(uint32_t curr_block_id)
        uint32_t acked_block = ESP_APPTRACE_RISCV_BLOCK_ID_GET(ctrl_reg);
        uint32_t host_to_read = ESP_APPTRACE_RISCV_BLOCK_LEN_GET(ctrl_reg);
        if (host_to_read != 0 || acked_block != (curr_block_id & ESP_APPTRACE_RISCV_BLOCK_ID_MSK)) {
-            ESP_APPTRACE_LOGD("[%d]: Can not switch %x %d %x %x/%lx", esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
+            ESP_APPTRACE_LOGD("[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32, esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
                curr_block_id & ESP_APPTRACE_RISCV_BLOCK_ID_MSK, curr_block_id);
            res = ESP_ERR_NO_MEM;
            goto _on_err;
--- a/components/app_trace/port/xtensa/port.c
+++ b/components/app_trace/port/xtensa/port.c
@@ -1,7 +1,7 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
 */

 //
@@ -288,7 +288,7 @@ static inline void esp_apptrace_trax_select_memory_block(int block_num)
                        : TRACEMEM_CORE0_MUX_BLK_BITS(TRACEMEM_MUX_BLK1_NUM);
    block_bits |= block_num ? TRACEMEM_CORE1_MUX_BLK_BITS(TRACEMEM_MUX_BLK0_NUM)
                        : TRACEMEM_CORE1_MUX_BLK_BITS(TRACEMEM_MUX_BLK1_NUM);
-    ESP_EARLY_LOGV(TAG, "Select block %d @ %p (bits 0x%x)", block_num, s_trax_blocks[block_num], block_bits);
+    ESP_EARLY_LOGV(TAG, "Select block %d @ %p (bits 0x%" PRIx32 ")", block_num, s_trax_blocks[block_num], block_bits);
    DPORT_WRITE_PERI_REG(SENSITIVE_INTERNAL_SRAM_USAGE_2_REG, block_bits);
 #endif
 }
@@ -498,7 +498,7 @@ static esp_err_t esp_apptrace_trax_buffer_swap_start(uint32_t curr_block_id)
        uint32_t acked_block = ESP_APPTRACE_TRAX_BLOCK_ID_GET(ctrl_reg);
        uint32_t host_to_read = ESP_APPTRACE_TRAX_BLOCK_LEN_GET(ctrl_reg);
        if (host_to_read != 0 || acked_block != (curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK)) {
-            ESP_APPTRACE_LOGD("HC[%d]: Can not switch %x %d %x %x/%lx", esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
+            ESP_APPTRACE_LOGD("HC[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32, esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
                curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK, curr_block_id);
            res = ESP_ERR_NO_MEM;
            goto _on_err;
--- a/components/esp_system/include/esp_private/dbg_stubs.h
+++ b/components/esp_system/include/esp_private/dbg_stubs.h
@@ -1,16 +1,9 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 #ifndef ESP_DBG_STUBS_H_
 #define ESP_DBG_STUBS_H_

@@ -28,8 +21,8 @@ typedef enum {
    ESP_DBG_STUB_TABLE_SIZE,
    ESP_DBG_STUB_CONTROL_DATA,   ///< stubs descriptor entry
    ESP_DBG_STUB_ENTRY_FIRST,
-    ESP_DBG_STUB_ENTRY_GCOV	///< GCOV entry
-        = ESP_DBG_STUB_ENTRY_FIRST,
+    ESP_DBG_STUB_ENTRY_GCOV ///< GCOV entry
+    = ESP_DBG_STUB_ENTRY_FIRST,
    ESP_DBG_STUB_ENTRY_CAPABILITIES,
    ESP_DBG_STUB_ENTRY_MAX
 } esp_dbg_stub_id_t;
@@ -49,7 +42,7 @@ void esp_dbg_stubs_init(void);
 *
 * @note   Should be called before any esp_apptrace_xxx call.
 *
- * @param id 	Stub ID.
+ * @param id    Stub ID.
 * @param entry Stub entry. Usually it is stub entry function address,
 *              but can be any value meaningfull for OpenOCD command/code
 *              such as capabilities
@@ -60,7 +53,7 @@ esp_err_t esp_dbg_stub_entry_set(esp_dbg_stub_id_t id, uint32_t entry);
 /**
 * @brief   Retrives the corresponding stub entry
 *
- * @param id 	Stub ID.
+ * @param id    Stub ID.
 * @param entry Stub entry. Usually it is stub entry function address,
 *              but can be any value meaningfull for OpenOCD command/code
 *              such as capabilities
@@ -73,4 +66,4 @@ esp_err_t esp_dbg_stub_entry_get(esp_dbg_stub_id_t id, uint32_t *entry);
 }
 #endif

-#endif //ESP_DBG_STUBS_H_
+#endif // ESP_DBG_STUBS_H_
--- a/components/app_trace/project_include.cmake
+++ b/components/app_trace/project_include.cmake
@@ -5,21 +5,25 @@ function(idf_create_coverage_report report_dir)
    set(gcov_tool ${_CMAKE_TOOLCHAIN_PREFIX}gcov)
    idf_build_get_property(project_name PROJECT_NAME)

+    file(TO_NATIVE_PATH "${report_dir}" _report_dir)
+    file(TO_NATIVE_PATH "${project_dir}" _project_dir)
+    file(TO_NATIVE_PATH "${report_dir}/html/index.html" _index_path)
+
    add_custom_target(pre-cov-report
-        COMMENT "Generating coverage report in: ${report_dir}"
+        COMMENT "Generating coverage report in: ${_report_dir}"
        COMMAND ${CMAKE_COMMAND} -E echo "Using gcov: ${gcov_tool}"
-        COMMAND ${CMAKE_COMMAND} -E make_directory ${report_dir}/html
+        COMMAND ${CMAKE_COMMAND} -E make_directory ${_report_dir}/html
        )

    add_custom_target(lcov-report
        COMMENT "WARNING: lcov-report is deprecated. Please use gcovr-report instead."
-        COMMAND lcov --gcov-tool ${gcov_tool} -c -d ${CMAKE_CURRENT_BINARY_DIR} -o ${report_dir}/${project_name}.info
-        COMMAND genhtml -o ${report_dir}/html ${report_dir}/${project_name}.info
+        COMMAND lcov --gcov-tool ${gcov_tool} -c -d ${CMAKE_CURRENT_BINARY_DIR} -o ${_report_dir}/${project_name}.info
+        COMMAND genhtml -o ${_report_dir}/html ${_report_dir}/${project_name}.info
        DEPENDS pre-cov-report
        )

    add_custom_target(gcovr-report
-        COMMAND gcovr -r ${project_dir} --gcov-executable ${gcov_tool} -s --html-details ${report_dir}/html/index.html
+        COMMAND gcovr -r ${_project_dir} --gcov-executable ${gcov_tool} -s --html-details ${_index_path}
        WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
        DEPENDS pre-cov-report
        )
@@ -29,7 +33,9 @@ endfunction()
 #
 # Clean coverage report.
 function(idf_clean_coverage_report report_dir)
+    file(TO_CMAKE_PATH "${report_dir}" _report_dir)
+
    add_custom_target(cov-data-clean
-        COMMENT "Clean coverage report in: ${report_dir}"
-        COMMAND ${CMAKE_COMMAND} -E remove_directory ${report_dir})
+        COMMENT "Clean coverage report in: ${_report_dir}"
+        COMMAND ${CMAKE_COMMAND} -E remove_directory ${_report_dir})
 endfunction()
--- a/components/app_trace/test_apps/.build-test-rules.yml
+++ b/components/app_trace/test_apps/.build-test-rules.yml
@@ -7,3 +7,7 @@ components/app_trace/test_apps:
    - soc
    - driver
    - esp_hw_support
+  disable:
+    - if: IDF_TARGET == "esp32c5"
+      temporary: true
+      reason: not support yet # TODO: [ESP32C5] IDF-8705
--- a/components/app_trace/test_apps/main/test_trace.c
+++ b/components/app_trace/test_apps/main/test_trace.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -135,9 +135,9 @@ static bool esp_apptrace_test_timer_isr_crash(gptimer_handle_t timer, const gpti
        memset(tim_arg->data.buf + 2 * sizeof(uint32_t), tim_arg->data.wr_cnt & tim_arg->data.mask, tim_arg->data.buf_sz - 2 * sizeof(uint32_t));
        int res = ESP_APPTRACE_TEST_WRITE_FROM_ISR(tim_arg->data.buf, tim_arg->data.buf_sz);
        if (res != ESP_OK) {
-            esp_rom_printf("tim-%x: Failed to write trace %d %x!\n", tim_arg->gptimer, res, tim_arg->data.wr_cnt & tim_arg->data.mask);
+            esp_rom_printf("tim-%p: Failed to write trace %d %" PRIx32 "!\n", tim_arg->gptimer, res, tim_arg->data.wr_cnt & tim_arg->data.mask);
        } else {
-            esp_rom_printf("tim-%x: Written chunk%d %d bytes, %x\n",
+            esp_rom_printf("tim-%p: Written chunk%" PRIu32 " %" PRIu32 " bytes, %" PRIx32 "\n",
                           timer, tim_arg->data.wr_cnt, tim_arg->data.buf_sz, tim_arg->data.wr_cnt & tim_arg->data.mask);
            tim_arg->data.wr_cnt++;
        }
@@ -153,7 +153,7 @@ static void esp_apptrace_dummy_task(void *p)
    esp_apptrace_test_task_arg_t *arg = (esp_apptrace_test_task_arg_t *) p;
    TickType_t tmo_ticks = arg->data.period / (1000 * portTICK_PERIOD_MS);

-    ESP_APPTRACE_TEST_LOGI("%x: run dummy task (period %u us, %u timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->timers_num);
+    ESP_APPTRACE_TEST_LOGI("%p: run dummy task (period %" PRIu32 " us, %" PRIu32 " timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->timers_num);

    for (int i = 0; i < arg->timers_num; i++) {
        gptimer_config_t timer_config = {
@@ -163,7 +163,7 @@ static void esp_apptrace_dummy_task(void *p)
        };
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &arg->timers[i].gptimer));
        *(uint32_t *)arg->timers[i].data.buf = (uint32_t)arg->timers[i].gptimer | (1 << 31);
-        ESP_APPTRACE_TEST_LOGI("%x: start timer %x period %u us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
+        ESP_APPTRACE_TEST_LOGI("%p: start timer %p period %" PRIu32 " us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
        gptimer_alarm_config_t alarm_config = {
            .reload_count = 0,
            .alarm_count = arg->timers[i].data.period,
@@ -180,7 +180,7 @@ static void esp_apptrace_dummy_task(void *p)

    int i = 0;
    while (!arg->stop) {
-        ESP_APPTRACE_TEST_LOGD("%x: dummy task work %d.%d", xTaskGetCurrentTaskHandle(), esp_cpu_get_core_id(), i++);
+        ESP_APPTRACE_TEST_LOGD("%p: dummy task work %d.%d", xTaskGetCurrentTaskHandle(), esp_cpu_get_core_id(), i++);
        if (tmo_ticks) {
            vTaskDelay(tmo_ticks);
        }
@@ -202,7 +202,7 @@ static void esp_apptrace_test_task(void *p)
    int res;
    TickType_t tmo_ticks = arg->data.period / (1000 * portTICK_PERIOD_MS);

-    ESP_APPTRACE_TEST_LOGI("%x: run (period %u us, stamp mask %x, %u timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);
+    ESP_APPTRACE_TEST_LOGI("%p: run (period %" PRIu32 " us, stamp mask %" PRIx8 ", %" PRIu32 " timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);

    for (int i = 0; i < arg->timers_num; i++) {
        gptimer_config_t timer_config = {
@@ -212,7 +212,7 @@ static void esp_apptrace_test_task(void *p)
        };
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &arg->timers[i].gptimer));
        *(uint32_t *)arg->timers[i].data.buf = ((uint32_t)arg->timers[i].gptimer) | (1 << 31) | (esp_cpu_get_core_id() ? 0x1 : 0);
-        ESP_APPTRACE_TEST_LOGI("%x: start timer %x period %u us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
+        ESP_APPTRACE_TEST_LOGI("%p: start timer %p period %" PRIu32 " us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
        gptimer_alarm_config_t alarm_config = {
            .reload_count = 0,
            .alarm_count = arg->timers[i].data.period,
@@ -242,14 +242,14 @@ static void esp_apptrace_test_task(void *p)
        }
        if (res) {
            if (1) { //arg->data.wr_err++ < ESP_APPTRACE_TEST_PRN_WRERR_MAX) {
-                ESP_APPTRACE_TEST_LOGE("%x: Failed to write trace %d %x!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
+                ESP_APPTRACE_TEST_LOGE("%p: Failed to write trace %d %" PRIx32 "!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
                if (arg->data.wr_err == ESP_APPTRACE_TEST_PRN_WRERR_MAX) {
                    ESP_APPTRACE_TEST_LOGE("\n");
                }
            }
        } else {
            if (0) {
-                ESP_APPTRACE_TEST_LOGD("%x:%x: Written chunk%d %d bytes, %x", xTaskGetCurrentTaskHandle(), *ts, arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
+                ESP_APPTRACE_TEST_LOGD("%p:%" PRIx32 ": Written chunk%" PRIu32 " %" PRIu32 " bytes, %" PRIx32, xTaskGetCurrentTaskHandle(), *ts, arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
            }
            arg->data.wr_err = 0;
        }
@@ -273,7 +273,7 @@ static void esp_apptrace_test_task_crash(void *p)
 {
    esp_apptrace_test_task_arg_t *arg = (esp_apptrace_test_task_arg_t *) p;

-    ESP_APPTRACE_TEST_LOGE("%x: run (period %u us, stamp mask %x, %u timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);
+    ESP_APPTRACE_TEST_LOGE("%p: run (period %" PRIu32 " us, stamp mask %" PRIx8 ", %" PRIu32 " timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);

    arg->data.wr_cnt = 0;
    *(uint32_t *)arg->data.buf = (uint32_t)xTaskGetCurrentTaskHandle();
@@ -283,9 +283,9 @@ static void esp_apptrace_test_task_crash(void *p)
        memset(arg->data.buf + sizeof(uint32_t), arg->data.wr_cnt & arg->data.mask, arg->data.buf_sz - sizeof(uint32_t));
        int res = ESP_APPTRACE_TEST_WRITE(arg->data.buf, arg->data.buf_sz);
        if (res) {
-            ESP_APPTRACE_TEST_LOGE("%x: Failed to write trace %d %x!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
+            ESP_APPTRACE_TEST_LOGE("%p: Failed to write trace %d %" PRIx32 "!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
        } else {
-            ESP_APPTRACE_TEST_LOGD("%x: Written chunk%d %d bytes, %x", xTaskGetCurrentTaskHandle(), arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
+            ESP_APPTRACE_TEST_LOGD("%p: Written chunk%" PRIu32 " %" PRIu32 " bytes, %" PRIx32, xTaskGetCurrentTaskHandle(), arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
        }
        arg->data.wr_cnt++;
    }
@@ -315,7 +315,7 @@ static void esp_apptrace_test_ts_init(void)
        .resolution_hz = 10000000,
    };
    TEST_ESP_OK(gptimer_new_timer(&timer_config, &ts_gptimer));
-    ESP_APPTRACE_TEST_LOGI("Use timer %x for TS", ts_gptimer);
+    ESP_APPTRACE_TEST_LOGI("Use timer %p for TS", ts_gptimer);
    TEST_ESP_OK(gptimer_enable(ts_gptimer));
    TEST_ESP_OK(gptimer_start(ts_gptimer));
 }
@@ -368,7 +368,7 @@ static void esp_apptrace_test(esp_apptrace_test_cfg_t *test_cfg)
        TaskHandle_t thnd;
        sprintf(name, "apptrace_test%d", i);
        xTaskCreatePinnedToCore(test_cfg->tasks[i].task_func, name, 2048, &test_cfg->tasks[i], test_cfg->tasks[i].prio, &thnd, test_cfg->tasks[i].core);
-        ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
+        ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
    }
    xTaskCreatePinnedToCore(esp_apptrace_dummy_task, "dummy0", 2048, &dummy_task_arg, dummy_task_arg.prio, NULL, 0);
 #if CONFIG_FREERTOS_UNICORE == 0
@@ -641,7 +641,7 @@ static void esp_logtrace_task(void *p)
 {
    esp_logtrace_task_t *arg = (esp_logtrace_task_t *) p;

-    ESP_APPTRACE_TEST_LOGI("%x: run log test task", xTaskGetCurrentTaskHandle());
+    ESP_APPTRACE_TEST_LOGI("%p: run log test task", xTaskGetCurrentTaskHandle());

    int i = 0;
    while (1) {
@@ -662,7 +662,7 @@ static void esp_logtrace_task(void *p)
        ESP_APPTRACE_TEST_LOGE("Failed to flush printf buf (%d)!", ret);
    }

-    ESP_APPTRACE_TEST_LOGI("%x: finished", xTaskGetCurrentTaskHandle());
+    ESP_APPTRACE_TEST_LOGI("%p: finished", xTaskGetCurrentTaskHandle());

    xSemaphoreGive(arg->done);
    vTaskDelay(1);
@@ -681,13 +681,13 @@ TEST_CASE("Log trace test (2 tasks)", "[trace][ignore]")
    };

    xTaskCreatePinnedToCore(esp_logtrace_task, "logtrace0", 2048, &arg1, 3, &thnd, 0);
-    ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
+    ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
 #if CONFIG_FREERTOS_UNICORE == 0
    xTaskCreatePinnedToCore(esp_logtrace_task, "logtrace1", 2048, &arg2, 3, &thnd, 1);
 #else
    xTaskCreatePinnedToCore(esp_logtrace_task, "logtrace1", 2048, &arg2, 3, &thnd, 0);
 #endif
-    ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
+    ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);

    xSemaphoreTake(arg1.done, portMAX_DELAY);
    vSemaphoreDelete(arg1.done);
@@ -760,7 +760,7 @@ static void esp_sysviewtrace_test_task(void *p)
            xSemaphoreGive(*arg->sync);
        }
    }
-    ESP_APPTRACE_TEST_LOGI("%x: finished", xTaskGetCurrentTaskHandle());
+    ESP_APPTRACE_TEST_LOGI("%p: finished", xTaskGetCurrentTaskHandle());

    xSemaphoreGive(arg->done);
    vTaskDelay(1);
@@ -809,13 +809,13 @@ TEST_CASE("SysView trace test 1", "[trace][ignore]")
    TEST_ESP_OK(gptimer_new_timer(&timer_config, &tim_arg2.gptimer));

    xTaskCreatePinnedToCore(esp_sysviewtrace_test_task, "svtrace0", 2048, &arg1, 3, &thnd, 0);
-    ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
+    ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
 #if CONFIG_FREERTOS_UNICORE == 0
    xTaskCreatePinnedToCore(esp_sysviewtrace_test_task, "svtrace1", 2048, &arg2, 5, &thnd, 1);
 #else
    xTaskCreatePinnedToCore(esp_sysviewtrace_test_task, "svtrace1", 2048, &arg2, 5, &thnd, 0);
 #endif
-    ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
+    ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);

    xSemaphoreTake(arg1.done, portMAX_DELAY);
    vSemaphoreDelete(arg1.done);
--- a/components/app_update/test_apps/.build-test-rules.yml
+++ b/components/app_update/test_apps/.build-test-rules.yml
@@ -2,6 +2,6 @@

 components/app_update/test_apps:
  disable:
-    - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4"]
+    - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4", "esp32c5"]
      temporary: true
-      reason: target esp32c6, esp32h2, esp32p4 is not supported yet # TODO: IDF-8068
+      reason: target esp32c6, esp32h2, esp32p4, esp32c5 is not supported yet # TODO: IDF-8068, [ESP32C5] IDF-8638
--- a/components/app_update/test_apps/CMakeLists.txt
+++ b/components/app_update/test_apps/CMakeLists.txt
@@ -2,6 +2,7 @@
 cmake_minimum_required(VERSION 3.16)

 set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
+set(COMPONENTS main)

 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(app_update_test)
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -6,7 +6,7 @@ menu "Bootloader config"
        hex
        default 0x1000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
        # the first 2 sectors are reserved for the key manager with AES-XTS (flash encryption) purpose
-        default 0x2000 if IDF_TARGET_ESP32P4
+        default 0x2000 if IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32C5
        default 0x0
        help
            Offset address that 2nd bootloader will be flashed to.
@@ -23,7 +23,6 @@ menu "Bootloader config"
            - The default "Size" setting will add the -0s flag to CFLAGS.
            - The "Debug" setting will add the -Og flag to CFLAGS.
            - The "Performance" setting will add the -O2 flag to CFLAGS.
-            - The "None" setting will add the -O0 flag to CFLAGS.

            Note that custom optimization levels may be unsupported.

@@ -34,7 +33,9 @@ menu "Bootloader config"
        config BOOTLOADER_COMPILER_OPTIMIZATION_PERF
            bool "Optimize for performance (-O2)"
        config BOOTLOADER_COMPILER_OPTIMIZATION_NONE
-            bool "Debug without optimization (-O0)"
+            bool "Debug without optimization (-O0) (Deprecated, will be removed in IDF v6.0)"
+            depends on IDF_TARGET_ARCH_XTENSA || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2
+
    endchoice

    choice BOOTLOADER_LOG_LEVEL
@@ -292,8 +293,11 @@ menu "Bootloader config"
            If this option is not set (default), then rtc_wdt will be disabled by ESP-IDF before calling
            the app_main() function.

-            Use function rtc_wdt_feed() for resetting counter of rtc_wdt.
-            Use function rtc_wdt_disable() for disabling rtc_wdt.
+            Use function wdt_hal_feed() for resetting counter of RTC_WDT.
+            For esp32/s2 you can also use rtc_wdt_feed().
+
+            Use function wdt_hal_disable() for disabling RTC_WDT.
+            For esp32/s2 you can also use rtc_wdt_disable().

    config BOOTLOADER_WDT_TIME_MS
        int "Timeout for RTC watchdog (ms)"
@@ -366,7 +370,7 @@ menu "Bootloader config"
        select EFUSE_VIRTUAL_KEEP_IN_FLASH
        help
            This option allows to emulate read/write operations with all eFuses and efuse secure version.
-            It allows to test anti-rollback implemention without permanent write eFuse bits.
+            It allows to test anti-rollback implementation without permanent write eFuse bits.
            There should be an entry in partition table with following details: `emul_efuse, data, efuse, , 0x2000`.

            This option enables: EFUSE_VIRTUAL and EFUSE_VIRTUAL_KEEP_IN_FLASH.
@@ -454,9 +458,24 @@ menu "Bootloader config"
            this area remains valid when rebooted, except for power loss.
            This memory is located at a fixed address and is available
            for both the bootloader and the application.
-            (The application and bootoloader must be compiled with the same option).
+            (The application and bootloader must be compiled with the same option).
            The RTC FAST memory has access only through PRO_CPU.

+    config BOOTLOADER_CUSTOM_RESERVE_RTC_IN_CRC
+        bool "Include custom memory in the CRC calculation"
+        depends on BOOTLOADER_CUSTOM_RESERVE_RTC
+        default n
+        help
+            This option allows the customer to use the legacy bootloader behavior when the
+            RTC FAST memory CRC calculation takes place. When this option is enabled, the
+            allocated user custom data will be taken into account in the CRC calculation.
+            This means that any change to the custom data would need a CRC update to prevent
+            the bootloader from marking this data as corrupted.
+            If this option is disabled, the custom data will not be taken into account when
+            calculating the RTC FAST memory CRC. The user custom data can be changed freely,
+            without the need to update the CRC.
+            THIS OPTION MUST BE THE SAME FOR BOTH THE BOOTLOADER AND THE APPLICATION BUILDS.
+
    config BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE
        hex "Size in bytes for custom purposes"
        default 0
@@ -782,7 +801,7 @@ menu "Security features"
        default N
        help
            When Secure Boot V2 is enabled, by default the bootloader is not flashed along with other artifacts
-            like the application and the partition table images, i.e. bootloader has to be seperately flashed
+            like the application and the partition table images, i.e. bootloader has to be separately flashed
            using the command `idf.py bootloader flash`, whereas, the application and partition table can be flashed
            using the command `idf.py flash` itself.
            Enabling this option allows flashing the bootloader along with the other artifacts
@@ -986,6 +1005,14 @@ menu "Security features"
                Revoking unused digest slots makes ensures that no trusted keys can be added later by an attacker.
                If set, it means that you have a plan to use unused digests slots later.

+                Note that if you plan to enable secure boot during the first boot up, the bootloader will intentionally
+                revoke the unused digest slots while enabling secure boot, even if the above config is enabled because
+                keeping the unused key slots un-revoked would a security hazard.
+                In case for any development workflow if you need to avoid this revocation, you should enable
+                secure boot externally (host based mechanism) rather than enabling it during the boot up,
+                so that the bootloader would not need to enable secure boot and thus you could avoid its revocation
+                strategy.
+
        config SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
            bool "Leave UART bootloader encryption enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
--- a/components/bootloader/subproject/main/CMakeLists.txt
+++ b/components/bootloader/subproject/main/CMakeLists.txt
@@ -1,10 +1,18 @@
 idf_component_register(SRCS "bootloader_start.c"
                    REQUIRES bootloader bootloader_support)

-idf_build_get_property(target IDF_TARGET)
-set(scripts "ld/${target}/bootloader.ld")
+if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    set(target_folder "esp32c5/beta3")
+elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+    set(target_folder "esp32c5/mp")
+else()
+    set(target_folder "${target}")
+endif()

-list(APPEND scripts "ld/${target}/bootloader.rom.ld")
+idf_build_get_property(target IDF_TARGET)
+set(scripts "ld/${target_folder}/bootloader.ld")
+
+list(APPEND scripts "ld/${target_folder}/bootloader.rom.ld")
 target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}")

 target_link_libraries(${COMPONENT_LIB} INTERFACE "-u bootloader_hooks_include")
--- a/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
@@ -0,0 +1,256 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  TODO: [ESP32C5] IDF-9358 Check this file whether need update for MP ROM
+ *  ESP32-C5 ROM static data usage is as follows:
+ *  - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4087ebc0 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4087cbc0).
+ */
+
+/* We consider 0x4087cbc0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4087cbc0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x5000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2200;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4086EBC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    /* we use either libgcc or compiler-rt, so put similar entries for them here */
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.bootdesc : ALIGN(0x10)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ * 0x4086b2b8 ------------------> _dram0_0_start
+ *            |               |
+ *            |               |
+ *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *            |               |
+ *            |               |
+ * 0x4087cbc0 ------------------> __stack_sentry
+ *            |               |
+ *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *            |               |
+ * 0x4087ebc0 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |
+ *            |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *            |               |      (can be freed when IDF runs)
+ *            |               |
+ *            |               |
+ * 0x4087fb14 ------------------> _dram0_rtos_reserved_start
+ *            |               |
+ *            |               |
+ *            |               |   4. Shared memory used in startup code and when IDF runs
+ *            |               |
+ *            |               |
+ * 0x4087fefc ------------------> _dram0_rtos_reserved_end
+ *            |               |
+ * 0x4087ffb8 ------------------> _data_start_interface
+ *            |               |
+ *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *            |               |
+ * 0x40880000 ------------------> _data_end_interface
+ */
--- a/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-C5 target */
--- a/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.ld
@@ -0,0 +1,255 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  ESP32-C5 ROM static data usage is as follows:
+ *  - 0x4084e9a0 - 0x4085c9a0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4085c9a0 - 0x4085e9a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4085e9a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4085c9a0).
+ */
+
+/* We consider 0x4085c9a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4085c9a0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x5000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2200;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4084E9A0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    /* we use either libgcc or compiler-rt, so put similar entries for them here */
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.bootdesc : ALIGN(0x10)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ * 0x4084e9a0 ------------------> _dram0_0_start
+ *            |               |
+ *            |               |
+ *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *            |               |
+ *            |               |
+ * 0x4085c9a0 ------------------> __stack_sentry
+ *            |               |
+ *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *            |               |
+ * 0x4085e9a0 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |
+ *            |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *            |               |      (can be freed when IDF runs)
+ *            |               |
+ *            |               |
+ * 0x4085f500 ------------------> _dram0_rtos_reserved_start
+ *            |               |
+ *            |               |
+ *            |               |   4. Shared memory used in startup code and when IDF runs
+ *            |               |
+ *            |               |
+ * 0x4085fc5c ------------------> _dram0_rtos_reserved_end
+ *            |               |
+ * 0x4085fc70 ------------------> _data_start_interface
+ *            |               |
+ *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *            |               |
+ * 0x40860000 ------------------> _data_end_interface
+ */
--- a/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.rom.ld
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-C5 target */
--- a/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld
@@ -24,7 +24,7 @@ bootloader_usable_dram_end = 0x4087c610;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
 bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
-bootloader_iram_seg_len = 0x2200;
+bootloader_iram_seg_len = 0x2500;

 /* Start of the lower region is determined by region size and the end of the higher region */
 bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
--- a/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld
@@ -0,0 +1,255 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  ESP32-C61 ROM static data usage is as follows:
+ *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4087c610).
+ */
+
+/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4084c9f0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x5000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2500;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c61/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4083E9F0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    /* we use either libgcc or compiler-rt, so put similar entries for them here */
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.bootdesc : ALIGN(0x10)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/** TODO: [ESP32C61] IDF-9405, update after rom freeze
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ * 0x4086ad08 ------------------> _dram0_0_start
+ *            |               |
+ *            |               |
+ *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *            |               |
+ *            |               |
+ * 0x4087c610 ------------------> __stack_sentry
+ *            |               |
+ *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *            |               |
+ * 0x4087e610 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |
+ *            |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *            |               |      (can be freed when IDF runs)
+ *            |               |
+ *            |               |
+ * 0x4087f564 ------------------> _dram0_rtos_reserved_start
+ *            |               |
+ *            |               |
+ *            |               |   4. Shared memory used in startup code and when IDF runs
+ *            |               |
+ *            |               |
+ * 0x4087fab0 ------------------> _dram0_rtos_reserved_end
+ *            |               |
+ * 0x4087fce8 ------------------> _data_start_interface
+ *            |               |
+ *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *            |               |
+ * 0x40880000 ------------------> _data_end_interface
+ */
--- a/components/bootloader/subproject/main/ld/esp32c61/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32c61/bootloader.rom.ld
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-C61 target */
--- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
@@ -25,7 +25,7 @@ bootloader_usable_dram_end = 0x4084cfd0;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
 bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
-bootloader_iram_seg_len = 0x2000;
+bootloader_iram_seg_len = 0x2500;

 /* Start of the lower region is determined by region size and the end of the higher region */
 bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
--- a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld
@@ -24,7 +24,7 @@
 /* These lengths can be adjusted, if necessary: */
 bootloader_usable_dram_end = 0x4ff3abd0;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
-bootloader_dram_seg_len = 0x4000;
+bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
 bootloader_iram_seg_len = 0x2000;

@@ -47,7 +47,7 @@ MEMORY
 * 2. Update the value in this assert.
 * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32p4/memory.ld.in to the same value.
 */
-ASSERT(bootloader_iram_loader_seg_start == 0x4FF2DBD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+ASSERT(bootloader_iram_loader_seg_start == 0x4FF2CBD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");

 /* Default entry point: */
 ENTRY(call_start_cpu0);
@@ -88,6 +88,7 @@ SECTIONS
    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:key_mgr_hal.*(.literal.key_mgr_hal_set_key_usage .text.key_mgr_hal_set_key_usage)
    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
--- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -10,9 +10,9 @@

 MEMORY
 {
-  iram_seg (RWX) :                  org = 0x4004B000, len = 0x4000  /* SRAM part of block 12 and 13 */
-  iram_loader_seg (RWX) :           org = 0x4004F000, len = 0x7000  /* SRAM part of block 13, Block 14 & part of 15 */
-  dram_seg (RW) :                   org = 0x3FFE6000, len = 0x4B00  /* Part SRAM Blocks 15 & 16, ROM static buffer starts at end of this region (reclaimed after app runs) */
+  iram_seg (RWX) :                  org = 0x4004A000, len = 0x4000  /* SRAM part of block 12 and 13 */
+  iram_loader_seg (RWX) :           org = 0x4004E000, len = 0x7000  /* SRAM part of block 13, Block 14 & part of 15 */
+  dram_seg (RW) :                   org = 0x3FFE5000, len = 0x5B00  /* Part SRAM Blocks 15 & 16, ROM static buffer starts at end of this region (reclaimed after app runs) */
 }

 /*  Default entry point:  */
--- a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld
@@ -26,7 +26,7 @@ iram_dram_offset = 0x6f0000;
 /* These lengths can be adjusted, if necessary: */
 bootloader_usable_dram_end = 0x3fce9700;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
-bootloader_dram_seg_len = 0x4000;
+bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
 bootloader_iram_seg_len = 0x3000;

@@ -49,7 +49,7 @@ MEMORY
 * 2. Update the value in this assert.
 * 3. Update SRAM_IRAM_END in components/esp_system/ld/esp32s3/memory.ld.in to the same value.
 */
-ASSERT(bootloader_iram_loader_seg_start == 0x403cc700, "bootloader_iram_loader_seg_start inconsistent with SRAM_IRAM_END");
+ASSERT(bootloader_iram_loader_seg_start == 0x403CB700, "bootloader_iram_loader_seg_start inconsistent with SRAM_IRAM_END");

 /* Default entry point: */
 ENTRY(call_start_cpu0);
--- a/components/bootloader_support/CMakeLists.txt
+++ b/components/bootloader_support/CMakeLists.txt
@@ -86,6 +86,10 @@ if(BOOTLOADER_BUILD)
        endif()
    endif()
 else()
+    if(CONFIG_SOC_SECURE_BOOT_SUPPORTED)
+        list(APPEND srcs "src/${IDF_TARGET}/secure_boot_secure_features.c")
+    endif()
+
    if(CONFIG_SECURE_SIGNED_ON_UPDATE)
        if(CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
            list(APPEND srcs "src/secure_boot_v1/secure_boot_signatures_app.c")
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@@ -187,7 +187,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
        return NULL; /* can't map twice */
    }
    if (size > MMAP_MMU_SIZE) {
-        ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
+        ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %" PRIx32, size);
        return NULL;
    }

@@ -214,13 +214,13 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
 #endif

    //---------------Do mapping------------------------
-    ESP_EARLY_LOGD(TAG, "rodata starts from paddr=0x%08x, size=0x%x, will be mapped to vaddr=0x%08x", src_paddr, size, MMU_BLOCK0_VADDR);
+    ESP_EARLY_LOGD(TAG, "rodata starts from paddr=0x%08" PRIx32 ", size=0x%" PRIx32 ", will be mapped to vaddr=0x%08" PRIx32, src_paddr, size, (uint32_t)MMU_BLOCK0_VADDR);
 #if CONFIG_IDF_TARGET_ESP32
    uint32_t count = GET_REQUIRED_MMU_PAGES(size, src_paddr);
    int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_paddr_aligned, 64, count);
-    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, count * SPI_FLASH_MMU_PAGE_SIZE);
+    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", src_paddr_aligned, (uint32_t)MMU_BLOCK0_VADDR, count * SPI_FLASH_MMU_PAGE_SIZE);
    if (e != 0) {
-        ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
+        ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d", e);
        Cache_Read_Enable(0);
        return NULL;
    }
@@ -231,7 +231,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
     */
    uint32_t actual_mapped_len = 0;
    mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_BLOCK0_VADDR, src_paddr_aligned, size_after_paddr_aligned, &actual_mapped_len);
-    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", src_paddr_aligned, (uint32_t)MMU_BLOCK0_VADDR, actual_mapped_len);
 #endif

    /**
@@ -326,7 +326,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
 #endif

            //---------------Do mapping------------------------
-            ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
+            ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
 #if CONFIG_IDF_TARGET_ESP32
            //Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
            int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
@@ -735,7 +735,7 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
    // If the RDID value is a valid XMC one, may skip the flow
    const bool fast_check = true;
    if (fast_check && is_xmc_chip_strict(g_rom_flashchip.device_id)) {
-        BOOTLOADER_FLASH_LOG(D, "XMC chip detected by RDID (%08X), skip.", g_rom_flashchip.device_id);
+        BOOTLOADER_FLASH_LOG(D, "XMC chip detected by RDID (%08" PRIX32 "), skip.", g_rom_flashchip.device_id);
        return ESP_OK;
    }

--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -11,9 +11,7 @@
 #include "esp_log.h"
 #include "esp_rom_gpio.h"
 #include "esp32c2/rom/spi_flash.h"
-#include "esp32c2/rom/efuse.h"
 #include "soc/gpio_periph.h"
-#include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -36,6 +34,11 @@ void bootloader_flash_update_id()
    chip->device_id = bootloader_read_flash_id();
 }

+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -12,9 +12,7 @@
 #include "esp_rom_gpio.h"
 #include "esp_rom_efuse.h"
 #include "esp32c3/rom/spi_flash.h"
-#include "esp32c3/rom/efuse.h"
 #include "soc/gpio_periph.h"
-#include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -37,6 +35,11 @@ void bootloader_flash_update_id()
    chip->device_id = bootloader_read_flash_id();
 }

+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
@@ -0,0 +1,307 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_rom_gpio.h"
+#include "esp32c5/rom/spi_flash.h"
+#include "esp32c5/rom/efuse.h"
+#include "soc/gpio_periph.h"
+#include "soc/io_mux_reg.h"
+// TODO: IDF-9197
+#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#include "esp_rom_efuse.h"
+#include "soc/efuse_reg.h"
+#endif
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_init.h"
+#include "hal/mmu_hal.h"
+#include "hal/mmu_ll.h"
+#include "hal/cache_hal.h"
+#include "hal/cache_ll.h"
+#include "hal/clk_tree_ll.h"
+
+void bootloader_flash_update_id()
+{
+    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+    chip->device_id = bootloader_read_flash_id();
+}
+
+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        spi_clk_div = 1;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        spi_clk_div = 2;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        spi_clk_div = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        spi_clk_div = 4;
+        break;
+    default:
+        break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+static const char *TAG = "boot.esp32c5";
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+    uint32_t size;
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        size = 1;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        size = 2;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        size = 4;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        size = 8;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        size = 16;
+        break;
+    default:
+        size = 2;
+    }
+    // Set flash chip size
+    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+    ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+    ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+    ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+    ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+    ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+    const char *str;
+    switch (bootloader_hdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        str = "40MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        str = "26.7MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        str = "20MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        str = "80MHz";
+        break;
+    default:
+        str = "20MHz";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
+
+    /* SPI mode could have been set to QIO during boot already,
+       so test the SPI registers not the flash header */
+    esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode();
+    switch (spi_mode) {
+    case ESP_ROM_SPIFLASH_QIO_MODE:
+        str = "QIO";
+        break;
+    case ESP_ROM_SPIFLASH_QOUT_MODE:
+        str = "QOUT";
+        break;
+    case ESP_ROM_SPIFLASH_DIO_MODE:
+        str = "DIO";
+        break;
+    case ESP_ROM_SPIFLASH_DOUT_MODE:
+        str = "DOUT";
+        break;
+    case ESP_ROM_SPIFLASH_FASTRD_MODE:
+        str = "FAST READ";
+        break;
+    default:
+        str = "SLOW READ";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
+
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        str = "1MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        str = "2MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        str = "4MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        str = "8MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        str = "16MB";
+        break;
+    default:
+        str = "2MB";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void IRAM_ATTR bootloader_init_flash_configure(void)
+{
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_cs_timing_config();
+}
+
+static void bootloader_spi_flash_resume(void)
+{
+    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+esp_err_t bootloader_init_spi_flash(void)
+{
+// TODO: IDF-9197
+#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+    // On ESP32C5, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
+    // Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
+    // 80MHz after the switch. PLL = 480MHz, so divider is 6.
+    clk_ll_mspi_fast_set_hs_divider(6);
+#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
+    /* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
+       need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
+       and we need to check flash freq before restart as well */
+    clk_ll_mspi_fast_set_divider(1);
+    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
+#endif
+
+    bootloader_init_flash_configure();
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+    bootloader_enable_qio_mode();
+#endif
+
+    print_flash_info(&bootloader_image_hdr);
+
+    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    update_flash_config(&bootloader_image_hdr);
+    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+    return ESP_OK;
+}
+
+#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr)
+{
+    esp_rom_spiflash_read_mode_t mode;
+    switch(pfhdr->spi_mode) {
+    case ESP_IMAGE_SPI_MODE_QIO:
+        mode = ESP_ROM_SPIFLASH_QIO_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_QOUT:
+        mode = ESP_ROM_SPIFLASH_QOUT_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_DIO:
+        mode = ESP_ROM_SPIFLASH_DIO_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_FAST_READ:
+        mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_SLOW_READ:
+        mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
+        break;
+    default:
+        mode = ESP_ROM_SPIFLASH_DIO_MODE;
+    }
+    esp_rom_spiflash_config_readmode(mode);
+}
+
+void bootloader_flash_hardware_init(void)
+{
+    esp_rom_spiflash_attach(0, false);
+
+    //init cache hal
+    cache_hal_init();
+    //init mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    esp_err_t ret = bootloader_flash_xmc_startup();
+    assert(ret == ESP_OK);
+
+    /* Alternative of bootloader_init_spi_flash */
+    // RAM app doesn't have headers in the flash. Make a default one for it.
+    esp_image_header_t WORD_ALIGNED_ATTR hdr = {
+        .spi_mode = ESP_IMAGE_SPI_MODE_DIO,
+        .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2,
+        .spi_size = ESP_IMAGE_FLASH_SIZE_2MB,
+    };
+
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_set_spi_mode(&hdr);
+    bootloader_flash_clock_config(&hdr);
+    // TODO: set proper dummy output
+    bootloader_flash_cs_timing_config();
+
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    update_flash_config(&hdr);
+    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+}
+#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -10,11 +10,8 @@
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp32c6/rom/spi_flash.h"
-#include "esp32c6/rom/efuse.h"
 #include "soc/gpio_periph.h"
-#include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -34,6 +31,11 @@ void bootloader_flash_update_id()
    chip->device_id = bootloader_read_flash_id();
 }

+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
@@ -0,0 +1,283 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_rom_gpio.h"
+#include "esp32c61/rom/spi_flash.h"
+#include "soc/gpio_periph.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_init.h"
+#include "hal/mmu_hal.h"
+#include "hal/mmu_ll.h"
+#include "hal/cache_hal.h"
+#include "hal/cache_ll.h"
+
+static const char *TAG __attribute__((unused))  = "boot.esp32c61";
+
+void bootloader_flash_update_id()
+{
+    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+    chip->device_id = bootloader_read_flash_id();
+}
+
+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        spi_clk_div = 1;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        spi_clk_div = 2;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        spi_clk_div = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        spi_clk_div = 4;
+        break;
+    default:
+        break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+    uint32_t size;
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        size = 1;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        size = 2;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        size = 4;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        size = 8;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        size = 16;
+        break;
+    default:
+        size = 2;
+    }
+    // Set flash chip size
+    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+    ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+    ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+    ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+    ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+    ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+    const char *str;
+    switch (bootloader_hdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        str = "80MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        str = "40MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        str = "26.7MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+    default:
+        str = "20MHz";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
+
+    /* SPI mode could have been set to QIO during boot already,
+       so test the SPI registers not the flash header */
+    esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode();
+    switch (spi_mode) {
+    case ESP_ROM_SPIFLASH_QIO_MODE:
+        str = "QIO";
+        break;
+    case ESP_ROM_SPIFLASH_QOUT_MODE:
+        str = "QOUT";
+        break;
+    case ESP_ROM_SPIFLASH_DIO_MODE:
+        str = "DIO";
+        break;
+    case ESP_ROM_SPIFLASH_DOUT_MODE:
+        str = "DOUT";
+        break;
+    case ESP_ROM_SPIFLASH_FASTRD_MODE:
+        str = "FAST READ";
+        break;
+    default:
+        str = "SLOW READ";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
+
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        str = "1MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        str = "2MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        str = "4MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        str = "8MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        str = "16MB";
+        break;
+    default:
+        str = "2MB";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void IRAM_ATTR bootloader_init_flash_configure(void)
+{
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_cs_timing_config();
+}
+
+static void bootloader_spi_flash_resume(void)
+{
+    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+esp_err_t bootloader_init_spi_flash(void)
+{
+    bootloader_init_flash_configure();
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+    bootloader_enable_qio_mode();
+#endif
+
+    print_flash_info(&bootloader_image_hdr);
+
+    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    update_flash_config(&bootloader_image_hdr);
+    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+    return ESP_OK;
+}
+
+#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr)
+{
+    esp_rom_spiflash_read_mode_t mode;
+    switch(pfhdr->spi_mode) {
+    case ESP_IMAGE_SPI_MODE_QIO:
+        mode = ESP_ROM_SPIFLASH_QIO_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_QOUT:
+        mode = ESP_ROM_SPIFLASH_QOUT_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_DIO:
+        mode = ESP_ROM_SPIFLASH_DIO_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_FAST_READ:
+        mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_SLOW_READ:
+        mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
+        break;
+    default:
+        mode = ESP_ROM_SPIFLASH_DIO_MODE;
+    }
+    esp_rom_spiflash_config_readmode(mode);
+}
+
+void bootloader_flash_hardware_init(void)
+{
+    esp_rom_spiflash_attach(0, false);
+
+    //init cache hal
+    cache_hal_init();
+    //init mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    esp_err_t ret = bootloader_flash_xmc_startup();
+    assert(ret == ESP_OK);
+
+    /* Alternative of bootloader_init_spi_flash */
+    // RAM app doesn't have headers in the flash. Make a default one for it.
+    esp_image_header_t WORD_ALIGNED_ATTR hdr = {
+        .spi_mode = ESP_IMAGE_SPI_MODE_DIO,
+        .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2,
+        .spi_size = ESP_IMAGE_FLASH_SIZE_2MB,
+    };
+
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_set_spi_mode(&hdr);
+    bootloader_flash_clock_config(&hdr);
+    // TODO: set proper dummy output
+    bootloader_flash_cs_timing_config();
+
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    update_flash_config(&hdr);
+    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+}
+#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -10,11 +10,8 @@
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp32h2/rom/spi_flash.h"
-#include "esp32h2/rom/efuse.h"
 #include "soc/gpio_periph.h"
-#include "soc/efuse_reg.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -35,6 +32,11 @@ void bootloader_flash_update_id()
    chip->device_id = bootloader_read_flash_id();
 }

+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
@@ -28,6 +28,11 @@ void bootloader_flash_update_id()
    chip->device_id = bootloader_read_flash_id();
 }

+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    SET_PERI_REG_MASK(SPI_MEM_C_USER_REG, SPI_MEM_C_CS_HOLD_M | SPI_MEM_C_CS_SETUP_M);
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -41,6 +41,11 @@ void bootloader_flash_update_id()
    chip->device_id = bootloader_read_flash_id();
 }

+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
    //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for FLASH, so we only need to set SPI0 related registers here
--- a/components/bootloader_support/include/esp_app_format.h
+++ b/components/bootloader_support/include/esp_app_format.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -8,6 +8,9 @@
 #include <inttypes.h>
 #include "esp_assert.h"

+// TODO: IDF-9197
+#include "sdkconfig.h"
+
 /**
 * @brief ESP chip ID
 *
@@ -21,7 +24,11 @@ typedef enum {
    ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
    ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
    ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
-    ESP_CHIP_ID_ESP32C5 = 0x0013, /*!< chip ID: ESP32-C5 */
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
+    ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
+#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
+#endif
    ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;

--- a/components/bootloader_support/include/esp_flash_encrypt.h
+++ b/components/bootloader_support/include/esp_flash_encrypt.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -82,7 +82,7 @@ bool esp_flash_encryption_enabled(void);
 * @note RTC_WDT will reset while encryption operations will be performed (if RTC_WDT is configured).
 *
 * @return ESP_OK if all operations succeeded, ESP_ERR_INVALID_STATE
- * if a fatal error occured during encryption of all partitions.
+ * if a fatal error occurred during encryption of all partitions.
 */
 esp_err_t esp_flash_encrypt_check_and_update(void);

@@ -178,12 +178,15 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void);
 */
 void esp_flash_encryption_init_checks(void);

+
+#if BOOTLOADER_BUILD && CONFIG_SECURE_FLASH_ENC_ENABLED
 /** @brief Set all secure eFuse features related to flash encryption
 *
 * @return
 *  - ESP_OK - Successfully
 */
 esp_err_t esp_flash_encryption_enable_secure_features(void);
+#endif /* BOOTLOADER_BUILD && CONFIG_SECURE_FLASH_ENC_ENABLED */

 /** @brief Returns the verification status for all physical security features of flash encryption in release mode
 *
--- a/components/bootloader_support/include/esp_image_format.h
+++ b/components/bootloader_support/include/esp_image_format.h
@@ -33,6 +33,7 @@ typedef struct {
  uint32_t segment_data[ESP_IMAGE_MAX_SEGMENTS]; /* Data offsets for each segment */
  uint32_t image_len; /* Length of image on flash, in bytes */
  uint8_t image_digest[32]; /* appended SHA-256 digest */
+  uint32_t secure_version; /* secure version for anti-rollback, it is covered by sha256 (set if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK=y) */
 } esp_image_metadata_t;

 typedef enum {
--- a/components/bootloader_support/include/esp_secure_boot.h
+++ b/components/bootloader_support/include/esp_secure_boot.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -292,7 +292,7 @@ void esp_secure_boot_init_checks(void);
 * @return
 *  - ESP_OK - At least one signature was found
 *  - ESP_ERR_NOT_FOUND - No signatures were found, num_digests value will be zero
- *  - ESP_FAIL - An error occured trying to read the signature blocks from flash
+ *  - ESP_FAIL - An error occurred trying to read the signature blocks from flash
 */
 esp_err_t esp_secure_boot_get_signature_blocks_for_running_app(bool digest_public_keys, esp_image_sig_public_key_digests_t *public_key_digests);

@@ -300,6 +300,11 @@ esp_err_t esp_secure_boot_get_signature_blocks_for_running_app(bool digest_publi

 /** @brief Set all secure eFuse features related to secure_boot
 *
+ *  @note
+ *      This API needs to be called in the eFuse batch mode.
+ *      i.e. A call to esp_efuse_batch_write_begin() should be made prior to calling this API to start the batch mode
+ *      After the API has been executed a call to esp_efuse_batch_write_commit()/esp_efuse_batch_write_cancel()
+ *      should be made accordingly.
 * @return
 *  - ESP_OK - Successfully
 */
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -9,7 +9,7 @@
 #include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"

-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4// TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 &&! CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-5645
 #include "soc/rtc_cntl_reg.h"
 #else
 #include "soc/lp_wdt_reg.h"
@@ -18,7 +18,7 @@
 #include "soc/pmu_reg.h"
 #endif

-#if CONFIG_IDF_TARGET_ESP32
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C5
 #include "hal/clk_tree_ll.h"
 #endif
 #include "esp_rom_sys.h"
@@ -31,7 +31,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
    // This is not needed on power on reset, when ROM bootloader is running at
    // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
    // and will be done with the bootloader much earlier than UART FIFO is empty.
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);

    /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
    int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
@@ -53,14 +53,21 @@ __attribute__((weak)) void bootloader_clock_configure(void)

        clk_cfg.cpu_freq_mhz = cpu_freq_mhz;

+#if CONFIG_IDF_TARGET_ESP32C5
+        // TODO: [ESP32C5] IDF-9009 Check whether SOC_RTC_SLOW_CLK_SRC_RC_SLOW can be used on C5 MP
+        // RC150K can't do calibrate on ESP32C5MPW so not use it
+        clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
+#else
        // Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
        // RTC_SLOW clock source will be switched according to Kconfig selection at application startup
        clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
        if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
            clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
        }
+#endif

-#if CONFIG_IDF_TARGET_ESP32C6
+//TODO: [ESP32C61] IDF-9274, basic rtc support
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
        // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
        // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
        clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
@@ -87,7 +94,13 @@ __attribute__((weak)) void bootloader_clock_configure(void)
 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL

 // TODO: IDF-8938 Need refactor! Does not belong to clock configuration.
-#if CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG            LP_ANA_LP_INT_ENA_REG
+#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA      LP_ANA_BOD_MODE0_LP_INT_ENA
+#define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG            LP_ANA_LP_INT_CLR_REG
+#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR      LP_ANA_BOD_MODE0_LP_INT_CLR
+#endif
    // CLR ENA
    CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA);                                      /* SWD */
    CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA);                           /* MAIN_TIMER */
--- a/components/bootloader_support/src/bootloader_common_loader.c
+++ b/components/bootloader_support/src/bootloader_common_loader.c
@@ -121,7 +121,7 @@ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata,
 #if CONFIG_BOOTLOADER_RESERVE_RTC_MEM

 static uint32_t rtc_retain_mem_size(void) {
-#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
+#if CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC && !CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_IN_CRC
    /* A custom memory has been reserved by the user, do not consider this memory into CRC calculation as it may change without
     * the have the user updating the CRC. Return the offset of the custom field, which is equivalent to size of the structure
     * minus the size of everything after (including) `custom` */
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -1,30 +1,33 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #include "sdkconfig.h"
 #include "bootloader_console.h"
+#include "soc/soc_caps.h"
 #include "soc/uart_periph.h"
 #include "soc/uart_channel.h"
 #include "soc/io_mux_reg.h"
 #include "soc/gpio_periph.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/rtc.h"
-#include "hal/clk_gate_ll.h"
 #include "hal/gpio_hal.h"
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/usb/cdc_acm.h"
 #include "esp32s2/rom/usb/usb_common.h"
 #endif
-#if SOC_USB_SERIAL_JTAG_SUPPORTED
-#include "hal/usb_fsls_phy_ll.h"
+#if CONFIG_ESP_CONSOLE_USB_CDC
+#include "hal/usb_wrap_ll.h"
 #endif
 #include "esp_rom_gpio.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_caps.h"
+#if CONFIG_IDF_TARGET_ESP32C5
+#include "soc/pcr_reg.h"
+#endif

 #ifdef CONFIG_ESP_CONSOLE_NONE
 void bootloader_console_init(void)
@@ -44,7 +47,7 @@ void bootloader_console_init(void)
    esp_rom_install_uart_printf();

    // Wait for UART FIFO to be empty.
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);

 #if CONFIG_ESP_CONSOLE_UART_CUSTOM
    // Some constants to make the following code less upper-case
@@ -52,7 +55,7 @@ void bootloader_console_init(void)
    const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;

    // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
-    esp_rom_uart_set_as_console(uart_num);
+    esp_rom_output_set_as_console(uart_num);

    // If console is attached to UART1 or if non-default pins are used,
    // need to reconfigure pins using GPIO matrix
@@ -85,6 +88,13 @@ void bootloader_console_init(void)
 #if ESP_ROM_UART_CLK_IS_XTAL
    clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
 #endif
+#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#if CONFIG_IDF_ENV_FPGA
+    clock_hz = CONFIG_XTAL_FREQ * MHZ;
+#else
+    clock_hz = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_CLK_XTAL_FREQ) * MHZ;
+#endif  // CONFIG_IDF_ENV_FPGA
+#endif  // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
    esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 }
 #endif // CONFIG_ESP_CONSOLE_UART
@@ -102,19 +112,25 @@ void bootloader_console_init(void)
    rom_usb_cdc_set_descriptor_patch();
 #endif

-    esp_rom_uart_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
-    esp_rom_uart_set_as_console(ESP_ROM_USB_OTG_NUM);
+    esp_rom_output_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
+    esp_rom_output_set_as_console(ESP_ROM_USB_OTG_NUM);
    esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
-#if SOC_USB_SERIAL_JTAG_SUPPORTED
-    usb_fsls_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
-    usb_fsls_phy_ll_int_otg_enable(&USB_WRAP);
-#endif
+    // Ensure that the USB FSLS PHY is mapped to the USB WRAP
+    usb_wrap_ll_phy_enable_pad(&USB_WRAP, true);
+    usb_wrap_ll_phy_enable_external(&USB_WRAP, false);
 }
 #endif //CONFIG_ESP_CONSOLE_USB_CDC

 #ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
 void bootloader_console_init(void)
 {
-    esp_rom_uart_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM);
+    esp_rom_output_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM);
+
+    /* Switch console channel to avoid output on UART and allow  */
+    esp_rom_output_set_as_console(ESP_ROM_USB_SERIAL_DEVICE_NUM);
+
+    /* ROM printf by default also prints to USB-Serial-JTAG on channel 2
+       need to disable to not print twice */
+    esp_rom_install_channel_putc(2, NULL);
 }
 #endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
--- a/components/bootloader_support/src/bootloader_console_loader.c
+++ b/components/bootloader_support/src/bootloader_console_loader.c
@@ -67,7 +67,7 @@ void bootloader_console_deinit(void)
 {
 #ifdef CONFIG_ESP_CONSOLE_UART
    /* Ensure any buffered log output is displayed */
-    esp_rom_uart_flush_tx(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_flush_tx(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 #endif // CONFIG_ESP_CONSOLE_UART

 #ifdef CONFIG_ESP_CONSOLE_USB_CDC
--- a/components/bootloader_support/src/bootloader_efuse.c
+++ b/components/bootloader_support/src/bootloader_efuse.c
@@ -30,6 +30,12 @@ int bootloader_clock_get_rated_freq_mhz(void)
 #elif CONFIG_IDF_TARGET_ESP32C6
    return 160;

+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: [ESP32C61] IDF-9282
+    return 160;
+
+#elif CONFIG_IDF_TARGET_ESP32C5
+    return 160;
+
 #elif CONFIG_IDF_TARGET_ESP32H2
    //IDF-6570
    return 96;
--- a/components/bootloader_support/src/bootloader_init.c
+++ b/components/bootloader_support/src/bootloader_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
--- a/components/bootloader_support/src/bootloader_mem.c
+++ b/components/bootloader_support/src/bootloader_mem.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -16,6 +16,12 @@
 #include "hal/apm_hal.h"
 #endif

+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-8615 Remove the workaround when APM supported on C5!
+#include "soc/hp_apm_reg.h"
+#include "soc/lp_apm_reg.h"
+#include "soc/lp_apm0_reg.h"
+#endif
+
 void bootloader_init_mem(void)
 {

@@ -30,8 +36,15 @@ void bootloader_init_mem(void)
    apm_hal_apm_ctrl_filter_enable_all(false);
 #endif

+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-8615 Remove the workaround when APM supported on C5!
+    // disable apm filter
+    REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
+    REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
+    REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
+#endif
+
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
    // protect memory region
-    esp_cpu_configure_region_protection();
+    esp_cpu_configure_region_protection();  // TODO: [ESP32C5] IDF-8833 PSRAM support write
 #endif
 }
--- a/components/bootloader_support/src/bootloader_random.c
+++ b/components/bootloader_support/src/bootloader_random.c
@@ -28,6 +28,9 @@
  #if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
    #define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
                                             // tested.
+  #elif CONFIG_IDF_TARGET_ESP32P4
+    // bootloader tested with around 63 KHz bytes reading frequency
+    #define RNG_CPU_WAIT_CYCLE_NUM (CPU_CLK_FREQ_MHZ_BTLD * 16)
  #else
    #define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
  #endif
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -0,0 +1,23 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "soc/pcr_reg.h"
+#include "soc/pmu_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "esp_log.h"
+
+void bootloader_random_enable(void)
+{
+// TODO: [ESP32C5] IDF-8626, IDF-9197
+    ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
+}
+
+void bootloader_random_disable(void)
+{
+// TODO: [ESP32C5] IDF-8626, IDF-9197
+    ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
+}
--- a/components/bootloader_support/src/bootloader_random_esp32p4.c
+++ b/components/bootloader_support/src/bootloader_random_esp32p4.c
@@ -1,22 +1,100 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
-#include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "esp_log.h"
+#include "soc/soc.h"
+#include "soc/adc_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/regi2c_saradc.h"
+#include "soc/hp_sys_clkrst_reg.h"
+#include "soc/rtcadc_reg.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "esp_rom_regi2c.h"

-static const char *TAG = "bootloader_random";
+// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
+
+#define I2C_SAR_ADC_INIT_CODE_VAL 2166
+
+typedef struct {
+    int atten;
+    int channel;
+} pattern_item;
+
+typedef struct {
+    pattern_item item[4];
+} pattern_table;
+
+static void adc1_fix_initcode_set(uint32_t initcode_value)
+{
+    uint32_t msb = initcode_value >> 8;
+    uint32_t lsb = initcode_value & 0xff;
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, msb);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, lsb);
+}
+
+//total 4 tables
+static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
+{
+    uint32_t wdata = 0;
+    wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
+            table.item[1].channel << 14|table.item[1].atten << 12 |
+            table.item[2].channel << 8 |table.item[2].atten << 6 |
+            table.item[3].channel << 2 |table.item[3].atten);
+    WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
+}

 void bootloader_random_enable(void)
 {
-    // TODO: IDF-6522
-    ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
+    pattern_table sar1_table[4] = {};
+    uint32_t pattern_len = 0;
+
+    SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
+    SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
+
+    SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
+
+    uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
+            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
+            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
+
+    SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
+
+    adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
+
+    //  cfg pattern table
+    sar1_table[0].item[0].channel = 10; //rand() % 6;
+    sar1_table[0].item[0].atten = 3;
+    sar1_table[0].item[1].channel = 10;
+    sar1_table[0].item[1].atten = 3;
+    sar1_table[0].item[2].channel = 10;
+    sar1_table[0].item[2].atten = 3;
+    sar1_table[0].item[3].channel = 10;
+    sar1_table[0].item[3].atten = 3;
+
+    hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
+    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
+
+    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
+    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
+
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
+
+    CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
+    SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
+    SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
+
+    while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
+
+    SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
 }

 void bootloader_random_disable(void)
 {
-    // TODO: IDF-6522
-    ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
+    // No-op for now TODO IDF-6497
+    // ADC should be set to defaults here, once ADC API is implemented
+    // OR just keep this empty and let application continue to use RNG initialized by the bootloader
 }
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -15,33 +15,7 @@
 #include "esp_rom_uart.h"
 #include "sdkconfig.h"
 #if CONFIG_IDF_TARGET_ESP32
-#include "soc/dport_reg.h"
 #include "esp32/rom/cache.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#elif CONFIG_IDF_TARGET_ESP32S3
-#elif CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/rom/efuse.h"
-#include "esp32c3/rom/crc.h"
-#include "esp32c3/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/efuse.h"
-#include "esp32c2/rom/crc.h"
-#include "esp32c2/rom/rtc.h"
-#include "esp32c2/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
-#include "esp32c6/rom/efuse.h"
-#include "esp32c6/rom/crc.h"
-#include "esp32c6/rom/rtc.h"
-#include "esp32c6/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/efuse.h"
-#include "esp32h2/rom/crc.h"
-#include "esp32h2/rom/rtc.h"
-#include "esp32h2/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32P4
-
-#else // CONFIG_IDF_TARGET_*
-#error "Unsupported IDF_TARGET"
 #endif
 #include "esp_rom_spiflash.h"

@@ -442,8 +416,7 @@ static bool try_load_partition(const esp_partition_pos_t *partition, esp_image_m
    }
 #ifdef BOOTLOADER_BUILD
    if (bootloader_load_image(partition, data) == ESP_OK) {
-        ESP_LOGI(TAG, "Loaded app from partition at offset 0x%x",
-                 partition->offset);
+        ESP_LOGI(TAG, "Loaded app from partition at offset 0x%" PRIx32, partition->offset);
        return true;
    }
 #endif
@@ -642,7 +615,25 @@ static void load_image(const esp_image_metadata_t *image_data)
     */
    ESP_LOGI(TAG, "Checking flash encryption...");
    bool flash_encryption_enabled = esp_flash_encrypt_state();
-    if (!flash_encryption_enabled) {
+    if (flash_encryption_enabled) {
+#if BOOTLOADER_BUILD
+        /* Ensure security eFuses are burnt */
+        esp_efuse_batch_write_begin();
+        esp_err_t err = esp_flash_encryption_enable_secure_features();
+        if (err != ESP_OK) {
+            ESP_LOGE(TAG, "Error setting security eFuses (err=0x%x).", err);
+            esp_efuse_batch_write_cancel();
+            return;
+        }
+
+        err = esp_efuse_batch_write_commit();
+        if (err != ESP_OK) {
+            ESP_LOGE(TAG, "Error programming security eFuses (err=0x%x).", err);
+            return;
+        }
+        ESP_LOGI(TAG, "Security eFuses are burnt");
+#endif // BOOTLOADER_BUILD
+    } else {
 #ifdef CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED
        ESP_LOGE(TAG, "flash encryption is not enabled, and SECURE_FLASH_REQUIRE_ALREADY_ENABLED is set, refusing to boot.");
        return;
@@ -707,7 +698,7 @@ static void load_image(const esp_image_metadata_t *image_data)
           so issue a system reset to ensure flash encryption
           cache resets properly */
        ESP_LOGI(TAG, "Resetting with flash encryption enabled...");
-        esp_rom_uart_tx_wait_idle(0);
+        esp_rom_output_tx_wait_idle(0);
        bootloader_reset();
    }
 #endif
@@ -837,7 +828,7 @@ static void set_cache_and_start_app(
    //-----------------------MAP DROM--------------------------
    uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
    uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK;
-    ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", drom_addr, drom_load_addr, drom_size);
+    ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08" PRIx32 ", vaddr=0x%08" PRIx32 ", size=0x%" PRIx32, drom_addr, drom_load_addr, drom_size);
    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
    drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
 #if CONFIG_IDF_TARGET_ESP32
@@ -846,17 +837,17 @@ static void set_cache_and_start_app(
    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
    rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
-    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
+    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
 #else
    uint32_t actual_mapped_len = 0;
    mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
-    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
 #endif

    //-----------------------MAP IROM--------------------------
    uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
    uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK;
-    ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", irom_addr, irom_load_addr, irom_size);
+    ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08" PRIx32 ", vaddr=0x%08" PRIx32 ", size=0x%" PRIx32, irom_addr, irom_load_addr, irom_size);
    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
    irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
 #if CONFIG_IDF_TARGET_ESP32
@@ -865,10 +856,10 @@ static void set_cache_and_start_app(
    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
    rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
    ESP_LOGV(TAG, "rc=%d", rc);
-    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
+    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
 #else
    mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
-    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
 #endif

    //----------------------Enable corresponding buses----------------
--- a/components/bootloader_support/src/esp32/flash_encryption_secure_features.c
+++ b/components/bootloader_support/src/esp32/flash_encryption_secure_features.c
@@ -35,7 +35,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
        crypt_config = EFUSE_FLASH_CRYPT_CONFIG;
        esp_efuse_write_field_blob(ESP_EFUSE_ENCRYPT_CONFIG, &crypt_config, 4);
    } else if (crypt_config != EFUSE_FLASH_CRYPT_CONFIG) {
-        ESP_LOGE(TAG, "EFUSE_ENCRYPT_CONFIG should be set 0xF but it is 0x%x", crypt_config);
+        ESP_LOGE(TAG, "EFUSE_ENCRYPT_CONFIG should be set 0xF but it is 0x%" PRIx32, crypt_config);
    }

 #ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
--- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
+++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
@@ -10,11 +10,9 @@
 #include "esp_image_format.h"
 #include "flash_qio_mode.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
-#include "soc/efuse_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/io_mux_reg.h"
 #include "soc/assist_debug_reg.h"
@@ -24,7 +22,6 @@
 #include "soc/extmem_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/system_reg.h"
-#include "esp32c2/rom/efuse.h"
 #include "esp32c2/rom/ets_sys.h"
 #include "esp32c2/rom/rtc.h"
 #include "bootloader_common.h"
--- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
+++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
@@ -10,11 +10,9 @@
 #include "esp_image_format.h"
 #include "flash_qio_mode.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
-#include "soc/efuse_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/io_mux_reg.h"
 #include "soc/assist_debug_reg.h"
@@ -26,7 +24,6 @@
 #include "soc/io_mux_reg.h"
 #include "soc/system_reg.h"
 #include "soc/chip_revision.h"
-#include "esp32c3/rom/efuse.h"
 #include "esp32c3/rom/ets_sys.h"
 #include "bootloader_common.h"
 #include "bootloader_init.h"
--- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
+++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
@@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_image_format.h"
+#include "flash_qio_mode.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "esp_rom_spiflash.h"
+#include "soc/soc_caps.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/io_mux_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "esp_cpu.h"
+#include "soc/rtc.h"
+#include "soc/spi_periph.h"
+#include "soc/cache_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/pcr_reg.h"
+#include "esp32c5/rom/ets_sys.h"
+#include "esp32c5/rom/spi_flash.h"
+#include "bootloader_common.h"
+#include "bootloader_init.h"
+#include "bootloader_clock.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "bootloader_console.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_soc.h"
+#include "esp_private/bootloader_flash_internal.h"
+#include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/lp_wdt_reg.h"
+#include "hal/efuse_hal.h"
+#include "hal/lpwdt_ll.h"
+#if SOC_MODEM_CLOCK_SUPPORTED
+#include "modem/modem_lpcon_reg.h"
+#endif
+
+static const char *TAG = "boot.esp32c5";
+
+static void wdt_reset_cpu0_info_enable(void)
+{
+    REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
+    REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
+    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
+}
+
+static void bootloader_check_wdt_reset(void)
+{
+    int wdt_rst = 0;
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
+        rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
+        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+        wdt_rst = 1;
+    }
+    if (wdt_rst) {
+        // if reset by WDT dump info from trace port
+        wdt_reset_info_dump(0);
+    }
+    wdt_reset_cpu0_info_enable();
+}
+
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
+    REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
+}
+
+static inline void bootloader_hardware_init(void)
+{
+    /* Enable analog i2c master clock */
+#if SOC_MODEM_CLOCK_SUPPORTED
+    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+#endif
+}
+
+static inline void bootloader_ana_reset_config(void)
+{
+    // TODO: [ESP32C5] IDF-8650
+    //Enable super WDT reset.
+    // bootloader_ana_super_wdt_reset_config(true);
+    // TODO: [ESP32C5] IDF-8647
+    //Enable BOD reset
+    // bootloader_ana_bod_reset_config(true);
+}
+
+esp_err_t bootloader_init(void)
+{
+    esp_err_t ret = ESP_OK;
+
+    bootloader_hardware_init();
+    bootloader_ana_reset_config();
+    bootloader_super_wdt_auto_feed();
+
+// In RAM_APP, memory will be initialized in `call_start_cpu0`
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    // protect memory region
+    bootloader_init_mem();
+    /* check that static RAM is after the stack */
+    assert(&_bss_start <= &_bss_end);
+    assert(&_data_start <= &_data_end);
+    // clear bss section
+    bootloader_clear_bss_section();
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // init eFuse virtual mode (read eFuses to RAM)
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_init_virtual_mode_in_ram();
+#endif
+#endif
+    // config clock
+    bootloader_clock_configure();
+    // initialize console, from now on, we can use esp_log
+    bootloader_console_init();
+    /* print 2nd bootloader banner */
+    bootloader_print_banner();
+
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    //init cache hal
+    cache_hal_init();
+    //init mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
+        ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
+        return ret;
+    }
+    // read bootloader header
+    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
+        return ret;
+    }
+    // read chip revision and check if it's compatible to bootloader
+    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
+        return ret;
+    }
+    // initialize spi flash
+    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
+        return ret;
+    }
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // check whether a WDT reset happend
+    bootloader_check_wdt_reset();
+    // config WDT
+    bootloader_config_wdt();
+    // enable RNG early entropy source
+    bootloader_enable_random();
+
+    return ret;
+}
--- a/components/bootloader_support/src/esp32c5/bootloader_sha.c
+++ b/components/bootloader_support/src/esp32c5/bootloader_sha.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "bootloader_sha.h"
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <sys/param.h>
+
+#include "esp32c5/rom/sha.h"
+
+static SHA_CTX ctx;
+
+bootloader_sha256_handle_t bootloader_sha256_start()
+{
+    // Enable SHA hardware
+    ets_sha_enable();
+    ets_sha_init(&ctx, SHA2_256);
+    return &ctx; // Meaningless non-NULL value
+}
+
+void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
+{
+    assert(handle != NULL);
+    /* C5 secure boot key field consists of 1 byte of curve identifier and 64 bytes of ECDSA public key.
+     * While verifying the signature block, we need to calculate the SHA of this key field which is of 65 bytes.
+     * ets_sha_update handles it cleanly so we can safely remove the check:
+     * assert(data_len % 4) == 0
+     */
+    ets_sha_update(&ctx, data, data_len, false);
+}
+
+void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
+{
+    assert(handle != NULL);
+
+    if (digest == NULL) {
+        bzero(&ctx, sizeof(ctx));
+        return;
+    }
+    ets_sha_finish(&ctx, digest);
+}
--- a/components/bootloader_support/src/esp32c5/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c5/bootloader_soc.c
@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "soc/soc.h"
+#include "soc/lp_analog_peri_reg.h"
+// TODO: [ESP32C5] IDF-8667 remove esp_log.h
+#include "esp_log.h"
+
+void bootloader_ana_super_wdt_reset_config(bool enable)
+{
+    // TODO: [ESP32C5] IDF-8667
+    ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
+}
+
+void bootloader_ana_bod_reset_config(bool enable)
+{
+     // TODO: [ESP32C5] IDF-8667
+    ESP_EARLY_LOGW("bootloader", "bootloader_ana_bod_reset_config() has not been implemented on C5 yet");
+}
+
+//Not supported but common bootloader calls the function. Do nothing
+void bootloader_ana_clock_glitch_reset_config(bool enable)
+{
+     // TODO: [ESP32C5] IDF-8667
+    (void)enable;
+}
--- a/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
+++ b/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
@@ -23,12 +23,13 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
 #endif

-#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
-    ESP_LOGI(TAG, "Disable UART bootloader cache...");
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-#else
-    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
-#endif
+// TODO: [ESP32C5] IDF-8623 check if the following code is still supported
+// #ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
+//     ESP_LOGI(TAG, "Disable UART bootloader cache...");
+//     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
+// #else
+//     ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
+// #endif

 #ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
    ESP_LOGI(TAG, "Disable JTAG...");
--- a/components/bootloader_support/src/esp32c5/secure_boot_secure_features.c
+++ b/components/bootloader_support/src/esp32c5/secure_boot_secure_features.c
@@ -0,0 +1,70 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "secure_boot";
+
+esp_err_t esp_secure_boot_enable_secure_features(void)
+{
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Enabling Security download mode...");
+    esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not enable Security download mode...");
+        return err;
+    }
+#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Disable ROM Download mode...");
+    esp_err_t err = esp_efuse_disable_rom_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not disable ROM Download mode...");
+        return err;
+    }
+#else
+    ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable hardware & software JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+    esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
+
+#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
+    bool rd_dis_now = true;
+#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
+    /* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
+       when Flash Encryption is being enabled */
+    rd_dis_now = esp_flash_encryption_enabled();
+#endif
+    if (rd_dis_now) {
+        ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
+        esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+    }
+#else
+    ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
+#endif
+
+    return ESP_OK;
+}
--- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
+++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
@@ -10,7 +10,6 @@
 #include "esp_image_format.h"
 #include "flash_qio_mode.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
@@ -23,7 +22,6 @@
 #include "soc/extmem_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/pcr_reg.h"
-#include "esp32c6/rom/efuse.h"
 #include "esp32c6/rom/ets_sys.h"
 #include "esp32c6/rom/spi_flash.h"
 #include "bootloader_common.h"
--- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
@@ -0,0 +1,179 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_image_format.h"
+#include "flash_qio_mode.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "esp_rom_spiflash.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/io_mux_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "esp_cpu.h"
+#include "soc/rtc.h"
+#include "soc/spi_periph.h"
+#include "soc/cache_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/pcr_reg.h"
+#include "esp32c61/rom/ets_sys.h"
+#include "esp32c61/rom/spi_flash.h"
+#include "bootloader_common.h"
+#include "bootloader_init.h"
+#include "bootloader_clock.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_bias.h"
+#include "bootloader_console.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_soc.h"
+#include "esp_private/bootloader_flash_internal.h"
+#include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/lp_wdt_reg.h"
+#include "hal/efuse_hal.h"
+#include "hal/lpwdt_ll.h"
+
+static const char *TAG = "boot.esp32c61";
+
+static void wdt_reset_cpu0_info_enable(void)
+{
+    REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
+    REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
+    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
+}
+
+static void bootloader_check_wdt_reset(void)
+{
+    int wdt_rst = 0;
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
+        rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
+        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+        wdt_rst = 1;
+    }
+    if (wdt_rst) {
+        // if reset by WDT dump info from trace port
+        wdt_reset_info_dump(0);
+    }
+    wdt_reset_cpu0_info_enable();
+}
+
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
+    REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
+}
+
+static inline void bootloader_hardware_init(void)
+{
+    // In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here
+#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM
+    clk_ll_mspi_fast_set_hs_divider(6);
+    esp_rom_spiflash_config_clk(1, 0);
+    esp_rom_spiflash_config_clk(1, 1);
+    esp_rom_spiflash_fix_dummylen(0, 1);
+    esp_rom_spiflash_fix_dummylen(1, 1);
+#endif
+
+//TODO: [ESP32C61] IDF-9276
+#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    ESP_EARLY_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
+#else
+    ESP_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
+#endif
+}
+
+static inline void bootloader_ana_reset_config(void)
+{
+    //Enable super WDT reset.
+    bootloader_ana_super_wdt_reset_config(true);
+    //Enable BOD reset
+    bootloader_ana_bod_reset_config(true);
+}
+
+esp_err_t bootloader_init(void)
+{
+    esp_err_t ret = ESP_OK;
+    bootloader_hardware_init();
+    // bootloader_ana_reset_config();   //TODO: [ESP32C61] IDF-9260
+    bootloader_super_wdt_auto_feed();
+
+// In RAM_APP, memory will be initialized in `call_start_cpu0`
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    // protect memory region
+    bootloader_init_mem();
+    /* check that static RAM is after the stack */
+    assert(&_bss_start <= &_bss_end);
+    assert(&_data_start <= &_data_end);
+    // clear bss section
+    bootloader_clear_bss_section();
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // init eFuse virtual mode (read eFuses to RAM)
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_init_virtual_mode_in_ram();
+#endif
+#endif
+    // config clock
+    bootloader_clock_configure();
+    // initialize console, from now on, we can use esp_log
+    bootloader_console_init();
+    /* print 2nd bootloader banner */
+    bootloader_print_banner();
+
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    //init cache hal
+    cache_hal_init();
+    //init mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
+        ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
+        return ret;
+    }
+    // read bootloader header
+    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
+        return ret;
+    }
+    // read chip revision and check if it's compatible to bootloader
+    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
+        return ret;
+    }
+    // initialize spi flash
+    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
+        return ret;
+    }
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // check whether a WDT reset happened
+    bootloader_check_wdt_reset();
+    // config WDT
+    bootloader_config_wdt();
+    // enable RNG early entropy source
+    bootloader_enable_random();
+
+    return ret;
+}
--- a/components/bootloader_support/src/esp32c61/bootloader_sha.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_sha.c
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "bootloader_sha.h"
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <sys/param.h>
+
+#include "esp32c61/rom/sha.h"
+
+static SHA_CTX ctx;
+
+//TODO: [ESP32C61] IDF-9234
+
+bootloader_sha256_handle_t bootloader_sha256_start()
+{
+    // Enable SHA hardware
+    ets_sha_enable();
+    ets_sha_init(&ctx, SHA2_256);
+    return &ctx; // Meaningless non-NULL value
+}
+
+void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
+{
+    assert(handle != NULL);
+    /* C61 secure boot key field consists of 1 byte of curve identifier and 64 bytes of ECDSA public key.
+     * While verifying the signature block, we need to calculate the SHA of this key field which is of 65 bytes.
+     * ets_sha_update handles it cleanly so we can safely remove the check:
+     * assert(data_len % 4) == 0
+     */
+    ets_sha_update(&ctx, data, data_len, false);
+}
+
+void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
+{
+    assert(handle != NULL);
+
+    if (digest == NULL) {
+        bzero(&ctx, sizeof(ctx));
+        return;
+    }
+    ets_sha_finish(&ctx, digest);
+}
--- a/components/bootloader_support/src/esp32c61/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_soc.c
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "soc/soc.h"
+#include "soc/lp_analog_peri_reg.h"
+
+//TODO: [ESP32C61] IDF-9260, commented in verify code, check
+
+void bootloader_ana_super_wdt_reset_config(bool enable)
+{
+    //C61 doesn't support bypass super WDT reset
+    assert(enable);
+    // lp_analog_peri_reg.h updated, now following registers
+    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
+}
+
+void bootloader_ana_bod_reset_config(bool enable)
+{
+    // lp_analog_peri_reg.h updated, now following registers
+    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
+
+    if (enable) {
+        REG_SET_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
+    } else {
+        REG_CLR_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
+    }
+}
+
+//Not supported but common bootloader calls the function. Do nothing
+void bootloader_ana_clock_glitch_reset_config(bool enable)
+{
+    (void)enable;
+}
--- a/components/bootloader_support/src/esp32c61/flash_encryption_secure_features.c
+++ b/components/bootloader_support/src/esp32c61/flash_encryption_secure_features.c
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "flash_encrypt";
+
+esp_err_t esp_flash_encryption_enable_secure_features(void)
+{
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
+    ESP_LOGI(TAG, "Disable UART bootloader encryption...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
+#endif
+
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
+    ESP_LOGI(TAG, "Disable UART bootloader cache...");
+    esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
+    // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
+    // otherwise the Flash Encryption key cannot be read protected
+    esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+#endif
+
+#ifndef CONFIG_SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE
+    // Set write-protection for DIS_ICACHE to prevent bricking chip in case it will be set accidentally.
+    // esp32c61 has DIS_ICACHE. Write-protection bit = 2.
+    // List of eFuses with the same write protection bit:
+    // SWAP_UART_SDIO_EN, DIS_ICACHE, DIS_USB_JTAG, DIS_DOWNLOAD_ICACHE,
+    // DIS_USB_SERIAL_JTAG, DIS_FORCE_DOWNLOAD, DIS_TWAI, JTAG_SEL_ENABLE,
+    // DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT.
+    esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_ICACHE);
+#endif
+
+    return ESP_OK;
+}
--- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
@@ -10,7 +10,6 @@
 #include "esp_image_format.h"
 #include "flash_qio_mode.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
@@ -23,7 +22,6 @@
 #include "soc/extmem_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/pcr_reg.h"
-#include "esp32h2/rom/efuse.h"
 #include "esp32h2/rom/ets_sys.h"
 #include "bootloader_common.h"
 #include "bootloader_init.h"
@@ -43,6 +41,7 @@
 #include "hal/cache_hal.h"
 #include "hal/lpwdt_ll.h"
 #include "soc/lp_wdt_reg.h"
+#include "soc/pmu_reg.h"
 #include "hal/efuse_hal.h"
 #include "modem/modem_lpcon_reg.h"

@@ -87,6 +86,9 @@ static void bootloader_super_wdt_auto_feed(void)

 static inline void bootloader_hardware_init(void)
 {
+    /* Disable RF pll by default */
+    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
    /* Enable analog i2c master clock */
    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
 }
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -10,7 +10,6 @@
 #include "esp_image_format.h"
 #include "flash_qio_mode.h"
 #include "esp_rom_gpio.h"
-#include "esp_rom_efuse.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
@@ -22,7 +21,6 @@
 #include "soc/spi_periph.h"
 #include "soc/cache_reg.h"
 #include "soc/io_mux_reg.h"
-#include "esp32p4/rom/efuse.h"
 #include "esp32p4/rom/ets_sys.h"
 #include "esp32p4/rom/spi_flash.h"
 #include "bootloader_common.h"
@@ -46,6 +44,7 @@
 #include "hal/efuse_hal.h"
 #include "soc/regi2c_syspll.h"
 #include "soc/regi2c_cpll.h"
+#include "soc/regi2c_bias.h"

 static const char *TAG = "boot.esp32p4";

@@ -66,8 +65,8 @@ static void bootloader_check_wdt_reset(void)
 {
    int wdt_rst = 0;
    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
-    if (rst_reason == RESET_REASON_SYS_HP_WDT || rst_reason == RESET_REASON_SYS_LP_WDT || rst_reason == RESET_REASON_CORE_HP_WDT ||
-        rst_reason == RESET_REASON_CORE_LP_WDT || rst_reason == RESET_REASON_CHIP_LP_WDT) {
+    if (rst_reason == RESET_REASON_CPU_MWDT || rst_reason == RESET_REASON_CPU_RWDT || rst_reason == RESET_REASON_CORE_MWDT ||
+        rst_reason == RESET_REASON_CORE_RWDT || rst_reason == RESET_REASON_SYS_RWDT) {
        ESP_LOGW(TAG, "CPU has been reset by WDT.");
        wdt_rst = 1;
    }
@@ -99,6 +98,8 @@ static inline void bootloader_hardware_init(void)
    REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
    REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
    esp_rom_delay_us(100);
+    REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
+    REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
 }

 static inline void bootloader_ana_reset_config(void)
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -11,25 +11,17 @@
 #include <esp_fault.h>
 #include <esp_log.h>
 #include <esp_attr.h>
-#include <spi_flash_mmap.h>
 #include <bootloader_flash_priv.h>
 #include <bootloader_random.h>
 #include <bootloader_sha.h>
 #include "bootloader_util.h"
 #include "bootloader_common.h"
 #include "esp_rom_sys.h"
+#include "esp_efuse.h"
+#include "esp_app_desc.h"
 #include "bootloader_memory_utils.h"
 #include "soc/soc_caps.h"
 #include "hal/cache_ll.h"
-#if CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
-#include "esp32c6/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32P4
-#include "esp32p4/rom/rtc.h"
-#endif

 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))

@@ -76,10 +68,10 @@ static bool should_map(uint32_t load_addr);

 static esp_err_t process_segments(esp_image_metadata_t *data, bool silent, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum);
 /* Load or verify a segment */
-static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segment_header_t *header, bool silent, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum);
+static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segment_header_t *header, bool silent, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum, esp_image_metadata_t *metadata);

 /* split segment and verify if data_len is too long */
-static esp_err_t process_segment_data(intptr_t load_addr, uint32_t data_addr, uint32_t data_len, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum);
+static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t data_addr, uint32_t data_len, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum, esp_image_metadata_t *metadata);

 /* Verify the main image header */
 static esp_err_t verify_image_header(uint32_t src_addr, const esp_image_header_t *image, bool silent);
@@ -224,9 +216,26 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
            }
        }
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+        /* We have manipulated data over dcache that will be read over icache and need
+           to writeback, else the data read might be invalid */
        cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
 #endif
    }
+
+#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
+    /* For anti-rollback case, reconfirm security version of the application to prevent FI attacks */
+    bool sec_ver = false;
+    if (do_load) {
+        sec_ver = esp_efuse_check_secure_version(data->secure_version);
+        if (!sec_ver) {
+            err = ESP_FAIL;
+            goto err;
+        }
+    }
+    /* Ensure that the security version check passes for image loading scenario */
+    ESP_FAULT_ASSERT(!do_load || sec_ver == true);
+#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
+
 #endif // BOOTLOADER_BUILD

    // Success!
@@ -509,7 +518,7 @@ static esp_err_t process_segments(esp_image_metadata_t *data, bool silent, bool
    for (int i = 0; i < data->image.segment_count; i++) {
        esp_image_segment_header_t *header = &data->segments[i];
        ESP_LOGV(TAG, "loading segment header %d at offset 0x%"PRIx32, i, next_addr);
-        CHECK_ERR(process_segment(i, next_addr, header, silent, do_load, sha_handle, checksum));
+        CHECK_ERR(process_segment(i, next_addr, header, silent, do_load, sha_handle, checksum, data));
        next_addr += sizeof(esp_image_segment_header_t);
        data->segment_data[i] = next_addr;
        next_addr += header->data_len;
@@ -530,7 +539,7 @@ err:
    return err;
 }

-static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segment_header_t *header, bool silent, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum)
+static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segment_header_t *header, bool silent, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum, esp_image_metadata_t *metadata)
 {
    esp_err_t err;

@@ -588,7 +597,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme
        uint32_t offset_page = ((data_addr & MMAP_ALIGNED_MASK) != 0) ? 1 : 0;
        /* Data we could map in case we are not aligned to PAGE boundary is one page size lesser. */
        data_len = MIN(data_len_remain, ((free_page_count - offset_page) * SPI_FLASH_MMU_PAGE_SIZE));
-        CHECK_ERR(process_segment_data(load_addr, data_addr, data_len, do_load, sha_handle, checksum));
+        CHECK_ERR(process_segment_data(index, load_addr, data_addr, data_len, do_load, sha_handle, checksum, metadata));
        data_addr += data_len;
        data_len_remain -= data_len;
    }
@@ -603,7 +612,42 @@ err:
    return err;
 }

-static esp_err_t process_segment_data(intptr_t load_addr, uint32_t data_addr, uint32_t data_len, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum)
+#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
+/* The __attribute__((optimize("O0"))) is used to disable optimizations for this function,
+ * preventing the compiler from potentially optimizing data_buffer and reading data directly from src.
+ * This is crucial as we want to read from Flash only once, ensuring the integrity of the data.
+ */
+__attribute__((optimize("O0")))
+static size_t process_esp_app_desc_data(const uint32_t *src, bootloader_sha256_handle_t sha_handle, uint32_t *checksum, esp_image_metadata_t *metadata)
+{
+    /* Using data_buffer here helps to securely read secure_version
+     * (for anti-rollback) from esp_app_desc_t, preventing FI attack.
+     * We read data from Flash into this buffer, which is covered by sha256.
+     * Therefore, if the flash is under attackers control and contents are modified
+     * the sha256 comparison will fail.
+     *
+     * The esp_app_desc_t structure is located in DROM and is always in segment #0.
+     *
+     * esp_app_desc_t is always at #0 segment (index==0).
+     * secure_version field of esp_app_desc_t is located at #2 word (w_i==1).
+     */
+    uint32_t data_buffer[2];
+    memcpy(data_buffer, src, sizeof(data_buffer));
+    assert(data_buffer[0] == ESP_APP_DESC_MAGIC_WORD);
+    metadata->secure_version = data_buffer[1];
+    if (checksum != NULL) {
+        *checksum ^= data_buffer[0] ^ data_buffer[1];
+    }
+    if (sha_handle != NULL) {
+        bootloader_sha256_data(sha_handle, data_buffer, sizeof(data_buffer));
+    }
+    ESP_FAULT_ASSERT(memcmp(data_buffer, src, sizeof(data_buffer)) == 0);
+    ESP_FAULT_ASSERT(memcmp(&metadata->secure_version, &src[1], sizeof(uint32_t)) == 0);
+    return sizeof(data_buffer);
+}
+#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
+
+static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t data_addr, uint32_t data_len, bool do_load, bootloader_sha256_handle_t sha_handle, uint32_t *checksum, esp_image_metadata_t *metadata)
 {
    // If we are not loading, and the checksum is empty, skip processing this
    // segment for data
@@ -621,6 +665,13 @@ static esp_err_t process_segment_data(intptr_t load_addr, uint32_t data_addr, ui

    if (checksum == NULL && sha_handle == NULL) {
        memcpy((void *)load_addr, data, data_len);
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+        if (esp_ptr_in_iram((uint32_t *)load_addr)) {
+            /* If we have manipulated data over dcache that will be read over icache then we need
+               to writeback, else the data read might be invalid */
+            cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
+        }
+#endif
        bootloader_munmap(data);
        return ESP_OK;
    }
@@ -636,10 +687,24 @@ static esp_err_t process_segment_data(intptr_t load_addr, uint32_t data_addr, ui
 #endif
    }
    uint32_t *dest = (uint32_t *)load_addr;
-#endif
+#endif // BOOTLOADER_BUILD

    const uint32_t *src = data;

+#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
+    // Case I: Bootloader verifying application
+    // Case II: Bootloader verifying bootloader
+    // Anti-rollback check should handle only Case I from above.
+    if (segment == 0 && metadata->start_addr != ESP_BOOTLOADER_OFFSET) {
+        ESP_LOGD(TAG, "additional anti-rollback check 0x%"PRIx32, data_addr);
+        // The esp_app_desc_t structure is located in DROM and is always in segment #0.
+        size_t len = process_esp_app_desc_data(src, sha_handle, checksum, metadata);
+        data_len -= len;
+        src += len / 4;
+        // In BOOTLOADER_BUILD, for DROM (segment #0) we do not load it into dest (only map it), do_load = false.
+    }
+#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
+
    for (size_t i = 0; i < data_len; i += 4) {
        int w_i = i / 4; // Word index
        uint32_t w = src[w_i];
@@ -662,7 +727,9 @@ static esp_err_t process_segment_data(intptr_t load_addr, uint32_t data_addr, ui
        }
    }
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-    if (do_load && esp_ptr_in_diram_iram((uint32_t *)load_addr)) {
+    if (do_load && esp_ptr_in_iram((uint32_t *)load_addr)) {
+        /* If we have manipulated data over dcache that will be read over icache then we need
+           to writeback, else the data read might be invalid */
        cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
    }
 #endif
--- a/components/bootloader_support/src/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encrypt.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -13,6 +13,8 @@
 #include "esp_secure_boot.h"
 #include "hal/efuse_hal.h"

+//TODO:[ESP32C61] IDf-9232
+
 #if CONFIG_IDF_TARGET_ESP32
 #define CRYPT_CNT ESP_EFUSE_FLASH_CRYPT_CNT
 #define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT
--- a/components/bootloader_support/src/flash_encryption/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -16,7 +16,8 @@
 #include "esp_log.h"
 #include "hal/wdt_hal.h"

-#if CONFIG_IDF_TARGET_ESP32P4 //TODO-IDF-7925
+#if SOC_KEY_MANAGER_SUPPORTED
+#include "hal/key_mgr_hal.h"
 #include "soc/keymng_reg.h"
 #endif

@@ -215,9 +216,9 @@ static esp_err_t check_and_generate_encryption_keys(void)
        ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
    }

-#if CONFIG_IDF_TARGET_ESP32P4 //TODO - IDF-7925
+#if SOC_KEY_MANAGER_SUPPORTED
    // Force Key Manager to use eFuse key for XTS-AES operation
-    REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
+    key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
 #endif

    return ESP_OK;
@@ -262,6 +263,13 @@ esp_err_t esp_flash_encrypt_contents(void)
    esp_partition_info_t partition_table[ESP_PARTITION_TABLE_MAX_ENTRIES];
    int num_partitions;

+#if CONFIG_IDF_TARGET_ESP32C5 && SOC_KEY_MANAGER_SUPPORTED
+    // TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
+    REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+    REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+    REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+#endif
+
 #ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
    REG_WRITE(SENSITIVE_XTS_AES_KEY_UPDATE_REG, 1);
 #endif
@@ -429,7 +437,7 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit
        return ESP_OK;
    } else {
        /* should_encrypt */
-        ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%x (length 0x%x)...", index, partition->pos.offset, size);
+        ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%" PRIx32 " (length 0x%" PRIx32 ")...", index, partition->pos.offset, size);

        err = esp_flash_encrypt_region(partition->pos.offset, size);
        ESP_LOGI(TAG, "Done encrypting");
@@ -447,7 +455,7 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length)
    uint32_t buf[FLASH_SECTOR_SIZE / sizeof(uint32_t)];

    if (src_addr % FLASH_SECTOR_SIZE != 0) {
-        ESP_LOGE(TAG, "esp_flash_encrypt_region bad src_addr 0x%x", src_addr);
+        ESP_LOGE(TAG, "esp_flash_encrypt_region bad src_addr 0x%" PRIx32, src_addr);
        return ESP_FAIL;
    }

--- a/components/bootloader_support/src/secure_boot_v1/secure_boot.c
+++ b/components/bootloader_support/src/secure_boot_v1/secure_boot.c
@@ -63,7 +63,7 @@ static bool secure_boot_generate(uint32_t image_len){
    /* generate digest from image contents */
    image = bootloader_mmap(ESP_BOOTLOADER_OFFSET, image_len);
    if (!image) {
-        ESP_LOGE(TAG, "bootloader_mmap(0x1000, 0x%x) failed", image_len);
+        ESP_LOGE(TAG, "bootloader_mmap(0x1000, 0x%" PRIx32 ") failed", image_len);
        return false;
    }
    for (size_t i = 0; i < image_len; i+= sizeof(digest.iv)) {
--- a/Show More
+++ b/Show More