e307f72005
Move context and register definition up.
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“all context definitions must come before constructors”
2022-01-25 20:10:07 +01:00
fa550ba9d2
add some unimpl fpu insns
2022-01-25 20:03:40 +01:00
08cb358913
Move loop* out of xtensaTodo.sinc
2022-01-25 20:00:23 +01:00
109a4649fe
implement Loop Option
2022-01-25 19:57:14 +01:00
cf8aa3fed9
Map special registers
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Backported from https://github.com/Ebiroll/ghidra-xtensa .
2022-01-16 22:10:04 +01:00
e4823d14bb
fix slli
2022-01-16 20:56:53 +01:00
94c353ae9d
Fix output <pentry>s
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Fixes “<pentry> tags within a group must be distinguished by size or
type”.
2022-01-16 15:55:35 +01:00
e8182f4460
Merge pull request #7 from IridiumXOR/master
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Enable DWARF mapping
2022-01-14 21:34:27 +01:00
0b73145bcc
Merge https://github.com/yath/ghidra-xtensa/pull/4
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Sorry for the delay.
2022-01-14 21:26:58 +01:00
4bbf6bc542
Add a build.gradle for building the extension.
2022-01-14 21:23:25 +01:00
b13b4d64ee
Add Xtensa ELF constants
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Put together by @mumbel, thanks!
2022-01-14 20:25:34 +01:00
6fe915e8d0
Fix indentation
2022-01-14 20:08:25 +01:00
2169d80370
Fix UTRUNC.S
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There is no unsigned trunc() pcodeop, so scale and truncate with double
precision and check for over-/underflow separately. The over- and
underflow values are taken from the documentation.
2022-01-14 20:08:09 +01:00
83112e48da
Fix DWARF register mappings
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auto_count apparently counts the starting register as the 1st, so count
one further to get to a15.
2022-01-14 20:08:01 +01:00
33ca0710c9
Fix XSR constructor pattern
2022-01-14 20:07:53 +01:00
1eb0067abe
Remove now unused nsau pcodeop.
2022-01-14 20:07:46 +01:00
fb39ee087a
Fix Shift Amount Register
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The least 5 significant bits is 0x1f, not 0xf. Also, don’t AND the SAR
when shifting; it’s already <32.
2022-01-14 20:07:37 +01:00
c21f1866e7
Implement NSAU
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The libgcc1 __umodsi3 implementation for xtensa-lx106 uses this as Count
Leading Zeros.
2022-01-14 20:07:21 +01:00
f0faee57e4
Truncate control flow after ILL
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GCC seems to insert a “DIV0” (in ASCII) after an ILL instruction, so
truncate control flow by looping endlessly.
2022-01-14 20:07:12 +01:00
9a837fe2dd
Zero-extend UFLOAT operand first
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Otherwise, int2float would consider the MSB a sign.
2022-01-14 20:06:52 +01:00
66fc608881
Remove some XXXs
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@mumbel says looks good.
2022-01-14 20:06:23 +01:00
868699f570
Simplify n_s4_4.7_nozero constructor
2022-01-14 20:06:00 +01:00
210fe20433
Fix s16_16.23_8.11 field signedness
2022-01-14 20:04:55 +01:00
87b33ea657
Enable DWARF mapping
2021-09-16 01:21:23 +02:00
c60fbd02e4
fix bbsi
2020-09-24 21:39:37 +02:00
b6866f44ef
Bump Ghidra version
2019-12-30 17:38:16 +01:00
687950dcd4
Fix MOVI.N immediate calculation
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Reported by @edi1 in #1 , thanks!
2019-12-30 17:32:41 +01:00
181c35f703
Remove TODO
2019-06-26 16:29:50 +02:00
760c816dbd
Add opinion file for ELF and titlecase the processor name
2019-06-26 16:28:50 +02:00
1cf4a63189
Add a .gitignore.
2019-06-23 12:02:51 +02:00
732995d76b
Add DWARF register mappings, but leave them commented out.
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With them, Ghidra contains about an invalid “scope” attribute in the
PCode XML(?) for some functions. I haven’t yet found a better source for
the DWARF layout than binutils. :(
2019-06-23 12:00:32 +02:00
10c070465a
Fix JX’s target.
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Jump to where the register is pointing in RAM, not to the register.
2019-06-23 11:16:11 +02:00
525579b938
Fix compiler spec
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Only a1 and a12-a15 are callee-saved. Also, a2 up to a5 can be used for
return values.
2019-06-22 22:04:43 +02:00
221b8c80c5
Add MIT license
2019-06-22 15:10:34 +02:00
9e34a2b211
Initial commit
2019-06-22 15:04:45 +02:00
