Merge branch 'fix/freertos_vtasklist_param_order_v5.3' into 'release/v5.3'

fix(freertos): Fix vTaskList() parameter print order (v5.3)

See merge request espressif/esp-idf!30476

.gitlab/CODEOWNERS

@@ -2,239 +2,5 @@
 #
 #    https://docs.gitlab.com/ee/user/project/code_owners.html#the-syntax-of-code-owners-files
 #
-# If more than one rule matches a given file, the latest rule is used.
-# The file should be generally kept sorted, except when it is necessary
-# to use a different order due to the fact above. In that case, use
-# '# sort-order-reset' comment line to reset the sort order.
-#
-# Recipes for a few common cases:
-#
-# 1. Specific directory with all its contents:
-#
-#    /components/app_trace/
-#
-#    Note the trailing slash!
-#
-# 2. File with certain extension in any subdirectory of a certain directory:
-#
-#    /examples/**/*.py
-#
-#    This includes an *.py files in /examples/ directory as well.
-#
-# 3. Contents of a directory with a certain name, anywhere in the tree:
-#
-#    test_*_host/
-#
-#    Will match everything under components/efuse/test_efuse_host/,
-#    components/heap/test_multi_heap_host/, components/lwip/test_afl_host/, etc.
-#
-# 4. Same as above, except limited to a specific place in the tree:
-#
-#    /components/esp32*/
-#
-#    Matches everything under /components/esp32, /components/esp32s2, etc.
-#    Doesn't match /tools/some-test/components/esp32s5.
-#
-# 5. Specific file:
-#
-#    /tools/tools.json
-#
-# 6. File with a certain name anywhere in the tree
-#
-#    .gitignore
-#
 
-* @esp-idf-codeowners/other
-
-/.*                                   @esp-idf-codeowners/tools
-/.codespellrc                         @esp-idf-codeowners/ci
-/.github/workflows/                   @esp-idf-codeowners/ci
-/.gitlab-ci.yml                       @esp-idf-codeowners/ci
-/.gitlab/ci/                          @esp-idf-codeowners/ci
-/.pre-commit-config.yaml              @esp-idf-codeowners/ci
-/.readthedocs.yml                     @esp-idf-codeowners/docs
-/.vale.ini                            @esp-idf-codeowners/docs
-/CMakeLists.txt                       @esp-idf-codeowners/build-config
-/COMPATIBILITY*.md                    @esp-idf-codeowners/peripherals
-/CONTRIBUTING.md                      @esp-idf-codeowners/docs
-/Kconfig                              @esp-idf-codeowners/build-config
-/README*.md                           @esp-idf-codeowners/docs
-/SUPPORT_POLICY*.md                   @esp-idf-codeowners/docs
-/add_path.sh                          @esp-idf-codeowners/tools
-/conftest.py                          @esp-idf-codeowners/ci
-/export.*                             @esp-idf-codeowners/tools
-/install.*                            @esp-idf-codeowners/tools
-/pytest.ini                           @esp-idf-codeowners/ci
-/sdkconfig.rename                     @esp-idf-codeowners/build-config
-/sonar-project.properties             @esp-idf-codeowners/ci
-
-# sort-order-reset
-
-/components/app_trace/                @esp-idf-codeowners/debugging
-/components/app_update/               @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities
-/components/bootloader*/              @esp-idf-codeowners/system @esp-idf-codeowners/security
-/components/bootloader_support/bootloader_flash/    @esp-idf-codeowners/peripherals
-/components/bt/                       @esp-idf-codeowners/bluetooth
-/components/cmock/                    @esp-idf-codeowners/system
-/components/console/                  @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities/console
-/components/cxx/                      @esp-idf-codeowners/system
-/components/driver/                   @esp-idf-codeowners/peripherals
-/components/efuse/                    @esp-idf-codeowners/system
-/components/esp_adc/                  @esp-idf-codeowners/peripherals
-/components/esp_app_format/           @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities
-/components/esp_bootloader_format/    @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities
-/components/esp_coex/                 @esp-idf-codeowners/wifi @esp-idf-codeowners/bluetooth @esp-idf-codeowners/ieee802154
-/components/esp_common/               @esp-idf-codeowners/system
-/components/esp_driver_*/             @esp-idf-codeowners/peripherals
-/components/esp_driver_sdmmc/         @esp-idf-codeowners/peripherals @esp-idf-codeowners/storage
-/components/esp_eth/                  @esp-idf-codeowners/network
-/components/esp_event/                @esp-idf-codeowners/system
-/components/esp_gdbstub/              @esp-idf-codeowners/debugging
-/components/esp_hid/                  @esp-idf-codeowners/bluetooth
-/components/esp_http_client/          @esp-idf-codeowners/app-utilities
-/components/esp_http_server/          @esp-idf-codeowners/app-utilities
-/components/esp_https_ota/            @esp-idf-codeowners/app-utilities
-/components/esp_https_server/         @esp-idf-codeowners/app-utilities
-/components/esp_hw_support/           @esp-idf-codeowners/system @esp-idf-codeowners/peripherals
-/components/esp_hw_support/lowpower/  @esp-idf-codeowners/power-management
-/components/esp_lcd/                  @esp-idf-codeowners/peripherals
-/components/esp_local_ctrl/           @esp-idf-codeowners/app-utilities
-/components/esp_mm/                   @esp-idf-codeowners/peripherals
-/components/esp_netif/                @esp-idf-codeowners/network
-/components/esp_netif_stack/          @esp-idf-codeowners/network
-/components/esp_partition/            @esp-idf-codeowners/storage
-/components/esp_phy/                  @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/ieee802154
-/components/esp_pm/                   @esp-idf-codeowners/power-management @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/system
-/components/esp_psram/                @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
-/components/esp_ringbuf/              @esp-idf-codeowners/system
-/components/esp_rom/                  @esp-idf-codeowners/system @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi
-/components/esp_system/               @esp-idf-codeowners/system
-/components/esp_timer/                @esp-idf-codeowners/system
-/components/esp-tls/                  @esp-idf-codeowners/app-utilities
-/components/esp_vfs_*/                @esp-idf-codeowners/storage
-/components/esp_vfs_console/          @esp-idf-codeowners/storage @esp-idf-codeowners/system
-/components/esp_wifi/                 @esp-idf-codeowners/wifi
-/components/espcoredump/              @esp-idf-codeowners/debugging
-/components/esptool_py/               @esp-idf-codeowners/tools
-/components/fatfs/                    @esp-idf-codeowners/storage
-/components/freertos/                 @esp-idf-codeowners/system
-/components/hal/                      @esp-idf-codeowners/peripherals
-/components/heap/                     @esp-idf-codeowners/system
-/components/http_parser/              @esp-idf-codeowners/app-utilities
-/components/idf_test/                 @esp-idf-codeowners/ci
-/components/ieee802154/               @esp-idf-codeowners/ieee802154
-/components/json/                     @esp-idf-codeowners/app-utilities
-/components/linux/                    @esp-idf-codeowners/system
-/components/log/                      @esp-idf-codeowners/system
-/components/lwip/                     @esp-idf-codeowners/lwip
-/components/mbedtls/                  @esp-idf-codeowners/app-utilities/mbedtls @esp-idf-codeowners/security
-/components/mqtt/                     @esp-idf-codeowners/network
-/components/newlib/                   @esp-idf-codeowners/system @esp-idf-codeowners/toolchain
-/components/nvs_flash/                @esp-idf-codeowners/storage
-/components/nvs_sec_provider/         @esp-idf-codeowners/storage @esp-idf-codeowners/security
-/components/openthread/               @esp-idf-codeowners/ieee802154
-/components/partition_table/          @esp-idf-codeowners/system
-/components/perfmon/                  @esp-idf-codeowners/debugging
-/components/protobuf-c/               @esp-idf-codeowners/app-utilities
-/components/protocomm/                @esp-idf-codeowners/app-utilities/provisioning
-/components/pthread/                  @esp-idf-codeowners/system
-/components/riscv/                    @esp-idf-codeowners/system
-/components/sdmmc/                    @esp-idf-codeowners/storage
-/components/soc/                      @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
-/components/spi_flash/                @esp-idf-codeowners/peripherals
-/components/spiffs/                   @esp-idf-codeowners/storage
-/components/tcp_transport/            @esp-idf-codeowners/network
-/components/touch_element/            @esp-idf-codeowners/peripherals
-/components/ulp/                      @esp-idf-codeowners/system
-/components/unity/                    @esp-idf-codeowners/ci
-/components/usb/                      @esp-idf-codeowners/peripherals/usb
-/components/vfs/                      @esp-idf-codeowners/storage
-/components/wear_levelling/           @esp-idf-codeowners/storage
-/components/wifi_provisioning/        @esp-idf-codeowners/app-utilities/provisioning
-/components/wpa_supplicant/           @esp-idf-codeowners/wifi @esp-idf-codeowners/app-utilities/mbedtls
-/components/xtensa/                   @esp-idf-codeowners/system
-
-/docs/                                   @esp-idf-codeowners/docs
-/docs/**/api-guides/tools/               @esp-idf-codeowners/tools
-/docs/en/api-guides/core_dump.rst        @esp-idf-codeowners/debugging
-/docs/en/api-guides/jtag-debugging/      @esp-idf-codeowners/debugging
-/docs/**/api-reference/bluetooth/        @esp-idf-codeowners/bluetooth
-/docs/**/api-reference/network/          @esp-idf-codeowners/network @esp-idf-codeowners/wifi
-/docs/**/api-reference/peripherals/      @esp-idf-codeowners/peripherals
-/docs/**/api-reference/peripherals/usb*  @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
-/docs/**/api-reference/protocols/        @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/docs/**/api-reference/provisioning/     @esp-idf-codeowners/app-utilities/provisioning
-/docs/**/api-reference/storage/          @esp-idf-codeowners/storage
-/docs/**/api-reference/system/           @esp-idf-codeowners/system
-/docs/**/security/                       @esp-idf-codeowners/security
-/docs/**/migration-guides/               @esp-idf-codeowners/docs @esp-idf-codeowners/all-maintainers
-
-/examples/README.md           @esp-idf-codeowners/docs @esp-idf-codeowners/ci
-/examples/**/*.py             @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-/examples/bluetooth/          @esp-idf-codeowners/bluetooth
-/examples/build_system/       @esp-idf-codeowners/build-config
-/examples/common_components/  @esp-idf-codeowners/system @esp-idf-codeowners/wifi @esp-idf-codeowners/lwip @esp-idf-codeowners/network
-/examples/custom_bootloader/  @esp-idf-codeowners/system
-/examples/cxx/                @esp-idf-codeowners/system
-/examples/ethernet/           @esp-idf-codeowners/network
-/examples/get-started/        @esp-idf-codeowners/system
-/examples/ieee802154/         @esp-idf-codeowners/ieee802154
-/examples/mesh/               @esp-idf-codeowners/wifi
-/examples/network/            @esp-idf-codeowners/network @esp-idf-codeowners/wifi
-/examples/openthread/         @esp-idf-codeowners/ieee802154
-/examples/peripherals/        @esp-idf-codeowners/peripherals
-/examples/peripherals/usb/    @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
-/examples/phy/                @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/ieee802154
-/examples/protocols/          @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/examples/provisioning/       @esp-idf-codeowners/app-utilities/provisioning
-/examples/security/           @esp-idf-codeowners/security
-/examples/storage/            @esp-idf-codeowners/storage
-/examples/system/             @esp-idf-codeowners/system
-/examples/system/ota/         @esp-idf-codeowners/app-utilities
-/examples/wifi/               @esp-idf-codeowners/wifi
-/examples/zigbee/             @esp-idf-codeowners/ieee802154
-
-/tools/                       @esp-idf-codeowners/tools
-/tools/ble/                   @esp-idf-codeowners/app-utilities
-/tools/catch/                 @esp-idf-codeowners/ci
-/tools/ci/                    @esp-idf-codeowners/ci
-/tools/cmake/                 @esp-idf-codeowners/build-config
-/tools/cmake/toolchain-*.cmake      @esp-idf-codeowners/toolchain
-/tools/esp_app_trace/         @esp-idf-codeowners/debugging
-/tools/esp_prov/              @esp-idf-codeowners/app-utilities
-/tools/gdb_panic_server.py    @esp-idf-codeowners/debugging
-/tools/kconfig*/              @esp-idf-codeowners/build-config
-/tools/ldgen/                 @esp-idf-codeowners/build-config
-/tools/mass_mfg/              @esp-idf-codeowners/app-utilities
-/tools/mocks/                 @esp-idf-codeowners/system
-
-/tools/test_apps/                    @esp-idf-codeowners/ci
-/tools/test_apps/README.md           @esp-idf-codeowners/docs @esp-idf-codeowners/ci
-
-## Note: owners here should be the same as the owners for the same example subdir, above
-/tools/test_apps/build_system/       @esp-idf-codeowners/build-config
-/tools/test_apps/configs/            @esp-idf-codeowners/system
-/tools/test_apps/linux_compatible/   @esp-idf-codeowners/system
-/tools/test_apps/peripherals/        @esp-idf-codeowners/peripherals
-/tools/test_apps/phy/                @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi @esp-idf-codeowners/ieee802154
-/tools/test_apps/protocols/          @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/tools/test_apps/security/           @esp-idf-codeowners/security
-/tools/test_apps/storage/            @esp-idf-codeowners/storage
-/tools/test_apps/system/             @esp-idf-codeowners/system
-
-/tools/test_apps/**/*.py             @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-
-/tools/test_build_system/     @esp-idf-codeowners/tools @esp-idf-codeowners/build-config
-
-/tools/tools.json             @esp-idf-codeowners/tools @esp-idf-codeowners/toolchain @esp-idf-codeowners/debugging
-
-/tools/unit-test-app/         @esp-idf-codeowners/system @esp-idf-codeowners/tools
-
-# sort-order-reset
-
-/components/**/test_apps/**/*.py     @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-
-# ignore lists
-/tools/ci/check_copyright_config.yaml                   @esp-idf-codeowners/all-maintainers
-/tools/ci/check_copyright_ignore.txt                    @esp-idf-codeowners/all-maintainers
-/tools/ci/mypy_ignore_list.txt                          @esp-idf-codeowners/tools
+* @esp-idf-codeowners/all-maintainers

.gitlab/ci/host-test.yml

@@ -133,7 +133,7 @@ test_cli_installer:
   script:
     # Tools must be downloaded for testing
     # We could use "idf_tools.py download all", but we don't want to install clang because of its huge size
-    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa
+    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa cmake
     - cd ${IDF_PATH}/tools/test_idf_tools
     - python3 -m pip install jsonschema
     - python3 ./test_idf_tools.py -v
@@ -228,6 +228,8 @@ test_tools:
     - pytest --noconftest test_idf_qemu.py     --junitxml=${IDF_PATH}/XUNIT_IDF_PY_QEMU.xml               || stat=1
     - cd ${IDF_PATH}/tools/test_mkdfu
     - pytest --noconftest test_mkdfu.py        --junitxml=${IDF_PATH}/XUNIT_MKDFU.xml                     || stat=1
+    - cd ${IDF_PATH}/tools/test_idf_size
+    - pytest --noconftest test_idf_size.py     --junitxml=${IDF_PATH}/XUNIT_IDF_SIZE.xml                  || stat=1
     - cd ${IDF_PATH}
     - shellcheck -s sh tools/detect_python.sh                                                             || stat=1
     - shellcheck -s bash tools/detect_python.sh                                                           || stat=1

.gitlab/ci/rules.yml

@@ -86,6 +86,7 @@
   - "tools/test_idf_py/**/*"
 
   - "tools/idf_size.py"
+  - "tools/test_idf_size/**/*"
 
   - "tools/tools.json"
   - "tools/tools_schema.json"

.gitlab/ci/test-win.yml

@@ -31,7 +31,7 @@ test_cli_installer_win:
     IDF_PATH: "$CI_PROJECT_DIR"
   script:
     # Tools must be downloaded for testing
-    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa
+    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa cmake
     - cd ${IDF_PATH}\tools\test_idf_tools
     - python -m pip install jsonschema
     - python .\test_idf_tools.py

components/bt/controller/esp32c2/Kconfig.in

@@ -349,7 +349,6 @@ config BT_LE_CRYPTO_STACK_MBEDTLS
     bool "Override TinyCrypt with mbedTLS for crypto computations"
     default y
     depends on !BT_NIMBLE_ENABLED
-    select MBEDTLS_ECP_RESTARTABLE
     select MBEDTLS_CMAC_C
     help
         Enable this option to choose mbedTLS instead of TinyCrypt for crypto

components/bt/controller/esp32c5/Kconfig.in

@@ -365,7 +365,6 @@ config BT_LE_CRYPTO_STACK_MBEDTLS
     bool "Override TinyCrypt with mbedTLS for crypto computations"
     default y
     depends on !BT_NIMBLE_ENABLED
-    select MBEDTLS_ECP_RESTARTABLE
     select MBEDTLS_CMAC_C
     help
         Enable this option to choose mbedTLS instead of TinyCrypt for crypto

components/bt/controller/esp32c6/Kconfig.in

@@ -365,7 +365,6 @@ config BT_LE_CRYPTO_STACK_MBEDTLS
     bool "Override TinyCrypt with mbedTLS for crypto computations"
     default y
     depends on !BT_NIMBLE_ENABLED
-    select MBEDTLS_ECP_RESTARTABLE
     select MBEDTLS_CMAC_C
     help
         Enable this option to choose mbedTLS instead of TinyCrypt for crypto

components/bt/controller/esp32h2/Kconfig.in

@@ -356,7 +356,6 @@ config BT_LE_CRYPTO_STACK_MBEDTLS
     bool "Override TinyCrypt with mbedTLS for crypto computations"
     default y
     depends on !BT_NIMBLE_ENABLED
-    select MBEDTLS_ECP_RESTARTABLE
     select MBEDTLS_CMAC_C
     help
         Enable this option to choose mbedTLS instead of TinyCrypt for crypto

components/bt/host/bluedroid/bta/hd/bta_hd_act.c

@@ -722,6 +722,26 @@ extern void bta_hd_exit_suspend_act(tBTA_HD_DATA *p_data)
     bta_sys_idle(BTA_ID_HD, 1, p_cback->addr);
 }
 
+/*******************************************************************************
+ *
+ * Function         bta_hd_open_failure
+ *
+ * Description
+ *
+ * Returns          void
+ *
+ ******************************************************************************/
+extern void bta_hd_open_failure(tBTA_HD_DATA *p_data)
+{
+    tBTA_HD_CBACK_DATA *p_cback = (tBTA_HD_CBACK_DATA *)p_data;
+    tBTA_HD cback_data = {0};
+
+    bdcpy(cback_data.conn.bda, p_cback->addr);
+    cback_data.conn.status = BTA_HD_ERROR;
+    cback_data.conn.conn_status = BTA_HD_CONN_STATE_DISCONNECTED;
+    bta_hd_cb.p_cback(BTA_HD_OPEN_EVT, &cback_data);
+}
+
 /*******************************************************************************
  *
  * Function         bta_hd_cback

components/bt/host/bluedroid/bta/hd/bta_hd_main.c

@@ -62,6 +62,7 @@ enum {
     BTA_HD_VC_UNPLUG_DONE_ACT,
     BTA_HD_SUSPEND_ACT,
     BTA_HD_EXIT_SUSPEND_ACT,
+    BTA_HD_OPEN_FAILURE,
     BTA_HD_NUM_ACTIONS
 };
 
@@ -74,7 +75,7 @@ const tBTA_HD_ACTION bta_hd_action[] = {
     bta_hd_disconnect_act,     bta_hd_add_device_act, bta_hd_remove_device_act, bta_hd_send_report_act,
     bta_hd_report_error_act,   bta_hd_vc_unplug_act,  bta_hd_open_act,          bta_hd_close_act,
     bta_hd_intr_data_act,      bta_hd_get_report_act, bta_hd_set_report_act,    bta_hd_set_protocol_act,
-    bta_hd_vc_unplug_done_act, bta_hd_suspend_act,    bta_hd_exit_suspend_act,
+    bta_hd_vc_unplug_done_act, bta_hd_suspend_act,    bta_hd_exit_suspend_act,  bta_hd_open_failure
 };
 
 /* state table information */
@@ -118,7 +119,7 @@ const uint8_t bta_hd_st_idle[][BTA_HD_NUM_COLS] = {
     /* BTA_HD_API_REPORT_ERROR_EVT   */ {BTA_HD_IGNORE, BTA_HD_IDLE_ST},
     /* BTA_HD_API_VC_UNPLUG_EVT      */ {BTA_HD_VC_UNPLUG_ACT, BTA_HD_IDLE_ST},
     /* BTA_HD_INT_OPEN_EVT           */ {BTA_HD_OPEN_ACT, BTA_HD_CONN_ST},
-    /* BTA_HD_INT_CLOSE_EVT          */ {BTA_HD_IGNORE, BTA_HD_IDLE_ST},
+    /* BTA_HD_INT_CLOSE_EVT          */ {BTA_HD_OPEN_FAILURE, BTA_HD_IDLE_ST},
     /* BTA_HD_INT_INTR_DATA_EVT      */ {BTA_HD_IGNORE, BTA_HD_IDLE_ST},
     /* BTA_HD_INT_GET_REPORT_EVT     */ {BTA_HD_IGNORE, BTA_HD_IDLE_ST},
     /* BTA_HD_INT_SET_REPORT_EVT     */ {BTA_HD_IGNORE, BTA_HD_IDLE_ST},

components/bt/host/bluedroid/bta/hd/include/bta_hd_int.h

@@ -164,5 +164,6 @@ extern void bta_hd_set_protocol_act(tBTA_HD_DATA *p_data);
 extern void bta_hd_vc_unplug_done_act(tBTA_HD_DATA *p_data);
 extern void bta_hd_suspend_act(tBTA_HD_DATA *p_data);
 extern void bta_hd_exit_suspend_act(tBTA_HD_DATA *p_data);
+extern void bta_hd_open_failure(tBTA_HD_DATA *p_data);
 
 #endif

components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c

@@ -261,7 +261,7 @@ static void btc_hd_deinit(void)
         }
 
         btc_hd_cb.service_dereg_active = FALSE;
-        // unresgister app will also relase the connection
+        // unregister app will also release the connection
         // and disable after receiving unregister event from lower layer
         if (is_hidd_app_register()) {
             btc_hd_unregister_app(true);
@@ -844,6 +844,8 @@ void btc_hd_cb_handler(btc_msg_t *msg)
             // }
             // btc_storage_set_hidd((bt_bdaddr_t *)&p_data->conn.bda);
             btc_hd_cb.status = BTC_HD_CONNECTED;
+        } else if (p_data->conn.conn_status == BTA_HD_CONN_STATE_DISCONNECTED) {
+            btc_hd_cb.status = BTC_HD_DISCONNECTED;
         }
         param.open.status = p_data->conn.status;
         param.open.conn_status = p_data->conn.conn_status;

components/bt/host/bluedroid/stack/btu/btu_hcif.c

@@ -1252,6 +1252,9 @@ static void btu_hcif_command_complete_evt(BT_HDR *response, void *context)
 static void btu_hcif_hdl_command_status (UINT16 opcode, UINT8 status, UINT8 *p_cmd,
         void *p_vsc_status_cback)
 {
+    if (status != HCI_SUCCESS){
+        HCI_TRACE_WARNING("%s,opcode:0x%04x,status:0x%02x", __func__, opcode,status);
+    }
     BD_ADDR         bd_addr;
     UINT16          handle;
 #if BTM_SCO_INCLUDED == TRUE

components/bt/host/bluedroid/stack/hid/hidd_conn.c

@@ -231,7 +231,7 @@ static void hidd_l2cif_connect_cfm(uint16_t cid, uint16_t result)
     tHID_CONN *p_hcon = &hd_cb.device.conn;
     HIDD_TRACE_EVENT("%s: cid=%04x result=%d, conn_state=%d", __func__, cid, result, p_hcon->conn_state);
     if (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         return;
     }
     if (!(p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) ||
@@ -243,10 +243,12 @@ static void hidd_l2cif_connect_cfm(uint16_t cid, uint16_t result)
     }
     if (result != L2CAP_CONN_OK) {
         HIDD_TRACE_WARNING("%s: connection failed, now disconnect", __func__);
-        if (cid == p_hcon->ctrl_cid)
+        if (cid == p_hcon->ctrl_cid) {
             p_hcon->ctrl_cid = 0;
-        else
+        } else {
             p_hcon->intr_cid = 0;
+        }
+
         hidd_conn_disconnect();
         hd_cb.callback(hd_cb.device.addr, HID_DHOST_EVT_CLOSE, HID_L2CAP_CONN_FAIL | (uint32_t)result, NULL);
         return;
@@ -278,7 +280,7 @@ static void hidd_l2cif_config_ind(uint16_t cid, tL2CAP_CFG_INFO *p_cfg)
     HIDD_TRACE_EVENT("%s: cid=%04x", __func__, cid);
     p_hcon = &hd_cb.device.conn;
     if (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         return;
     }
     if ((!p_cfg->mtu_present) || (p_cfg->mtu > HID_DEV_MTU_SIZE))
@@ -297,7 +299,8 @@ static void hidd_l2cif_config_ind(uint16_t cid, tL2CAP_CFG_INFO *p_cfg)
     // update flags
     if (cid == p_hcon->ctrl_cid) {
         p_hcon->conn_flags |= HID_CONN_FLAGS_HIS_CTRL_CFG_DONE;
-        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) && (p_hcon->conn_flags & HID_CONN_FLAGS_MY_CTRL_CFG_DONE)) {
+        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) && (p_hcon->conn_flags & HID_CONN_FLAGS_MY_CTRL_CFG_DONE) &&
+            (p_hcon->conn_state != HID_CONN_STATE_CONNECTING_INTR)) {
             p_hcon->disc_reason = HID_L2CAP_CONN_FAIL;
             if ((p_hcon->intr_cid = L2CA_ConnectReq(HID_PSM_INTERRUPT, hd_cb.device.addr)) == 0) {
                 p_hcon->conn_state = HID_CONN_STATE_UNUSED;
@@ -330,7 +333,7 @@ static void hidd_l2cif_config_cfm(uint16_t cid, tL2CAP_CFG_INFO *p_cfg)
     HIDD_TRACE_EVENT("%s: cid=%04x pcfg->result=%d", __func__, cid, p_cfg->result);
     p_hcon = &hd_cb.device.conn;
     if (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         return;
     }
     if (p_hcon->intr_cid == cid && p_cfg->result == L2CAP_CFG_UNACCEPTABLE_PARAMS && p_cfg->qos_present) {
@@ -357,7 +360,8 @@ static void hidd_l2cif_config_cfm(uint16_t cid, tL2CAP_CFG_INFO *p_cfg)
     // update flags
     if (cid == p_hcon->ctrl_cid) {
         p_hcon->conn_flags |= HID_CONN_FLAGS_MY_CTRL_CFG_DONE;
-        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) && (p_hcon->conn_flags & HID_CONN_FLAGS_HIS_CTRL_CFG_DONE)) {
+        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) && (p_hcon->conn_flags & HID_CONN_FLAGS_HIS_CTRL_CFG_DONE) &&
+            (p_hcon->conn_state != HID_CONN_STATE_CONNECTING_INTR)) {
             p_hcon->disc_reason = HID_L2CAP_CONN_FAIL;
             if ((p_hcon->intr_cid = L2CA_ConnectReq(HID_PSM_INTERRUPT, hd_cb.device.addr)) == 0) {
                 p_hcon->conn_state = HID_CONN_STATE_UNUSED;
@@ -389,11 +393,14 @@ static void hidd_l2cif_disconnect_ind(uint16_t cid, bool ack_needed)
     HIDD_TRACE_EVENT("%s: cid=%04x ack_needed=%d", __func__, cid, ack_needed);
     p_hcon = &hd_cb.device.conn;
     if (p_hcon->conn_state == HID_CONN_STATE_UNUSED || (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid)) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         return;
     }
-    if (ack_needed)
+
+    if (ack_needed) {
         L2CA_DisconnectRsp(cid);
+    }
+
     if (cid == p_hcon->ctrl_cid) {
         p_hcon->ctrl_cid = 0;
         p_hcon->conn_state = HID_CONN_STATE_DISCONNECTING_CTRL;
@@ -417,7 +424,7 @@ static void hidd_l2cif_disconnect_ind(uint16_t cid, bool ack_needed)
  *
  * Function         hidd_l2cif_disconnect_cfm
  *
- * Description      Handles L2CAP disconection response
+ * Description      Handles L2CAP disconnection response
  *
  * Returns          void
  *
@@ -428,7 +435,7 @@ static void hidd_l2cif_disconnect_cfm(uint16_t cid, uint16_t result)
     HIDD_TRACE_EVENT("%s: cid=%04x result=%d", __func__, cid, result);
     p_hcon = &hd_cb.device.conn;
     if (p_hcon->conn_state == HID_CONN_STATE_UNUSED || (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid)) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         return;
     }
     if (cid == p_hcon->ctrl_cid) {
@@ -465,7 +472,7 @@ static void hidd_l2cif_cong_ind(uint16_t cid, bool congested)
     HIDD_TRACE_EVENT("%s: cid=%04x congested=%d", __func__, cid, congested);
     p_hcon = &hd_cb.device.conn;
     if (p_hcon->conn_state == HID_CONN_STATE_UNUSED || (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid)) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         return;
     }
     if (congested) {
@@ -492,7 +499,7 @@ static void hidd_l2cif_data_ind(uint16_t cid, BT_HDR *p_msg)
     HIDD_TRACE_EVENT("%s: cid=%04x", __func__, cid);
     p_hcon = &hd_cb.device.conn;
     if (p_hcon->conn_state == HID_CONN_STATE_UNUSED || (p_hcon->ctrl_cid != cid && p_hcon->intr_cid != cid)) {
-        HIDD_TRACE_WARNING("%s: unknown cid", __func__);
+        HIDD_TRACE_WARNING("%s: unknown cid=%04x", __func__, cid);
         osi_free(p_msg);
         return;
     }
@@ -645,7 +652,7 @@ tHID_STATUS hidd_conn_initiate(void)
     p_dev->conn.ctrl_cid = 0;
     p_dev->conn.intr_cid = 0;
     p_dev->conn.disc_reason = HID_L2CAP_CONN_FAIL;
-    p_dev->conn.conn_flags = HID_CONN_FLAGS_IS_ORIG;
+    p_dev->conn.conn_flags |= HID_CONN_FLAGS_IS_ORIG;
     BTM_SetOutService(p_dev->addr, BTM_SEC_SERVICE_HIDD_SEC_CTRL, HIDD_SEC_CHN);
     /* Check if L2CAP started the connection process */
     if ((p_dev->conn.ctrl_cid = L2CA_ConnectReq(HID_PSM_CONTROL, p_dev->addr)) == 0) {

components/bt/host/bluedroid/stack/hid/hidh_api.c

@@ -379,7 +379,6 @@ tHID_STATUS HID_HostAddDev ( BD_ADDR addr, UINT16 attr_mask, UINT8 *handle )
     if (!hh_cb.devices[i].in_use) {
         hh_cb.devices[i].in_use = TRUE;
         hh_cb.devices[i].delay_remove = FALSE;
-        hh_cb.devices[i].is_orig = FALSE;
         memcpy( hh_cb.devices[i].addr, addr, sizeof( BD_ADDR ) ) ;
         hh_cb.devices[i].state = HID_DEV_NO_CONN;
         hh_cb.devices[i].conn_tries = 0 ;
@@ -487,7 +486,6 @@ tHID_STATUS HID_HostOpenDev ( UINT8 dev_handle )
     }
 
     hh_cb.devices[dev_handle].conn_tries = 1;
-    hh_cb.devices[dev_handle].is_orig = TRUE;
     return hidh_conn_initiate( dev_handle );
 }
 
@@ -666,7 +664,7 @@ BOOLEAN HID_HostConnectOrig(UINT8 dev_handle)
             break;
         }
 
-        ret = hh_cb.devices[dev_handle].is_orig;
+        ret = hidh_conn_is_orig(dev_handle);
     } while (0);
 
     return ret;

components/bt/host/bluedroid/stack/hid/hidh_conn.c

@@ -457,8 +457,8 @@ static void hidh_l2cif_config_ind (UINT16 l2cap_cid, tL2CAP_CFG_INFO *p_cfg)
 
     if (l2cap_cid == p_hcon->ctrl_cid) {
         p_hcon->conn_flags |= HID_CONN_FLAGS_HIS_CTRL_CFG_DONE;
-        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) &&
-                (p_hcon->conn_flags & HID_CONN_FLAGS_MY_CTRL_CFG_DONE)) {
+        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) && (p_hcon->conn_flags & HID_CONN_FLAGS_MY_CTRL_CFG_DONE) &&
+            (p_hcon->conn_state != HID_CONN_STATE_CONNECTING_INTR)) {
             /* Connect interrupt channel */
             p_hcon->disc_reason = HID_L2CAP_CONN_FAIL;  /* Reset initial reason for CLOSE_EVT: Connection Attempt was made but failed */
             if ((p_hcon->intr_cid = L2CA_ConnectReq (HID_PSM_INTERRUPT, hh_cb.devices[dhandle].addr)) == 0) {
@@ -528,8 +528,8 @@ static void hidh_l2cif_config_cfm (UINT16 l2cap_cid, tL2CAP_CFG_INFO *p_cfg)
 
     if (l2cap_cid == p_hcon->ctrl_cid) {
         p_hcon->conn_flags |= HID_CONN_FLAGS_MY_CTRL_CFG_DONE;
-        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) &&
-                (p_hcon->conn_flags & HID_CONN_FLAGS_HIS_CTRL_CFG_DONE)) {
+        if ((p_hcon->conn_flags & HID_CONN_FLAGS_IS_ORIG) && (p_hcon->conn_flags & HID_CONN_FLAGS_HIS_CTRL_CFG_DONE) &&
+            (p_hcon->conn_state != HID_CONN_STATE_CONNECTING_INTR)) {
             /* Connect interrupt channel */
             p_hcon->disc_reason = HID_L2CAP_CONN_FAIL;  /* Reset initial reason for CLOSE_EVT: Connection Attempt was made but failed */
             if ((p_hcon->intr_cid = L2CA_ConnectReq (HID_PSM_INTERRUPT, hh_cb.devices[dhandle].addr)) == 0) {
@@ -968,7 +968,7 @@ tHID_STATUS hidh_conn_initiate (UINT8 dhandle)
     p_dev->conn.disc_reason = HID_L2CAP_CONN_FAIL;  /* Reset initial reason for CLOSE_EVT: Connection Attempt was made but failed */
 
     /* We are the originator of this connection */
-    p_dev->conn.conn_flags = HID_CONN_FLAGS_IS_ORIG;
+    p_dev->conn.conn_flags |= HID_CONN_FLAGS_IS_ORIG;
 
     if (p_dev->attr_mask & HID_SEC_REQUIRED) {
         service_id = BTM_SEC_SERVICE_HIDH_SEC_CTRL;
@@ -989,6 +989,20 @@ tHID_STATUS hidh_conn_initiate (UINT8 dhandle)
     return ( HID_SUCCESS );
 }
 
+/*******************************************************************************
+**
+** Function         hidh_conn_is_orig
+**
+** Description      This function check if we are the originator of this connection
+**
+** Returns          BOOLEAN
+**
+*******************************************************************************/
+BOOLEAN hidh_conn_is_orig(UINT8 dhandle)
+{
+    tHID_HOST_DEV_CTB *p_dev = &hh_cb.devices[dhandle];
+    return (p_dev->conn.conn_flags & HID_CONN_FLAGS_IS_ORIG);
+}
 
 /*******************************************************************************
 **

components/bt/host/bluedroid/stack/hid/include/hid_int.h

@@ -35,7 +35,6 @@ enum { HID_DEV_NO_CONN, HID_DEV_CONNECTED };
 typedef struct per_device_ctb {
     BOOLEAN        in_use;
     BOOLEAN        delay_remove;
-    BOOLEAN        is_orig;
     BD_ADDR        addr;  /* BD-Addr of the host device */
     UINT16         attr_mask; /* 0x01- virtual_cable; 0x02- normally_connectable; 0x03- reconn_initiate;
                                  0x04- sdp_disable; */
@@ -66,6 +65,7 @@ extern tHID_STATUS hidh_conn_reg (void);
 extern void hidh_conn_dereg( void );
 extern tHID_STATUS hidh_conn_disconnect (UINT8 dhandle);
 extern tHID_STATUS hidh_conn_initiate (UINT8 dhandle);
+extern BOOLEAN hidh_conn_is_orig(UINT8 dhandle);
 extern void hidh_proc_repage_timeout (TIMER_LIST_ENT *p_tle);
 #ifdef __cplusplus
 extern "C" {

components/bt/host/nimble/Kconfig.in

@@ -498,7 +498,6 @@ config BT_NIMBLE_CRYPTO_STACK_MBEDTLS
     bool "Override TinyCrypt with mbedTLS for crypto computations"
     default y
     depends on BT_NIMBLE_ENABLED
-    select MBEDTLS_ECP_RESTARTABLE
     select MBEDTLS_CMAC_C
     help
         Enable this option to choose mbedTLS instead of TinyCrypt for crypto
@@ -597,7 +596,7 @@ if BT_NIMBLE_EXT_ADV
             Enable this option to start periodic advertisement.
 
     config BT_NIMBLE_PERIODIC_ADV_SYNC_TRANSFER
-        bool "Enable Transer Sync Events"
+        bool "Enable Transfer Sync Events"
         depends on BT_NIMBLE_ENABLE_PERIODIC_ADV
         default y
         help
@@ -666,7 +665,7 @@ config BT_NIMBLE_GATT_CACHING_MAX_DSCS
     depends on BT_NIMBLE_GATT_CACHING
     default 64
     help
-        Set this option to set the upper limit on number of discriptors per connection to be cached.
+        Set this option to set the upper limit on number of descriptors per connection to be cached.
 
 config BT_NIMBLE_WHITELIST_SIZE
     int "BLE white list size"

components/esp-tls/CMakeLists.txt

@@ -1,4 +1,4 @@
-set(srcs esp_tls.c esp-tls-crypto/esp_tls_crypto.c esp_tls_error_capture.c)
+set(srcs esp_tls.c esp-tls-crypto/esp_tls_crypto.c esp_tls_error_capture.c esp_tls_platform_port.c)
 if(CONFIG_ESP_TLS_USING_MBEDTLS)
     list(APPEND srcs
         "esp_tls_mbedtls.c")
@@ -9,7 +9,7 @@ if(CONFIG_ESP_TLS_USING_WOLFSSL)
         "esp_tls_wolfssl.c")
 endif()
 
-set(priv_req http_parser)
+set(priv_req http_parser esp_timer)
 if(NOT ${IDF_TARGET} STREQUAL "linux")
     list(APPEND priv_req lwip)
 endif()
@@ -17,7 +17,7 @@ endif()
 idf_component_register(SRCS "${srcs}"
                     INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR} esp-tls-crypto
                     PRIV_INCLUDE_DIRS "private_include"
-                    # mbedtls is public requirements becasue esp_tls.h
+                    # mbedtls is public requirements because esp_tls.h
                     # includes mbedtls header files.
                     REQUIRES mbedtls
                     PRIV_REQUIRES ${priv_req})

components/esp-tls/esp_tls.c

@@ -16,6 +16,7 @@
 #include "sdkconfig.h"
 #include "esp_tls.h"
 #include "esp_tls_private.h"
+#include "esp_tls_platform_port.h"
 #include "esp_tls_error_capture_internal.h"
 #include <fcntl.h>
 #include <errno.h>
@@ -537,9 +538,8 @@ int esp_tls_conn_new_sync(const char *hostname, int hostlen, int port, const esp
     if (!cfg || !tls || !hostname || hostlen < 0) {
         return -1;
     }
-    struct timeval time = {};
-    gettimeofday(&time, NULL);
-    uint32_t start_time_ms = (time.tv_sec * 1000) + (time.tv_usec / 1000);
+    uint64_t start_time_us;
+    start_time_us = esp_tls_get_platform_time();
     while (1) {
         int ret = esp_tls_low_level_conn(hostname, hostlen, port, cfg, tls);
         if (ret == 1) {
@@ -548,10 +548,8 @@ int esp_tls_conn_new_sync(const char *hostname, int hostlen, int port, const esp
             ESP_LOGE(TAG, "Failed to open new connection");
             return -1;
         } else if (ret == 0 && cfg->timeout_ms >= 0) {
-            gettimeofday(&time, NULL);
-            uint32_t current_time_ms = (time.tv_sec * 1000) + (time.tv_usec / 1000);
-            uint32_t elapsed_time_ms = current_time_ms - start_time_ms;
-            if (elapsed_time_ms >= cfg->timeout_ms) {
+            uint64_t elapsed_time_us = esp_tls_get_platform_time() - start_time_us;
+            if ((elapsed_time_us / 1000) >= cfg->timeout_ms) {
                 ESP_LOGW(TAG, "Failed to open new connection in specified timeout");
                 ESP_INT_EVENT_TRACKER_CAPTURE(tls->error_handle, ESP_TLS_ERR_TYPE_ESP, ESP_ERR_ESP_TLS_CONNECTION_TIMEOUT);
                 return 0;

components/esp-tls/esp_tls_platform_port.c

@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+
+#if CONFIG_IDF_TARGET_LINUX
+#include <sys/time.h>
+#include <time.h>
+#else
+#include "esp_timer.h"
+#endif
+
+uint64_t esp_tls_get_platform_time(void)
+{
+#if CONFIG_IDF_TARGET_LINUX
+    // Use gettimeofday for Linux/MacOS, Ideally esp_timer should be used but it is not implemented for Linux/MacOS.
+    struct timeval time = {};
+    gettimeofday(&time, NULL);
+    uint64_t curr_time = ((uint64_t)time.tv_sec * 1000000) + (time.tv_usec);
+    return curr_time;
+#else
+    // For all other esp targets use esp_timer
+    return esp_timer_get_time();
+#endif
+}

components/esp-tls/private_include/esp_tls_platform_port.h

@@ -0,0 +1,24 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This file contains APIs which have different implementation across different targets e.g., Linux, ESP.
+
+#pragma once
+
+#include <stdint.h>
+
+/* @brief
+ *
+ *      Behaviour
+ *      Linux:
+ *          Returns the system time (64 bit) using gettimeofday in microseconds. This shall get changed if someone changes the system time using settimeofday
+ *      ESP targets:
+ *          Returns the time (64 bit) since boot obtained using esp_timer_get_time() in microseconds
+ * @return
+ *      time    uint64_t bit time value
+ *
+ */
+uint64_t esp_tls_get_platform_time(void);

components/esp_driver_cam/esp_cam_ctlr.c

@@ -84,7 +84,7 @@ esp_err_t esp_cam_ctlr_get_frame_buffer_len(esp_cam_ctlr_handle_t handle, size_t
     return handle->get_buffer_len(handle, ret_fb_len);
 }
 
-esp_err_t esp_cam_del_ctlr(esp_cam_ctlr_handle_t handle)
+esp_err_t esp_cam_ctlr_del(esp_cam_ctlr_handle_t handle)
 {
     ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
     ESP_RETURN_ON_FALSE(handle->del, ESP_ERR_NOT_SUPPORTED, TAG, "controller driver function not supported");

components/esp_driver_cam/include/esp_cam_ctlr.h

@@ -87,7 +87,7 @@ esp_err_t esp_cam_ctlr_receive(esp_cam_ctlr_handle_t handle, esp_cam_ctlr_trans_
  *        - ESP_ERR_INVALID_ARG:   Invalid argument
  *        - ESP_ERR_INVALID_STATE: Invalid state
  */
-esp_err_t esp_cam_del_ctlr(esp_cam_ctlr_handle_t handle);
+esp_err_t esp_cam_ctlr_del(esp_cam_ctlr_handle_t handle);
 
 /**
  * @brief Register ESP CAM controller event callbacks

components/esp_driver_cam/test_apps/csi/main/test_csi_driver.c

@@ -32,7 +32,7 @@ TEST_CASE("TEST CSI driver allocation", "[csi]")
     TEST_ESP_OK(esp_cam_ctlr_get_frame_buffer_len(handle, &bk_buffer_len));
     TEST_ASSERT_NOT_NULL(bk_buffer);
     TEST_ASSERT_EQUAL((csi_config.h_res * csi_config.v_res * 2), bk_buffer_len); // out type RGB565 using 2 byte / pixel
-    TEST_ESP_OK(esp_cam_del_ctlr(handle));
+    TEST_ESP_OK(esp_cam_ctlr_del(handle));
 }
 
 TEST_CASE("TEST CSI driver no backup buffer usage", "[csi]")
@@ -59,5 +59,5 @@ TEST_CASE("TEST CSI driver no backup buffer usage", "[csi]")
     TEST_ESP_ERR(ESP_ERR_INVALID_STATE, esp_cam_ctlr_get_frame_buffer_len(handle, &bk_buffer_len));
     TEST_ASSERT_NULL(bk_buffer);
     TEST_ASSERT_EQUAL(0, bk_buffer_len);
-    TEST_ESP_OK(esp_cam_del_ctlr(handle));
+    TEST_ESP_OK(esp_cam_ctlr_del(handle));
 }

components/esp_driver_gpio/include/driver/gpio_etm.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,20 +13,29 @@
 extern "C" {
 #endif
 
+#define GPIO_ETM_EVENT_EDGE_TYPES   3   /*!< GPIO ETM edge events are POS/NEG/ANY */
+#define GPIO_ETM_TASK_ACTION_TYPES  3   /*!< GPIO ETM action tasks are SET/CLEAR/TOGGLE */
+
 /**
  * @brief GPIO edges that can be used as ETM event
  */
 typedef enum {
-    GPIO_ETM_EVENT_EDGE_POS, /*!< A rising edge on the GPIO will generate an ETM event signal */
-    GPIO_ETM_EVENT_EDGE_NEG, /*!< A falling edge on the GPIO will generate an ETM event signal */
-    GPIO_ETM_EVENT_EDGE_ANY, /*!< Any edge on the GPIO can generate an ETM event signal */
+    GPIO_ETM_EVENT_EDGE_POS = 1,    /*!< A rising edge on the GPIO will generate an ETM event signal */
+    GPIO_ETM_EVENT_EDGE_NEG,        /*!< A falling edge on the GPIO will generate an ETM event signal */
+    GPIO_ETM_EVENT_EDGE_ANY,        /*!< Any edge on the GPIO can generate an ETM event signal */
 } gpio_etm_event_edge_t;
 
 /**
  * @brief GPIO ETM event configuration
+ *
+ * If more than one kind of ETM edge event want to be triggered on the same GPIO pin, you can configure them together.
+ * It helps to save GPIO ETM event channel resources for other GPIOs.
  */
 typedef struct {
-    gpio_etm_event_edge_t edge; /*!< Which kind of edge can trigger the ETM event module */
+    union {
+        gpio_etm_event_edge_t edge;                                 /*!< Which kind of edge can trigger the ETM event module */
+        gpio_etm_event_edge_t edges[GPIO_ETM_EVENT_EDGE_TYPES];     /*!< Array of kinds of edges to trigger the ETM event module on the same GPIO */
+    };
 } gpio_etm_event_config_t;
 
 /**
@@ -34,9 +43,11 @@ typedef struct {
  *
  * @note The created ETM event object can be deleted later by calling `esp_etm_del_event`
  * @note The newly created ETM event object is not bind to any GPIO, you need to call `gpio_etm_event_bind_gpio` to bind the wanted GPIO
+ * @note Every success call to this function will acquire a free GPIO ETM event channel
  *
  * @param[in] config GPIO ETM event configuration
  * @param[out] ret_event Returned ETM event handle
+ * @param[out] ...  Other returned ETM event handles if any (the order of the returned event handles is aligned with the array order in field `edges` in `gpio_etm_event_config_t`)
  * @return
  *      - ESP_OK: Create ETM event successfully
  *      - ESP_ERR_INVALID_ARG: Create ETM event failed because of invalid argument
@@ -44,7 +55,7 @@ typedef struct {
  *      - ESP_ERR_NOT_FOUND: Create ETM event failed because all events are used up and no more free one
  *      - ESP_FAIL: Create ETM event failed because of other reasons
  */
-esp_err_t gpio_new_etm_event(const gpio_etm_event_config_t *config, esp_etm_event_handle_t *ret_event);
+esp_err_t gpio_new_etm_event(const gpio_etm_event_config_t *config, esp_etm_event_handle_t *ret_event, ...);
 
 /**
  * @brief Bind the GPIO with the ETM event
@@ -65,16 +76,21 @@ esp_err_t gpio_etm_event_bind_gpio(esp_etm_event_handle_t event, int gpio_num);
  * @brief GPIO actions that can be taken by the ETM task
  */
 typedef enum {
-    GPIO_ETM_TASK_ACTION_SET, /*!< Set the GPIO level to high */
-    GPIO_ETM_TASK_ACTION_CLR, /*!< Clear the GPIO level to low */
-    GPIO_ETM_TASK_ACTION_TOG, /*!< Toggle the GPIO level */
+    GPIO_ETM_TASK_ACTION_SET = 1,   /*!< Set the GPIO level to high */
+    GPIO_ETM_TASK_ACTION_CLR,       /*!< Clear the GPIO level to low */
+    GPIO_ETM_TASK_ACTION_TOG,       /*!< Toggle the GPIO level */
 } gpio_etm_task_action_t;
 
 /**
  * @brief GPIO ETM task configuration
+ *
+ * If multiple actions wants to be added to the same GPIO pin, you have to configure all the GPIO ETM tasks together.
  */
 typedef struct {
-    gpio_etm_task_action_t action; /*!< Which action to take by the ETM task module */
+    union {
+        gpio_etm_task_action_t action;                                  /*!< Action to take by the ETM task module */
+        gpio_etm_task_action_t actions[GPIO_ETM_TASK_ACTION_TYPES];     /*!< Array of actions to take by the ETM task module on the same GPIO */
+    };
 } gpio_etm_task_config_t;
 
 /**
@@ -83,9 +99,11 @@ typedef struct {
  * @note The created ETM task object can be deleted later by calling `esp_etm_del_task`
  * @note The GPIO ETM task works like a container, a newly created ETM task object doesn't have GPIO members to be managed.
  *       You need to call `gpio_etm_task_add_gpio` to put one or more GPIOs to the container.
+ * @note Every success call to this function will acquire a free GPIO ETM task channel
  *
  * @param[in] config GPIO ETM task configuration
  * @param[out] ret_task Returned ETM task handle
+ * @param[out] ...  Other returned ETM task handles if any (the order of the returned task handles is aligned with the array order in field `actions` in `gpio_etm_task_config_t`)
  * @return
  *      - ESP_OK: Create ETM task successfully
  *      - ESP_ERR_INVALID_ARG: Create ETM task failed because of invalid argument
@@ -93,7 +111,7 @@ typedef struct {
  *      - ESP_ERR_NOT_FOUND: Create ETM task failed because all tasks are used up and no more free one
  *      - ESP_FAIL: Create ETM task failed because of other reasons
  */
-esp_err_t gpio_new_etm_task(const gpio_etm_task_config_t *config, esp_etm_task_handle_t *ret_task);
+esp_err_t gpio_new_etm_task(const gpio_etm_task_config_t *config, esp_etm_task_handle_t *ret_task, ...);
 
 /**
  * @brief Add GPIO to the ETM task.

components/esp_driver_gpio/src/gpio_etm.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,19 +34,23 @@ typedef struct gpio_etm_event_t gpio_etm_event_t;
 typedef struct gpio_etm_group_t {
     portMUX_TYPE spinlock;
     gpio_etm_dev_t *dev;
-    gpio_etm_task_t *tasks[SOC_GPIO_ETM_TASKS_PER_GROUP];
-    gpio_etm_event_t *events[SOC_GPIO_ETM_EVENTS_PER_GROUP];
+    uint8_t tasks[GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP];           // Array of the acquired action masks in each GPIO ETM task channel
+    uint8_t events[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP];         // Array of the acquired event masks in each GPIO ETM event channel
+    uint8_t actions[SOC_GPIO_PIN_COUNT];                          // Array of the masks of the added actions to each GPIO
+    uint8_t edges[GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP];          // Array of the masks of the bound event edges in each GPIO ETM event channel
 } gpio_etm_group_t;
 
 struct gpio_etm_event_t {
     esp_etm_event_t base;
     int chan_id;
+    gpio_etm_event_edge_t edge_id;
     gpio_etm_group_t *group;
 };
 
 struct gpio_etm_task_t {
     esp_etm_task_t base;
     int chan_id;
+    gpio_etm_task_action_t action_id;
     gpio_etm_group_t *group;
     size_t num_of_gpios;     // record the number of GPIOs that are bound to the etm task
 };
@@ -56,81 +60,65 @@ static gpio_etm_group_t s_gpio_etm_group = {
     .spinlock = portMUX_INITIALIZER_UNLOCKED,
 };
 
-static esp_err_t gpio_etm_event_register_to_group(gpio_etm_event_t *event)
+static esp_err_t gpio_etm_acquire_event_channel(uint8_t event_mask, int *chan_id)
 {
+    assert(chan_id);
     gpio_etm_group_t *group = &s_gpio_etm_group;
-    int chan_id = -1;
-    // loop to search free one in the group
+
+    int free_chan_id = -1;
+    // loop to search free event channel in the group
     portENTER_CRITICAL(&group->spinlock);
-    for (int j = 0; j < SOC_GPIO_ETM_EVENTS_PER_GROUP; j++) {
+    for (int j = 0; j < GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP; j++) {
         if (!group->events[j]) {
-            chan_id = j;
-            group->events[j] = event;
+            free_chan_id = j;
+            group->events[j] = event_mask;
             break;
         }
     }
     portEXIT_CRITICAL(&group->spinlock);
 
-    ESP_RETURN_ON_FALSE(chan_id != -1, ESP_ERR_NOT_FOUND, TAG, "no free event channel");
-    event->group = group;
-    event->chan_id = chan_id;
+    ESP_RETURN_ON_FALSE(free_chan_id != -1, ESP_ERR_NOT_FOUND, TAG, "no free event channel");
+    *chan_id = free_chan_id;
     return ESP_OK;
 }
 
-static esp_err_t gpio_etm_task_register_to_group(gpio_etm_task_t *task)
+static esp_err_t gpio_etm_release_event_channel(int chan_id, uint8_t event_mask)
 {
     gpio_etm_group_t *group = &s_gpio_etm_group;
-    int chan_id = -1;
-    // loop to search free one in the group
     portENTER_CRITICAL(&group->spinlock);
-    for (int j = 0; j < SOC_GPIO_ETM_TASKS_PER_GROUP; j++) {
+    group->events[chan_id] &= ~event_mask;
+    portEXIT_CRITICAL(&group->spinlock);
+    return ESP_OK;
+}
+
+static esp_err_t gpio_etm_acquire_task_channel(uint8_t task_mask, int *chan_id)
+{
+    assert(chan_id);
+    gpio_etm_group_t *group = &s_gpio_etm_group;
+
+    int free_chan_id = -1;
+    // loop to search free task channel in the group
+    portENTER_CRITICAL(&group->spinlock);
+    for (int j = 0; j < GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP; j++) {
         if (!group->tasks[j]) {
-            chan_id = j;
-            group->tasks[j] = task;
+            free_chan_id = j;
+            group->tasks[j] = task_mask;
             break;
         }
     }
     portEXIT_CRITICAL(&group->spinlock);
 
-    ESP_RETURN_ON_FALSE(chan_id != -1, ESP_ERR_NOT_FOUND, TAG, "no free task channel");
-    task->group = group;
-    task->chan_id = chan_id;
+    ESP_RETURN_ON_FALSE(free_chan_id != -1, ESP_ERR_NOT_FOUND, TAG, "no free task channel");
+    *chan_id = free_chan_id;
     return ESP_OK;
 }
 
-static void gpio_etm_event_unregister_from_group(gpio_etm_event_t *event)
+static esp_err_t gpio_etm_release_task_channel(int chan_id, uint8_t task_mask)
 {
-    gpio_etm_group_t *group = event->group;
-    int chan_id = event->chan_id;
+    gpio_etm_group_t *group = &s_gpio_etm_group;
     portENTER_CRITICAL(&group->spinlock);
-    group->events[chan_id] = NULL;
+    group->tasks[chan_id] &= ~task_mask;
     portEXIT_CRITICAL(&group->spinlock);
-}
-
-static void gpio_etm_task_unregister_from_group(gpio_etm_task_t *task)
-{
-    gpio_etm_group_t *group = task->group;
-    int chan_id = task->chan_id;
-    portENTER_CRITICAL(&group->spinlock);
-    group->tasks[chan_id] = NULL;
-    portEXIT_CRITICAL(&group->spinlock);
-}
-
-static esp_err_t gpio_etm_event_destroy(gpio_etm_event_t *event)
-{
-    if (event->group) {
-        gpio_etm_event_unregister_from_group(event);
-    }
-    free(event);
-    return ESP_OK;
-}
-
-static esp_err_t gpio_etm_task_destroy(gpio_etm_task_t *task)
-{
-    if (task->group) {
-        gpio_etm_task_unregister_from_group(task);
-    }
-    free(task);
     return ESP_OK;
 }
 
@@ -138,9 +126,16 @@ static esp_err_t gpio_del_etm_event(esp_etm_event_t *event)
 {
     gpio_etm_event_t *gpio_event = __containerof(event, gpio_etm_event_t, base);
     gpio_etm_group_t *group = gpio_event->group;
-    // disable event channel
-    gpio_ll_etm_enable_event_channel(group->dev, gpio_event->chan_id, false);
-    gpio_etm_event_destroy(gpio_event);
+    // unbind it from the GPIO and check if the GPIO ETM event channel can be disabled
+    portENTER_CRITICAL(&group->spinlock);
+    group->edges[gpio_event->chan_id] &= ~(1 << gpio_event->edge_id);
+    if (!group->edges[gpio_event->chan_id]) {
+        gpio_ll_etm_enable_event_channel(group->dev, gpio_event->chan_id, false);
+    }
+    portEXIT_CRITICAL(&group->spinlock);
+
+    gpio_etm_release_event_channel(gpio_event->chan_id, 1 << gpio_event->edge_id);
+    free(gpio_event);
     return ESP_OK;
 }
 
@@ -149,95 +144,192 @@ static esp_err_t gpio_del_etm_task(esp_etm_task_t *task)
     gpio_etm_task_t *gpio_task = __containerof(task, gpio_etm_task_t, base);
     // make sure user has called `gpio_etm_task_rm_gpio` to clean the etm task channel
     ESP_RETURN_ON_FALSE(gpio_task->num_of_gpios == 0, ESP_ERR_INVALID_STATE, TAG, "some GPIO till bounded to the etm task");
-    gpio_etm_task_destroy(gpio_task);
+    gpio_etm_release_task_channel(gpio_task->chan_id, 1 << gpio_task->action_id);
+    free(gpio_task);
     return ESP_OK;
 }
 
-esp_err_t gpio_new_etm_event(const gpio_etm_event_config_t *config, esp_etm_event_handle_t *ret_event)
+esp_err_t gpio_new_etm_event(const gpio_etm_event_config_t *config, esp_etm_event_handle_t *ret_event, ...)
 {
 #if CONFIG_ETM_ENABLE_DEBUG_LOG
     esp_log_level_set(TAG, ESP_LOG_DEBUG);
 #endif
     esp_err_t ret = ESP_OK;
-    gpio_etm_event_t *event = NULL;
-    ESP_GOTO_ON_FALSE(config && ret_event, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    int chan_id = -1;
+    uint8_t event_mask = 0;
+    esp_etm_event_handle_t *ret_event_itor = ret_event;
+    va_list args;
+    ESP_RETURN_ON_FALSE(config && ret_event, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    for (int i = 0; i < GPIO_ETM_EVENT_EDGE_TYPES; i++) {
+        if (config->edges[i]) {
+            uint8_t msk = (1 << config->edges[i]);
+            ESP_RETURN_ON_FALSE(!(msk & event_mask), ESP_ERR_INVALID_ARG, TAG, "no identical edge event allowed in one call");
+            event_mask |= msk;
+        }
+    }
+    ESP_RETURN_ON_FALSE(event_mask, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    uint32_t event_num = __builtin_popcount(event_mask);
+    gpio_etm_event_t *events[event_num];
 
-    event = heap_caps_calloc(1, sizeof(gpio_etm_event_t), ETM_MEM_ALLOC_CAPS);
-    ESP_GOTO_ON_FALSE(event, ESP_ERR_NO_MEM, err, TAG, "no mem for event channel");
-    // register the event channel to the group
-    ESP_GOTO_ON_ERROR(gpio_etm_event_register_to_group(event), err, TAG, "register event channel to group failed");
-    int chan_id = event->chan_id;
-
-    uint32_t event_id = 0;
-    switch (config->edge) {
-    case GPIO_ETM_EVENT_EDGE_ANY:
-        event_id = GPIO_LL_ETM_EVENT_ID_ANY_EDGE(chan_id);
-        break;
-    case GPIO_ETM_EVENT_EDGE_POS:
-        event_id = GPIO_LL_ETM_EVENT_ID_POS_EDGE(chan_id);
-        break;
-    case GPIO_ETM_EVENT_EDGE_NEG:
-        event_id = GPIO_LL_ETM_EVENT_ID_NEG_EDGE(chan_id);
-        break;
-    default:
-        ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid edge");
+    for (int i = 0; i < event_num; i++) {
+        events[i] = (gpio_etm_event_t *)heap_caps_calloc(1, sizeof(gpio_etm_event_t), ETM_MEM_ALLOC_CAPS);
+        ESP_GOTO_ON_FALSE(events[i], ESP_ERR_NO_MEM, err, TAG, "no mem for event channel(s)");
     }
 
-    event->base.del = gpio_del_etm_event;
-    event->base.event_id = event_id;
-    event->base.trig_periph = ETM_TRIG_PERIPH_GPIO;
-    ESP_LOGD(TAG, "new event @%p, event_id=%"PRIu32", chan_id=%d", event, event_id, chan_id);
-    *ret_event = &event->base;
+    // register the event channel to the group
+    ESP_GOTO_ON_ERROR(gpio_etm_acquire_event_channel(event_mask, &chan_id), err, TAG, "register event channel to group failed");
+
+    bool no_avail_ret_arg = false;
+    va_start(args, ret_event);
+    for (int i = 0, j = 0; i < event_num; i++, j++) {
+        if (!ret_event_itor) {
+            no_avail_ret_arg = true;
+            break;
+        }
+        // assign to the ret_event handles in the configuration order
+        gpio_etm_event_edge_t event_edge;
+        do {
+            event_edge = config->edges[j];
+        } while (!event_edge && ++j);
+        uint32_t event_id = 0;
+        switch (event_edge) {
+        case GPIO_ETM_EVENT_EDGE_ANY:
+            event_id = GPIO_LL_ETM_EVENT_ID_ANY_EDGE(chan_id);
+            break;
+        case GPIO_ETM_EVENT_EDGE_POS:
+            event_id = GPIO_LL_ETM_EVENT_ID_POS_EDGE(chan_id);
+            break;
+        case GPIO_ETM_EVENT_EDGE_NEG:
+            event_id = GPIO_LL_ETM_EVENT_ID_NEG_EDGE(chan_id);
+            break;
+        default:
+            va_end(args);
+            ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid edge");
+        }
+
+        gpio_etm_event_t *event = events[i];
+        event->base.del = gpio_del_etm_event;
+        event->base.event_id = event_id;
+        event->base.trig_periph = ETM_TRIG_PERIPH_GPIO;
+        event->group = &s_gpio_etm_group;
+        event->chan_id = chan_id;
+        event->edge_id = event_edge;
+        ESP_LOGD(TAG, "new event @%p, event_id=%"PRIu32", chan_id=%d", event, event_id, chan_id);
+        *ret_event_itor = &event->base;
+        ret_event_itor = va_arg(args, esp_etm_event_handle_t *);
+    }
+    va_end(args);
+    ESP_GOTO_ON_FALSE(!no_avail_ret_arg, ESP_ERR_INVALID_ARG, err, TAG, "mismatch number of events with number of pointers to store event handles");
     return ESP_OK;
 
 err:
-    if (event) {
-        gpio_etm_event_destroy(event);
+    if (chan_id != -1) {
+        gpio_etm_release_event_channel(chan_id, event_mask);
     }
+    for (int i = 0; i < event_num; i++) {
+        if (events[i]) {
+            free(events[i]);
+        }
+    }
+    ret_event_itor = ret_event;
+    va_start(args, ret_event);
+    while (ret_event_itor) {
+        *ret_event_itor = NULL;
+        ret_event_itor = va_arg(args, esp_etm_event_handle_t *);
+    }
+    va_end(args);
     return ret;
 }
 
-esp_err_t gpio_new_etm_task(const gpio_etm_task_config_t *config, esp_etm_task_handle_t *ret_task)
+esp_err_t gpio_new_etm_task(const gpio_etm_task_config_t *config, esp_etm_task_handle_t *ret_task, ...)
 {
 #if CONFIG_ETM_ENABLE_DEBUG_LOG
     esp_log_level_set(TAG, ESP_LOG_DEBUG);
 #endif
     esp_err_t ret = ESP_OK;
-    gpio_etm_task_t *task = NULL;
-    ESP_GOTO_ON_FALSE(config && ret_task, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    int chan_id = -1;
+    uint8_t task_mask = 0;
+    esp_etm_task_handle_t *ret_task_itor = ret_task;
+    va_list args;
+    ESP_RETURN_ON_FALSE(config && ret_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    for (int i = 0; i < GPIO_ETM_TASK_ACTION_TYPES; i++) {
+        if (config->actions[i]) {
+            uint8_t msk = (1 << config->actions[i]);
+            ESP_RETURN_ON_FALSE(!(msk & task_mask), ESP_ERR_INVALID_ARG, TAG, "no identical action allowed in one call");
+            task_mask |= msk;
+        }
+    }
+    ESP_RETURN_ON_FALSE(task_mask, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    uint32_t task_num = __builtin_popcount(task_mask);
+    gpio_etm_task_t *tasks[task_num];
 
-    task = heap_caps_calloc(1, sizeof(gpio_etm_task_t), ETM_MEM_ALLOC_CAPS);
-    ESP_GOTO_ON_FALSE(task, ESP_ERR_NO_MEM, err, TAG, "no mem for task channel");
-    // register the task channel to the group
-    ESP_GOTO_ON_ERROR(gpio_etm_task_register_to_group(task), err, TAG, "register task channel to group failed");
-    int chan_id = task->chan_id;
-
-    uint32_t task_id = 0;
-    switch (config->action) {
-    case GPIO_ETM_TASK_ACTION_SET:
-        task_id = GPIO_LL_ETM_TASK_ID_SET(chan_id);
-        break;
-    case GPIO_ETM_TASK_ACTION_CLR:
-        task_id = GPIO_LL_ETM_TASK_ID_CLR(chan_id);
-        break;
-    case GPIO_ETM_TASK_ACTION_TOG:
-        task_id = GPIO_LL_ETM_TASK_ID_TOG(chan_id);
-        break;
-    default:
-        ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid action");
+    for (int i = 0; i < task_num; i++) {
+        tasks[i] = (gpio_etm_task_t *)heap_caps_calloc(1, sizeof(gpio_etm_task_t), ETM_MEM_ALLOC_CAPS);
+        ESP_GOTO_ON_FALSE(tasks[i], ESP_ERR_NO_MEM, err, TAG, "no mem for task channel(s)");
     }
 
-    task->base.del = gpio_del_etm_task;
-    task->base.task_id = task_id;
-    task->base.trig_periph = ETM_TRIG_PERIPH_GPIO;
-    ESP_LOGD(TAG, "new task @%p, task_id=%"PRIu32", chan_id=%d", task, task_id, chan_id);
-    *ret_task = &task->base;
+    // register the task channel to the group
+    ESP_GOTO_ON_ERROR(gpio_etm_acquire_task_channel(task_mask, &chan_id), err, TAG, "register task channel to group failed");
+
+    bool no_avail_ret_arg = false;
+    va_start(args, ret_task);
+    for (int i = 0, j = 0; i < task_num; i++, j++) {
+        if (!ret_task_itor) {
+            no_avail_ret_arg = true;
+            break;
+        }
+        // assign to the ret_task handles in the configuration order
+        gpio_etm_task_action_t action;
+        do {
+            action = config->actions[i];
+        } while (!action && ++j);
+        uint32_t task_id = 0;
+        switch (action) {
+        case GPIO_ETM_TASK_ACTION_SET:
+            task_id = GPIO_LL_ETM_TASK_ID_SET(chan_id);
+            break;
+        case GPIO_ETM_TASK_ACTION_CLR:
+            task_id = GPIO_LL_ETM_TASK_ID_CLR(chan_id);
+            break;
+        case GPIO_ETM_TASK_ACTION_TOG:
+            task_id = GPIO_LL_ETM_TASK_ID_TOG(chan_id);
+            break;
+        default:
+            va_end(args);
+            ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid action");
+        }
+
+        gpio_etm_task_t *task = tasks[i];
+        task->base.del = gpio_del_etm_task;
+        task->base.task_id = task_id;
+        task->base.trig_periph = ETM_TRIG_PERIPH_GPIO;
+        task->group = &s_gpio_etm_group;
+        task->chan_id = chan_id;
+        task->action_id = action;
+        ESP_LOGD(TAG, "new task @%p, task_id=%"PRIu32", gpio_etm_task_chan_id=%d", task, task_id, chan_id);
+        *ret_task_itor = &task->base;
+        ret_task_itor = va_arg(args, esp_etm_task_handle_t *);
+    }
+    va_end(args);
+    ESP_GOTO_ON_FALSE(!no_avail_ret_arg, ESP_ERR_INVALID_ARG, err, TAG, "mismatch number of tasks with number of pointers to store task handles");
     return ESP_OK;
 
 err:
-    if (task) {
-        gpio_etm_task_destroy(task);
+    if (chan_id != -1) {
+        gpio_etm_release_task_channel(chan_id, task_mask);
     }
+    for (int i = 0; i < task_num; i++) {
+        if (tasks[i]) {
+            free(tasks[i]);
+        }
+    }
+    ret_task_itor = ret_task;
+    va_start(args, ret_task);
+    while (ret_task_itor) {
+        *ret_task_itor = NULL;
+        ret_task_itor = va_arg(args, esp_etm_task_handle_t *);
+    }
+    va_end(args);
     return ret;
 }
 
@@ -248,12 +340,27 @@ esp_err_t gpio_etm_event_bind_gpio(esp_etm_event_handle_t event, int gpio_num)
     ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "gpio is not input capable");
     gpio_etm_event_t *gpio_event = __containerof(event, gpio_etm_event_t, base);
     gpio_etm_group_t *group = gpio_event->group;
-    // disable gpio etm event channel first
-    gpio_ll_etm_enable_event_channel(group->dev, gpio_event->chan_id, false);
-    // then set the gpio number
-    gpio_ll_etm_event_channel_set_gpio(group->dev, gpio_event->chan_id, gpio_num);
-    // enable gpio etm event channel again
-    gpio_ll_etm_enable_event_channel(group->dev, gpio_event->chan_id, true);
+
+    bool allowed = true;
+    portENTER_CRITICAL(&group->spinlock);
+    // check if the GPIO ETM event channel where the new event belongs to has previously been bound to another GPIO
+    // one GPIO ETM event channel can only be bound to one GPIO
+    if (group->edges[gpio_event->chan_id]) {
+        if (gpio_ll_etm_event_channel_get_gpio(group->dev, gpio_event->chan_id) != gpio_num) {
+            allowed = false;
+        }
+    } else {
+        // set the GPIO number
+        gpio_ll_etm_event_channel_set_gpio(group->dev, gpio_event->chan_id, gpio_num);
+        // enable GPIO ETM event channel
+        gpio_ll_etm_enable_event_channel(group->dev, gpio_event->chan_id, true);
+    }
+
+    if (allowed) {
+        group->edges[gpio_event->chan_id] |= (1 << gpio_event->edge_id);
+    }
+    portEXIT_CRITICAL(&group->spinlock);
+    ESP_RETURN_ON_FALSE(allowed, ESP_ERR_INVALID_ARG, TAG, "the GPIO ETM event channel where the event belongs to has already been bound to another GPIO");
     return ESP_OK;
 }
 
@@ -264,19 +371,28 @@ esp_err_t gpio_etm_task_add_gpio(esp_etm_task_handle_t task, int gpio_num)
     ESP_RETURN_ON_FALSE(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "gpio is not output capable");
     gpio_etm_task_t *gpio_task = __containerof(task, gpio_etm_task_t, base);
     gpio_etm_group_t *group = gpio_task->group;
-    bool gpio_not_enabled = true;
+
+    bool allowed = true;
     // use spinlock as this function may be called with different task object in different threads
     // and the gpio_num might reside in the same register
     portENTER_CRITICAL(&group->spinlock);
-    // check if the gpio has been enabled
-    if (!gpio_ll_etm_is_task_gpio_enabled(group->dev, gpio_num)) {
+    // check if the new task is compatible with the tasks that has previously been added to the GPIO
+    // the tasks have to be from the same GPIO ETM task channel
+    if (group->actions[gpio_num]) {
+        if (gpio_ll_etm_gpio_get_task_channel(group->dev, gpio_num) != gpio_task->chan_id) {
+            allowed = false;
+        }
+    } else {
+        // first action added to the GPIO
         gpio_ll_etm_gpio_set_task_channel(group->dev, gpio_num, gpio_task->chan_id);
         gpio_ll_etm_enable_task_gpio(group->dev, gpio_num, true);
-    } else {
-        gpio_not_enabled = false;
+    }
+
+    if (allowed) {
+        group->actions[gpio_num] |= (1 << gpio_task->action_id);
     }
     portEXIT_CRITICAL(&group->spinlock);
-    ESP_RETURN_ON_FALSE(gpio_not_enabled, ESP_ERR_INVALID_STATE, TAG, "gpio already enabled by other task channel");
+    ESP_RETURN_ON_FALSE(allowed, ESP_ERR_INVALID_ARG, TAG, "the task does not belong to the GPIO ETM task channel that the GPIO has already binded to");
     gpio_task->num_of_gpios++;
     return ESP_OK;
 }
@@ -287,19 +403,24 @@ esp_err_t gpio_etm_task_rm_gpio(esp_etm_task_handle_t task, int gpio_num)
     ESP_RETURN_ON_FALSE(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "gpio is not output capable");
     gpio_etm_task_t *gpio_task = __containerof(task, gpio_etm_task_t, base);
     gpio_etm_group_t *group = gpio_task->group;
-    bool gpio_enabled_by_this_task = true;
+
+    bool allowed = true;
     // use spinlock as this function may be called with different task object in different threads
     // and the gpio_num might reside in the same register
     portENTER_CRITICAL(&group->spinlock);
-    // check if the gpio is managed by this etm task channel
-    if (gpio_ll_etm_is_task_gpio_enabled(group->dev, gpio_num) &&
+    if ((group->actions[gpio_num] & (1 << gpio_task->action_id)) &&
+            gpio_ll_etm_is_task_gpio_enabled(group->dev, gpio_num) &&
             (gpio_ll_etm_gpio_get_task_channel(group->dev, gpio_num) == gpio_task->chan_id)) {
-        gpio_ll_etm_enable_task_gpio(group->dev, gpio_num, false);
+        group->actions[gpio_num] &= ~(1 << gpio_task->action_id);
+        if (!group->actions[gpio_num]) {
+            // all actions removed from the GPIO
+            gpio_ll_etm_enable_task_gpio(group->dev, gpio_num, false);
+        }
     } else {
-        gpio_enabled_by_this_task = false;
+        allowed = false;
     }
     portEXIT_CRITICAL(&group->spinlock);
-    ESP_RETURN_ON_FALSE(gpio_enabled_by_this_task, ESP_ERR_INVALID_STATE, TAG, "gpio is not enabled by this task channel");
+    ESP_RETURN_ON_FALSE(allowed, ESP_ERR_INVALID_ARG, TAG, "the task was not added to the GPIO");
     gpio_task->num_of_gpios--;
     return ESP_OK;
 }

components/esp_driver_jpeg/jpeg_decode.c

@@ -271,7 +271,6 @@ err:
 esp_err_t jpeg_del_decoder_engine(jpeg_decoder_handle_t decoder_engine)
 {
     ESP_RETURN_ON_FALSE(decoder_engine, ESP_ERR_INVALID_ARG, TAG, "jpeg decode handle is null");
-    ESP_RETURN_ON_ERROR(jpeg_release_codec_handle(decoder_engine->codec_base), TAG, "release codec failed");
 
     if (decoder_engine) {
         if (decoder_engine->rxlink) {
@@ -295,6 +294,7 @@ esp_err_t jpeg_del_decoder_engine(jpeg_decoder_handle_t decoder_engine)
         if (decoder_engine->intr_handle) {
             jpeg_isr_deregister(decoder_engine->codec_base, decoder_engine->intr_handle);
         }
+        ESP_RETURN_ON_ERROR(jpeg_release_codec_handle(decoder_engine->codec_base), TAG, "release codec failed");
         free(decoder_engine);
     }
     return ESP_OK;

components/esp_driver_jpeg/jpeg_encode.c

@@ -262,6 +262,7 @@ esp_err_t jpeg_encoder_process(jpeg_encoder_handle_t encoder_engine, const jpeg_
         }
 
         if (s_rcv_event.dma_evt & JPEG_DMA2D_RX_EOF) {
+            ESP_GOTO_ON_ERROR(esp_cache_msync((void*)encoder_engine->rxlink, encoder_engine->dma_desc_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C), err, TAG, "sync memory to cache failed");
             compressed_size = s_dma_desc_get_len(encoder_engine->rxlink);
             uint32_t _compressed_size = JPEG_ALIGN_UP(compressed_size, cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA));
             ESP_GOTO_ON_ERROR(esp_cache_msync((void*)(bit_stream + encoder_engine->header_info->header_len), _compressed_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C), err, TAG, "sync memory to cache failed");
@@ -283,7 +284,6 @@ err:
 esp_err_t jpeg_del_encoder_engine(jpeg_encoder_handle_t encoder_engine)
 {
     ESP_RETURN_ON_FALSE(encoder_engine, ESP_ERR_INVALID_ARG, TAG, "jpeg encoder handle is null");
-    ESP_RETURN_ON_ERROR(jpeg_release_codec_handle(encoder_engine->codec_base), TAG, "release codec failed");
 
     if (encoder_engine) {
         if (encoder_engine->rxlink) {
@@ -307,6 +307,7 @@ esp_err_t jpeg_del_encoder_engine(jpeg_encoder_handle_t encoder_engine)
         if (encoder_engine->intr_handle) {
             jpeg_isr_deregister(encoder_engine->codec_base, encoder_engine->intr_handle);
         }
+        ESP_RETURN_ON_ERROR(jpeg_release_codec_handle(encoder_engine->codec_base), TAG, "release codec failed");
         free(encoder_engine);
     }
     return ESP_OK;

components/esp_driver_jpeg/jpeg_parse_marker.c

@@ -130,10 +130,10 @@ esp_err_t jpeg_parse_sof_marker(jpeg_dec_header_info_t *header_info)
 
     // The vertical and horizontal in process must be divided by mcu block.
     if (header_info->origin_v % header_info->mcuy != 0) {
-        header_info->process_v = (ceil(header_info->origin_v / header_info->mcuy) + 1) * header_info->mcuy;
+        header_info->process_v = (uint32_t)(ceil(header_info->origin_v / header_info->mcuy) + 1) * header_info->mcuy;
     }
     if (header_info->origin_h % header_info->mcux != 0) {
-        header_info->process_h = (ceil(header_info->origin_h / header_info->mcux) + 1) * header_info->mcux;
+        header_info->process_h = (uint32_t)(ceil(header_info->origin_h / header_info->mcux) + 1) * header_info->mcux;
     }
 
     return ESP_OK;

components/esp_driver_jpeg/jpeg_private.h

@@ -87,7 +87,7 @@ typedef struct {
     uint8_t huffcode[2][2][JPEG_HUFFMAN_AC_VALUE_TABLE_LEN];    // Huffman decoded data tables [id][dcac]
     uint32_t tmp_huff[JPEG_HUFFMAN_AC_VALUE_TABLE_LEN];         // temp buffer to store huffman code
     bool dri_marker;                                            // If we have dri marker in table
-    uint8_t ri;                                                 // Restart interval
+    uint16_t ri;                                                // Restart interval
 } jpeg_dec_header_info_t;
 
 struct jpeg_decoder_t {

components/esp_hw_support/dma/Kconfig.dma

@@ -19,7 +19,7 @@ menu "GDMA Configurations"
         bool "Enable debug log"
         default n
         help
-            Wether to enable the debug log message for GDMA driver.
+            Whether to enable the debug log message for GDMA driver.
             Note that, this option only controls the GDMA driver log, won't affect other drivers.
 endmenu # GDMA Configurations
 
@@ -40,6 +40,13 @@ menu "DW_GDMA Configurations"
             Place DW_GDMA setter functions (e.g. dw_gdma_channel_set_block_markers) into IRAM,
             so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
 
+    config DW_GDMA_GETTER_FUNC_IN_IRAM
+        bool
+        default n
+        help
+            Place DW_GDMA getter functions (e.g. dw_gdma_link_list_get_item) into IRAM,
+            so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
+
     config DW_GDMA_ISR_IRAM_SAFE
         bool
         default n
@@ -52,7 +59,7 @@ menu "DW_GDMA Configurations"
         bool "Enable debug log"
         default n
         help
-            Wether to enable the debug log message for DW_GDMA driver.
+            Whether to enable the debug log message for DW_GDMA driver.
             Note that, this option only controls the DW_GDMA driver log, won't affect other drivers.
 endmenu # DW_GDMA Configurations
 

components/esp_hw_support/dma/linker.lf

@@ -78,10 +78,15 @@ entries:
     # put DW_GDMA control functions in IRAM
     if DW_GDMA_CTRL_FUNC_IN_IRAM = y:
         dw_gdma: dw_gdma_channel_continue (noflash)
+        dw_gdma: dw_gdma_channel_enable_ctrl (noflash)
 
     if DW_GDMA_SETTER_FUNC_IN_IRAM = y:
         dw_gdma: dw_gdma_channel_set_block_markers (noflash)
         dw_gdma: dw_gdma_lli_set_block_markers (noflash)
+        dw_gdma: dw_gdma_channel_use_link_list (noflash)
+
+    if DW_GDMA_GETTER_FUNC_IN_IRAM = y:
+        dw_gdma: dw_gdma_link_list_get_item (noflash)
 
 [mapping:dma2d_driver]
 archive: libesp_hw_support.a

components/esp_hw_support/port/linux/esp_random.c

@@ -17,13 +17,16 @@ static void __attribute__((constructor)) esp_random_init(void) { }
 uint32_t esp_random(void)
 {
     uint32_t random_number;
-    assert(getentropy(&random_number, sizeof(random_number)) == 0);
+    int result = getentropy(&random_number, sizeof(random_number));
+    assert(result == 0);
+    (void)result;
     return random_number;
 }
 
 void esp_fill_random(void *buf, size_t len)
 {
     assert(buf != NULL);
+    int result;
 
     // Note that we can't use getentropy() with len > 256 directly (see getentropy man page),
     // hence reading in chunks
@@ -31,8 +34,12 @@ void esp_fill_random(void *buf, size_t len)
     const size_t REST_CHUNK_SIZE = len % GETENTROPY_MAX_LEN;
 
     for (size_t chunk_num = 0; chunk_num < FULL_CHUNKS_NUM; chunk_num++) {
-        assert(getentropy(buf + chunk_num * GETENTROPY_MAX_LEN, GETENTROPY_MAX_LEN) == 0);
+        result = getentropy(buf + chunk_num * GETENTROPY_MAX_LEN, GETENTROPY_MAX_LEN);
+        assert(result == 0);
+        (void)result;
     }
 
-    assert(getentropy(buf + FULL_CHUNKS_NUM * GETENTROPY_MAX_LEN, REST_CHUNK_SIZE) == 0);
+    result = getentropy(buf + FULL_CHUNKS_NUM * GETENTROPY_MAX_LEN, REST_CHUNK_SIZE);
+    assert(result == 0);
+    (void)result;
 }

components/esp_hw_support/test_apps/dma/main/CMakeLists.txt

@@ -8,12 +8,20 @@ if(CONFIG_SOC_GDMA_SUPPORTED)
     list(APPEND srcs "test_gdma.c")
 endif()
 
+if(CONFIG_SOC_ETM_SUPPORTED AND CONFIG_SOC_GDMA_SUPPORT_ETM)
+    list(APPEND srcs "test_gdma_etm.c")
+endif()
+
 if(CONFIG_SOC_DW_GDMA_SUPPORTED)
     list(APPEND srcs "test_dw_gdma.c")
 endif()
 
+if(CONFIG_SOC_GDMA_SUPPORT_CRC)
+    list(APPEND srcs "test_gdma_crc.c")
+endif()
+
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES unity esp_mm
+                       PRIV_REQUIRES unity esp_mm esp_driver_gpio
                        WHOLE_ARCHIVE)

components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c

@@ -18,6 +18,7 @@
 #include "esp_async_memcpy.h"
 #include "soc/soc_caps.h"
 #include "hal/dma_types.h"
+#include "esp_dma_utils.h"
 
 #define IDF_LOG_PERFORMANCE(item, value_fmt, value, ...) \
     printf("[Performance][%s]: " value_fmt "\n", item, value, ##__VA_ARGS__)
@@ -26,10 +27,7 @@
 #define ALIGN_DOWN(size, align)  ((size) & ~((align) - 1))
 
 #if CONFIG_IDF_TARGET_ESP32P4
-#define TEST_MEMCPY_DST_BASE_ALIGN 64
 #define TEST_MEMCPY_BUFFER_SIZE_MUST_ALIGN_CACHE 1
-#else
-#define TEST_MEMCPY_DST_BASE_ALIGN 4
 #endif
 
 typedef struct {
@@ -56,23 +54,23 @@ static void async_memcpy_setup_testbench(memcpy_testbench_context_t *test_contex
     uint8_t *dst_buf = NULL;
     uint8_t *from_addr = NULL;
     uint8_t *to_addr = NULL;
-#if CONFIG_SPIRAM && SOC_AHB_GDMA_SUPPORT_PSRAM
+
+    esp_dma_mem_info_t mem_info = {
+        .dma_alignment_bytes = test_context->align,
+    };
     if (test_context->src_in_psram) {
-        src_buf = heap_caps_aligned_alloc(test_context->align, buffer_size, MALLOC_CAP_SPIRAM);
+        mem_info.extra_heap_caps = MALLOC_CAP_SPIRAM;
     } else {
-        src_buf = heap_caps_aligned_alloc(test_context->align, buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+        mem_info.extra_heap_caps = 0;
     }
+    TEST_ESP_OK(esp_dma_capable_calloc(1, buffer_size, &mem_info, (void **)&src_buf, NULL));
     if (test_context->dst_in_psram) {
-        dst_buf = heap_caps_aligned_alloc(test_context->align, buffer_size, MALLOC_CAP_SPIRAM);
+        mem_info.extra_heap_caps = MALLOC_CAP_SPIRAM;
     } else {
-        dst_buf = heap_caps_aligned_alloc(test_context->align, buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+        mem_info.extra_heap_caps = 0;
     }
-#else
-    src_buf = heap_caps_aligned_alloc(test_context->align, buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
-    dst_buf = heap_caps_aligned_alloc(test_context->align, buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
-#endif
-    TEST_ASSERT_NOT_NULL_MESSAGE(src_buf, "allocate source buffer failed");
-    TEST_ASSERT_NOT_NULL_MESSAGE(dst_buf, "allocate destination buffer failed");
+    TEST_ESP_OK(esp_dma_capable_calloc(1, buffer_size, &mem_info, (void **)&dst_buf, NULL));
+
     // adding extra offset
     from_addr = src_buf + test_context->offset;
     to_addr = dst_buf;
@@ -113,8 +111,13 @@ TEST_CASE("memory copy the same buffer with different content", "[async mcp]")
     async_memcpy_config_t config = ASYNC_MEMCPY_DEFAULT_CONFIG();
     async_memcpy_handle_t driver = NULL;
     TEST_ESP_OK(esp_async_memcpy_install(&config, &driver));
-    uint8_t *sbuf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
-    uint8_t *dbuf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    uint8_t *sbuf = NULL;
+    uint8_t *dbuf = NULL;
+    esp_dma_mem_info_t mem_info = {
+        .dma_alignment_bytes = 4,
+    };
+    TEST_ESP_OK(esp_dma_capable_calloc(1, 256, &mem_info, (void **)&sbuf, NULL));
+    TEST_ESP_OK(esp_dma_capable_calloc(1, 256, &mem_info, (void **)&dbuf, NULL));
     for (int j = 0; j < 20; j++) {
         TEST_ESP_OK(esp_async_memcpy(driver, dbuf, sbuf, 256, NULL, NULL));
         vTaskDelay(pdMS_TO_TICKS(10));
@@ -136,7 +139,7 @@ static void test_memory_copy_one_by_one(async_memcpy_handle_t driver)
 {
     uint32_t aligned_test_buffer_size[] = {256, 512, 1024, 2048, 4096};
     memcpy_testbench_context_t test_context = {
-        .align = TEST_MEMCPY_DST_BASE_ALIGN,
+        .align = 4,
     };
 
     for (int i = 0; i < sizeof(aligned_test_buffer_size) / sizeof(aligned_test_buffer_size[0]); i++) {
@@ -216,9 +219,13 @@ TEST_CASE("memory copy done callback", "[async mcp]")
     async_memcpy_handle_t driver = NULL;
     TEST_ESP_OK(esp_async_memcpy_install(&config, &driver));
 
-    uint8_t *src_buf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
-    // destination address should aligned to data cache line
-    uint8_t *dst_buf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    uint8_t *src_buf = NULL;
+    uint8_t *dst_buf = NULL;
+    esp_dma_mem_info_t mem_info = {
+        .dma_alignment_bytes = 4,
+    };
+    TEST_ESP_OK(esp_dma_capable_calloc(1, 256, &mem_info, (void **)&src_buf, NULL));
+    TEST_ESP_OK(esp_dma_capable_calloc(1, 256, &mem_info, (void **)&dst_buf, NULL));
 
     SemaphoreHandle_t sem = xSemaphoreCreateBinary();
     TEST_ESP_OK(esp_async_memcpy(driver, dst_buf, src_buf, 256, test_async_memcpy_cb_v1, sem));
@@ -235,38 +242,39 @@ TEST_CASE("memory copy by DMA on the fly", "[async mcp]")
     async_memcpy_handle_t driver = NULL;
     TEST_ESP_OK(esp_async_memcpy_install(&config, &driver));
 
-    uint32_t test_buffer_len[] = {512, 1024, 2048, 4096, 5011};
+    uint32_t aligned_test_buffer_size[] = {512, 1024, 2048, 4096, 4608};
     memcpy_testbench_context_t test_context[5] = {
         [0 ... 4] = {
-            .align = TEST_MEMCPY_DST_BASE_ALIGN,
+            .align = 4,
         }
     };
 
     // Aligned case
-    for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) {
+    for (int i = 0; i < sizeof(aligned_test_buffer_size) / sizeof(aligned_test_buffer_size[0]); i++) {
         test_context[i].seed = i;
-        test_context[i].buffer_size = test_buffer_len[i];
+        test_context[i].buffer_size = aligned_test_buffer_size[i];
         async_memcpy_setup_testbench(&test_context[i]);
     }
-    for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) {
+    for (int i = 0; i < sizeof(aligned_test_buffer_size) / sizeof(aligned_test_buffer_size[0]); i++) {
         TEST_ESP_OK(esp_async_memcpy(driver, test_context[i].to_addr, test_context[i].from_addr, test_context[i].copy_size, NULL, NULL));
     }
-    for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) {
+    for (int i = 0; i < sizeof(aligned_test_buffer_size) / sizeof(aligned_test_buffer_size[0]); i++) {
         async_memcpy_verify_and_clear_testbench(i, test_context[i].copy_size, test_context[i].src_buf, test_context[i].dst_buf, test_context[i].from_addr, test_context[i].to_addr);
     }
 
 #if !TEST_MEMCPY_BUFFER_SIZE_MUST_ALIGN_CACHE
+    uint32_t unaligned_test_buffer_size[] = {511, 1023, 2047, 4095, 5011};
     // Non-aligned case
-    for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) {
+    for (int i = 0; i < sizeof(unaligned_test_buffer_size) / sizeof(unaligned_test_buffer_size[0]); i++) {
         test_context[i].seed = i;
-        test_context[i].buffer_size = test_buffer_len[i];
+        test_context[i].buffer_size = unaligned_test_buffer_size[i];
         test_context[i].offset = 3;
         async_memcpy_setup_testbench(&test_context[i]);
     }
-    for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) {
+    for (int i = 0; i < sizeof(unaligned_test_buffer_size) / sizeof(unaligned_test_buffer_size[0]); i++) {
         TEST_ESP_OK(esp_async_memcpy(driver, test_context[i].to_addr, test_context[i].from_addr, test_context[i].copy_size, NULL, NULL));
     }
-    for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) {
+    for (int i = 0; i < sizeof(unaligned_test_buffer_size) / sizeof(unaligned_test_buffer_size[0]); i++) {
         async_memcpy_verify_and_clear_testbench(i, test_context[i].copy_size, test_context[i].src_buf, test_context[i].dst_buf, test_context[i].from_addr, test_context[i].to_addr);
     }
 #endif
@@ -328,7 +336,7 @@ static void memcpy_performance_test(uint32_t buffer_size)
     IDF_LOG_PERFORMANCE("CPU_COPY", "%.2f MB/s, dir: SRAM->SRAM, size: %zu Bytes", throughput, test_context.buffer_size);
     async_memcpy_verify_and_clear_testbench(test_context.seed, test_context.copy_size, test_context.src_buf, test_context.dst_buf, test_context.from_addr, test_context.to_addr);
 
-#if CONFIG_SPIRAM && SOC_AHB_GDMA_SUPPORT_PSRAM
+#if SOC_AHB_GDMA_SUPPORT_PSRAM
     // 2. PSRAM->PSRAM
     test_context.src_in_psram = true;
     test_context.dst_in_psram = true;

components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c

@@ -56,17 +56,20 @@ TEST_CASE("DW_GDMA M2M Test: Contiguous Mode", "[DW_GDMA]")
     TEST_ASSERT_NOT_NULL(done_sem);
 
     printf("prepare the source and destination buffers\r\n");
-    uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
-    uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    size_t sram_alignment = 0;
+    TEST_ESP_OK(esp_cache_get_alignment(0, &sram_alignment));
+    size_t alignment = MAX(sram_alignment, 8);
+    uint8_t *src_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *dst_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_buf);
     TEST_ASSERT_NOT_NULL(dst_buf);
     for (int i = 0; i < 256; i++) {
         src_buf[i] = i;
     }
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the source data because it's in the cache
-    TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
-#endif
+    if (sram_alignment) {
+        // do write-back for the source data because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+    }
 
     printf("allocate a channel for memory copy\r\n");
     dw_gdma_channel_static_config_t static_config = {
@@ -117,10 +120,10 @@ TEST_CASE("DW_GDMA M2M Test: Contiguous Mode", "[DW_GDMA]")
     TEST_ASSERT_EQUAL(pdFALSE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100)));
 
     printf("check the memory copy result\r\n");
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (sram_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
     for (int i = 0; i < 256; i++) {
         TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]);
     }
@@ -145,17 +148,20 @@ TEST_CASE("DW_GDMA M2M Test: Reload Mode", "[DW_GDMA]")
     TEST_ASSERT_NOT_NULL(done_sem);
 
     printf("prepare the source and destination buffers\r\n");
-    uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
-    uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    size_t sram_alignment = 0;
+    TEST_ESP_OK(esp_cache_get_alignment(0, &sram_alignment));
+    size_t alignment = MAX(sram_alignment, 8);
+    uint8_t *src_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *dst_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_buf);
     TEST_ASSERT_NOT_NULL(dst_buf);
     for (int i = 0; i < 256; i++) {
         src_buf[i] = i;
     }
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the source data because it's in the cache
-    TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
-#endif
+    if (sram_alignment) {
+        // do write-back for the source data because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+    }
 
     printf("allocate a channel for memory copy\r\n");
     dw_gdma_channel_static_config_t static_config = {
@@ -212,10 +218,10 @@ TEST_CASE("DW_GDMA M2M Test: Reload Mode", "[DW_GDMA]")
     TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100)));
 
     printf("check the memory copy result\r\n");
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (sram_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
     for (int i = 0; i < 256; i++) {
         TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]);
     }
@@ -264,17 +270,20 @@ TEST_CASE("DW_GDMA M2M Test: Shadow Mode", "[DW_GDMA]")
     TEST_ASSERT_NOT_NULL(done_sem);
 
     printf("prepare the source and destination buffers\r\n");
-    uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
-    uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    size_t sram_alignment = 0;
+    TEST_ESP_OK(esp_cache_get_alignment(0, &sram_alignment));
+    size_t alignment = MAX(sram_alignment, 8);
+    uint8_t *src_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *dst_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_buf);
     TEST_ASSERT_NOT_NULL(dst_buf);
     for (int i = 0; i < 256; i++) {
         src_buf[i] = i;
     }
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the source data because it's in the cache
-    TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
-#endif
+    if (sram_alignment) {
+        // do write-back for the source data because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+    }
 
     printf("allocate a channel for memory copy\r\n");
     dw_gdma_channel_static_config_t static_config = {
@@ -334,10 +343,10 @@ TEST_CASE("DW_GDMA M2M Test: Shadow Mode", "[DW_GDMA]")
     TEST_ASSERT_EQUAL_UINT8(1, user_data.count);
 
     printf("check the memory copy result\r\n");
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (sram_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
     for (int i = 0; i < 256; i++) {
         TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]);
     }
@@ -387,17 +396,20 @@ TEST_CASE("DW_GDMA M2M Test: Link-List Mode", "[DW_GDMA]")
     TEST_ASSERT_NOT_NULL(done_sem);
 
     printf("prepare the source and destination buffers\r\n");
-    uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
-    uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    size_t sram_alignment = 0;
+    TEST_ESP_OK(esp_cache_get_alignment(0, &sram_alignment));
+    size_t alignment = MAX(sram_alignment, 8);
+    uint8_t *src_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *dst_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_buf);
     TEST_ASSERT_NOT_NULL(dst_buf);
     for (int i = 0; i < 256; i++) {
         src_buf[i] = i;
     }
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the source data because it's in the cache
-    TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
-#endif
+    if (sram_alignment) {
+        // do write-back for the source data because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+    }
 
     printf("allocate a channel for memory copy\r\n");
     dw_gdma_channel_static_config_t static_config = {
@@ -472,10 +484,10 @@ TEST_CASE("DW_GDMA M2M Test: Link-List Mode", "[DW_GDMA]")
     TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(1000)));
 
     printf("check the memory copy result\r\n");
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (sram_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
     for (int i = 0; i < 256; i++) {
         TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]);
     }
@@ -504,10 +516,10 @@ TEST_CASE("DW_GDMA M2M Test: Link-List Mode", "[DW_GDMA]")
     TEST_ASSERT_EQUAL_UINT8(1, user_data.count);
 
     printf("check the memory copy result\r\n");
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (sram_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
     for (int i = 0; i < 256; i++) {
         TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]);
     }
@@ -536,10 +548,10 @@ TEST_CASE("DW_GDMA M2M Test: memory set with fixed address", "[DW_GDMA]")
         src_buf[i] = 0;
     }
     src_buf[0] = 66;
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the source data because it's in the cache
-    TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
-#endif
+    if (ext_mem_alignment) {
+        // do write-back for the source data because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+    }
 
     printf("allocate a channel for memory set\r\n");
     dw_gdma_channel_static_config_t static_config = {
@@ -581,10 +593,10 @@ TEST_CASE("DW_GDMA M2M Test: memory set with fixed address", "[DW_GDMA]")
     vTaskDelay(pdMS_TO_TICKS(100));
 
     printf("check the memory set result\r\n");
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (int_mem_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
     for (int i = 0; i < 256; i++) {
         TEST_ASSERT_EQUAL_UINT8(66, dst_buf[i]);
     }

components/esp_hw_support/test_apps/dma/main/test_gdma.c

@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <string.h>
 #include <inttypes.h>
+#include <sys/param.h>
 #include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
@@ -16,6 +17,7 @@
 #include "soc/soc_caps.h"
 #include "hal/gdma_ll.h"
 #include "hal/cache_ll.h"
+#include "hal/cache_hal.h"
 #include "esp_cache.h"
 
 TEST_CASE("GDMA channel allocation", "[GDMA]")
@@ -174,80 +176,71 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl
     TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
     TEST_ESP_OK(gdma_connect(rx_chan, m2m_trigger));
 
-    uint8_t *src_buf = heap_caps_aligned_alloc(64, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
-    uint8_t *dst_buf = heap_caps_aligned_alloc(64, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    // allocate the source and destination buffer from SRAM
+    // |--------------------------------------------------|
+    // | 128 bytes DMA descriptor | 128 bytes data buffer |
+    // |--------------------------------------------------|
+    size_t sram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+    size_t alignment = MAX(sram_alignment, 8);
+    uint8_t *src_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    uint8_t *dst_buf = heap_caps_aligned_calloc(alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     TEST_ASSERT_NOT_NULL(src_buf);
     TEST_ASSERT_NOT_NULL(dst_buf);
-    memset(src_buf, 0, 256);
-    memset(dst_buf, 0, 256);
-
     dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf;
     dma_descriptor_align8_t *rx_descs = (dma_descriptor_align8_t *) dst_buf;
-    uint8_t *src_data = src_buf + 64;
-    uint8_t *dst_data = dst_buf + 64;
+    uint8_t *src_data = src_buf + 128;
+    uint8_t *dst_data = dst_buf + 128;
 
     // prepare the source data
     for (int i = 0; i < 128; i++) {
         src_data[i] = i;
     }
+    if (sram_alignment) {
+        // do write-back for the source data because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)src_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+    }
 
-#if CONFIG_IDF_TARGET_ESP32P4
-    // CPU and DMA both can write to the DMA descriptor, so if there is a cache, multiple descriptors may reside in the same cache line
-    // causing data inconsistency. To avoid this, we want to access the descriptor memory without the cache.
-    dma_descriptor_align8_t *tx_descs_noncache = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(tx_descs));
-    dma_descriptor_align8_t *rx_descs_noncache = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(rx_descs));
-
-    tx_descs_noncache[0].buffer = src_data;
-    tx_descs_noncache[0].dw0.size = 64;
-    tx_descs_noncache[0].dw0.length = 64;
-    tx_descs_noncache[0].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    tx_descs_noncache[0].dw0.suc_eof = 0;
-    tx_descs_noncache[0].next = &tx_descs[1]; // Note, the DMA doesn't recognize a non-cacheable address, here must be the cached address
-
-    tx_descs_noncache[1].buffer = src_data + 64;
-    tx_descs_noncache[1].dw0.size = 64;
-    tx_descs_noncache[1].dw0.length = 64;
-    tx_descs_noncache[1].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    tx_descs_noncache[1].dw0.suc_eof = 1;
-    tx_descs_noncache[1].next = NULL;
-
-    rx_descs_noncache->buffer = dst_data;
-    rx_descs_noncache->dw0.size = 128;
-    rx_descs_noncache->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    rx_descs_noncache->dw0.suc_eof = 1;
-    rx_descs_noncache->next = NULL;
+#ifdef CACHE_LL_L2MEM_NON_CACHE_ADDR
+    dma_descriptor_align8_t *tx_descs_nc = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(tx_descs));
+    dma_descriptor_align8_t *rx_descs_nc = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(rx_descs));
 #else
-    tx_descs->buffer = src_data;
-    tx_descs->dw0.size = 128;
-    tx_descs->dw0.length = 128;
-    tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    tx_descs->dw0.suc_eof = 1;
-    tx_descs->next = NULL;
-
-    rx_descs->buffer = dst_data;
-    rx_descs->dw0.size = 128;
-    rx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    rx_descs->next = NULL;
+    dma_descriptor_align8_t *tx_descs_nc = tx_descs;
+    dma_descriptor_align8_t *rx_descs_nc = rx_descs;
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the source data because it's in the cache
-    TEST_ESP_OK(esp_cache_msync((void *)src_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
-#endif
+    tx_descs_nc[0].buffer = src_data;
+    tx_descs_nc[0].dw0.size = 64;
+    tx_descs_nc[0].dw0.length = 64;
+    tx_descs_nc[0].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
+    tx_descs_nc[0].dw0.suc_eof = 0;
+    tx_descs_nc[0].next = &tx_descs[1]; // Note, the DMA doesn't recognize a non-cacheable address, here must be the cached address
+
+    tx_descs_nc[1].buffer = src_data + 64;
+    tx_descs_nc[1].dw0.size = 64;
+    tx_descs_nc[1].dw0.length = 64;
+    tx_descs_nc[1].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
+    tx_descs_nc[1].dw0.suc_eof = 1;
+    tx_descs_nc[1].next = NULL;
+
+    rx_descs_nc->buffer = dst_data;
+    rx_descs_nc->dw0.size = 128;
+    rx_descs_nc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
+    rx_descs_nc->dw0.suc_eof = 1;
+    rx_descs_nc->next = NULL;
 
     TEST_ESP_OK(gdma_start(rx_chan, (intptr_t)rx_descs));
     TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs));
 
     xSemaphoreTake(done_sem, portMAX_DELAY);
 
-#if CONFIG_IDF_TARGET_ESP32P4
-    // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
-    TEST_ESP_OK(esp_cache_msync((void *)dst_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
-#endif
+    if (sram_alignment) {
+        // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
+        TEST_ESP_OK(esp_cache_msync((void *)dst_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
+    }
 
     // check the DMA descriptor write-back feature
-    TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, tx_descs[0].dw0.owner);
-    TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, rx_descs[0].dw0.owner);
+    TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, tx_descs_nc[0].dw0.owner);
+    TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, rx_descs_nc[0].dw0.owner);
 
     for (int i = 0; i < 128; i++) {
         TEST_ASSERT_EQUAL(i, dst_data[i]);
@@ -257,7 +250,7 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl
     vSemaphoreDelete(done_sem);
 }
 
-TEST_CASE("GDMA M2M Mode", "[GDMA]")
+TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]")
 {
     gdma_channel_handle_t tx_chan = NULL;
     gdma_channel_handle_t rx_chan = NULL;
@@ -300,117 +293,3 @@ TEST_CASE("GDMA M2M Mode", "[GDMA]")
     TEST_ESP_OK(gdma_del_channel(rx_chan));
 #endif // SOC_AXI_GDMA_SUPPORTED
 }
-
-#if SOC_GDMA_SUPPORT_CRC
-typedef struct {
-    uint32_t init_value;
-    uint32_t crc_bit_width;
-    uint32_t poly_hex;
-    bool reverse_data_mask;
-    uint32_t expected_result;
-} test_crc_case_t;
-static test_crc_case_t crc_test_cases[] = {
-    // CRC8, x^8+x^2+x+1
-    [0] = {
-        .crc_bit_width = 8,
-        .init_value = 0x00,
-        .poly_hex = 0x07,
-        .expected_result = 0xC6,
-    },
-    [1] = {
-        .crc_bit_width = 8,
-        .init_value = 0x00,
-        .poly_hex = 0x07,
-        .reverse_data_mask = true, // refin = true
-        .expected_result = 0xDE,
-    },
-    // CRC16, x^16+x^12+x^5+1
-    [2] = {
-        .crc_bit_width = 16,
-        .init_value = 0xFFFF,
-        .poly_hex = 0x1021,
-        .expected_result = 0x5289,
-    },
-    // CRC32, x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
-    [3] = {
-        .crc_bit_width = 32,
-        .init_value = 0xFFFFFFFF,
-        .poly_hex = 0x04C11DB7,
-        .expected_result = 0x63B3E283,
-    }
-};
-
-// CRC online: https://www.lddgo.net/en/encrypt/crc
-static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_num_crc_algorithm)
-{
-    uint32_t crc_result = 0;
-    const char *test_input_string = "Share::Connect::Innovate";
-    size_t input_data_size = strlen(test_input_string);
-    printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
-
-    gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
-    // get a free DMA trigger ID
-    uint32_t free_m2m_id_mask = 0;
-    gdma_get_free_m2m_trig_id_mask(tx_chan, &free_m2m_id_mask);
-    m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask);
-    TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
-
-    uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
-    TEST_ASSERT_NOT_NULL(src_buf);
-    dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf;
-    uint8_t *src_data = src_buf + 64;
-    memcpy(src_data, test_input_string, input_data_size);
-
-    tx_descs->buffer = src_data;
-    tx_descs->dw0.size = 256 - 64;
-    tx_descs->dw0.length = input_data_size;
-    tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    tx_descs->dw0.suc_eof = 1;
-    tx_descs->next = NULL;
-
-#if CONFIG_IDF_TARGET_ESP32P4
-    // do write-back for the buffer because it's in the cache
-    Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)src_buf, 256);
-#endif
-
-    for (int i = 0; i < test_num_crc_algorithm; i++) {
-        gdma_crc_calculator_config_t crc_config = {
-            .crc_bit_width = crc_test_cases[i].crc_bit_width,
-            .init_value = crc_test_cases[i].init_value,
-            .poly_hex = crc_test_cases[i].poly_hex,
-            .reverse_data_mask = crc_test_cases[i].reverse_data_mask,
-        };
-        TEST_ESP_OK(gdma_config_crc_calculator(tx_chan, &crc_config));
-        TEST_ESP_OK(gdma_reset(tx_chan));
-        TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs));
-        // simply wait for the transfer done
-        vTaskDelay(pdMS_TO_TICKS(100));
-        TEST_ESP_OK(gdma_crc_get_result(tx_chan, &crc_result));
-        printf("CRC Result: 0x%"PRIx32"\r\n", crc_result);
-        TEST_ASSERT_EQUAL(crc_test_cases[i].expected_result, crc_result);
-    }
-
-    free(src_buf);
-}
-
-TEST_CASE("GDMA CRC Calculation", "[GDMA]")
-{
-    gdma_channel_handle_t tx_chan = NULL;
-    gdma_channel_alloc_config_t tx_chan_alloc_config = {
-        .direction = GDMA_CHANNEL_DIRECTION_TX,
-    };
-#if SOC_AHB_GDMA_SUPPORTED
-    printf("Test CRC calculation for AHB GDMA\r\n");
-    TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan));
-    test_gdma_crc_calculation(tx_chan, 4);
-    TEST_ESP_OK(gdma_del_channel(tx_chan));
-#endif // SOC_AHB_GDMA_SUPPORTED
-
-#if SOC_AXI_GDMA_SUPPORTED
-    printf("Test CRC calculation for AXI GDMA\r\n");
-    TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan));
-    test_gdma_crc_calculation(tx_chan, 3);
-    TEST_ESP_OK(gdma_del_channel(tx_chan));
-#endif // SOC_AXI_GDMA_SUPPORTED
-}
-#endif // SOC_GDMA_SUPPORT_CRC

components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c

@@ -0,0 +1,134 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <string.h>
+#include <inttypes.h>
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "unity.h"
+#include "esp_heap_caps.h"
+#include "esp_memory_utils.h"
+#include "esp_private/gdma.h"
+#include "hal/dma_types.h"
+#include "soc/soc_caps.h"
+#include "hal/cache_hal.h"
+#include "hal/cache_ll.h"
+#include "esp_cache.h"
+
+typedef struct {
+    uint32_t init_value;
+    uint32_t crc_bit_width;
+    uint32_t poly_hex;
+    bool reverse_data_mask;
+    uint32_t expected_result;
+} test_crc_case_t;
+static test_crc_case_t crc_test_cases[] = {
+    // CRC8, x^8+x^2+x+1
+    [0] = {
+        .crc_bit_width = 8,
+        .init_value = 0x00,
+        .poly_hex = 0x07,
+        .expected_result = 0xC6,
+    },
+    [1] = {
+        .crc_bit_width = 8,
+        .init_value = 0x00,
+        .poly_hex = 0x07,
+        .reverse_data_mask = true, // refin = true
+        .expected_result = 0xDE,
+    },
+    // CRC16, x^16+x^12+x^5+1
+    [2] = {
+        .crc_bit_width = 16,
+        .init_value = 0xFFFF,
+        .poly_hex = 0x1021,
+        .expected_result = 0x5289,
+    },
+    // CRC32, x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
+    [3] = {
+        .crc_bit_width = 32,
+        .init_value = 0xFFFFFFFF,
+        .poly_hex = 0x04C11DB7,
+        .expected_result = 0x63B3E283,
+    }
+};
+
+// CRC online: https://www.lddgo.net/en/encrypt/crc
+static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_num_crc_algorithm)
+{
+    uint32_t crc_result = 0;
+    const char *test_input_string = "Share::Connect::Innovate";
+    size_t input_data_size = strlen(test_input_string);
+    // this test case also test the GDMA can fetch data from MSPI Flash
+    TEST_ASSERT_TRUE(esp_ptr_in_drom(test_input_string));
+    printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
+
+    gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
+    // get a free DMA trigger ID
+    uint32_t free_m2m_id_mask = 0;
+    gdma_get_free_m2m_trig_id_mask(tx_chan, &free_m2m_id_mask);
+    m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask);
+    TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
+
+    size_t sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+    size_t alignment = MAX(sram_cache_line_size, 8);
+    dma_descriptor_align8_t *tx_descs = heap_caps_aligned_calloc(alignment, 1, sizeof(dma_descriptor_align8_t),
+                                                                 MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+    TEST_ASSERT_NOT_NULL(tx_descs);
+
+    tx_descs->buffer = (void *)test_input_string;
+    tx_descs->dw0.size = input_data_size + 1; // +1 for '\0'
+    tx_descs->dw0.length = input_data_size;
+    tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
+    tx_descs->dw0.suc_eof = 1;
+    tx_descs->next = NULL;
+
+    if (sram_cache_line_size) {
+        // do write-back for the buffer because it's in the cache
+        TEST_ESP_OK(esp_cache_msync((void *)tx_descs, sizeof(dma_descriptor_align8_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED));
+    }
+
+    for (int i = 0; i < test_num_crc_algorithm; i++) {
+        gdma_crc_calculator_config_t crc_config = {
+            .crc_bit_width = crc_test_cases[i].crc_bit_width,
+            .init_value = crc_test_cases[i].init_value,
+            .poly_hex = crc_test_cases[i].poly_hex,
+            .reverse_data_mask = crc_test_cases[i].reverse_data_mask,
+        };
+        TEST_ESP_OK(gdma_config_crc_calculator(tx_chan, &crc_config));
+        TEST_ESP_OK(gdma_reset(tx_chan));
+        TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs));
+        // simply wait for the transfer done
+        vTaskDelay(pdMS_TO_TICKS(100));
+        TEST_ESP_OK(gdma_crc_get_result(tx_chan, &crc_result));
+        printf("CRC Result: 0x%"PRIx32"\r\n", crc_result);
+        TEST_ASSERT_EQUAL(crc_test_cases[i].expected_result, crc_result);
+    }
+
+    free(tx_descs);
+}
+
+TEST_CASE("GDMA CRC Calculation", "[GDMA][CRC]")
+{
+    gdma_channel_handle_t tx_chan = NULL;
+    gdma_channel_alloc_config_t tx_chan_alloc_config = {
+        .direction = GDMA_CHANNEL_DIRECTION_TX,
+    };
+#if SOC_AHB_GDMA_SUPPORTED
+    printf("Test CRC calculation for AHB GDMA\r\n");
+    TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan));
+    test_gdma_crc_calculation(tx_chan, 4);
+    TEST_ESP_OK(gdma_del_channel(tx_chan));
+#endif // SOC_AHB_GDMA_SUPPORTED
+
+#if SOC_AXI_GDMA_SUPPORTED
+    printf("Test CRC calculation for AXI GDMA\r\n");
+    TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan));
+    test_gdma_crc_calculation(tx_chan, 3);
+    TEST_ESP_OK(gdma_del_channel(tx_chan));
+#endif // SOC_AXI_GDMA_SUPPORTED
+}

components/esp_hw_support/test_apps/dma/main/test_gdma_etm.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,7 @@
 #include "driver/gpio.h"
 #include "esp_async_memcpy.h"
 
-TEST_CASE("async_memcpy_eof_event", "[etm]")
+TEST_CASE("async_memcpy_eof_event", "[GDMA][ETM]")
 {
     const uint32_t output_gpio = 1;
     // async_memcpy done ---> ETM channel A ---> GPIO toggle

components/esp_hw_support/test_apps/etm/main/CMakeLists.txt

@@ -13,10 +13,6 @@ if(CONFIG_SOC_SYSTIMER_SUPPORT_ETM)
     list(APPEND srcs "test_systimer_etm.c")
 endif()
 
-if(CONFIG_SOC_GDMA_SUPPORT_ETM)
-    list(APPEND srcs "test_gdma_etm.c")
-endif()
-
 if(CONFIG_SOC_MCPWM_SUPPORT_ETM)
     list(APPEND srcs "test_mcpwm_etm.c")
 endif()

components/esp_hw_support/test_apps/etm/main/test_gpio_etm.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -81,7 +81,7 @@ TEST_CASE("gpio_etm_self_trigger", "[etm]")
     // delete gpio etm task without remove all bounded GPIOs should fail
     TEST_ESP_ERR(ESP_ERR_INVALID_STATE, esp_etm_del_task(gpio_task));
     // remove unrelated GPIO from the task should fail
-    TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gpio_etm_task_rm_gpio(gpio_task, 10));
+    TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gpio_etm_task_rm_gpio(gpio_task, 10));
 
     // delete etm primitives
     TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task, output_gpio));
@@ -90,3 +90,118 @@ TEST_CASE("gpio_etm_self_trigger", "[etm]")
     TEST_ESP_OK(esp_etm_del_event(gpio_event));
     TEST_ESP_OK(esp_etm_del_channel(etm_channel_a));
 }
+
+TEST_CASE("gpio_etm_self_trigger_multi_action", "[etm]")
+{
+    // GPIO 0 pos edge event ---> GPIO 1 set level task
+    // GPIO 22 pos edge event ---> GPIO 1 clear level task
+
+    const uint32_t input_gpio1 = 0;
+    const uint32_t input_gpio2 = 22;
+    const uint32_t output_gpio = 1;
+    printf("allocate etm channels\r\n");
+    esp_etm_channel_config_t etm_config = {};
+    esp_etm_channel_handle_t etm_channel_a = NULL;
+    esp_etm_channel_handle_t etm_channel_b = NULL;
+    TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_a));
+    TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_b));
+
+    printf("allocate GPIO etm event and task\r\n");
+    esp_etm_task_handle_t gpio_task_a = NULL;
+    esp_etm_event_handle_t gpio_event_a = NULL;
+    esp_etm_task_handle_t gpio_task_b = NULL;
+    esp_etm_event_handle_t gpio_event_b = NULL;
+    gpio_etm_event_config_t gpio_event_config = {};
+    gpio_event_config.edges[0] = GPIO_ETM_EVENT_EDGE_POS;
+    TEST_ESP_OK(gpio_new_etm_event(&gpio_event_config, &gpio_event_a));
+    esp_etm_event_handle_t gpio_event_c = NULL; // an extra event only used for testing binding
+    gpio_event_config.edges[1] = GPIO_ETM_EVENT_EDGE_ANY;
+    TEST_ESP_OK(gpio_new_etm_event(&gpio_event_config, &gpio_event_b, &gpio_event_c));
+    gpio_etm_task_config_t gpio_task_config = {};
+    gpio_task_config.actions[0] = GPIO_ETM_TASK_ACTION_CLR;
+    gpio_task_config.actions[1] = GPIO_ETM_TASK_ACTION_SET;
+    TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config, &gpio_task_b, &gpio_task_a));
+
+    // bind GPIO to the event and task
+    TEST_ESP_OK(gpio_etm_event_bind_gpio(gpio_event_a, input_gpio1));
+    TEST_ESP_OK(gpio_etm_event_bind_gpio(gpio_event_b, input_gpio2));
+    TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task_a, output_gpio));
+    TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task_b, output_gpio));
+
+    // try an infeasible bind of second event to a GPIO
+    TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gpio_etm_event_bind_gpio(gpio_event_c, input_gpio1));
+    // try a feasible bind of second event to a GPIO
+    TEST_ESP_OK(gpio_etm_event_bind_gpio(gpio_event_c, input_gpio2));
+    // delete the event to unbind it from the GPIO
+    TEST_ESP_OK(esp_etm_del_event(gpio_event_c));
+
+    printf("initialize gpio\r\n");
+    gpio_config_t task_gpio_config = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_INPUT_OUTPUT, // we want to read the GPIO value, so it should be input and output
+        .pin_bit_mask = 1ULL << output_gpio,
+    };
+    TEST_ESP_OK(gpio_config(&task_gpio_config));
+    // set the initial level
+    TEST_ESP_OK(gpio_set_level(output_gpio, 0));
+
+    gpio_config_t event_gpio_config = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_INPUT_OUTPUT, // we want to simulate the edge signal by software, so it should be input and output
+        .pull_up_en = GPIO_PULLUP_ENABLE,
+        .pull_down_en = GPIO_PULLDOWN_DISABLE,
+        .pin_bit_mask = (1ULL << input_gpio1) | (1ULL << input_gpio2),
+    };
+    TEST_ESP_OK(gpio_config(&event_gpio_config));
+    // set the initial level
+    TEST_ESP_OK(gpio_set_level(input_gpio1, 0));
+    TEST_ESP_OK(gpio_set_level(input_gpio2, 0));
+
+    printf("connect event and task to the channel\r\n");
+    TEST_ESP_OK(esp_etm_channel_connect(etm_channel_a, gpio_event_a, gpio_task_a));
+    TEST_ESP_OK(esp_etm_channel_connect(etm_channel_b, gpio_event_b, gpio_task_b));
+
+    TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a));
+    TEST_ESP_OK(esp_etm_channel_enable(etm_channel_b));
+
+    // input_gpio1 pos edge ---> output_gpio level being set
+    TEST_ESP_OK(gpio_set_level(input_gpio1, 1));
+    vTaskDelay(pdMS_TO_TICKS(100));
+    TEST_ASSERT_EQUAL(1, gpio_get_level(output_gpio));
+
+    // input_gpio1 neg edge does not affect output_gpio level
+    TEST_ESP_OK(gpio_set_level(input_gpio1, 0));
+    vTaskDelay(pdMS_TO_TICKS(100));
+    TEST_ASSERT_EQUAL(1, gpio_get_level(output_gpio));
+
+    // input_gpio2 pos edge ---> output_gpio level being cleared
+    TEST_ESP_OK(gpio_set_level(input_gpio2, 1));
+    vTaskDelay(pdMS_TO_TICKS(100));
+    TEST_ASSERT_EQUAL(0, gpio_get_level(output_gpio));
+
+    // input_gpio2 neg edge does not affect output_gpio level
+    TEST_ESP_OK(gpio_set_level(input_gpio2, 0));
+    vTaskDelay(pdMS_TO_TICKS(100));
+    TEST_ASSERT_EQUAL(0, gpio_get_level(output_gpio));
+
+    // Create a new gpio etm task separately, and add it to the output_gpio should fail (the task does not belong to the same GPIO ETM task channel as gpio_task_a and gpio_task_b)
+    esp_etm_task_handle_t gpio_task_c = NULL;
+    gpio_etm_task_config_t gpio_task_config_2 = {
+        .action = GPIO_ETM_TASK_ACTION_TOG,
+    };
+    TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config_2, &gpio_task_c));
+    TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gpio_etm_task_add_gpio(gpio_task_c, output_gpio));
+
+    // delete etm primitives
+    TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task_a, output_gpio));
+    TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task_b, output_gpio));
+    TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a));
+    TEST_ESP_OK(esp_etm_channel_disable(etm_channel_b));
+    TEST_ESP_OK(esp_etm_del_task(gpio_task_a));
+    TEST_ESP_OK(esp_etm_del_task(gpio_task_b));
+    TEST_ESP_OK(esp_etm_del_task(gpio_task_c));
+    TEST_ESP_OK(esp_etm_del_event(gpio_event_a));
+    TEST_ESP_OK(esp_etm_del_event(gpio_event_b));
+    TEST_ESP_OK(esp_etm_del_channel(etm_channel_a));
+    TEST_ESP_OK(esp_etm_del_channel(etm_channel_b));
+}

components/esp_lcd/Kconfig

@@ -36,5 +36,20 @@ menu "LCD and Touch Panel"
                     Only need to enable it when in your application, the DMA can't deliver data
                     as fast as the LCD consumes it.
         endif # SOC_LCD_RGB_SUPPORTED
+
+        if SOC_MIPI_DSI_SUPPORTED
+            config LCD_DSI_ISR_IRAM_SAFE
+                bool "DSI LCD ISR IRAM-Safe"
+                default n
+                select DW_GDMA_ISR_IRAM_SAFE
+                select DW_GDMA_CTRL_FUNC_IN_IRAM
+                select DW_GDMA_SETTER_FUNC_IN_IRAM
+                select DW_GDMA_GETTER_FUNC_IN_IRAM
+                help
+                    Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be
+                    executable when the cache is disabled (e.g. SPI Flash write).
+                    If you want the LCD driver to keep flushing the screen even when cache ops disabled,
+                    you can enable this option. Note, this will also increase the IRAM usage.
+        endif # SOC_MIPI_DSI_SUPPORTED
     endmenu
 endmenu

components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c

@@ -21,6 +21,8 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
 {
     esp_err_t ret = ESP_OK;
     ESP_RETURN_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    ESP_RETURN_ON_FALSE(bus_config->num_data_lanes <= MIPI_DSI_LL_MAX_DATA_LANES,
+                        ESP_ERR_INVALID_ARG, TAG, "invalid number of data lanes %d", bus_config->num_data_lanes);
     ESP_RETURN_ON_FALSE(bus_config->lane_bit_rate_mbps >= MIPI_DSI_LL_MIN_PHY_MBPS &&
                         bus_config->lane_bit_rate_mbps <= MIPI_DSI_LL_MAX_PHY_MBPS, ESP_ERR_INVALID_ARG, TAG,
                         "invalid lane bit rate %"PRIu32, bus_config->lane_bit_rate_mbps);
@@ -55,11 +57,25 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
         mipi_dsi_ll_enable_phy_reference_clock(bus_id, true);
     }
 
+#if CONFIG_PM_ENABLE
+    // When MIPI DSI is working, we don't expect the clock source would be turned off
+    esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP;
+    ret  = esp_pm_lock_create(pm_lock_type, 0, "dsi_phy", &dsi_bus->pm_lock);
+    ESP_GOTO_ON_ERROR(ret, err, TAG, "create PM lock failed");
+    // before we configure the PLL, we want the clock source to be stable
+    esp_pm_lock_acquire(dsi_bus->pm_lock);
+#endif
+
+    // if the number of data lanes is not assigned, fallback to the maximum number of data lanes
+    int num_data_lanes = bus_config->num_data_lanes;
+    if (num_data_lanes == 0) {
+        num_data_lanes = MIPI_DSI_LL_MAX_DATA_LANES;
+    }
     // initialize HAL context
     mipi_dsi_hal_config_t hal_config = {
         .bus_id = bus_id,
         .lane_bit_rate_mbps = bus_config->lane_bit_rate_mbps,
-        .num_data_lanes = bus_config->num_data_lanes,
+        .num_data_lanes = num_data_lanes,
     };
     mipi_dsi_hal_init(&dsi_bus->hal, &hal_config);
     mipi_dsi_hal_context_t *hal = &dsi_bus->hal;
@@ -75,7 +91,7 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
     while (!mipi_dsi_phy_ll_is_pll_locked(hal->host)) {
         vTaskDelay(pdMS_TO_TICKS(1));
     }
-    while (!mipi_dsi_phy_ll_are_lanes_stopped(hal->host)) {
+    while (!mipi_dsi_phy_ll_are_lanes_stopped(hal->host, num_data_lanes)) {
         vTaskDelay(pdMS_TO_TICKS(1));
     }
 
@@ -125,6 +141,10 @@ esp_err_t esp_lcd_del_dsi_bus(esp_lcd_dsi_bus_handle_t bus)
     DSI_RCC_ATOMIC() {
         mipi_dsi_ll_enable_bus_clock(bus_id, false);
     }
+    if (bus->pm_lock) {
+        esp_pm_lock_release(bus->pm_lock);
+        esp_pm_lock_delete(bus->pm_lock);
+    }
     free(bus);
     return ESP_OK;
 }

components/esp_lcd/dsi/esp_lcd_panel_dpi.c

@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <sys/param.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/semphr.h"
@@ -14,6 +15,7 @@
 #include "esp_cache.h"
 #include "mipi_dsi_priv.h"
 #include "esp_async_fbcpy.h"
+#include "esp_memory_utils.h"
 #include "esp_private/dw_gdma.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
@@ -42,6 +44,7 @@ struct esp_lcd_dpi_panel_t {
     dw_gdma_link_list_handle_t link_lists[DPI_PANEL_MAX_FB_NUM]; // DMA link list
     esp_async_fbcpy_handle_t fbcpy_handle; // Use DMA2D to do frame buffer copy
     SemaphoreHandle_t draw_sem;            // A semaphore used to synchronize the draw operations when DMA2D is used
+    esp_pm_lock_handle_t pm_lock;          // Power management lock
     esp_lcd_dpi_panel_color_trans_done_cb_t on_color_trans_done; // Callback invoked when color data transfer has finished
     esp_lcd_dpi_panel_refresh_done_cb_t on_refresh_done; // Callback invoked when one refresh operation finished (kinda like a vsync end)
     void *user_ctx; // User context for the callback
@@ -232,6 +235,14 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_
         mipi_dsi_ll_enable_dpi_clock(bus_id, true);
     }
 
+#if CONFIG_PM_ENABLE
+    // When MIPI DSI is working, we don't expect the clock source would be turned off
+    esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP;
+    ret  = esp_pm_lock_create(pm_lock_type, 0, "dsi_dpi", &dpi_panel->pm_lock);
+    ESP_GOTO_ON_ERROR(ret, err, TAG, "create PM lock failed");
+    esp_pm_lock_acquire(dpi_panel->pm_lock);
+#endif
+
     // create DMA resources
     ESP_GOTO_ON_ERROR(dpi_panel_create_dma_link(dpi_panel), err, TAG, "initialize DMA link failed");
 
@@ -318,6 +329,10 @@ static esp_err_t dpi_panel_del(esp_lcd_panel_t *panel)
     if (dpi_panel->draw_sem) {
         vSemaphoreDelete(dpi_panel->draw_sem);
     }
+    if (dpi_panel->pm_lock) {
+        esp_pm_lock_release(dpi_panel->pm_lock);
+        esp_pm_lock_delete(dpi_panel->pm_lock);
+    }
     free(dpi_panel);
     return ESP_OK;
 }
@@ -403,6 +418,14 @@ static esp_err_t dpi_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
     size_t frame_buffer_size = dpi_panel->frame_buffer_size;
     size_t bytes_per_pixel = dpi_panel->bytes_per_pixel;
 
+    // clip to boundaries
+    int h_res = dpi_panel->h_pixels;
+    int v_res = dpi_panel->v_pixels;
+    x_start = MAX(x_start, 0);
+    x_end = MIN(x_end, h_res);
+    y_start = MAX(y_start, 0);
+    y_end = MIN(y_end, v_res);
+
     bool do_copy = false;
     uint8_t draw_buf_fb_index = 0;
     // check if the user draw buffer resides in any frame buffer's memory range
@@ -515,6 +538,17 @@ esp_err_t esp_lcd_dpi_panel_register_event_callbacks(esp_lcd_panel_handle_t pane
 {
     ESP_RETURN_ON_FALSE(panel && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     esp_lcd_dpi_panel_t *dpi_panel = __containerof(panel, esp_lcd_dpi_panel_t, base);
+#if CONFIG_LCD_DSI_ISR_IRAM_SAFE
+    if (cbs->on_color_trans_done) {
+        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_color_trans_done), ESP_ERR_INVALID_ARG, TAG, "on_color_trans_done callback not in IRAM");
+    }
+    if (cbs->on_refresh_done) {
+        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_refresh_done), ESP_ERR_INVALID_ARG, TAG, "on_refresh_done callback not in IRAM");
+    }
+    if (user_ctx) {
+        ESP_RETURN_ON_FALSE(esp_ptr_internal(user_ctx), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
+    }
+#endif // CONFIG_LCD_RGB_ISR_IRAM_SAFE
     dpi_panel->on_color_trans_done = cbs->on_color_trans_done;
     dpi_panel->on_refresh_done = cbs->on_refresh_done;
     dpi_panel->user_ctx = user_ctx;

components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h

@@ -21,7 +21,7 @@ extern "C" {
  */
 typedef struct {
     int bus_id;                              /*!< Select which DSI controller, index from 0 */
-    uint8_t num_data_lanes;                  /*!< Number of data lanes */
+    uint8_t num_data_lanes;                  /*!< Number of data lanes, if set to 0, the driver will fallback to use maximum number of lanes */
     mipi_dsi_phy_clock_source_t phy_clk_src; /*!< MIPI DSI PHY clock source */
     uint32_t lane_bit_rate_mbps;             /*!< Lane bit rate in Mbps */
 } esp_lcd_dsi_bus_config_t;

components/esp_lcd/dsi/mipi_dsi_priv.h

@@ -9,6 +9,7 @@
 #include "hal/mipi_dsi_ll.h"
 #include "esp_heap_caps.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_pm.h"
 
 #if SOC_PERIPH_CLK_CTRL_SHARED
 #define DSI_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
@@ -22,7 +23,11 @@
 #define DSI_RCC_ATOMIC()
 #endif
 
-#define DSI_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
+#if CONFIG_LCD_DSI_ISR_IRAM_SAFE
+#define DSI_MEM_ALLOC_CAPS      (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
+#else
+#define DSI_MEM_ALLOC_CAPS      MALLOC_CAP_DEFAULT
+#endif
 
 #define DPI_PANEL_MAX_FB_NUM 3 // maximum number of supported frame buffers for DPI panel
 
@@ -35,6 +40,7 @@ extern "C" {
 typedef struct esp_lcd_dsi_bus_t {
     int bus_id;
     mipi_dsi_hal_context_t hal;
+    esp_pm_lock_handle_t pm_lock;
 } esp_lcd_dsi_bus_t;
 
 #ifdef __cplusplus

components/esp_lcd/rgb/esp_lcd_panel_rgb.c

@@ -706,7 +706,6 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
 {
     esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base);
     ESP_RETURN_ON_FALSE(rgb_panel->num_fbs > 0, ESP_ERR_NOT_SUPPORTED, TAG, "no frame buffer installed");
-    assert((x_start < x_end) && (y_start < y_end) && "start position must be smaller than end position");
 
     // check if we need to copy the draw buffer (pointed by the color_data) to the driver's frame buffer
     bool do_copy = false;
@@ -726,18 +725,19 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
     y_start += rgb_panel->y_gap;
     x_end += rgb_panel->x_gap;
     y_end += rgb_panel->y_gap;
-    // round the boundary
+
+    // clip to boundaries
     int h_res = rgb_panel->timings.h_res;
     int v_res = rgb_panel->timings.v_res;
     if (rgb_panel->rotate_mask & ROTATE_MASK_SWAP_XY) {
-        x_start = MIN(x_start, v_res);
+        x_start = MAX(x_start, 0);
         x_end = MIN(x_end, v_res);
-        y_start = MIN(y_start, h_res);
+        y_start = MAX(y_start, 0);
         y_end = MIN(y_end, h_res);
     } else {
-        x_start = MIN(x_start, h_res);
+        x_start = MAX(x_start, 0);
         x_end = MIN(x_end, h_res);
-        y_start = MIN(y_start, v_res);
+        y_start = MAX(y_start, 0);
         y_end = MIN(y_end, v_res);
     }
 

components/esp_lcd/src/esp_lcd_panel_nt35510.c

@@ -188,7 +188,6 @@ static esp_err_t panel_nt35510_draw_bitmap(esp_lcd_panel_t *panel, int x_start,
                                            const void *color_data)
 {
     nt35510_panel_t *nt35510 = __containerof(panel, nt35510_panel_t, base);
-    assert((x_start < x_end) && (y_start < y_end) && "start position must be smaller than end position");
     esp_lcd_panel_io_handle_t io = nt35510->io;
 
     x_start += nt35510->x_gap;

components/esp_lcd/src/esp_lcd_panel_ops.c

@@ -32,6 +32,7 @@ esp_err_t esp_lcd_panel_del(esp_lcd_panel_handle_t panel)
 esp_err_t esp_lcd_panel_draw_bitmap(esp_lcd_panel_handle_t panel, int x_start, int y_start, int x_end, int y_end, const void *color_data)
 {
     ESP_RETURN_ON_FALSE(panel, ESP_ERR_INVALID_ARG, TAG, "invalid panel handle");
+    ESP_RETURN_ON_FALSE((x_start < x_end) && (y_start < y_end), ESP_ERR_INVALID_ARG, TAG, "start position must be smaller than end position");
     ESP_RETURN_ON_FALSE(panel->draw_bitmap, ESP_ERR_NOT_SUPPORTED, TAG, "draw_bitmap is not supported by this panel");
     return panel->draw_bitmap(panel, x_start, y_start, x_end, y_end, color_data);
 }

components/esp_lcd/src/esp_lcd_panel_ssd1306.c

@@ -168,7 +168,6 @@ static esp_err_t panel_ssd1306_init(esp_lcd_panel_t *panel)
 static esp_err_t panel_ssd1306_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int y_start, int x_end, int y_end, const void *color_data)
 {
     ssd1306_panel_t *ssd1306 = __containerof(panel, ssd1306_panel_t, base);
-    assert((x_start < x_end) && (y_start < y_end) && "start position must be smaller than end position");
     esp_lcd_panel_io_handle_t io = ssd1306->io;
 
     // adding extra gap

components/esp_lcd/src/esp_lcd_panel_st7789.c

@@ -198,7 +198,6 @@ static esp_err_t panel_st7789_draw_bitmap(esp_lcd_panel_t *panel, int x_start, i
                                           const void *color_data)
 {
     st7789_panel_t *st7789 = __containerof(panel, st7789_panel_t, base);
-    assert((x_start < x_end) && (y_start < y_end) && "start position must be smaller than end position");
     esp_lcd_panel_io_handle_t io = st7789->io;
 
     x_start += st7789->x_gap;

components/esp_lcd/test_apps/.build-test-rules.yml

@@ -38,7 +38,7 @@ components/esp_lcd/test_apps/mipi_dsi_lcd:
   disable_test:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
-      reason: lack of runners
+      reason: lack of runners, DSI can't work without an LCD connected
 
 components/esp_lcd/test_apps/rgb_lcd:
   depends_components:

components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt

@@ -6,3 +6,16 @@ set(COMPONENTS main)
 
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(mipi_dsi_lcd_panel_test)
+
+if(CONFIG_COMPILER_DUMP_RTL_FILES)
+    add_custom_target(check_test_app_sections ALL
+                      COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
+                      --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_lcd/,${CMAKE_BINARY_DIR}/esp-idf/hal/
+                      --elf-file ${CMAKE_BINARY_DIR}/mipi_dsi_lcd_panel_test.elf
+                      find-refs
+                      --from-sections=.iram0.text
+                      --to-sections=.flash.text,.flash.rodata
+                      --exit-code
+                      DEPENDS ${elf}
+                      )
+endif()

components/esp_lcd/test_apps/mipi_dsi_lcd/main/CMakeLists.txt

@@ -2,6 +2,10 @@ set(srcs "test_app_main.c"
          "test_mipi_dsi_board.c"
          "test_mipi_dsi_panel.c")
 
+if(CONFIG_LCD_DSI_ISR_IRAM_SAFE)
+    list(APPEND srcs "test_mipi_dsi_iram.c")
+endif()
+
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}

components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c

@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "esp_lcd_mipi_dsi.h"
+#include "esp_lcd_panel_ops.h"
+#include "esp_lcd_panel_io.h"
+#include "esp_random.h"
+#include "esp_attr.h"
+#include "test_mipi_dsi_board.h"
+#include "esp_lcd_ili9881c.h"
+
+IRAM_ATTR static bool test_rgb_panel_count_in_callback(esp_lcd_panel_handle_t panel, esp_lcd_dpi_panel_event_data_t *edata, void *user_ctx)
+{
+    uint32_t *count = (uint32_t *)user_ctx;
+    *count = *count + 1;
+    return false;
+}
+
+static void IRAM_ATTR test_delay_post_cache_disable(void *args)
+{
+    esp_rom_delay_us(200000);
+}
+
+#define TEST_IMG_SIZE (100 * 100 * sizeof(uint16_t))
+
+TEST_CASE("MIPI DSI draw bitmap (ILI9881C) IRAM Safe", "[mipi_dsi]")
+{
+    esp_lcd_dsi_bus_handle_t mipi_dsi_bus;
+    esp_lcd_panel_io_handle_t mipi_dbi_io;
+    esp_lcd_panel_handle_t mipi_dpi_panel;
+    esp_lcd_panel_handle_t ili9881c_ctrl_panel;
+
+    test_bsp_enable_dsi_phy_power();
+
+    uint8_t *img = malloc(TEST_IMG_SIZE);
+    TEST_ASSERT_NOT_NULL(img);
+
+    esp_lcd_dsi_bus_config_t bus_config = {
+        .bus_id = 0,
+        .num_data_lanes = 2,
+        .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT,
+        .lane_bit_rate_mbps = 1000, // 1000 Mbps
+    };
+    TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus));
+
+    esp_lcd_dbi_io_config_t dbi_config = {
+        .virtual_channel = 0,
+        .lcd_cmd_bits = 8,
+        .lcd_param_bits = 8,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io));
+
+    esp_lcd_panel_dev_config_t lcd_dev_config = {
+        .bits_per_pixel = 16,
+        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
+        .reset_gpio_num = -1,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_ili9881c(mipi_dbi_io, &lcd_dev_config, &ili9881c_ctrl_panel));
+    TEST_ESP_OK(esp_lcd_panel_reset(ili9881c_ctrl_panel));
+    TEST_ESP_OK(esp_lcd_panel_init(ili9881c_ctrl_panel));
+    // turn on display
+    TEST_ESP_OK(esp_lcd_panel_disp_on_off(ili9881c_ctrl_panel, true));
+
+    esp_lcd_dpi_panel_config_t dpi_config = {
+        .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
+        .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ,
+        .virtual_channel = 0,
+        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB565,
+        .video_timing = {
+            .h_size = MIPI_DSI_LCD_H_RES,
+            .v_size = MIPI_DSI_LCD_V_RES,
+            .hsync_back_porch = MIPI_DSI_LCD_HBP,
+            .hsync_pulse_width = MIPI_DSI_LCD_HSYNC,
+            .hsync_front_porch = MIPI_DSI_LCD_HFP,
+            .vsync_back_porch = MIPI_DSI_LCD_VBP,
+            .vsync_pulse_width = MIPI_DSI_LCD_VSYNC,
+            .vsync_front_porch = MIPI_DSI_LCD_VFP,
+        },
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_dpi(mipi_dsi_bus, &dpi_config, &mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel));
+    uint32_t callback_calls = 0;
+    esp_lcd_dpi_panel_event_callbacks_t cbs = {
+        .on_refresh_done = test_rgb_panel_count_in_callback,
+    };
+    TEST_ESP_OK(esp_lcd_dpi_panel_register_event_callbacks(mipi_dpi_panel, &cbs, &callback_calls));
+
+    uint8_t color_byte = rand() & 0xFF;
+    int x_start = rand() % (MIPI_DSI_LCD_H_RES - 100);
+    int y_start = rand() % (MIPI_DSI_LCD_V_RES - 100);
+    memset(img, color_byte, TEST_IMG_SIZE);
+    esp_lcd_panel_draw_bitmap(mipi_dpi_panel, x_start, y_start, x_start + 100, y_start + 100, img);
+    vTaskDelay(pdMS_TO_TICKS(100));
+
+    printf("The LCD driver should keep flushing the color block in the background\r\n");
+
+    // disable the cache for a while, the LCD driver should stay working
+    printf("disable the cache for a while\r\n");
+    unity_utils_run_cache_disable_stub(test_delay_post_cache_disable, NULL);
+    printf("callback calls: %"PRIu32"\r\n", callback_calls);
+    TEST_ASSERT(callback_calls > 2);
+
+    TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_del(ili9881c_ctrl_panel));
+    TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io));
+    TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus));
+    free(img);
+
+    test_bsp_disable_dsi_phy_power();
+}

components/esp_lcd/test_apps/mipi_dsi_lcd/pytest_mipi_dsi_lcd.py

@@ -1,11 +1,18 @@
 # SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 from pytest_embedded import Dut
 
 
 @pytest.mark.esp32p4
 @pytest.mark.generic
-def test_rgb_lcd(dut: Dut) -> None:
+@pytest.mark.parametrize(
+    'config',
+    [
+        'iram_safe',
+        'release',
+    ],
+    indirect=True,
+)
+def test_dsi_lcd(dut: Dut) -> None:
     dut.run_all_single_board_cases()

components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.iram_safe

@@ -0,0 +1,8 @@
+CONFIG_COMPILER_DUMP_RTL_FILES=y
+CONFIG_COMPILER_OPTIMIZATION_NONE=y
+# silent the error check, as the error string are stored in rodata, causing RTL check failure
+CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
+# place non-ISR FreeRTOS functions in Flash
+CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y
+CONFIG_LCD_DSI_ISR_IRAM_SAFE=y

components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.release

@@ -0,0 +1,5 @@
+CONFIG_PM_ENABLE=y
+CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

components/esp_system/port/soc/esp32c2/clk.c

@@ -77,11 +77,16 @@ __attribute__((weak)) void esp_clk_init(void)
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
     // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
-    // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
+    // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec on 40MHz XTAL and 2.5 sec on 26MHz XTAL).
     // This prevents excessive delay before resetting in case the supply voltage is drawdown.
-    // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
+    // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec 40MHz XTAL,
+    //  or 11.72 sec on 26MHz XTAL).
     wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#ifdef CONFIG_XTAL_FREQ_26
+    uint32_t stage_timeout_ticks = (uint32_t)(2500ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
+#else
     uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
+#endif
     wdt_hal_write_protect_disable(&rtc_wdt_ctx);
     wdt_hal_feed(&rtc_wdt_ctx);
     //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same

components/freertos/FreeRTOS-Kernel/tasks.c

@@ -5478,7 +5478,7 @@ static void prvResetNextTaskUnblockTime( void )
                 #if ( configTASKLIST_INCLUDE_COREID == 1 )
                 {
                     const BaseType_t xCoreID = ( pxTaskStatusArray[ x ].xCoreID == tskNO_AFFINITY ) ? -1 : pxTaskStatusArray[ x ].xCoreID;
-                    sprintf( pcWriteBuffer, "\t%c\t%u\t%d\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( int ) xCoreID, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                    sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\t%d\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber, ( int ) xCoreID ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
                 }
                 #else /* configTASKLIST_INCLUDE_COREID == 1 */
                 {

components/hal/esp32c6/include/hal/gpio_etm_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,15 +22,20 @@
 #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
 #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
 
+#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP    8
+#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP     8
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
- * @brief Set which GPIO to be bounded to the event channel
+ * @brief Set which GPIO to be bound to the event channel
+ *
+ * @note Different channels can be bound to one GPIO
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
  * @param gpio_num GPIO number
  */
 static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
@@ -39,10 +44,10 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3
 }
 
 /**
- * @brief Wether to enable the event channel
+ * @brief Whether to enable the event channel
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
  * @param enable True to enable, false to disable
  */
 static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
@@ -51,12 +56,24 @@ static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_
 }
 
 /**
- * @brief Set which GPIO to be bounded to the task channel
- *
- * @note One channel can be bounded to multiple different GPIOs
+ * @brief Get which GPIO is bound to the event channel
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
+ * @return GPIO number
+ */
+static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
+{
+    return dev->event_chn_cfg[chan].etm_chn_event_sel;
+}
+
+/**
+ * @brief Set which GPIO to be bound to the task channel
+ *
+ * @note One channel can be bound to multiple different GPIOs
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Task channel number
  * @param gpio_num GPIO number
  */
 static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
@@ -70,7 +87,7 @@ static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32
 }
 
 /**
- * @brief Wether to enable the GPIO to be managed by the task channel
+ * @brief Whether to enable the GPIO to be managed by the task channel
  *
  * @param dev Register base address
  * @param gpio_num GPIO number
@@ -101,7 +118,7 @@ static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_
 }
 
 /**
- * @brief Get the channel number that the GPIO is bounded to
+ * @brief Get the channel number that the GPIO is bound to
  *
  * @param dev Register base address
  * @param gpio_num GPIO number

components/hal/esp32h2/include/hal/gpio_etm_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,15 +22,20 @@
 #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
 #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
 
+#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP    8
+#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP     8
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
- * @brief Set which GPIO to be bounded to the event channel
+ * @brief Set which GPIO to be bound to the event channel
+ *
+ * @note Different channels can be bound to one GPIO
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
  * @param gpio_num GPIO number
  */
 static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
@@ -39,10 +44,10 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3
 }
 
 /**
- * @brief Wether to enable the event channel
+ * @brief Whether to enable the event channel
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
  * @param enable True to enable, false to disable
  */
 static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
@@ -51,12 +56,24 @@ static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_
 }
 
 /**
- * @brief Set which GPIO to be bounded to the task channel
- *
- * @note One channel can be bounded to multiple different GPIOs
+ * @brief Get which GPIO is bound to the event channel
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
+ * @return GPIO number
+ */
+static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
+{
+    return dev->etm_event_chn_cfg[chan].etm_chn_event_sel;
+}
+
+/**
+ * @brief Set which GPIO to be bound to the task channel
+ *
+ * @note One channel can be bound to multiple different GPIOs
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Task channel number
  * @param gpio_num GPIO number
  */
 static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
@@ -70,7 +87,7 @@ static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32
 }
 
 /**
- * @brief Wether to enable the GPIO to be managed by the task channel
+ * @brief Whether to enable the GPIO to be managed by the task channel
  *
  * @param dev Register base address
  * @param gpio_num GPIO number
@@ -101,7 +118,7 @@ static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_
 }
 
 /**
- * @brief Get the channel number that the GPIO is bounded to
+ * @brief Get the channel number that the GPIO is bound to
  *
  * @param dev Register base address
  * @param gpio_num GPIO number

components/hal/esp32p4/include/hal/ahb_dma_ll.h

@@ -57,6 +57,18 @@ static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
     dev->misc_conf.ahbm_rst_inter = 0;
 }
 
+/**
+ * @brief Preset valid memory range for AHB-DMA
+ *
+ * @param dev DMA register base address
+ */
+static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev)
+{
+    // AHB-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
+    dev->intr_mem_start_addr.val = 0x40000000;
+    dev->intr_mem_end_addr.val = 0x4FFC0000;
+}
+
 ///////////////////////////////////// RX /////////////////////////////////////////
 /**
  * @brief Get DMA RX channel interrupt status word

components/hal/esp32p4/include/hal/axi_dma_ll.h

@@ -59,6 +59,20 @@ static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
     dev->misc_conf.axim_rst_wr_inter = 0;
 }
 
+/**
+ * @brief Preset valid memory range for AXI-DMA
+ *
+ * @param dev DMA register base address
+ */
+static inline void axi_dma_ll_set_default_memory_range(axi_dma_dev_t *dev)
+{
+    // AXI-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
+    dev->intr_mem_start_addr.val = 0x4FC00000;
+    dev->intr_mem_end_addr.val = 0x4FFC0000;
+    dev->extr_mem_start_addr.val = 0x40000000;
+    dev->extr_mem_end_addr.val = 0x4C000000;
+}
+
 ///////////////////////////////////// RX /////////////////////////////////////////
 /**
  * @brief Get DMA RX channel interrupt status word

components/hal/esp32p4/include/hal/gpio_etm_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,15 +22,20 @@
 #define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
 #define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
 
+#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP    8
+#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP     8
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
- * @brief Set which GPIO to be bounded to the event channel
+ * @brief Set which GPIO to be bound to the event channel
+ *
+ * @note Different channels can be bound to one GPIO
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
  * @param gpio_num GPIO number
  */
 static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
@@ -39,10 +44,10 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3
 }
 
 /**
- * @brief Wether to enable the event channel
+ * @brief Whether to enable the event channel
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
  * @param enable True to enable, false to disable
  */
 static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
@@ -51,12 +56,24 @@ static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_
 }
 
 /**
- * @brief Set which GPIO to be bounded to the task channel
- *
- * @note One channel can be bounded to multiple different GPIOs
+ * @brief Get which GPIO is bound to the event channel
  *
  * @param dev Register base address
- * @param chan Channel number
+ * @param chan GPIO ETM Event channel number
+ * @return GPIO number
+ */
+static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
+{
+    return dev->etm_event_chn_cfg[chan].etm_chn_event_sel;
+}
+
+/**
+ * @brief Set which GPIO to be bound to the task channel
+ *
+ * @note One channel can be bound to multiple different GPIOs
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Task channel number
  * @param gpio_num GPIO number
  */
 static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
@@ -70,7 +87,7 @@ static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32
 }
 
 /**
- * @brief Wether to enable the GPIO to be managed by the task channel
+ * @brief Whether to enable the GPIO to be managed by the task channel
  *
  * @param dev Register base address
  * @param gpio_num GPIO number
@@ -101,7 +118,7 @@ static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_
 }
 
 /**
- * @brief Get the channel number that the GPIO is bounded to
+ * @brief Get the channel number that the GPIO is bound to
  *
  * @param dev Register base address
  * @param gpio_num GPIO number

components/hal/esp32p4/include/hal/mipi_dsi_ll.h

@@ -14,7 +14,8 @@
 #include "hal/mipi_dsi_brg_ll.h"
 #include "hal/mipi_dsi_phy_ll.h"
 
-#define MIPI_DSI_LL_NUM_BUS 1 // 1 MIPI DSI bus
+#define MIPI_DSI_LL_NUM_BUS        1 // support only 1 MIPI DSI bus
+#define MIPI_DSI_LL_MAX_DATA_LANES 2 // support up to 2 data lanes
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h

@@ -81,12 +81,19 @@ static inline bool mipi_dsi_phy_ll_is_pll_locked(dsi_host_dev_t *dev)
  * @brief Check if the all active lanes are in the stop state
  *
  * @param dev Pointer to the DSI Host controller register base address
+ * @param num_data_lanes Number of data lanes
  * @return True if the lanes are all in stop state, False otherwise
  */
-static inline bool mipi_dsi_phy_ll_are_lanes_stopped(dsi_host_dev_t *dev)
+static inline bool mipi_dsi_phy_ll_are_lanes_stopped(dsi_host_dev_t *dev, uint8_t num_data_lanes)
 {
     uint32_t status = dev->phy_status.val;
-    const uint32_t mask = 1 << 2 | 1 << 4 | 1 << 7;
+    uint32_t mask = 1 << 2;
+    if (num_data_lanes > 0) {
+        mask |= 1 << 4;
+    }
+    if (num_data_lanes > 1) {
+        mask |= 1 << 7;
+    }
     return (status & mask) == mask;
 }
 

components/hal/gdma_hal_ahb_v2.c

@@ -244,4 +244,5 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
 #if SOC_GDMA_SUPPORT_ETM
     hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
 #endif // SOC_GDMA_SUPPORT_ETM
+    ahb_dma_ll_set_default_memory_range(hal->ahb_dma_dev);
 }

components/hal/gdma_hal_axi.c

@@ -244,4 +244,5 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
 #if SOC_GDMA_SUPPORT_ETM
     hal->enable_etm_task = gdma_axi_hal_enable_etm_task;
 #endif // SOC_GDMA_SUPPORT_ETM
+    axi_dma_ll_set_default_memory_range(hal->axi_dma_dev);
 }

components/mbedtls/port/ecc/ecc_alt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,11 +11,6 @@
 #include "mbedtls/ecp.h"
 #include "mbedtls/platform_util.h"
 
-#define ECP_VALIDATE_RET( cond )    \
-    MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA )
-#define ECP_VALIDATE( cond )        \
-    MBEDTLS_INTERNAL_VALIDATE( cond )
-
 #if defined(MBEDTLS_ECP_MUL_ALT) || defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK)
 
 #define MAX_SIZE            32     // 256 bits
@@ -94,8 +89,9 @@ int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp,
 #endif
     }
 
-    ECP_VALIDATE_RET( grp != NULL );
-    ECP_VALIDATE_RET( pt  != NULL );
+    if (grp == NULL || pt == NULL) {
+        return MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
+    }
 
     /* Must use affine coordinates */
     if( mbedtls_mpi_cmp_int( &pt->MBEDTLS_PRIVATE(Z), 1 ) != 0 )

components/nvs_flash/test_apps/main/test_nvs.c

@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <sys/param.h>
 
 #include <ctype.h>
 #include <errno.h>
@@ -587,6 +588,7 @@ TEST_CASE("test nvs apis for nvs partition generator utility with encryption ena
     extern const char nvs_key_start[] asm("_binary_encryption_keys_bin_start");
     extern const char nvs_key_end[]   asm("_binary_encryption_keys_bin_end");
     extern const char nvs_data_sch0_start[] asm("_binary_partition_encrypted_bin_start");
+    extern const char nvs_data_sch0_end[] asm("_binary_partition_encrypted_bin_end");
 
     const esp_partition_t* key_part = esp_partition_find_first(
             ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS_KEYS, NULL);
@@ -600,15 +602,24 @@ TEST_CASE("test nvs apis for nvs partition generator utility with encryption ena
         ESP_ERROR_CHECK( esp_partition_write(key_part, i, nvs_key_start + i, SPI_FLASH_SEC_SIZE) );
     }
 
-    for (int i = 0; i < nvs_part->size; i+= SPI_FLASH_SEC_SIZE) {
+    const int content_size = nvs_data_sch0_end - nvs_data_sch0_start - 1;
+    TEST_ASSERT_TRUE((content_size % SPI_FLASH_SEC_SIZE) == 0);
+
+    const int size_to_write = MIN(content_size, nvs_part->size);
+    for (int i = 0; i < size_to_write; i+= SPI_FLASH_SEC_SIZE) {
         ESP_ERROR_CHECK( esp_partition_write(nvs_part, i, nvs_data_sch0_start + i, SPI_FLASH_SEC_SIZE) );
     }
 
     err = nvs_flash_read_security_cfg(key_part, &xts_cfg);
 #elif CONFIG_NVS_SEC_KEY_PROTECT_USING_HMAC
     extern const char nvs_data_sch1_start[]    asm("_binary_partition_encrypted_hmac_bin_start");
+    extern const char nvs_data_sch1_end[]    asm("_binary_partition_encrypted_hmac_bin_end");
 
-    for (int i = 0; i < nvs_part->size; i+= SPI_FLASH_SEC_SIZE) {
+    const int content_size = nvs_data_sch1_end - nvs_data_sch1_start - 1;
+    TEST_ASSERT_TRUE((content_size % SPI_FLASH_SEC_SIZE) == 0);
+
+    const int size_to_write = MIN(content_size, nvs_part->size);
+    for (int i = 0; i < size_to_write; i+= SPI_FLASH_SEC_SIZE) {
         ESP_ERROR_CHECK( esp_partition_write(nvs_part, i, nvs_data_sch1_start + i, SPI_FLASH_SEC_SIZE) );
     }
 

components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in

@@ -251,14 +251,6 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
     bool
     default y
 
-config SOC_GPIO_ETM_EVENTS_PER_GROUP
-    int
-    default 8
-
-config SOC_GPIO_ETM_TASKS_PER_GROUP
-    int
-    default 8
-
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y

components/soc/esp32c5/beta3/include/soc/soc_caps.h

@@ -193,8 +193,6 @@
 
 // GPIO peripheral has the ETM extension
 // #define SOC_GPIO_SUPPORT_ETM          1
-#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
-#define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
 // Target has the full LP IO subsystem
 // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.

components/soc/esp32c5/mp/include/soc/soc_caps.h

@@ -183,8 +183,6 @@
 
 // GPIO peripheral has the ETM extension
 // #define SOC_GPIO_SUPPORT_ETM          1
-// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
-// #define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
 // Target has the full LP IO subsystem
 // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -471,14 +471,6 @@ config SOC_GPIO_SUPPORT_ETM
     bool
     default y
 
-config SOC_GPIO_ETM_EVENTS_PER_GROUP
-    int
-    default 8
-
-config SOC_GPIO_ETM_TASKS_PER_GROUP
-    int
-    default 8
-
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -186,8 +186,6 @@
 
 // GPIO peripheral has the ETM extension
 #define SOC_GPIO_SUPPORT_ETM          1
-#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
-#define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
 // Target has the full LP IO subsystem
 // On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -163,14 +163,6 @@ config SOC_GPIO_PIN_COUNT
     int
     default 25
 
-config SOC_GPIO_ETM_EVENTS_PER_GROUP
-    int
-    default 8
-
-config SOC_GPIO_ETM_TASKS_PER_GROUP
-    int
-    default 8
-
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -187,8 +187,6 @@
 
 // GPIO peripheral has the ETM extension
 // #define SOC_GPIO_SUPPORT_ETM          1  //TODO: [ESP32C61] IDF-9340
-#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
-#define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
 // Target has the full LP IO subsystem
 // On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -483,14 +483,6 @@ config SOC_GPIO_SUPPORT_ETM
     bool
     default y
 
-config SOC_GPIO_ETM_EVENTS_PER_GROUP
-    int
-    default 8
-
-config SOC_GPIO_ETM_TASKS_PER_GROUP
-    int
-    default 8
-
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -190,8 +190,6 @@
 
 // GPIO peripheral has the ETM extension
 #define SOC_GPIO_SUPPORT_ETM          1
-#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
-#define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
 // Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
 // Digital IOs have their own registers to control pullup/down/capability

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -451,6 +451,10 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US
     int
     default 1100
 
+config SOC_DMA_CAN_ACCESS_MSPI_MEM
+    bool
+    default y
+
 config SOC_AHB_GDMA_VERSION
     int
     default 2
@@ -519,14 +523,6 @@ config SOC_GPIO_SUPPORT_ETM
     bool
     default y
 
-config SOC_GPIO_ETM_EVENTS_PER_GROUP
-    int
-    default 8
-
-config SOC_GPIO_ETM_TASKS_PER_GROUP
-    int
-    default 8
-
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y

components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,502 +10,397 @@
 extern "C" {
 #endif
 
-/** Group: TEE HP2LP TEE PMS DATE REG */
-/** Type of hp2lp_tee_pms_date register
- *  NA
+/** Group: Version Control Registers */
+/** Type of hp2lp_peri_pms_date register
+ *  Version control register
  */
 typedef union {
     struct {
-        /** tee_date : R/W; bitpos: [31:0]; default: 2294790;
-         *  NA
+        /** hp2lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294790;
+         *  Version control register
          */
-        uint32_t tee_date:32;
+        uint32_t hp2lp_peri_pms_date:32;
     };
     uint32_t val;
-} tee_hp2lp_tee_pms_date_reg_t;
+} pms_hp2lp_peri_pms_date_reg_t;
 
 
-/** Group: TEE PMS CLK EN REG */
-/** Type of pms_clk_en register
- *  NA
+/** Group: Clock Gating Registers */
+/** Type of hp2lp_peri_pms_clk_en register
+ *  Clock gating register
  */
 typedef union {
     struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** hp2lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: Enable automatic clock gating
+         *  1: Keep the clock always on
          */
-        uint32_t reg_clk_en:1;
+        uint32_t hp2lp_peri_pms_clk_en:1;
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} tee_pms_clk_en_reg_t;
+} pms_hp2lp_peri_pms_clk_en_reg_t;
 
 
-/** Group: TEE HP CORE0 MM PMS REG0 REG */
-/** Type of hp_core0_mm_pms_reg0 register
- *  NA
+/** Group: HP CPU Permission Control Registers */
+/** Type of hp_coren_mm_pms_reg0 register
+ *  Permission control register0 for HP CPUn in machine mode
  */
 typedef union {
     struct {
-        /** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** hp_coren_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP System
+         *  Registers.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
-        /** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_sysreg_allow:1;
+        /** hp_coren_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP_AONCLKRST.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
-        /** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_aonclkrst_allow:1;
+        /** hp_coren_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP timer.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_timer_allow:1;
-        /** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_timer_allow:1;
+        /** hp_coren_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP ANAPERI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
-        /** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_anaperi_allow:1;
+        /** hp_coren_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP PMU.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
-        /** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_pmu_allow:1;
+        /** hp_coren_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP WDT.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
-        /** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_wdt_allow:1;
+        /** hp_coren_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP Mailbox
+         *  Controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
-        /** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_mailbox_allow:1;
+        /** hp_coren_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP RTC.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
-        /** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_rtc_allow:1;
+        /** hp_coren_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP PERICLKRST.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
-        /** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_periclkrst_allow:1;
+        /** hp_coren_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP UART.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_uart_allow:1;
-        /** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_uart_allow:1;
+        /** hp_coren_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP I2C.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
-        /** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_i2c_allow:1;
+        /** hp_coren_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP SPI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_spi_allow:1;
-        /** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_spi_allow:1;
+        /** hp_coren_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP I2C master.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
-        /** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_i2cmst_allow:1;
+        /** hp_coren_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP I2S.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
-        /** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_i2s_allow:1;
+        /** hp_coren_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP ADC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_adc_allow:1;
-        /** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_adc_allow:1;
+        /** hp_coren_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP touch
+         *  sensor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_touch_allow:1;
-        /** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_touch_allow:1;
+        /** hp_coren_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP IO MUX.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
-        /** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_iomux_allow:1;
+        /** hp_coren_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP INTR.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_intr_allow:1;
-        /** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_intr_allow:1;
+        /** hp_coren_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP eFuse.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
-        /** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_efuse_allow:1;
+        /** hp_coren_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access
+         *  LP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_pms_allow:1;
-        /** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_pms_allow:1;
+        /** hp_coren_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access
+         *  HP2LP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
-        /** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_hp2lp_pms_allow:1;
+        /** hp_coren_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP temperature
+         *  sensor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
-        /** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_tsens_allow:1;
+        /** hp_coren_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to LP HUK.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_huk_allow:1;
-        /** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
+        uint32_t hp_coren_mm_lp_huk_allow:1;
+        /** hp_coren_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
+         *  Configures whether HP CPUn in machine mode has permission to access LP SRAM.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
+        uint32_t hp_coren_mm_lp_sram_allow:1;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} tee_hp_core0_mm_pms_reg0_reg_t;
+} pms_hp_coren_mm_pms_reg0_reg_t;
 
-
-/** Group: TEE HP CORE0 UM PMS REG0 REG */
-/** Type of hp_core0_um_pms_reg0 register
- *  NA
+/** Type of hp_coren_um_pms_reg0 register
+ *  Permission control register0 for HP CPUn in user mode
  */
 typedef union {
     struct {
-        /** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** hp_coren_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP System
+         *  Registers.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
-        /** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_sysreg_allow:1;
+        /** hp_coren_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP_AONCLKRST.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
-        /** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_aonclkrst_allow:1;
+        /** hp_coren_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP timer.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_timer_allow:1;
-        /** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_timer_allow:1;
+        /** hp_coren_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP ANAPERI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
-        /** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_anaperi_allow:1;
+        /** hp_coren_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP PMU.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_pmu_allow:1;
-        /** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_pmu_allow:1;
+        /** hp_coren_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP WDT.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_wdt_allow:1;
-        /** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_wdt_allow:1;
+        /** hp_coren_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP Mailbox
+         *  Controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
-        /** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_mailbox_allow:1;
+        /** hp_coren_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP RTC.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core0_um_lp_rtc_allow:1;
-        /** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_rtc_allow:1;
+        /** hp_coren_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP PERICLKRST.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
-        /** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_periclkrst_allow:1;
+        /** hp_coren_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP UART.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_uart_allow:1;
-        /** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_uart_allow:1;
+        /** hp_coren_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP I2C.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_i2c_allow:1;
-        /** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_i2c_allow:1;
+        /** hp_coren_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP SPI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_spi_allow:1;
-        /** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_spi_allow:1;
+        /** hp_coren_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP I2C master.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
-        /** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_i2cmst_allow:1;
+        /** hp_coren_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP I2S.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_i2s_allow:1;
-        /** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_i2s_allow:1;
+        /** hp_coren_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP ADC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_adc_allow:1;
-        /** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_adc_allow:1;
+        /** hp_coren_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP touch sensor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_touch_allow:1;
-        /** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_touch_allow:1;
+        /** hp_coren_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP IO MUX.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_iomux_allow:1;
-        /** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_iomux_allow:1;
+        /** hp_coren_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP INTR.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_intr_allow:1;
-        /** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_intr_allow:1;
+        /** hp_coren_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP eFuse.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_efuse_allow:1;
-        /** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_efuse_allow:1;
+        /** hp_coren_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_pms_allow:1;
-        /** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_pms_allow:1;
+        /** hp_coren_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access
+         *  HP2LP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
-        /** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_hp2lp_pms_allow:1;
+        /** hp_coren_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP temperature
+         *  sensor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_tsens_allow:1;
-        /** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_tsens_allow:1;
+        /** hp_coren_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to LP HUK.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_huk_allow:1;
-        /** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
+        uint32_t hp_coren_um_lp_huk_allow:1;
+        /** hp_coren_um_lp_sram_allow : R/W; bitpos: [23]; default: 1;
+         *  Configures whether HP CPUn in user mode has permission to access LP SRAM.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
+        uint32_t hp_coren_um_lp_sram_allow:1;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} tee_hp_core0_um_pms_reg0_reg_t;
+} pms_hp_coren_um_pms_reg0_reg_t;
 
 
-/** Group: TEE HP CORE1 MM PMS REG0 REG */
-/** Type of hp_core1_mm_pms_reg0 register
- *  NA
+/** Group: TEE Peripheral Permission Control Register */
+/** Type of regdma_lp_peri_pms register
+ *  LP Peripheral Permission register for REGDMA
  */
 typedef union {
     struct {
-        /** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** regdma_peri_lp_sram_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether REGDMA has permission to access LP SRAM.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
-        /** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t regdma_peri_lp_sram_allow:1;
+        /** regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether REGDMA has permission to access  all LP peripherals.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
-        /** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_timer_allow:1;
-        /** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
-        /** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
-        /** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
-        /** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
-        /** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
-        /** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
-        /** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_uart_allow:1;
-        /** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
-        /** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_spi_allow:1;
-        /** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
-        /** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
-        /** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_adc_allow:1;
-        /** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_touch_allow:1;
-        /** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
-        /** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_intr_allow:1;
-        /** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
-        /** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_pms_allow:1;
-        /** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
-        /** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
-        /** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_huk_allow:1;
-        /** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} tee_hp_core1_mm_pms_reg0_reg_t;
-
-
-/** Group: TEE HP CORE1 UM PMS REG0 REG */
-/** Type of hp_core1_um_pms_reg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
-        /** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
-        /** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_timer_allow:1;
-        /** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
-        /** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_pmu_allow:1;
-        /** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_wdt_allow:1;
-        /** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
-        /** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_rtc_allow:1;
-        /** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
-        /** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_uart_allow:1;
-        /** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_i2c_allow:1;
-        /** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_spi_allow:1;
-        /** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
-        /** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_i2s_allow:1;
-        /** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_adc_allow:1;
-        /** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_touch_allow:1;
-        /** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_iomux_allow:1;
-        /** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_intr_allow:1;
-        /** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_efuse_allow:1;
-        /** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_pms_allow:1;
-        /** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
-        /** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_tsens_allow:1;
-        /** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_huk_allow:1;
-        /** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
-         */
-        uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} tee_hp_core1_um_pms_reg0_reg_t;
-
-
-/** Group: TEE REGDMA PERI PMS REG */
-/** Type of regdma_peri_pms register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t reg_regdma_peri_lp_ram_allow:1;
-        /** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t reg_regdma_peri_lp_peri_allow:1;
+        uint32_t regdma_peri_lp_peri_allow:1;
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} tee_regdma_peri_pms_reg_t;
+} pms_regdma_lp_peri_pms_reg_t;
 
 
 typedef struct {
-    volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
-    volatile tee_pms_clk_en_reg_t pms_clk_en;
-    volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
-    volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
-    volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
-    volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
-    volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
-} tee_dev_t;
+    volatile pms_hp2lp_peri_pms_date_reg_t hp2lp_peri_pms_date;
+    volatile pms_hp2lp_peri_pms_clk_en_reg_t hp2lp_peri_pms_clk_en;
+    volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
+    volatile pms_hp_coren_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
+    volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
+    volatile pms_hp_coren_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
+    volatile pms_regdma_lp_peri_pms_reg_t regdma_lp_peri_pms;
+} hp2lp_peri_pms_dev_t;
 
+extern hp2lp_peri_pms_dev_t HP2LP_PERI_PMS;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
+_Static_assert(sizeof(hp2lp_peri_pms_dev_t) == 0x1c, "Invalid size of hp2lp_peri_pms_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,398 +10,574 @@
 extern "C" {
 #endif
 
-/** Group: TEE LP2HP PMS DATE REG */
-/** Type of lp2hp_pms_date register
- *  NA
+/** Group: Version Control Registers */
+/** Type of lp2hp_peri_pms_date register
+ *  Version control register
  */
 typedef union {
     struct {
-        /** tee_date : R/W; bitpos: [31:0]; default: 2294790;
-         *  NA
+        /** lp2hp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294790;
+         *  Version control register.
          */
-        uint32_t tee_date:32;
+        uint32_t lp2hp_peri_pms_date:32;
     };
     uint32_t val;
-} tee_lp2hp_pms_date_reg_t;
+} pms_lp2hp_peri_pms_date_reg_t;
 
 
-/** Group: TEE PMS CLK EN REG */
-/** Type of pms_clk_en register
- *  NA
+/** Group: Clock Gating Registers */
+/** Type of lp2hp_peri_pms_clk_en register
+ *  Clock gating register
  */
 typedef union {
     struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp2hp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: Enable automatic clock gating.
+         *  1: Keep the clock always on.
          */
-        uint32_t reg_clk_en:1;
+        uint32_t lp2hp_peri_pms_clk_en:1;
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} tee_pms_clk_en_reg_t;
+} pms_lp2hp_peri_pms_clk_en_reg_t;
 
 
-/** Group: TEE LP MM PMS REG0 REG */
+/** Group: LP CPU Permission Control Registers */
 /** Type of lp_mm_pms_reg0 register
- *  NA
+ *  Permission control register0 for the LP CPU in machine mode
  */
 typedef union {
     struct {
-        /** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access external RAM
+         *  without going through cache.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_psram_allow:1;
-        /** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t lp_mm_psram_allow:1;
+        /** lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access external
+         *  flash without going through cache.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_flash_allow:1;
-        /** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t lp_mm_flash_allow:1;
+        /** lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP L2M2M
+         *  without going through cache.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_l2mem_allow:1;
-        /** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t lp_mm_l2mem_allow:1;
+        /** lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP ROM
+         *  without going through cache.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_l2rom_allow:1;
+        uint32_t lp_mm_l2rom_allow:1;
         uint32_t reserved_4:2;
-        /** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
+        /** lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access TRACE0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_trace0_allow:1;
-        /** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
+        uint32_t lp_mm_trace0_allow:1;
+        /** lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access TRACE1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_trace1_allow:1;
-        /** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
+        uint32_t lp_mm_trace1_allow:1;
+        /** lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access CPU bus
+         *  monitor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_cpu_bus_mon_allow:1;
-        /** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
+        uint32_t lp_mm_cpu_bus_mon_allow:1;
+        /** lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access L2MEM
+         *  monitor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_l2mem_mon_allow:1;
-        /** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
+        uint32_t lp_mm_l2mem_mon_allow:1;
+        /** lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access TCM monitor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_tcm_mon_allow:1;
-        /** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
+        uint32_t lp_mm_tcm_mon_allow:1;
+        /** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access cache.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_cache_allow:1;
+        uint32_t lp_mm_cache_allow:1;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} tee_lp_mm_pms_reg0_reg_t;
+} pms_lp_mm_pms_reg0_reg_t;
 
-
-/** Group: TEE LP MM PMS REG1 REG */
 /** Type of lp_mm_pms_reg1 register
- *  NA
+ *  Permission control register1 for the LP CPU in machine mode
  */
 typedef union {
     struct {
-        /** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP
+         *  high-speed USB 2.0 OTG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_usbotg_allow:1;
-        /** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_usbotg_allow:1;
+        /** lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP
+         *  full-speed USB 2.0 OTG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_usbotg11_allow:1;
-        /** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_usbotg11_allow:1;
+        /** lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP
+         *  full-speed USB 2.0 OTG's wrap.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1;
-        /** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_usbotg11_wrap_allow:1;
+        /** lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_gdma_allow:1;
-        /** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_gdma_allow:1;
+        /** lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP GDMA (DW
+         *  GDMA).
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_lp_mm_hp_regdma_allow:1;
-        /** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_regdma_allow:1;
+        /** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_sdmmc_allow:1;
-        /** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_sdmmc_allow:1;
+        /** lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access GDMA-AHB.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_ahb_pdma_allow:1;
-        /** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_ahb_pdma_allow:1;
+        /** lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP JPEG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_jpeg_allow:1;
-        /** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_jpeg_allow:1;
+        /** lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP PPA.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_ppa_allow:1;
-        /** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_ppa_allow:1;
+        /** lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_dma2d_allow:1;
-        /** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_dma2d_allow:1;
+        /** lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP key
+         *  manager.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_key_manager_allow:1;
-        /** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_key_manager_allow:1;
+        /** lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_axi_pdma_allow:1;
-        /** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_axi_pdma_allow:1;
+        /** lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP flash
+         *  MSPI controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_flash_allow:1;
-        /** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_flash_allow:1;
+        /** lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP PSRAM
+         *  MSPI controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_psram_allow:1;
-        /** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_psram_allow:1;
+        /** lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP CRYPTO.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_crypto_allow:1;
-        /** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_crypto_allow:1;
+        /** lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP EMAC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_gmac_allow:1;
-        /** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_gmac_allow:1;
+        /** lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP
+         *  high-speed USB 2.0 OTG PHY.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_usb_phy_allow:1;
-        /** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_usb_phy_allow:1;
+        /** lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP PVT.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_lp_mm_hp_pvt_allow:1;
-        /** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_pvt_allow:1;
+        /** lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI
+         *  host.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_csi_host_allow:1;
-        /** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_csi_host_allow:1;
+        /** lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI
+         *  host.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_dsi_host_allow:1;
-        /** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_dsi_host_allow:1;
+        /** lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP ISP.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_isp_allow:1;
-        /** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_isp_allow:1;
+        /** lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP H264
+         *  Encoder.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_h264_core_allow:1;
-        /** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_h264_core_allow:1;
+        /** lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP RMT.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_rmt_allow:1;
-        /** reg_lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_rmt_allow:1;
+        /** lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP bit
+         *  scrambler.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_bitsrambler_allow:1;
-        /** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_bitsrambler_allow:1;
+        /** lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP AXI ICM.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_axi_icm_allow:1;
-        /** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_axi_icm_allow:1;
+        /** lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access
+         *  HP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_peri_pms_allow:1;
-        /** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_peri_pms_allow:1;
+        /** lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access
+         *  LP2HP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1;
-        /** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp2hp_peri_pms_allow:1;
+        /** lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access
+         *  HP_DMA_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_dma_pms_allow:1;
-        /** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
-         *  NA
+        uint32_t lp_mm_dma_pms_allow:1;
+        /** lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access 2D-DMA.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_h264_dma2d_allow:1;
+        uint32_t lp_mm_hp_h264_dma2d_allow:1;
         uint32_t reserved_29:3;
     };
     uint32_t val;
-} tee_lp_mm_pms_reg1_reg_t;
+} pms_lp_mm_pms_reg1_reg_t;
 
-
-/** Group: TEE LP MM PMS REG2 REG */
 /** Type of lp_mm_pms_reg2 register
- *  NA
+ *  Permission control register2 for the LP CPU in machine mode
  */
 typedef union {
     struct {
-        /** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_mcpwm0_allow:1;
-        /** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_mcpwm0_allow:1;
+        /** lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_mcpwm1_allow:1;
-        /** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_mcpwm1_allow:1;
+        /** lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP timer
+         *  group0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_timer_group0_allow:1;
-        /** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_timer_group0_allow:1;
+        /** lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP timer
+         *  group1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_timer_group1_allow:1;
-        /** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_timer_group1_allow:1;
+        /** lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I2C0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i2c0_allow:1;
-        /** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i2c0_allow:1;
+        /** lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I2C1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i2c1_allow:1;
-        /** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i2c1_allow:1;
+        /** lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I2S0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i2s0_allow:1;
-        /** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i2s0_allow:1;
+        /** lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I2S1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i2s1_allow:1;
-        /** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i2s1_allow:1;
+        /** lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I2S2.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i2s2_allow:1;
-        /** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i2s2_allow:1;
+        /** lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP PCNT.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_pcnt_allow:1;
-        /** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_pcnt_allow:1;
+        /** lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP UART0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_uart0_allow:1;
-        /** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_uart0_allow:1;
+        /** lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP UART1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_uart1_allow:1;
-        /** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_uart1_allow:1;
+        /** lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP UART2.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_uart2_allow:1;
-        /** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_uart2_allow:1;
+        /** lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP UART3.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_uart3_allow:1;
-        /** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_uart3_allow:1;
+        /** lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP UART4.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_uart4_allow:1;
-        /** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_uart4_allow:1;
+        /** lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP PARLIO.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_parlio_allow:1;
-        /** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_parlio_allow:1;
+        /** lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_gpspi2_allow:1;
-        /** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_gpspi2_allow:1;
+        /** lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_gpspi3_allow:1;
-        /** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_gpspi3_allow:1;
+        /** lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP
+         *  USB/Serial JTAG Controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_usbdevice_allow:1;
-        /** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_usbdevice_allow:1;
+        /** lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP LEDC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_ledc_allow:1;
+        uint32_t lp_mm_hp_ledc_allow:1;
         uint32_t reserved_20:1;
-        /** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
+        /** lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP ETM.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_etm_allow:1;
-        /** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_etm_allow:1;
+        /** lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP interrupt
+         *  matrix.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_intrmtx_allow:1;
-        /** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_intrmtx_allow:1;
+        /** lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP TWAI0.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_twai0_allow:1;
-        /** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_twai0_allow:1;
+        /** lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP TWAI1.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_twai1_allow:1;
-        /** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_twai1_allow:1;
+        /** lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP TWAI2.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_twai2_allow:1;
-        /** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_twai2_allow:1;
+        /** lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I3C
+         *  master controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i3c_mst_allow:1;
-        /** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i3c_mst_allow:1;
+        /** lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP I3C slave
+         *  controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_i3c_slv_allow:1;
-        /** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_i3c_slv_allow:1;
+        /** lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_lcdcam_allow:1;
+        uint32_t lp_mm_hp_lcdcam_allow:1;
         uint32_t reserved_29:1;
-        /** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
-         *  NA
+        /** lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP ADC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_adc_allow:1;
-        /** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_adc_allow:1;
+        /** lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP UHCI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_uhci_allow:1;
+        uint32_t lp_mm_hp_uhci_allow:1;
     };
     uint32_t val;
-} tee_lp_mm_pms_reg2_reg_t;
+} pms_lp_mm_pms_reg2_reg_t;
 
-
-/** Group: TEE LP MM PMS REG3 REG */
 /** Type of lp_mm_pms_reg3 register
- *  NA
+ *  Permission control register3 for the LP CPU in machine mode
  */
 typedef union {
     struct {
-        /** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP GPIO
+         *  Matrix.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_gpio_allow:1;
-        /** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_gpio_allow:1;
+        /** lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP IO MUX.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_iomux_allow:1;
-        /** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_iomux_allow:1;
+        /** lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP system
+         *  timer.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_systimer_allow:1;
-        /** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_systimer_allow:1;
+        /** lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access HP system
+         *  register.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_sys_reg_allow:1;
-        /** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp_sys_reg_allow:1;
+        /** lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  Configures whether the LP CPU in machine mode has permission to access
+         *  HP_SYS_CLKRST.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp_clkrst_allow:1;
+        uint32_t lp_mm_hp_clkrst_allow:1;
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} tee_lp_mm_pms_reg3_reg_t;
+} pms_lp_mm_pms_reg3_reg_t;
 
 
 typedef struct {
-    volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date;
-    volatile tee_pms_clk_en_reg_t pms_clk_en;
-    volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
+    volatile pms_lp2hp_peri_pms_date_reg_t lp2hp_peri_pms_date;
+    volatile pms_lp2hp_peri_pms_clk_en_reg_t lp2hp_peri_pms_clk_en;
+    volatile pms_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
     uint32_t reserved_00c[9];
-    volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
+    volatile pms_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
     uint32_t reserved_034[28];
-    volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
+    volatile pms_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
     uint32_t reserved_0a8[29];
-    volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
-} tee_dev_t;
+    volatile pms_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
+} lp2hp_peri_pms_dev_t;
 
+extern lp2hp_peri_pms_dev_t LP2HP_PERI_PMS;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure");
+_Static_assert(sizeof(lp2hp_peri_pms_dev_t) == 0x120, "Invalid size of lp2hp_peri_pms_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/lp_peri_pms_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -11,290 +11,366 @@
 extern "C" {
 #endif
 
-/** TEE_PMS_DATE_REG register
- *  NA
+/** PMS_LP_PERI_PMS_DATE_REG register
+ *  Version control register
  */
-#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
-/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2294537;
- *  NA
+#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
+/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
+ *  Version control register
  */
-#define TEE_TEE_DATE    0xFFFFFFFFU
-#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
-#define TEE_TEE_DATE_V  0xFFFFFFFFU
-#define TEE_TEE_DATE_S  0
+#define PMS_LP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_LP_PERI_PMS_DATE_M  (PMS_LP_PERI_PMS_DATE_V << PMS_LP_PERI_PMS_DATE_S)
+#define PMS_LP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_LP_PERI_PMS_DATE_S  0
 
-/** TEE_PMS_CLK_EN_REG register
- *  NA
+/** PMS_LP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
  */
-#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
-/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  NA
+#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
+/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
  */
-#define TEE_REG_CLK_EN    (BIT(0))
-#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
-#define TEE_REG_CLK_EN_V  0x00000001U
-#define TEE_REG_CLK_EN_S  0
+#define PMS_LP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_LP_PERI_PMS_CLK_EN_M  (PMS_LP_PERI_PMS_CLK_EN_V << PMS_LP_PERI_PMS_CLK_EN_S)
+#define PMS_LP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_LP_PERI_PMS_CLK_EN_S  0
 
-/** TEE_LP_MM_PMS_REG0_REG register
- *  NA
+/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for LP CPU in machine mode
  */
-#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
-/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
+/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP system
+ *  registers.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_SYSREG_ALLOW    (BIT(0))
-#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M  (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S)
-#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S  0
-/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_LP_MM_LP_SYSREG_ALLOW_M  (PMS_LP_MM_LP_SYSREG_ALLOW_V << PMS_LP_MM_LP_SYSREG_ALLOW_S)
+#define PMS_LP_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
+ *  always-on clock and reset).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW    (BIT(1))
-#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S)
-#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S  1
-/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_M  (PMS_LP_MM_LP_AONCLKRST_ALLOW_V << PMS_LP_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_TIMER_ALLOW    (BIT(2))
-#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M  (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S)
-#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S  2
-/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_LP_MM_LP_TIMER_ALLOW_M  (PMS_LP_MM_LP_TIMER_ALLOW_V << PMS_LP_MM_LP_TIMER_ALLOW_S)
+#define PMS_LP_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TIMER_ALLOW_S  2
+/** PMS_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP ANAPERI
+ *  (analog peripherals).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW    (BIT(3))
-#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S)
-#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S  3
-/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_M  (PMS_LP_MM_LP_ANAPERI_ALLOW_V << PMS_LP_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP PMU (Power
+ *  Management Unit).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_PMU_ALLOW    (BIT(4))
-#define TEE_REG_LP_MM_LP_PMU_ALLOW_M  (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S)
-#define TEE_REG_LP_MM_LP_PMU_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_PMU_ALLOW_S  4
-/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_LP_MM_LP_PMU_ALLOW_M  (PMS_LP_MM_LP_PMU_ALLOW_V << PMS_LP_MM_LP_PMU_ALLOW_S)
+#define PMS_LP_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PMU_ALLOW_S  4
+/** PMS_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
+ *  timer).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_WDT_ALLOW    (BIT(5))
-#define TEE_REG_LP_MM_LP_WDT_ALLOW_M  (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S)
-#define TEE_REG_LP_MM_LP_WDT_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_WDT_ALLOW_S  5
-/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_LP_MM_LP_WDT_ALLOW_M  (PMS_LP_MM_LP_WDT_ALLOW_V << PMS_LP_MM_LP_WDT_ALLOW_S)
+#define PMS_LP_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_WDT_ALLOW_S  5
+/** PMS_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW    (BIT(6))
-#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S)
-#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S  6
-/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_M  (PMS_LP_MM_LP_MAILBOX_ALLOW_V << PMS_LP_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_LP_MM_LP_RTC_ALLOW    (BIT(7))
-#define TEE_REG_LP_MM_LP_RTC_ALLOW_M  (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S)
-#define TEE_REG_LP_MM_LP_RTC_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_RTC_ALLOW_S  7
-/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_LP_MM_LP_RTC_ALLOW_M  (PMS_LP_MM_LP_RTC_ALLOW_V << PMS_LP_MM_LP_RTC_ALLOW_S)
+#define PMS_LP_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_RTC_ALLOW_S  7
+/** PMS_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access  LP PREICLKRST
+ *  (peripheral clock and reset).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW    (BIT(8))
-#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S)
-#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S  8
-/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_M  (PMS_LP_MM_LP_PERICLKRST_ALLOW_V << PMS_LP_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access  LP UART.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_UART_ALLOW    (BIT(9))
-#define TEE_REG_LP_MM_LP_UART_ALLOW_M  (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S)
-#define TEE_REG_LP_MM_LP_UART_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_UART_ALLOW_S  9
-/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_LP_MM_LP_UART_ALLOW_M  (PMS_LP_MM_LP_UART_ALLOW_V << PMS_LP_MM_LP_UART_ALLOW_S)
+#define PMS_LP_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_UART_ALLOW_S  9
+/** PMS_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_I2C_ALLOW    (BIT(10))
-#define TEE_REG_LP_MM_LP_I2C_ALLOW_M  (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S)
-#define TEE_REG_LP_MM_LP_I2C_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_I2C_ALLOW_S  10
-/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_LP_MM_LP_I2C_ALLOW_M  (PMS_LP_MM_LP_I2C_ALLOW_V << PMS_LP_MM_LP_I2C_ALLOW_S)
+#define PMS_LP_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2C_ALLOW_S  10
+/** PMS_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_SPI_ALLOW    (BIT(11))
-#define TEE_REG_LP_MM_LP_SPI_ALLOW_M  (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S)
-#define TEE_REG_LP_MM_LP_SPI_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_SPI_ALLOW_S  11
-/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_LP_MM_LP_SPI_ALLOW_M  (PMS_LP_MM_LP_SPI_ALLOW_V << PMS_LP_MM_LP_SPI_ALLOW_S)
+#define PMS_LP_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SPI_ALLOW_S  11
+/** PMS_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_I2CMST_ALLOW    (BIT(12))
-#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M  (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S)
-#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S  12
-/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_LP_MM_LP_I2CMST_ALLOW_M  (PMS_LP_MM_LP_I2CMST_ALLOW_V << PMS_LP_MM_LP_I2CMST_ALLOW_S)
+#define PMS_LP_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_I2S_ALLOW    (BIT(13))
-#define TEE_REG_LP_MM_LP_I2S_ALLOW_M  (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S)
-#define TEE_REG_LP_MM_LP_I2S_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_I2S_ALLOW_S  13
-/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_LP_MM_LP_I2S_ALLOW_M  (PMS_LP_MM_LP_I2S_ALLOW_V << PMS_LP_MM_LP_I2S_ALLOW_S)
+#define PMS_LP_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_I2S_ALLOW_S  13
+/** PMS_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_ADC_ALLOW    (BIT(14))
-#define TEE_REG_LP_MM_LP_ADC_ALLOW_M  (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S)
-#define TEE_REG_LP_MM_LP_ADC_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_ADC_ALLOW_S  14
-/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_LP_MM_LP_ADC_ALLOW_M  (PMS_LP_MM_LP_ADC_ALLOW_V << PMS_LP_MM_LP_ADC_ALLOW_S)
+#define PMS_LP_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_ADC_ALLOW_S  14
+/** PMS_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_TOUCH_ALLOW    (BIT(15))
-#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M  (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S)
-#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S  15
-/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_LP_MM_LP_TOUCH_ALLOW_M  (PMS_LP_MM_LP_TOUCH_ALLOW_V << PMS_LP_MM_LP_TOUCH_ALLOW_S)
+#define PMS_LP_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_IOMUX_ALLOW    (BIT(16))
-#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M  (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S)
-#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S  16
-/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_LP_MM_LP_IOMUX_ALLOW_M  (PMS_LP_MM_LP_IOMUX_ALLOW_V << PMS_LP_MM_LP_IOMUX_ALLOW_S)
+#define PMS_LP_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP INTR
+ *  (interrupt).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_INTR_ALLOW    (BIT(17))
-#define TEE_REG_LP_MM_LP_INTR_ALLOW_M  (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S)
-#define TEE_REG_LP_MM_LP_INTR_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_INTR_ALLOW_S  17
-/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_LP_MM_LP_INTR_ALLOW_M  (PMS_LP_MM_LP_INTR_ALLOW_V << PMS_LP_MM_LP_INTR_ALLOW_S)
+#define PMS_LP_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_INTR_ALLOW_S  17
+/** PMS_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_EFUSE_ALLOW    (BIT(18))
-#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M  (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S)
-#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S  18
-/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_LP_MM_LP_EFUSE_ALLOW_M  (PMS_LP_MM_LP_EFUSE_ALLOW_V << PMS_LP_MM_LP_EFUSE_ALLOW_S)
+#define PMS_LP_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_PMS_ALLOW    (BIT(19))
-#define TEE_REG_LP_MM_LP_PMS_ALLOW_M  (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S)
-#define TEE_REG_LP_MM_LP_PMS_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_PMS_ALLOW_S  19
-/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_LP_MM_LP_PMS_ALLOW_M  (PMS_LP_MM_LP_PMS_ALLOW_V << PMS_LP_MM_LP_PMS_ALLOW_S)
+#define PMS_LP_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_PMS_ALLOW_S  19
+/** PMS_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW    (BIT(20))
-#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S)
-#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S  20
-/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
- *  NA
+#define PMS_LP_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_M  (PMS_LP_MM_HP2LP_PMS_ALLOW_V << PMS_LP_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_TSENS_ALLOW    (BIT(21))
-#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M  (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S)
-#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S  21
-/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_LP_MM_LP_TSENS_ALLOW_M  (PMS_LP_MM_LP_TSENS_ALLOW_V << PMS_LP_MM_LP_TSENS_ALLOW_S)
+#define PMS_LP_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_TSENS_ALLOW_S  21
+/** PMS_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
+ *  Unique Key).
+ *  0: Not allowed
+ *  1: Allowed
  */
-#define TEE_REG_LP_MM_LP_HUK_ALLOW    (BIT(22))
-#define TEE_REG_LP_MM_LP_HUK_ALLOW_M  (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S)
-#define TEE_REG_LP_MM_LP_HUK_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_HUK_ALLOW_S  22
-/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
- *  NA
+#define PMS_LP_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_LP_MM_LP_HUK_ALLOW_M  (PMS_LP_MM_LP_HUK_ALLOW_V << PMS_LP_MM_LP_HUK_ALLOW_S)
+#define PMS_LP_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_HUK_ALLOW_S  22
+/** PMS_LP_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether LP CPU in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW    (BIT(23))
-#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S)
-#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
-#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S  23
+#define PMS_LP_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_LP_MM_LP_SRAM_ALLOW_M  (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S)
+#define PMS_LP_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_LP_MM_LP_SRAM_ALLOW_S  23
 
-/** TEE_PERI_REGION0_LOW_REG register
- *  NA
+/** PMS_PERI_REGION0_LOW_REG register
+ *  Region0 start address configuration register
  */
-#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc)
-/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
- *  NA
+#define PMS_PERI_REGION0_LOW_REG (DR_REG_PMS_BASE + 0xc)
+/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  Configures the high 30 bits of the start address of peripheral register's region0.
  */
-#define TEE_REG_PERI_REGION0_LOW    0x3FFFFFFFU
-#define TEE_REG_PERI_REGION0_LOW_M  (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S)
-#define TEE_REG_PERI_REGION0_LOW_V  0x3FFFFFFFU
-#define TEE_REG_PERI_REGION0_LOW_S  2
+#define PMS_PERI_REGION0_LOW    0x3FFFFFFFU
+#define PMS_PERI_REGION0_LOW_M  (PMS_PERI_REGION0_LOW_V << PMS_PERI_REGION0_LOW_S)
+#define PMS_PERI_REGION0_LOW_V  0x3FFFFFFFU
+#define PMS_PERI_REGION0_LOW_S  2
 
-/** TEE_PERI_REGION0_HIGH_REG register
- *  NA
+/** PMS_PERI_REGION0_HIGH_REG register
+ *  Region0 end address configuration register
  */
-#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10)
-/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
- *  NA
+#define PMS_PERI_REGION0_HIGH_REG (DR_REG_PMS_BASE + 0x10)
+/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  Configures the high 30 bits of the end address of peripheral register's region0.
  */
-#define TEE_REG_PERI_REGION0_HIGH    0x3FFFFFFFU
-#define TEE_REG_PERI_REGION0_HIGH_M  (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S)
-#define TEE_REG_PERI_REGION0_HIGH_V  0x3FFFFFFFU
-#define TEE_REG_PERI_REGION0_HIGH_S  2
+#define PMS_PERI_REGION0_HIGH    0x3FFFFFFFU
+#define PMS_PERI_REGION0_HIGH_M  (PMS_PERI_REGION0_HIGH_V << PMS_PERI_REGION0_HIGH_S)
+#define PMS_PERI_REGION0_HIGH_V  0x3FFFFFFFU
+#define PMS_PERI_REGION0_HIGH_S  2
 
-/** TEE_PERI_REGION1_LOW_REG register
- *  NA
+/** PMS_PERI_REGION1_LOW_REG register
+ *  Region1 start address configuration register
  */
-#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14)
-/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
- *  NA
+#define PMS_PERI_REGION1_LOW_REG (DR_REG_PMS_BASE + 0x14)
+/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
+ *  Configures the high 30 bits of the start address of peripheral register's region1.
  */
-#define TEE_REG_PERI_REGION1_LOW    0x3FFFFFFFU
-#define TEE_REG_PERI_REGION1_LOW_M  (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S)
-#define TEE_REG_PERI_REGION1_LOW_V  0x3FFFFFFFU
-#define TEE_REG_PERI_REGION1_LOW_S  2
+#define PMS_PERI_REGION1_LOW    0x3FFFFFFFU
+#define PMS_PERI_REGION1_LOW_M  (PMS_PERI_REGION1_LOW_V << PMS_PERI_REGION1_LOW_S)
+#define PMS_PERI_REGION1_LOW_V  0x3FFFFFFFU
+#define PMS_PERI_REGION1_LOW_S  2
 
-/** TEE_PERI_REGION1_HIGH_REG register
- *  NA
+/** PMS_PERI_REGION1_HIGH_REG register
+ *  Region1 end address configuration register
  */
-#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18)
-/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
- *  NA
+#define PMS_PERI_REGION1_HIGH_REG (DR_REG_PMS_BASE + 0x18)
+/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
+ *  Configures the high 30 bits of the end address of peripheral register's region1.
  */
-#define TEE_REG_PERI_REGION1_HIGH    0x3FFFFFFFU
-#define TEE_REG_PERI_REGION1_HIGH_M  (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S)
-#define TEE_REG_PERI_REGION1_HIGH_V  0x3FFFFFFFU
-#define TEE_REG_PERI_REGION1_HIGH_S  2
+#define PMS_PERI_REGION1_HIGH    0x3FFFFFFFU
+#define PMS_PERI_REGION1_HIGH_M  (PMS_PERI_REGION1_HIGH_V << PMS_PERI_REGION1_HIGH_S)
+#define PMS_PERI_REGION1_HIGH_V  0x3FFFFFFFU
+#define PMS_PERI_REGION1_HIGH_S  2
 
-/** TEE_PERI_REGION_PMS_REG register
- *  NA
+/** PMS_PERI_REGION_PMS_REG register
+ *  Permission register of  region
  */
-#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c)
-/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
- *  NA
+#define PMS_PERI_REGION_PMS_REG (DR_REG_PMS_BASE + 0x1c)
+/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
+ *  Configures whether LP core in machine mode has permission to access address region0
+ *  and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_LP_CORE_REGION_PMS    0x00000003U
-#define TEE_REG_LP_CORE_REGION_PMS_M  (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S)
-#define TEE_REG_LP_CORE_REGION_PMS_V  0x00000003U
-#define TEE_REG_LP_CORE_REGION_PMS_S  0
-/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
- *  NA
+#define PMS_LP_CORE_REGION_PMS    0x00000003U
+#define PMS_LP_CORE_REGION_PMS_M  (PMS_LP_CORE_REGION_PMS_V << PMS_LP_CORE_REGION_PMS_S)
+#define PMS_LP_CORE_REGION_PMS_V  0x00000003U
+#define PMS_LP_CORE_REGION_PMS_S  0
+/** PMS_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
+ *  Configures whether HP CPU0 in user mode has permission to access address region0
+ *  and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_HP_CORE0_UM_REGION_PMS    0x00000003U
-#define TEE_REG_HP_CORE0_UM_REGION_PMS_M  (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S)
-#define TEE_REG_HP_CORE0_UM_REGION_PMS_V  0x00000003U
-#define TEE_REG_HP_CORE0_UM_REGION_PMS_S  2
-/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
- *  NA
+#define PMS_HP_CORE0_UM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE0_UM_REGION_PMS_M  (PMS_HP_CORE0_UM_REGION_PMS_V << PMS_HP_CORE0_UM_REGION_PMS_S)
+#define PMS_HP_CORE0_UM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE0_UM_REGION_PMS_S  2
+/** PMS_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
+ *  Configures whether HP CPU0 in machine mode has permission to access address region0
+ *  and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_HP_CORE0_MM_REGION_PMS    0x00000003U
-#define TEE_REG_HP_CORE0_MM_REGION_PMS_M  (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S)
-#define TEE_REG_HP_CORE0_MM_REGION_PMS_V  0x00000003U
-#define TEE_REG_HP_CORE0_MM_REGION_PMS_S  4
-/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
- *  NA
+#define PMS_HP_CORE0_MM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE0_MM_REGION_PMS_M  (PMS_HP_CORE0_MM_REGION_PMS_V << PMS_HP_CORE0_MM_REGION_PMS_S)
+#define PMS_HP_CORE0_MM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE0_MM_REGION_PMS_S  4
+/** PMS_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
+ *  Configures whether HP CPU1 in user mode has permission to access address region0
+ *  and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_HP_CORE1_UM_REGION_PMS    0x00000003U
-#define TEE_REG_HP_CORE1_UM_REGION_PMS_M  (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S)
-#define TEE_REG_HP_CORE1_UM_REGION_PMS_V  0x00000003U
-#define TEE_REG_HP_CORE1_UM_REGION_PMS_S  6
-/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
- *  NA
+#define PMS_HP_CORE1_UM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE1_UM_REGION_PMS_M  (PMS_HP_CORE1_UM_REGION_PMS_V << PMS_HP_CORE1_UM_REGION_PMS_S)
+#define PMS_HP_CORE1_UM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE1_UM_REGION_PMS_S  6
+/** PMS_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
+ *  Configures whether HP CPU1 in machine mode has permission to access address region0
+ *  and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
+ *  0: Not allowed
+ *  1: Allow
  */
-#define TEE_REG_HP_CORE1_MM_REGION_PMS    0x00000003U
-#define TEE_REG_HP_CORE1_MM_REGION_PMS_M  (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S)
-#define TEE_REG_HP_CORE1_MM_REGION_PMS_V  0x00000003U
-#define TEE_REG_HP_CORE1_MM_REGION_PMS_S  8
+#define PMS_HP_CORE1_MM_REGION_PMS    0x00000003U
+#define PMS_HP_CORE1_MM_REGION_PMS_M  (PMS_HP_CORE1_MM_REGION_PMS_V << PMS_HP_CORE1_MM_REGION_PMS_S)
+#define PMS_HP_CORE1_MM_REGION_PMS_V  0x00000003U
+#define PMS_HP_CORE1_MM_REGION_PMS_S  8
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/lp_peri_pms_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,255 +10,298 @@
 extern "C" {
 #endif
 
-/** Group: TEE PMS DATE REG */
-/** Type of pms_date register
- *  NA
+/** Group: Version Control Registers */
+/** Type of lp_peri_pms_date register
+ *  Version control register
  */
 typedef union {
     struct {
-        /** tee_date : R/W; bitpos: [31:0]; default: 2294537;
-         *  NA
+        /** lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294537;
+         *  Version control register
          */
-        uint32_t tee_date:32;
+        uint32_t lp_peri_pms_date:32;
     };
     uint32_t val;
-} tee_pms_date_reg_t;
+} pms_lp_peri_pms_date_reg_t;
 
 
-/** Group: TEE PMS CLK EN REG */
-/** Type of pms_clk_en register
- *  NA
+/** Group: Clock Gating Registers */
+/** Type of lp_peri_pms_clk_en register
+ *  Clock gating register
  */
 typedef union {
     struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: Enable automatic clock gating
+         *  1: Keep the clock always on
          */
-        uint32_t reg_clk_en:1;
+        uint32_t lp_peri_pms_clk_en:1;
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} tee_pms_clk_en_reg_t;
+} pms_lp_peri_pms_clk_en_reg_t;
 
 
-/** Group: TEE LP MM PMS REG0 REG */
-/** Type of lp_mm_pms_reg0 register
- *  NA
+/** Group: LP CPU Permission Control Registers */
+/** Type of lp_mm_lp_peri_pms_reg0 register
+ *  Permission control register0 for LP CPU in machine mode
  */
 typedef union {
     struct {
-        /** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
-         *  NA
+        /** lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP system
+         *  registers.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_sysreg_allow:1;
-        /** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_sysreg_allow:1;
+        /** lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
+         *  always-on clock and reset).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_aonclkrst_allow:1;
-        /** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_aonclkrst_allow:1;
+        /** lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP timer.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_timer_allow:1;
-        /** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_timer_allow:1;
+        /** lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP ANAPERI
+         *  (analog peripherals).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_anaperi_allow:1;
-        /** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_anaperi_allow:1;
+        /** lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP PMU (Power
+         *  Management Unit).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_pmu_allow:1;
-        /** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_pmu_allow:1;
+        /** lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
+         *  timer).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_wdt_allow:1;
-        /** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_wdt_allow:1;
+        /** lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP Mailbox
+         *  Controller.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_mailbox_allow:1;
-        /** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_mailbox_allow:1;
+        /** lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP RTC.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_lp_mm_lp_rtc_allow:1;
-        /** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_rtc_allow:1;
+        /** lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access  LP PREICLKRST
+         *  (peripheral clock and reset).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_periclkrst_allow:1;
-        /** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_periclkrst_allow:1;
+        /** lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access  LP UART.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_uart_allow:1;
-        /** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_uart_allow:1;
+        /** lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_i2c_allow:1;
-        /** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_i2c_allow:1;
+        /** lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP SPI.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_spi_allow:1;
-        /** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_spi_allow:1;
+        /** lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP I2C master.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_i2cmst_allow:1;
-        /** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_i2cmst_allow:1;
+        /** lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP I2S.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_i2s_allow:1;
-        /** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_i2s_allow:1;
+        /** lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP ADC.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_adc_allow:1;
-        /** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_adc_allow:1;
+        /** lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP touch sensor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_touch_allow:1;
-        /** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_touch_allow:1;
+        /** lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP IO MUX.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_iomux_allow:1;
-        /** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_iomux_allow:1;
+        /** lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP INTR
+         *  (interrupt).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_intr_allow:1;
-        /** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_intr_allow:1;
+        /** lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP eFuse.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_efuse_allow:1;
-        /** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_efuse_allow:1;
+        /** lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_pms_allow:1;
-        /** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_pms_allow:1;
+        /** lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access
+         *  HP2LP_PERI_PMS_REG.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_hp2lp_pms_allow:1;
-        /** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
-         *  NA
+        uint32_t lp_mm_hp2lp_pms_allow:1;
+        /** lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP temperature
+         *  sensor.
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_tsens_allow:1;
-        /** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_tsens_allow:1;
+        /** lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
+         *  Unique Key).
+         *  0: Not allowed
+         *  1: Allowed
          */
-        uint32_t reg_lp_mm_lp_huk_allow:1;
-        /** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
-         *  NA
+        uint32_t lp_mm_lp_huk_allow:1;
+        /** lp_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
+         *  Configures whether LP CPU in machine mode has permission to access LP SRAM.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_lp_mm_lp_tcm_ram_allow:1;
+        uint32_t lp_mm_lp_sram_allow:1;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} tee_lp_mm_pms_reg0_reg_t;
+} pms_lp_mm_lp_peri_pms_reg0_reg_t;
 
 
-/** Group: TEE PERI REGION0 LOW REG */
-/** Type of peri_region0_low register
- *  NA
+/** Group: Configurable Address Range Configuration Registers */
+/** Type of peri_regionn_low register
+ *  Regionn start address configuration register
  */
 typedef union {
     struct {
         uint32_t reserved_0:2;
-        /** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0;
-         *  NA
+        /** peri_regionn_low : R/W; bitpos: [31:2]; default: 0;
+         *  Configures the high 30 bits of the start address of peripheral register's regionn.
          */
-        uint32_t reg_peri_region0_low:30;
+        uint32_t peri_regionn_low:30;
     };
     uint32_t val;
-} tee_peri_region0_low_reg_t;
+} pms_peri_regionn_low_reg_t;
 
-
-/** Group: TEE PERI REGION0 HIGH REG */
-/** Type of peri_region0_high register
- *  NA
+/** Type of peri_regionn_high register
+ *  Regionn end address configuration register
  */
 typedef union {
     struct {
         uint32_t reserved_0:2;
-        /** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823;
-         *  NA
+        /** peri_regionn_high : R/W; bitpos: [31:2]; default: 1073741823;
+         *  Configures the high 30 bits of the end address of peripheral register's regionn.
          */
-        uint32_t reg_peri_region0_high:30;
+        uint32_t peri_regionn_high:30;
     };
     uint32_t val;
-} tee_peri_region0_high_reg_t;
+} pms_peri_regionn_high_reg_t;
 
 
-/** Group: TEE PERI REGION1 LOW REG */
-/** Type of peri_region1_low register
- *  NA
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_peri_region1_low:30;
-    };
-    uint32_t val;
-} tee_peri_region1_low_reg_t;
-
-
-/** Group: TEE PERI REGION1 HIGH REG */
-/** Type of peri_region1_high register
- *  NA
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823;
-         *  NA
-         */
-        uint32_t reg_peri_region1_high:30;
-    };
-    uint32_t val;
-} tee_peri_region1_high_reg_t;
-
-
-/** Group: TEE PERI REGION PMS REG */
+/** Group: PMS Peripheral Region Permission Control Registers */
 /** Type of peri_region_pms register
- *  NA
+ *  Permission register of  region
  */
 typedef union {
     struct {
-        /** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
-         *  NA
+        /** lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
+         *  Configures whether LP core in machine mode has permission to access address region0
+         *  and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_lp_core_region_pms:2;
-        /** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
-         *  NA
+        uint32_t lp_core_region_pms:2;
+        /** hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
+         *  Configures whether HP CPU0 in user mode has permission to access address region0
+         *  and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core0_um_region_pms:2;
-        /** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
-         *  NA
+        uint32_t hp_core0_um_region_pms:2;
+        /** hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
+         *  Configures whether HP CPU0 in machine mode has permission to access address region0
+         *  and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core0_mm_region_pms:2;
-        /** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
-         *  NA
+        uint32_t hp_core0_mm_region_pms:2;
+        /** hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
+         *  Configures whether HP CPU1 in user mode has permission to access address region0
+         *  and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core1_um_region_pms:2;
-        /** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
-         *  NA
+        uint32_t hp_core1_um_region_pms:2;
+        /** hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
+         *  Configures whether HP CPU1 in machine mode has permission to access address region0
+         *  and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
+         *  0: Not allowed
+         *  1: Allow
          */
-        uint32_t reg_hp_core1_mm_region_pms:2;
+        uint32_t hp_core1_mm_region_pms:2;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} tee_peri_region_pms_reg_t;
+} pms_peri_region_pms_reg_t;
 
 
 typedef struct {
-    volatile tee_pms_date_reg_t pms_date;
-    volatile tee_pms_clk_en_reg_t pms_clk_en;
-    volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
-    volatile tee_peri_region0_low_reg_t peri_region0_low;
-    volatile tee_peri_region0_high_reg_t peri_region0_high;
-    volatile tee_peri_region1_low_reg_t peri_region1_low;
-    volatile tee_peri_region1_high_reg_t peri_region1_high;
-    volatile tee_peri_region_pms_reg_t peri_region_pms;
-} tee_dev_t;
+    volatile pms_lp_peri_pms_date_reg_t lp_peri_pms_date;
+    volatile pms_lp_peri_pms_clk_en_reg_t lp_peri_pms_clk_en;
+    volatile pms_lp_mm_lp_peri_pms_reg0_reg_t lp_mm_lp_peri_pms_reg0;
+    volatile pms_peri_regionn_low_reg_t peri_region0_low;
+    volatile pms_peri_regionn_high_reg_t peri_region0_high;
+    volatile pms_peri_regionn_low_reg_t peri_region1_low;
+    volatile pms_peri_regionn_high_reg_t peri_region1_high;
+    volatile pms_peri_region_pms_reg_t peri_region_pms;
+} lp_peri_pms_dev_t;
 
+extern lp_peri_pms_dev_t LP_PERI_PMS;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(tee_dev_t) == 0x20, "Invalid size of tee_dev_t structure");
+_Static_assert(sizeof(lp_peri_pms_dev_t) == 0x20, "Invalid size of lp_peri_pms_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/soc_caps.h

@@ -182,6 +182,9 @@
     See TRM DS chapter for more details */
 #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
 
+/*-------------------------- DMA Common CAPS ----------------------------------------*/
+#define SOC_DMA_CAN_ACCESS_MSPI_MEM 1 /*!< DMA can access MSPI memory (e.g. Flash, PSRAM) */
+
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_AHB_GDMA_VERSION                2
 #define SOC_GDMA_SUPPORT_CRC                1
@@ -211,8 +214,6 @@
 
 // GPIO peripheral has the ETM extension
 #define SOC_GPIO_SUPPORT_ETM          1
-#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
-#define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
 // Target has the full LP IO subsystem
 // On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.

components/soc/esp32p4/ld/esp32p4.peripherals.ld

@@ -19,6 +19,9 @@ PROVIDE ( I2C1              = 0x500C5000 );
 PROVIDE ( UHCI0             = 0x500DF000 );
 PROVIDE ( RMT               = 0x500A2000 );
 PROVIDE ( RMTMEM            = 0x500A2800 );
+PROVIDE ( HP_PERI_PMS       = 0x500A5000 );
+PROVIDE ( LP2HP_PERI_PMS    = 0x500A5800 );
+PROVIDE ( DMA_PMS           = 0x500A6000 );
 PROVIDE ( LEDC              = 0x500D3000 );
 PROVIDE ( LEDC_GAMMA_RAM  = 0x500D3400 );
 PROVIDE ( TIMERG0           = 0x500C2000 );
@@ -79,6 +82,8 @@ PROVIDE ( LP_WDT        = 0x50116000 );
 PROVIDE ( LP_I2S        = 0x50125000 );
 PROVIDE ( LP_TOUCH      = 0x50128000 );
 PROVIDE ( LP_GPIO         = 0x5012A000 );
+PROVIDE ( LP_PERI_PMS   = 0x5012E000 );
+PROVIDE ( HP2LP_PERI_PMS = 0x5012E800 );
 PROVIDE ( LP_I2C_ANA_MST = 0x50124000 );
 PROVIDE ( LP_ANA_PERI   = 0x50113000 );
 PROVIDE ( LP_APM        = 0x600B3800 ); /* TODO: IDF-7542 */