Merge branch 'feat/lwip/ipv6_dup_detect_tries' into 'master'

feat(lwip/config): add menuconfig option for setting LWIP_IPV6_DUP_DETECT_ATTEMPTS

Closes IDFGH-9320

See merge request espressif/esp-idf!39080

.gitignore

@@ -37,6 +37,7 @@ components/**/build/
 components/**/build_*_*/
 components/**/sdkconfig
 components/**/sdkconfig.old
+components/**/test_apps/wifi_nvs_config/nvs_data_suffix.csv
 
 # Example project files
 examples/**/build/

.gitlab/ci/common.yml

@@ -140,6 +140,13 @@ variables:
   if [[ -n "$IDF_DONT_USE_MIRRORS" ]]; then
     export IDF_MIRROR_PREFIX_MAP=
   fi
+  # Optimize pip install
+  if echo "${CI_RUNNER_TAGS}" | grep "shiny"; then
+    export PIP_INDEX_URL="${PIP_INDEX_URL_SHINY}"
+  fi
+  if [[ "$(uname -m)" == "x86_64" ]] || [[ "$(uname -m)" == "aarch64" ]]; then
+    export IDF_PIP_WHEELS_URL=""
+  fi
 
   if [[ "${CI_JOB_STAGE}" != "target_test" ]]; then
     section_start "running_install_sh" "Running install.sh"
@@ -191,13 +198,21 @@ variables:
   fi
 
   # Custom OpenOCD
-  if [[ ! -z "$OOCD_DISTRO_URL" && "$CI_JOB_STAGE" == "target_test" ]]; then
-    echo "Using custom OpenOCD from ${OOCD_DISTRO_URL}"
-    wget $OOCD_DISTRO_URL
-    ARCH_NAME=$(basename $OOCD_DISTRO_URL)
-    tar -x -f $ARCH_NAME
-    export OPENOCD_SCRIPTS=$PWD/openocd-esp32/share/openocd/scripts
-    export PATH=$PWD/openocd-esp32/bin:$PATH
+  if [[ "$CI_JOB_STAGE" == "target_test" ]]; then
+    machine="$(uname -m)"
+    if [[ "$machine" == "armv7l" ]] ; then
+      OOCD_DISTRO_URL="$OOCD_DISTRO_URL_ARMHF"
+    elif [[ "$machine" == "aarch64" ]] ; then
+      OOCD_DISTRO_URL="$OOCD_DISTRO_URL_ARM64"
+    fi
+    if [[ ! -z "$OOCD_DISTRO_URL" ]]; then
+      echo "Using custom OpenOCD from ${OOCD_DISTRO_URL}"
+      wget $OOCD_DISTRO_URL
+      ARCH_NAME=$(basename $OOCD_DISTRO_URL)
+      tar -x -f $ARCH_NAME
+      export OPENOCD_SCRIPTS=$PWD/openocd-esp32/share/openocd/scripts
+      export PATH=$PWD/openocd-esp32/bin:$PATH
+    fi
   fi
 
   if [[ -n "$CI_PYTHON_TOOL_REPO" ]]; then

.gitlab/ci/default-build-test-rules.yml

@@ -16,6 +16,7 @@ bypass_check_test_targets:
   - esp32h21
   - esp32h4
   - esp32c5
+  - esp32c61
 
 #
 # These lines would

.gitlab/ci/deploy.yml

@@ -3,7 +3,6 @@
   image: $ESP_ENV_IMAGE
   tags: [ deploy ]
 
-# Check this before push_to_github
 check_submodule_sync:
   extends:
     - .deploy_job_template
@@ -31,8 +30,9 @@ push_to_github:
   extends:
     - .deploy_job_template
     - .before_script:minimal
-    - .rules:push_to_github
+    - .rules:protected:deploy
   needs:
+    # submodule must be synced before pushing to github
     - check_submodule_sync
   tags: [ brew, github_sync ]
   variables:
@@ -50,7 +50,7 @@ deploy_update_SHA_in_esp-dockerfiles:
   extends:
     - .deploy_job_template
     - .before_script:minimal
-    - .rules:protected-no_label-always
+    - .rules:protected:deploy
   dependencies: []
   variables:
     GIT_DEPTH: 2

.gitlab/ci/docs.yml

@@ -19,12 +19,9 @@
 .patterns-docs-preview: &patterns-docs-preview
   - "docs/**/*"
 
-.if-protected: &if-protected
+.if-protected-check: &if-protected-check
   if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/)'
 
-.if-protected-no_label: &if-protected-no_label
-  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && $BOT_TRIGGER_WITH_LABEL == null'
-
 .if-qa-test-tag: &if-qa-test-tag
   if: '$CI_COMMIT_TAG =~ /^qa-test/'
 
@@ -41,7 +38,7 @@
   rules:
     - <<: *if-qa-test-tag
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build_docs
     - <<: *if-label-docs_full
     - <<: *if-dev-push
@@ -64,7 +61,7 @@ check_readme_links:
   tags: ["build", "amd64", "internet"]
   allow_failure: true
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-dev-push
       changes: *patterns-example-readme
   script:
@@ -96,7 +93,7 @@ check_docs_lang_sync:
   parallel:
     matrix:
       - DOCLANG: ["en", "zh_CN"]
-        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c61", "esp32c5","esp32h2", "esp32h21", "esp32p4"]
+        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c61", "esp32c5", "esp32h2", "esp32h4", "esp32h21", "esp32p4"]
 
 check_docs_gh_links:
   image: $ESP_IDF_DOC_ENV_IMAGE
@@ -188,8 +185,7 @@ deploy_docs_production:
   # The DOCS_PROD_* variables used by this job are "Protected" so these branches must all be marked "Protected" in Gitlab settings
   extends:
     - .deploy_docs_template
-  rules:
-    - <<: *if-protected-no_label
+    - .rules:protected:deploy
   stage: post_deploy
   dependencies:  # set dependencies to null to avoid missing artifacts issue
   needs: # ensure runs after push_to_github succeeded
@@ -208,8 +204,7 @@ deploy_docs_production:
 check_doc_links:
   extends:
     - .build_docs_template
-  rules:
-    - <<: *if-protected-no_label
+    - .rules:protected:deploy
   stage: post_deploy
   needs:
     - job: deploy_docs_production

.gitlab/ci/post_deploy.yml

@@ -1,11 +1,15 @@
-generate_failed_jobs_report:
+.post_deploy_template:
   stage: post_deploy
-  tags: [build, shiny]
   image: $ESP_ENV_IMAGE
+
+generate_failed_jobs_report:
+  extends:
+    - .post_deploy_template
+  tags: [build, shiny]
   when: always
   dependencies: []  # Do not download artifacts from the previous stages
   artifacts:
-    expire_in: 1 week
+    expire_in: 2 week
     when: always
     paths:
       - job_report.html
@@ -13,12 +17,13 @@ generate_failed_jobs_report:
     - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type job
 
 sync_support_status:
-  stage: post_deploy
   extends:
-    - .rules:sync_support_status
+    - .post_deploy_template
+    - .rules:master:push
+  tags: [ brew, github_sync ]
   needs:
     - push_to_github
-  image: $ESP_ENV_IMAGE
-  tags: [ brew, github_sync ]
+  cache: []
+  before_script: []
   script:
     - curl --fail --request POST --form token="$IDF_STATUS_TRIG_TOKEN" --form ref="$IDF_STATUS_BRANCH" --form "variables[UPLOAD_TO_S3]=true" "$IDF_STATUS_TRIG_URL"

.gitlab/ci/pre_check.yml

@@ -10,7 +10,7 @@ check_version:
   # esp_idf_version.h in a branch before tagging the next version.
   extends:
     - .pre_check_template
-    - .rules:protected
+    - .rules:protected:check
   tags: [ brew, github_sync ]
   variables:
     # need a full clone to get the latest tag
@@ -165,6 +165,8 @@ pipeline_variables:
       if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
         echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
       fi
+    - echo "OOCD_DISTRO_URL_ARMHF=$OOCD_DISTRO_URL_ARMHF" >> pipeline.env
+    - echo "OOCD_DISTRO_URL_ARM64=$OOCD_DISTRO_URL_ARM64" >> pipeline.env
     - python tools/ci/ci_process_description.py
     - cat pipeline.env
     - python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report

.gitlab/ci/rules.yml

@@ -167,22 +167,19 @@
 ##############
 # if anchors #
 ##############
-.if-ref-master: &if-ref-master
-  if: '$CI_COMMIT_REF_NAME == "master"'
+.if-master-push: &if-master-push
+  if: '$CI_COMMIT_REF_NAME == "master" && $CI_PIPELINE_SOURCE == "push"'
 
-.if-ref-master-no_label: &if-ref-master-no_label
-  if: '$CI_COMMIT_REF_NAME == "master" && $BOT_TRIGGER_WITH_LABEL == null'
-
-.if-tag-release: &if-tag-release
+.if-release-tag: &if-release-tag
   if: '$CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/'
 
-.if-protected: &if-protected
+.if-protected-check: &if-protected-check
   if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) || $CI_COMMIT_TAG =~ /^qa-test/'
 
-.if-protected-no_label: &if-protected-no_label
-  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && $BOT_TRIGGER_WITH_LABEL == null'
+.if-protected-deploy: &if-protected-deploy
+  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && ($CI_PIPELINE_SOURCE == "push" || $CI_PIPELINE_SOURCE == "api")'
 
-.if-protected-ref-push: &if-protected-ref-push
+.if-protected-branch-push: &if-protected-branch-push
   # rules:changes always evaluates to true for new branch pipelines or when there is no Git push event
   if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/) && $CI_PIPELINE_SOURCE == "push"'
 
@@ -192,9 +189,6 @@
 .if-dev-push: &if-dev-push
   if: '$CI_COMMIT_REF_NAME != "master" && $CI_COMMIT_BRANCH !~ /^release\/v/ && $CI_COMMIT_TAG !~ /^v\d+\.\d+(\.\d+)?($|-)/ && $CI_COMMIT_TAG !~ /^qa-test/ && ($CI_PIPELINE_SOURCE == "push" || $CI_PIPELINE_SOURCE == "merge_request_event")'
 
-.if-schedule: &if-schedule
-  if: '$CI_PIPELINE_SOURCE == "schedule"'
-
 .if-schedule-nightly: &if-schedule-nightly
   if: '$CI_PIPELINE_SOURCE == "schedule" && $INCLUDE_NIGHTLY_RUN == "1"'
 
@@ -214,51 +208,41 @@
 # Rules #
 #########
 ### Branches ###
-.rules:protected:
+.rules:protected:check:
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
 
-.rules:push_to_github:
+.rules:protected:deploy:
   rules:
     - <<: *if-qa-test-tag
       when: never
-    - <<: *if-protected-no_label
+    - <<: *if-protected-deploy
 
-# Not uploading on release branches
-.rules:sync_support_status:
+.rules:master:push:
   rules:
-    - <<: *if-ref-master-no_label
-
-.rules:protected-no_label-always:
-  rules:
-    - <<: *if-qa-test-tag
-      when: never
-    - <<: *if-protected-no_label
-      when: always
+    - <<: *if-master-push
 
 .rules:tag:release:
   rules:
-    - <<: *if-tag-release
+    - <<: *if-release-tag
 
 .rules:dev-push:
   rules:
     - <<: *if-dev-push
 
-# Do not upload caches on dev branches by default
 .rules:upload-python-cache:
   rules:
-    - <<: *if-tag-release
+    - <<: *if-release-tag
     - <<: *if-schedule-nightly
-    - <<: *if-protected-ref-push
+    - <<: *if-protected-branch-push
       changes: *patterns-python-cache
     - <<: *if-label-upload_cache
       when: manual
 
 .rules:upload-submodule-cache:
   rules:
-    # Needn't upload submodule cache in schedule pipeline
-    - <<: *if-tag-release
-    - <<: *if-protected-ref-push
+    - <<: *if-release-tag
+    - <<: *if-protected-branch-push
       changes: *patterns-submodule
     - <<: *if-label-upload_cache
       when: manual
@@ -266,11 +250,10 @@
 ### Patterns ###
 .rules:patterns:clang_tidy:
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-dev-push
       changes: *patterns-c-files
 
-
 #.rules:patterns:static-code-analysis-preview:
 #  rules:
 #    - <<: *if-dev-push
@@ -282,7 +265,7 @@
 
 .rules:patterns:idf-pytest-plugin:
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-dev-push
       changes: *patterns-idf-pytest-plugin
 
@@ -326,7 +309,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-dev-push
       changes: *patterns-build_components
@@ -339,7 +322,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-dev-push
       changes: *patterns-build_check
@@ -354,7 +337,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-label-docker
     - <<: *if-dev-push
@@ -370,7 +353,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-label-macos
     - <<: *if-label-macos_test
@@ -385,7 +368,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-dev-push
       changes: *patterns-build_components
@@ -415,7 +398,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build-only
       when: never
     - <<: *if-label-host_test
@@ -426,7 +409,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build-only
       when: never
     - <<: *if-label-submodule

.gitlab/ci/static-code-analysis.yml

@@ -85,7 +85,7 @@ clang_tidy_check:
 #code_quality_report:
 #  extends:
 #    - .sonar_scan_template
-#    - .rules:protected
+#    - .rules:protected:check
 #  allow_failure: true  # it's using exit code to indicate the code analysis result,
 #                       # we don't want to block ci when critical issues founded
 #  script:

.gitlab/ci/test-win.yml

@@ -21,6 +21,7 @@ test_cli_installer_win:
   extends:
     - .host_test_win_template
     - .rules:labels:windows_pytest_build_system
+  allow_failure: true
   artifacts:
     when: on_failure
     paths:

.gitmodules

@@ -54,8 +54,9 @@
 	sbom-supplier = Person: Dave Gamble
 	sbom-url = https://github.com/DaveGamble/cJSON
 	sbom-description = Ultralightweight JSON parser in ANSI C
-	sbom-hash = acc76239bee01d8e9c858ae2cab296704e52d916
+	sbom-hash = 8f2beb57ddad1f94bed899790b00f46df893ccac
 	sbom-cve-exclude-list = CVE-2024-31755 Resolved in v1.7.18
+	sbom-cve-exclude-list = CVE-2023-26819 Resolved in commit a328d65ad490b64da8c87523cbbfe16050ba5bf6
 
 [submodule "components/mbedtls/mbedtls"]
 	path = components/mbedtls/mbedtls

.pre-commit-config.yaml

@@ -212,7 +212,7 @@ repos:
       - id: check-copyright
         args: ['--ignore', 'tools/ci/check_copyright_ignore.txt', '--config', 'tools/ci/check_copyright_config.yaml']
   - repo: https://github.com/espressif/conventional-precommit-linter
-    rev: v1.7.0
+    rev: v1.10.0
     hooks:
       - id: conventional-precommit-linter
         stages: [commit-msg]

Kconfig

@@ -118,8 +118,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32c5"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
-        # TODO: [ESPTOOL-1044] remove when stub supported
-        select IDF_ENV_BRINGUP
 
     config IDF_TARGET_ESP32P4
         bool

components/app_trace/app_trace_membufs_proto.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -148,6 +148,18 @@ static esp_err_t esp_apptrace_membufs_swap_waitus(esp_apptrace_membufs_proto_dat
         if (res != ESP_OK) {
             break;
         }
+#if CONFIG_IDF_TARGET_ESP32S3
+        /*
+        * ESP32S3 has a serious data corruption issue with the transferred data to host.
+        * This delay helps reduce the failure rate by temporarily reducing heavy memory writes
+        * from RTOS-level tracing and giving OpenOCD more time to read trace memory before
+        * the current thread continues execution. While this doesn't completely prevent
+        * memory access from other threads/cores/ISRs, it has shown to significantly improve
+        * reliability when combined with CRC checks in OpenOCD. In practice, this reduces the
+        * number of retries needed to read an entire block without corruption.
+        */
+        esp_rom_delay_us(100);
+#endif
     }
     return res;
 }
@@ -339,7 +351,7 @@ uint8_t *esp_apptrace_membufs_up_buffer_get(esp_apptrace_membufs_proto_data_t *p
 esp_err_t esp_apptrace_membufs_up_buffer_put(esp_apptrace_membufs_proto_data_t *proto, uint8_t *ptr, esp_apptrace_tmo_t *tmo)
 {
     esp_apptrace_membufs_pkt_end(ptr);
-    // TODO: mark block as busy in order not to re-use it for other tracing calls until it is completely written
+    // TODO: mark block as busy in order not to reuse it for other tracing calls until it is completely written
     // TODO: avoid potential situation when all memory is consumed by low prio tasks which can not complete writing due to
     // higher prio tasks and the latter can not allocate buffers at all
     // this is abnormal situation can be detected on host which will receive only uncompleted buffers

components/app_trace/port/xtensa/port.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -12,7 +12,7 @@
 // ======================
 
 // Xtensa has useful feature: TRAX debug module. It allows recording program execution flow at run-time without disturbing CPU.
-// Exectution flow data are written to configurable Trace RAM block. Besides accessing Trace RAM itself TRAX module also allows to read/write
+// Execution flow data are written to configurable Trace RAM block. Besides accessing Trace RAM itself TRAX module also allows to read/write
 // trace memory via its registers by means of JTAG, APB or ERI transactions.
 // ESP32 has two Xtensa cores with separate TRAX modules on them and provides two special memory regions to be used as trace memory.
 // Chip allows muxing access to those trace memory blocks in such a way that while one block is accessed by CPUs another one can be accessed by host
@@ -47,7 +47,7 @@
 // 2. TRAX Registers layout
 // ========================
 
-// This module uses two TRAX HW registers to communicate with host SW (OpenOCD).
+// This module uses two TRAX HW registers and one Performance Monitor register to communicate with host SW (OpenOCD).
 //  - Control register uses TRAX_DELAYCNT as storage. Only lower 24 bits of TRAX_DELAYCNT are writable. Control register has the following bitfields:
 //   | 31..XXXXXX..24 | 23 .(host_connect). 23| 22..(block_id)..15 | 14..(block_len)..0 |
 //    14..0  bits - actual length of user data in trace memory block. Target updates it every time it fills memory block and exposes it to host.
@@ -55,9 +55,15 @@
 //    21..15 bits - trace memory block transfer ID. Block counter. It can overflow. Updated by target, host should not modify it. Actually can be 2 bits;
 //    22     bit  - 'host data present' flag. If set to one there is data from host, otherwise - no host data;
 //    23     bit  - 'host connected' flag. If zero then host is not connected and tracing module works in post-mortem mode, otherwise in streaming mode;
-// - Status register uses TRAX_TRIGGERPC as storage. If this register is not zero then current CPU is changing TRAX registers and
-//   this register holds address of the instruction which application will execute when it finishes with those registers modifications.
-//   See 'Targets Connection' setion for details.
+//  - Status register uses TRAX_TRIGGERPC as storage. If this register is not zero then current CPU is changing TRAX registers and
+//    this register holds address of the instruction which application will execute when it finishes with those registers modifications.
+//    See 'Targets Connection' section for details.
+//  - CRC16 register uses ERI_PERFMON_PM1 as storage. This register is used to store CRC16 checksum of the exposed trace memory block.
+//    The register has the following format:
+//    | 31..16 (CRC indicator) | 15..0 (CRC16 value) |
+//    CRC indicator (0xA55A) is used to distinguish valid CRC values from other data that might be in the register.
+//    CRC16 is calculated over the entire exposed block and is updated every time a block is exposed to the host.
+//    This allows the host to verify data integrity of the received trace data.
 
 // 3. Modes of operation
 // =====================
@@ -127,7 +133,7 @@
 
 // Access to internal module's data is synchronized with custom mutex. Mutex is a wrapper for portMUX_TYPE and uses almost the same sync mechanism as in
 // vPortCPUAcquireMutex/vPortCPUReleaseMutex. The mechanism uses S32C1I Xtensa instruction to implement exclusive access to module's data from tasks and
-// ISRs running on both cores. Also custom mutex allows specifying timeout for locking operation. Locking routine checks underlaying mutex in cycle until
+// ISRs running on both cores. Also custom mutex allows specifying timeout for locking operation. Locking routine checks underlying mutex in cycle until
 // it gets its ownership or timeout expires. The differences of application tracing module's mutex implementation from vPortCPUAcquireMutex/vPortCPUReleaseMutex are:
 // - Support for timeouts.
 // - Local IRQs for CPU which owns the mutex are disabled till the call to unlocking routine. This is made to avoid possible task's prio inversion.
@@ -142,9 +148,9 @@
 
 // Timeout mechanism is based on xthal_get_ccount() routine and supports timeout values in microseconds.
 // There are two situations when task/ISR can be delayed by tracing API call. Timeout mechanism takes into account both conditions:
-// - Trace data are locked by another task/ISR. When wating on trace data lock.
+// - Trace data are locked by another task/ISR. When waiting on trace data lock.
 // - Current TRAX memory input block is full when working in streaming mode (host is connected). When waiting for host to complete previous block reading.
-// When wating for any of above conditions xthal_get_ccount() is called periodically to calculate time elapsed from trace API routine entry. When elapsed
+// When waiting for any of above conditions xthal_get_ccount() is called periodically to calculate time elapsed from trace API routine entry. When elapsed
 // time exceeds specified timeout value operation is canceled and ESP_ERR_TIMEOUT code is returned.
 #include "sdkconfig.h"
 #include "soc/soc.h"
@@ -159,11 +165,15 @@
 #include "esp_log.h"
 #include "esp_app_trace_membufs_proto.h"
 #include "esp_app_trace_port.h"
+#include "esp_rom_crc.h"
 
 // TRAX is disabled, so we use its registers for our own purposes
 // | 31..XXXXXX..24 | 23 .(host_connect). 23 | 22 .(host_data). 22| 21..(block_id)..15 | 14..(block_len)..0 |
 #define ESP_APPTRACE_TRAX_CTRL_REG              ERI_TRAX_DELAYCNT
 #define ESP_APPTRACE_TRAX_STAT_REG              ERI_TRAX_TRIGGERPC
+#define ESP_APPTRACE_TRAX_CRC16_REG             ERI_PERFMON_PM1
+
+#define ESP_APPTRACE_CRC_INDICATOR              (0xA55AU << 16)
 
 #define ESP_APPTRACE_TRAX_BLOCK_LEN_MSK         0x7FFFUL
 #define ESP_APPTRACE_TRAX_BLOCK_LEN(_l_)        ((_l_) & ESP_APPTRACE_TRAX_BLOCK_LEN_MSK)
@@ -498,7 +508,8 @@ static esp_err_t esp_apptrace_trax_buffer_swap_start(uint32_t curr_block_id)
         uint32_t acked_block = ESP_APPTRACE_TRAX_BLOCK_ID_GET(ctrl_reg);
         uint32_t host_to_read = ESP_APPTRACE_TRAX_BLOCK_LEN_GET(ctrl_reg);
         if (host_to_read != 0 || acked_block != (curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK)) {
-            ESP_APPTRACE_LOGD("HC[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32, esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
+            ESP_APPTRACE_LOGD("HC[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32,
+                esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
                 curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK, curr_block_id);
             res = ESP_ERR_NO_MEM;
             goto _on_err;
@@ -514,6 +525,14 @@ static esp_err_t esp_apptrace_trax_buffer_swap_end(uint32_t new_block_id, uint32
 {
     uint32_t ctrl_reg = eri_read(ESP_APPTRACE_TRAX_CTRL_REG);
     uint32_t host_connected = ESP_APPTRACE_TRAX_HOST_CONNECT & ctrl_reg;
+
+    /* calculate CRC16 of the already switched block */
+    if (prev_block_len > 0) {
+        const uint8_t *prev_block_start = s_trax_blocks[!((new_block_id % 2))];
+        uint16_t crc16 = esp_rom_crc16_le(0, prev_block_start, prev_block_len);
+        eri_write(ESP_APPTRACE_TRAX_CRC16_REG, crc16 | ESP_APPTRACE_CRC_INDICATOR);
+        ESP_APPTRACE_LOGD("CRC16:%x %d @%x", crc16, prev_block_len, prev_block_start);
+    }
     eri_write(ESP_APPTRACE_TRAX_CTRL_REG, ESP_APPTRACE_TRAX_BLOCK_ID(new_block_id) |
               host_connected | ESP_APPTRACE_TRAX_BLOCK_LEN(prev_block_len));
     esp_apptrace_trax_buffer_swap_unlock();

components/app_trace/sys_view/Sample/FreeRTOSV10.4/SEGGER_SYSVIEW_FreeRTOS.c

@@ -108,7 +108,7 @@ static void _cbSendTaskList(void) {
 *    Called from SystemView when asked by the host, returns the
 *    current system time in micro seconds.
 */
-static U64 _cbGetTime(void) {
+__attribute__((unused)) static U64 _cbGetTime(void) {
   U64 Time;
 
   Time = xTaskGetTickCountFromISR();
@@ -260,7 +260,10 @@ void SYSVIEW_SendTaskInfo(U32 TaskID, const char* sName, unsigned Prio, U32 Stac
 */
 // Callbacks provided to SYSTEMVIEW by FreeRTOS
 const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI = {
-  _cbGetTime,
+  /* Callback _cbGetTime locks xKernelLock inside xTaskGetTickCountFromISR, this can cause deadlock on multi-core.
+     To prevent deadlock, always lock xKernelLock before s_sys_view_lock. Omitting the callback here results in sending
+     SYSVIEW_EVTID_SYSTIME_CYCLES events instead of SYSVIEW_EVTID_SYSTIME_US */
+  NULL,
   _cbSendTaskList,
 };
 

components/app_update/esp_ota_ops.c

@@ -33,7 +33,7 @@
 #include "esp_flash.h"
 #include "esp_flash_internal.h"
 
-#define SUB_TYPE_ID(i) (i & 0x0F)
+#define OTA_SLOT(i) (i & 0x0F)
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
 /* Partial_data is word aligned so no reallocation is necessary for encrypted flash write */
@@ -539,6 +539,69 @@ static esp_err_t rewrite_ota_seq(esp_ota_select_entry_t *two_otadata, uint32_t s
     }
 }
 
+/**
+ * @brief Calculate the next OTA sequence number that will boot the given OTA slot.
+ *
+ * Based on the ESP-IDF OTA boot scheme, the system selects the OTA slot to boot by:
+ *   boot_slot = (seq - 1) % ota_app_count
+ *
+ * This function determines the required seq value that would cause the given ota_slot_idx
+ * to be selected on next boot.
+ *
+ * @param current_seq     Current active OTA sequence number
+ * @param ota_slot_idx    Target OTA slot index (0-based)
+ * @param ota_app_count   Total number of OTA slots
+ *
+ * @return New sequence number that will result in booting ota_slot_idx
+ */
+static uint32_t compute_ota_seq_for_target_slot(uint32_t current_seq, uint32_t ota_slot_idx, uint8_t ota_app_count)
+{
+    if (ota_app_count == 0) {
+        return 0;
+    }
+    /* ESP-IDF stores OTA boot information in the OTA data partition, which consists of two sectors.
+     * Each sector holds an esp_ota_select_entry_t structure: otadata[0] and otadata[1].
+     * These structures record the OTA sequence number (ota_seq) used to determine the current boot partition.
+     *
+     * Boot selection logic:
+     * - If both otadata[0].ota_seq and otadata[1].ota_seq are 0xFFFFFFFF (invalid), it is the initial state:
+     *     → Boot the factory app, if it exists.
+     *     → Otherwise, fall back to booting ota[0].
+     *
+     * - If both otadata entries have valid sequence numbers and CRCs:
+     *     → Choose the higher sequence number (max_seq).
+     *     → Determine the OTA partition for boot (or running partition) using:
+     *          running_ota_slot = (max_seq - 1) % ota_app_count
+     *       where ota_app_count is the total number of OTA app partitions.
+     *
+     * Example:
+     *     otadata[0].ota_seq = 4
+     *     otadata[1].ota_seq = 5
+     *     ota_app_count = 8 (available OTA slots: ota_0 to ota_7)
+     *     → max_seq = 5
+     *     → running slot = (5 - 1) % 8 = 4
+     *     → So ota_4 is currently running
+     *
+     * If you want to switch to boot a different OTA slot (e.g., ota_7):
+     *     → You need to compute a new sequence number such that:
+     *          (new_seq - 1) % ota_app_count == 7
+     *       while ensuring new_seq > current_seq.
+     *
+     * General formula:
+     *         x = current OTA slot ID
+     *         ota_slot_idx = desired OTA slot ID
+     *         seq = current ota_seq
+     *
+     *     To find the next ota_seq that will boot ota_y, use:
+     *         new_seq = ((ota_slot_idx + 1) % ota_app_count) + ota_app_count * i;
+     *         // where i is the smallest non-negative integer such that new_seq > seq
+     */
+    uint32_t i = 0;
+    uint32_t base = (ota_slot_idx + 1) % ota_app_count;
+    while (current_seq > (base + i * ota_app_count)) { i++; };
+    return base + i * ota_app_count;
+}
+
 uint8_t esp_ota_get_app_partition_count(void)
 {
     uint16_t ota_app_count = 0;
@@ -549,6 +612,30 @@ uint8_t esp_ota_get_app_partition_count(void)
     return ota_app_count;
 }
 
+/**
+ * @brief Update the OTA data partition to set the given OTA app subtype as the next boot target.
+ *
+ * ESP-IDF uses the OTA data partition to track which OTA app should boot.
+ * This partition contains two entries (otadata[0] and otadata[1]), each storing an esp_ota_select_entry_t struct,
+ * which includes the OTA sequence number (ota_seq).
+ *
+ * On boot, the chip determines the current running OTA slot using:
+ *     current_slot = (max(ota_seq) - 1) % ota_app_count
+ *
+ * This function updates the OTA data to switch the next boot to the partition with the given subtype.
+ *
+ * Behavior:
+ * - If the currently selected OTA slot already matches the requested subtype,
+ *   only the state field is updated (e.g., to mark the app as newly downloaded).
+ * - Otherwise, it calculates the next valid ota_seq that will cause the bootloader to select
+ *   the requested OTA slot on reboot, and writes it to the inactive OTA data sector.
+ *
+ * @param subtype The OTA partition subtype (e.g., ESP_PARTITION_SUBTYPE_APP_OTA_0, ..._OTA_1, ...)
+ * @return
+ *     - ESP_OK if update was successful
+ *     - ESP_ERR_NOT_FOUND if OTA data partition not found
+ *     - ESP_ERR_INVALID_ARG if subtype is out of range
+ */
 static esp_err_t esp_rewrite_ota_data(esp_partition_subtype_t subtype)
 {
     esp_ota_select_entry_t otadata[2];
@@ -558,42 +645,31 @@ static esp_err_t esp_rewrite_ota_data(esp_partition_subtype_t subtype)
     }
 
     uint8_t ota_app_count = esp_ota_get_app_partition_count();
-    if (SUB_TYPE_ID(subtype) >= ota_app_count) {
+    if (OTA_SLOT(subtype) >= ota_app_count) {
         return ESP_ERR_INVALID_ARG;
     }
-
-    //esp32_idf use two sector for store information about which partition is running
-    //it defined the two sector as ota data partition,two structure esp_ota_select_entry_t is saved in the two sector
-    //named data in first sector as otadata[0], second sector data as otadata[1]
-    //e.g.
-    //if otadata[0].ota_seq == otadata[1].ota_seq == 0xFFFFFFFF,means ota info partition is in init status
-    //so it will boot factory application(if there is),if there's no factory application,it will boot ota[0] application
-    //if otadata[0].ota_seq != 0 and otadata[1].ota_seq != 0,it will choose a max seq ,and get value of max_seq%max_ota_app_number
-    //and boot a subtype (mask 0x0F) value is (max_seq - 1)%max_ota_app_number,so if want switch to run ota[x],can use next formulas.
-    //for example, if otadata[0].ota_seq = 4, otadata[1].ota_seq = 5, and there are 8 ota application,
-    //current running is (5-1)%8 = 4,running ota[4],so if we want to switch to run ota[7],
-    //we should add otadata[0].ota_seq (is 4) to 4 ,(8-1)%8=7,then it will boot ota[7]
-    //if      A=(B - C)%D
-    //then    B=(A + C)%D + D*n ,n= (0,1,2...)
-    //so current ota app sub type id is x , dest bin subtype is y,total ota app count is n
-    //seq will add (x + n*1 + 1 - seq)%n
-
     int active_otadata = bootloader_common_get_active_otadata(otadata);
+    int next_otadata;
+    uint32_t new_seq;
     if (active_otadata != -1) {
-        uint32_t seq = otadata[active_otadata].ota_seq;
-        uint32_t i = 0;
-        while (seq > (SUB_TYPE_ID(subtype) + 1) % ota_app_count + i * ota_app_count) {
-            i++;
+        uint32_t ota_slot = (otadata[active_otadata].ota_seq - 1) % ota_app_count;
+        if (ota_slot == OTA_SLOT(subtype)) {
+            // ota_data is already valid and points to the correct OTA slot.
+            // So after reboot the requested partition will be selected for boot.
+            // Only update the ota_state of the requested partition.
+            next_otadata = active_otadata;
+            new_seq = otadata[active_otadata].ota_seq;
+        } else {
+            next_otadata = (~active_otadata) & 1; // if 0 -> will be next 1. and if 1 -> will be next 0.
+            new_seq = compute_ota_seq_for_target_slot(otadata[active_otadata].ota_seq, OTA_SLOT(subtype), ota_app_count);
         }
-        int next_otadata = (~active_otadata)&1; // if 0 -> will be next 1. and if 1 -> will be next 0.
-        otadata[next_otadata].ota_state = set_new_state_otadata();
-        return rewrite_ota_seq(otadata, (SUB_TYPE_ID(subtype) + 1) % ota_app_count + i * ota_app_count, next_otadata, otadata_partition);
     } else {
         /* Both OTA slots are invalid, probably because unformatted... */
-        int next_otadata = 0;
-        otadata[next_otadata].ota_state = set_new_state_otadata();
-        return rewrite_ota_seq(otadata, SUB_TYPE_ID(subtype) + 1, next_otadata, otadata_partition);
+        next_otadata = 0;
+        new_seq = OTA_SLOT(subtype) + 1;
     }
+    otadata[next_otadata].ota_state = set_new_state_otadata();
+    return rewrite_ota_seq(otadata, new_seq, next_otadata, otadata_partition);
 }
 
 esp_err_t esp_ota_set_boot_partition(const esp_partition_t *partition)

components/app_update/test_apps/test_app_update/main/test_switch_ota.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -204,15 +204,13 @@ static const esp_partition_t* get_running_firmware(void)
 {
     const esp_partition_t *configured = esp_ota_get_boot_partition();
     const esp_partition_t *running = esp_ota_get_running_partition();
+    // If a reboot hasn't occurred after app_update(), the configured and running partitions may differ
     ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08"PRIx32")",
             running->type, running->subtype, running->address);
     ESP_LOGI(TAG, "Configured partition type %d subtype %d (offset 0x%08"PRIx32")",
             configured->type, configured->subtype, configured->address);
     TEST_ASSERT_NOT_EQUAL(NULL, configured);
     TEST_ASSERT_NOT_EQUAL(NULL, running);
-    if (running->subtype != ESP_PARTITION_SUBTYPE_APP_TEST) {
-        TEST_ASSERT_EQUAL_PTR(running, configured);
-    }
     return running;
 }
 
@@ -930,3 +928,51 @@ static void test_rollback3_1(void)
 }
 
 TEST_CASE_MULTIPLE_STAGES("Test rollback. Updated partition invalidated after esp_ota_begin", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET, DEEPSLEEP_RESET, SW_CPU_RESET]", start_test, test_rollback3, test_rollback3, test_rollback3, test_rollback3_1);
+
+static void test_rollback4(void)
+{
+    uint8_t boot_count = get_boot_count_from_nvs();
+    boot_count++;
+    set_boot_count_in_nvs(boot_count);
+    ESP_LOGI(TAG, "boot count %d", boot_count);
+    const esp_partition_t *cur_app = get_running_firmware();
+    switch (boot_count) {
+        case 2:
+            ESP_LOGI(TAG, "Factory");
+            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_FACTORY, cur_app->subtype);
+            app_update();
+            reboot_as_deep_sleep();
+            break;
+        case 3:
+            ESP_LOGI(TAG, "OTA0");
+            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_0, cur_app->subtype);
+            TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
+            app_update();
+
+            // Do not reboot and call app_update again.
+            // This will not change the running partition since we haven't rebooted.
+            // The esp_rewrite_otadata() will update the otadata for the non-running partition only.
+            app_update();
+#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
+            // The last call to esp_rewrite_otadata should have updated the otadata for the non-running partition only.
+            // Therefore, calling esp_ota_get_state_partition on the running partition should succeed and not return ESP_ERR_NOT_FOUND
+            const esp_partition_t* running_partition;
+            running_partition = esp_ota_get_running_partition();
+            esp_ota_img_states_t ota_state;
+            TEST_ESP_OK(esp_ota_get_state_partition(running_partition, &ota_state));
+#endif
+            reboot_as_deep_sleep();
+            break;
+        case 4:
+            ESP_LOGI(TAG, "OTA1");
+            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_1, cur_app->subtype);
+            TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
+            break;
+        default:
+            erase_ota_data();
+            TEST_FAIL_MESSAGE("Unexpected stage");
+            break;
+    }
+}
+
+TEST_CASE_MULTIPLE_STAGES("Test esp_rewrite_otadata. Updated sequence number for non-running partition always", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET, DEEPSLEEP_RESET, SW_CPU_RESET]", start_test, test_rollback4, test_rollback4, test_rollback4);

components/app_update/test_apps/test_app_update/pytest_app_update_ut.py

@@ -20,7 +20,7 @@ TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_app_update(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
 
 
 @pytest.mark.generic
@@ -33,7 +33,7 @@ def test_app_update(dut: Dut) -> None:
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_app_update_xip_psram(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
 
 
 @pytest.mark.generic
@@ -46,7 +46,7 @@ def test_app_update_xip_psram(dut: Dut) -> None:
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
 
 
 @pytest.mark.generic
@@ -59,4 +59,4 @@ def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
 )
 @idf_parametrize('target', ['esp32', 'esp32c3', 'esp32s3', 'esp32p4'], indirect=['target'])
 def test_app_update_with_rollback(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)

components/bootloader/Kconfig.log.settings

@@ -21,6 +21,7 @@ menu "Settings"
         config BOOTLOADER_LOG_MODE_BINARY
             bool "Binary Log Mode"
             select BOOTLOADER_LOG_MODE_BINARY_EN
+            depends on BOOTLOADER_LOG_VERSION_2
             help
                 Enables binary logging with host-side format string expansion. In this mode, the
                 format argument of ESP_LOGx, ESP_EARLY_LOG, and ESP_DRAM_LOG macros is stored in a

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -136,7 +136,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 #if ESP_TEE_BUILD
 #include "esp_fault.h"
 #include "esp_flash_partitions.h"
-#include "esp32c6/rom/spi_flash.h"
+#include "rom/spi_flash.h"
 
 extern bool esp_tee_flash_check_paddr_in_active_tee_part(size_t paddr);
 #endif

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -55,7 +55,8 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
+    mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -52,7 +52,8 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
-    mspi_ll_fast_set_hs_divider(6);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
+    mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

components/bootloader_support/private_include/bootloader_soc.h

@@ -25,12 +25,11 @@ void bootloader_ana_super_wdt_reset_config(bool enable);
 void bootloader_ana_clock_glitch_reset_config(bool enable);
 
 /**
- * @brief Configure analog power glitch reset & glitch reset dref
+ * @brief Configure analog power glitch reset
  *
  * @param enable Boolean to enable or disable power glitch reset
- * @param dref voltage threshold
  */
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
+void bootloader_power_glitch_reset_config(bool enable);
 
 #ifdef __cplusplus
 }

components/bootloader_support/src/bootloader_common_loader.c

@@ -28,6 +28,7 @@
 
 #define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
 #define IS_FIELD_SET(rev_full) (((rev_full) != 65535) && ((rev_full) != 0))
+#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
 static const char* TAG = "boot_comm";
 
@@ -264,7 +265,10 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
 #if ESP_ROM_HAS_LP_ROM
     #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW)
 #else
-    #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t))
+    /* Since the structure containing the retain_mem_t is aligned on 8 by the linker, make sure we align this
+     * structure size here too */
+    #define RETAIN_MEM_SIZE     ALIGN_UP(sizeof(rtc_retain_mem_t), 8)
+    #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE)
 #endif //ESP_ROM_HAS_LP_ROM
     static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR;
     return s_bootloader_retain_mem;

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;

components/bootloader_support/src/bootloader_random_esp32c6.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_2;

components/bootloader_support/src/bootloader_random_esp32c61.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;

components/bootloader_support/src/bootloader_random_esp32h2.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.atten = ADC_ATTEN_DB_2_5;

components/bootloader_support/src/bootloader_random_esp32p4.c

@@ -1,108 +1,72 @@
 /*
  * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+#include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "soc/soc.h"
-#include "soc/adc_reg.h"
-#include "soc/pmu_reg.h"
-#include "soc/regi2c_saradc.h"
-#include "soc/hp_sys_clkrst_reg.h"
-#include "soc/lp_adc_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "esp_rom_regi2c.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
 
-// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
+#include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 
 #define I2C_SAR_ADC_INIT_CODE_VAL 2166
 
-typedef struct {
-    int atten;
-    int channel;
-} pattern_item;
-
-typedef struct {
-    pattern_item item[4];
-} pattern_table;
-
-static void adc1_fix_initcode_set(uint32_t initcode_value)
-{
-    uint32_t msb = initcode_value >> 8;
-    uint32_t lsb = initcode_value & 0xff;
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
-}
-
-//total 4 tables
-static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
-{
-    uint32_t wdata = 0;
-    wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
-            table.item[1].channel << 14|table.item[1].atten << 12 |
-            table.item[2].channel << 8 |table.item[2].atten << 6 |
-            table.item[3].channel << 2 |table.item[3].atten);
-    WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
-}
-
 void bootloader_random_enable(void)
 {
-    pattern_table sar1_table[4] = {};
-    uint32_t pattern_len = 0;
+    _adc_ll_reset_register();
+    _adc_ll_enable_bus_clock(true);
 
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(0, 0, 0);
 
-    SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
-
-    uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
-
-    SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_enable();
+#else
+    regi2c_ctrl_ll_i2c_sar_periph_enable();
+#endif
 
     // enable analog i2c master clock for RNG runtime
     ANALOG_CLOCK_ENABLE();
 
-    adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_regi2c_init();
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
 
-    //  cfg pattern table
-    sar1_table[0].item[0].channel = 10; //rand() % 6;
-    sar1_table[0].item[0].atten = 3;
-    sar1_table[0].item[1].channel = 10;
-    sar1_table[0].item[1].atten = 3;
-    sar1_table[0].item[2].channel = 10;
-    sar1_table[0].item[2].atten = 3;
-    sar1_table[0].item[3].channel = 10;
-    sar1_table[0].item[3].atten = 3;
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.unit = ADC_UNIT_1;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_10;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 1, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 2, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 3, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
 
-    hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
+    adc_ll_digi_set_power_manage(ADC_UNIT_1, ADC_LL_POWER_SW_ON);
 
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
-
-    CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
-    SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
-    SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
-
-    while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
-
-    SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(100);
+    adc_ll_digi_trigger_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_regi2c_adc_deinit();
+
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_disable();
+#endif
+
     // disable analog i2c master clock
     ANALOG_CLOCK_DISABLE();
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
 }

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -86,7 +86,6 @@ static void bootloader_super_wdt_auto_feed(void)
 static inline void bootloader_hardware_init(void)
 {
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
-    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 
@@ -94,11 +93,7 @@ static inline void bootloader_ana_reset_config(void)
 {
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
-    if (efuse_hal_chip_revision() == 0) {
-        // decrease power glitch reset voltage to avoid start the glitch reset
-        uint8_t power_glitch_dref = 0;
-        bootloader_power_glitch_reset_config(true, power_glitch_dref);
-    }
+    bootloader_power_glitch_reset_config(true);
 }
 
 esp_err_t bootloader_init(void)

components/bootloader_support/src/esp32c5/bootloader_soc.c

@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
     (void)enable;
 }
 
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+void bootloader_power_glitch_reset_config(bool enable)
 {
-    assert(dref < 8);
-    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    //only detect VDDPST POWER GLITCH
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_XTAL, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
+
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO1
     if (enable) {
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
-        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO1
     } else {
         REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
     }

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -87,7 +87,6 @@ static void bootloader_super_wdt_auto_feed(void)
 static inline void bootloader_hardware_init(void)
 {
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
-    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 
@@ -95,8 +94,7 @@ static inline void bootloader_ana_reset_config(void)
 {
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
-    uint8_t power_glitch_dref = 0;
-    bootloader_power_glitch_reset_config(true, power_glitch_dref);
+    bootloader_power_glitch_reset_config(true);
 }
 
 esp_err_t bootloader_init(void)

components/bootloader_support/src/esp32c61/bootloader_soc.c

@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
     (void)enable;
 }
 
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+void bootloader_power_glitch_reset_config(bool enable)
 {
-    assert(dref < 8);
-    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    //only detect VDDPST POWER GLITCH
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
+
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO2
     if (enable) {
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
-        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO2
     } else {
         REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
     }

components/bootloader_support/src/esp32h2/secure_boot_secure_features.c

@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <strings.h>
+#include "hal/ecdsa_ll.h"
 #include "esp_flash_encrypt.h"
 #include "esp_secure_boot.h"
 #include "esp_efuse.h"
@@ -36,6 +37,12 @@ esp_err_t esp_secure_boot_enable_secure_features(void)
     ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
 #endif
 
+#ifdef SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
+    }
+#endif
+
 #ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
     ESP_LOGI(TAG, "Disable hardware & software JTAG...");
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);

components/bootloader_support/src/esp32h21/bootloader_esp32h21.c

@@ -89,8 +89,8 @@ static inline void bootloader_hardware_init(void)
     CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
 
-    //TODO: [ESP32H21] IDF-11550, regi2c atomic clock
-    regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-11548 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 

components/bootloader_support/src/esp_image_format.c

@@ -796,20 +796,27 @@ static esp_err_t verify_segment_header(int index, const esp_image_segment_header
     bool map_segment = should_map(load_addr);
 
 #if SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    esp_err_t err = ESP_FAIL;
+
     /* ESP APP descriptor is present in the DROM segment #0 */
     if (index == 0 && !is_bootloader(metadata->start_addr)) {
-        const esp_app_desc_t *app_desc = (const esp_app_desc_t *)bootloader_mmap(segment_data_offs, sizeof(esp_app_desc_t));
-        if (!app_desc || app_desc->magic_word != ESP_APP_DESC_MAGIC_WORD) {
+        uint32_t mmu_page_size = 0, magic_word = 0;
+        const uint32_t mmu_page_size_offset = segment_data_offs + offsetof(esp_app_desc_t, mmu_page_size);
+        CHECK_ERR(bootloader_flash_read(segment_data_offs, &magic_word, sizeof(uint32_t), true));
+        CHECK_ERR(bootloader_flash_read(mmu_page_size_offset, &mmu_page_size, sizeof(uint32_t), true));
+        // Extract only the lowest byte from mmu_page_size (as per image format)
+        mmu_page_size &= 0xFF;
+
+        if (magic_word != ESP_APP_DESC_MAGIC_WORD) {
             ESP_LOGE(TAG, "Failed to fetch app description header!");
             return ESP_FAIL;
         }
 
         // Convert from log base 2 number to actual size while handling legacy image case (value 0)
-        metadata->mmu_page_size = (app_desc->mmu_page_size > 0) ? (1UL << app_desc->mmu_page_size) : SPI_FLASH_MMU_PAGE_SIZE;
+        metadata->mmu_page_size = (mmu_page_size > 0) ? (1UL << mmu_page_size) : SPI_FLASH_MMU_PAGE_SIZE;
         if (metadata->mmu_page_size != SPI_FLASH_MMU_PAGE_SIZE) {
             ESP_LOGI(TAG, "MMU page size mismatch, configured: 0x%x, found: 0x%"PRIx32, SPI_FLASH_MMU_PAGE_SIZE, metadata->mmu_page_size);
         }
-        bootloader_munmap(app_desc);
     } else if (index == 0 && is_bootloader(metadata->start_addr)) {
         // Bootloader always uses the default MMU page size
         metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
@@ -836,6 +843,10 @@ static esp_err_t verify_segment_header(int index, const esp_image_segment_header
     }
 
     return ESP_OK;
+#if SOC_MMU_PAGE_SIZE_CONFIGURABLE
+err:
+    return err;
+#endif
 }
 
 static bool should_map(uint32_t load_addr)

components/bootloader_support/src/secure_boot.c

@@ -12,6 +12,10 @@
 #include "esp_secure_boot.h"
 #include "hal/efuse_hal.h"
 
+#ifdef SOC_ECDSA_SUPPORTED
+#include "hal/ecdsa_ll.h"
+#endif
+
 #ifndef BOOTLOADER_BUILD
 static __attribute__((unused)) const char *TAG = "secure_boot";
 
@@ -341,15 +345,17 @@ bool esp_secure_boot_cfg_verify_release_mode(void)
     }
 
 #ifdef SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
-    secure = esp_efuse_read_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
-    if (!secure) {
-        uint8_t current_curve;
-        esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_ECDSA_CURVE_MODE, &current_curve, ESP_EFUSE_ECDSA_CURVE_MODE[0]->bit_count);
-        if (err == ESP_OK) {
-            if (current_curve != ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED) {
-                // If not P256 mode
-                result &= secure;
-                ESP_LOGW(TAG, "Not write disabled ECDSA curve mode (set WR_DIS_ECDSA_CURVE_MODE->1)");
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        secure = esp_efuse_read_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
+        if (!secure) {
+            uint8_t current_curve;
+            esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_ECDSA_CURVE_MODE, &current_curve, ESP_EFUSE_ECDSA_CURVE_MODE[0]->bit_count);
+            if (err == ESP_OK) {
+                if (current_curve != ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED) {
+                    // If not P256 mode
+                    result &= secure;
+                    ESP_LOGW(TAG, "Not write disabled ECDSA curve mode (set WR_DIS_ECDSA_CURVE_MODE->1)");
+                }
             }
         }
     }

components/bt/common/Kconfig.in

@@ -48,7 +48,7 @@ config BT_BLE_LOG_SPI_OUT_LL_TASK_BUF_SIZE
     depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
     default 1024
     help
-        SPI transaction buffer size for upper layer task logs.
+        SPI transaction buffer size for lower layer task logs.
         There will be 2 SPI DMA buffers with the same size.
 
 config BT_BLE_LOG_SPI_OUT_LL_ISR_BUF_SIZE
@@ -56,9 +56,17 @@ config BT_BLE_LOG_SPI_OUT_LL_ISR_BUF_SIZE
     depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
     default 512
     help
-        SPI transaction buffer size for upper layer ISR logs.
+        SPI transaction buffer size for lower layer ISR logs.
         There will be 2 SPI DMA buffers with the same size.
 
+config BT_BLE_LOG_SPI_OUT_LL_HCI_BUF_SIZE
+    int "SPI transaction buffer size for lower layer HCI logs"
+    depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
+    default 512
+    help
+        SPI transaction buffer size for upper layer HCI logs.
+        There will be 2 SPI DMA buffers with the same size
+
 config BT_BLE_LOG_SPI_OUT_MOSI_IO_NUM
     int "GPIO number of SPI MOSI"
     depends on BT_BLE_LOG_SPI_OUT_ENABLED
@@ -94,6 +102,13 @@ config BT_BLE_LOG_SPI_OUT_SYNC_IO_NUM
     help
         GPIO number of SYNC IO
 
+config BT_BLE_LOG_SPI_OUT_TS_SYNC_SLEEP_SUPPORT
+    bool "Enable ble log & logic analyzer log time sync sleep support"
+    depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
+    default n
+    help
+        Enable ble log & logic analyzer log time sync sleep support
+
 config BT_BLE_LOG_SPI_OUT_FLUSH_TIMER_ENABLED
     bool "Enable periodic buffer flush out"
     depends on BT_BLE_LOG_SPI_OUT_ENABLED
@@ -108,3 +123,18 @@ config BT_BLE_LOG_SPI_OUT_FLUSH_TIMEOUT
     default 1000
     help
         Buffer flush out period in unit of ms
+
+config BT_BLE_LOG_SPI_OUT_LE_AUDIO_ENABLED
+    bool "Enable LE Audio log output to SPI"
+    depends on BT_BLE_LOG_SPI_OUT_ENABLED
+    default n
+    help
+        Enable LE Audio log output to SPI
+
+config BT_BLE_LOG_SPI_OUT_LE_AUDIO_BUF_SIZE
+    int "SPI transaction buffer size for LE Audio logs"
+    depends on BT_BLE_LOG_SPI_OUT_LE_AUDIO_ENABLED
+    default 1024
+    help
+        SPI transaction buffer size for LE Audio logs.
+        There will be 2 SPI DMA buffers with the same size.

components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h

@@ -14,27 +14,33 @@
 #include "esp_log.h"
 #include "freertos/semphr.h"
 
-// Public typedefs
-#define BLE_LOG_SPI_OUT_SOURCE_ESP 0
-#define BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY 1
-#define BLE_LOG_SPI_OUT_SOURCE_BLUEDROID 2
-#define BLE_LOG_SPI_OUT_SOURCE_NIMBLE 3
-#define BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM 4
-#define BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM 5
-#define BLE_LOG_SPI_OUT_SOURCE_ESP_ISR 6
-#define BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY_ISR 7
-#define BLE_LOG_SPI_OUT_SOURCE_USER 0x10
-#define BLE_LOG_SPI_OUT_SOURCE_SYNC 0xFE
-#define BLE_LOG_SPI_OUT_SOURCE_LOSS 0xFF
+// Public enums
+enum {
+    BLE_LOG_SPI_OUT_SOURCE_ESP = 0,
+    BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY,
+    BLE_LOG_SPI_OUT_SOURCE_BLUEDROID,
+    BLE_LOG_SPI_OUT_SOURCE_NIMBLE,
+    BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM,
+    BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM,
+    BLE_LOG_SPI_OUT_SOURCE_ESP_ISR,
+    BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY_ISR,
+    BLE_LOG_SPI_OUT_SOURCE_LL_HCI,
+    BLE_LOG_SPI_OUT_SOURCE_LE_AUDIO,
+    BLE_LOG_SPI_OUT_SOURCE_USER = 0x10,
+    BLE_LOG_SPI_OUT_SOURCE_SSC = 0xFD,
+    BLE_LOG_SPI_OUT_SOURCE_SYNC,
+    BLE_LOG_SPI_OUT_SOURCE_LOSS,
+};
 
-// SPI Log Level Definitions
-#define BLE_LOG_SPI_OUT_LEVEL_NONE      0  /*!< No log output */
-#define BLE_LOG_SPI_OUT_LEVEL_ERROR     1  /*!< Critical errors that SPI driver cannot recover from */
-#define BLE_LOG_SPI_OUT_LEVEL_WARN      2  /*!< Recoverable error conditions in SPI communication */
-#define BLE_LOG_SPI_OUT_LEVEL_INFO      3  /*!< Informational messages about SPI transactions */
-#define BLE_LOG_SPI_OUT_LEVEL_DEBUG     4  /*!< Detailed debug information, such as SPI register values */
-#define BLE_LOG_SPI_OUT_LEVEL_VERBOSE   5  /*!< Very detailed debugging logs, potentially flooding output */
-#define BLE_LOG_SPI_OUT_LEVEL_MAX       6  /*!< Number of SPI log levels supported */
+enum {
+    BLE_LOG_SPI_OUT_LEVEL_NONE = 0,
+    BLE_LOG_SPI_OUT_LEVEL_ERROR,
+    BLE_LOG_SPI_OUT_LEVEL_WARN,
+    BLE_LOG_SPI_OUT_LEVEL_INFO,
+    BLE_LOG_SPI_OUT_LEVEL_DEBUG,
+    BLE_LOG_SPI_OUT_LEVEL_VERBOSE,
+    BLE_LOG_SPI_OUT_LEVEL_MAX,
+};
 
 // Public functions
 int ble_log_spi_out_init(void);
@@ -50,5 +56,8 @@ int ble_log_spi_out_printf(uint8_t source, const char *format, ...);
 int ble_log_spi_out_printf_enh(uint8_t source, uint8_t level, const char *tag, const char *format, ...);
 int ble_log_spi_out_write_with_ts(uint8_t source, const uint8_t *addr, uint16_t len);
 void ble_log_spi_out_dump_all(void);
+void ble_log_spi_out_enable(bool enable);
+void ble_log_spi_out_flush(void);
+void ble_log_spi_out_le_audio_write(const uint8_t *addr, uint16_t len);
 
 #endif // __BT_SPI_OUT_H__

components/bt/controller/esp32c2/bt.c

@@ -119,6 +119,11 @@ struct ext_funcs_t {
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
 /* External functions or variables
@@ -411,20 +416,22 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }

components/bt/controller/esp32c3/Kconfig.in

@@ -231,7 +231,7 @@ config BT_CTRL_DFT_TX_POWER_LEVEL_EFF
 
 config BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP
     bool "BLE adv report flow control supported"
-    depends on (!BT_CTRL_RUN_IN_FLASH_ONLY) || (BT_CTRL_RUN_IN_FLASH_ONLY && BT_CTRL_BLE_SCAN)
+    depends on BT_CTRL_BLE_SCAN
     default y
     help
         The function is mainly used to enable flow control for advertising reports. When it is enabled,
@@ -530,30 +530,31 @@ config BT_CTRL_RUN_IN_FLASH_ONLY
         impact on Bluetooth performance.
 
 config BT_CTRL_DTM_ENABLE
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
     bool "Enable direct test mode feature"
-    default n
-
-config BT_CTRL_BLE_MASTER
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
-    bool "Enable BLE master role feature"
     default y
 
+config BT_CTRL_BLE_MASTER
+    bool "Enable BLE connection feature"
+    default y
+    help
+        If this option is disabled, it is not recommended to use connectable ADV.
+
 config BT_CTRL_BLE_TEST
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
-    bool "Enable BLE QA test feature"
+    bool "Enable BLE QA test feature (Not Used)"
     default n
 
 config BT_CTRL_BLE_SCAN
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
     bool "Enable BLE scan feature"
     default y
 
 config BT_CTRL_BLE_SECURITY_ENABLE
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
     bool "Enable BLE security feature"
     default y
 
+config BT_CTRL_BLE_ADV
+    bool "Enable BLE ADV feature"
+    default y
+
 config BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
     bool "Enable enhanced Access Address check in CONNECT_IND"
     default n

components/bt/controller/esp32c3/bt.c

@@ -312,6 +312,17 @@ extern void advFilter_stack_enableDupExcListVsCmd(bool en);
 extern void chanSel_stack_enableSetCsaVsCmd(bool en);
 #endif // (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
 
+extern void ble_dtm_funcs_reset(void);
+extern void ble_scan_funcs_reset(void);
+extern void ble_42_adv_funcs_reset(void);
+extern void ble_init_funcs_reset(void);
+extern void ble_con_funcs_reset(void);
+extern void ble_cca_funcs_reset(void);
+extern void ble_ext_adv_funcs_reset(void);
+extern void ble_ext_scan_funcs_reset(void);
+extern void ble_base_funcs_reset(void);
+extern void ble_enc_funcs_reset(void);
+
 extern uint32_t _bt_bss_start;
 extern uint32_t _bt_bss_end;
 extern uint32_t _bt_controller_bss_start;
@@ -1265,6 +1276,46 @@ static void btdm_funcs_table_ready_wrapper(void)
 #if BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED
     btdm_aa_check_enhance_enable();
 #endif
+#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
+    // do nothing
+#else
+    ESP_LOGI(BT_LOG_TAG, "Feature Config, ADV:%d, BLE_50:%d, DTM:%d, SCAN:%d, CCA:%d, SMP:%d, CONNECT:%d",
+                        BT_CTRL_BLE_ADV, BT_CTRL_50_FEATURE_SUPPORT, BT_CTRL_DTM_ENABLE, BT_CTRL_BLE_SCAN,
+                        BT_BLE_CCA_MODE, BLE_SECURITY_ENABLE, BT_CTRL_BLE_MASTER);
+
+    ble_base_funcs_reset();
+#if CONFIG_BT_CTRL_BLE_ADV
+    ble_42_adv_funcs_reset();
+#if (BT_CTRL_50_FEATURE_SUPPORT == 1)
+    ble_ext_adv_funcs_reset();
+#endif //
+#endif // CONFIG_BT_CTRL_BLE_ADV
+
+#if CONFIG_BT_CTRL_DTM_ENABLE
+    ble_dtm_funcs_reset();
+#endif // CONFIG_BT_CTRL_DTM_ENABLE
+
+#if CONFIG_BT_CTRL_BLE_SCAN
+    ble_scan_funcs_reset();
+#if (BT_CTRL_50_FEATURE_SUPPORT == 1)
+    ble_ext_scan_funcs_reset();
+#endif // (BT_CTRL_50_FEATURE_SUPPORT == 1)
+#endif // CONFIG_BT_CTRL_BLE_SCAN
+
+#if (BT_BLE_CCA_MODE != 0)
+    ble_cca_funcs_reset();
+#endif // (BT_BLE_CCA_MODE != 0)
+
+#if CONFIG_BT_CTRL_BLE_SECURITY_ENABLE
+    ble_enc_funcs_reset();
+#endif // CONFIG_BT_CTRL_BLE_SECURITY_ENABLE
+
+#if CONFIG_BT_CTRL_BLE_MASTER
+    ble_init_funcs_reset();
+    ble_con_funcs_reset();
+#endif // CONFIG_BT_CTRL_BLE_MASTER
+
+#endif // CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
 }
 
 bool bt_async_wakeup_request(void)

components/bt/controller/esp32c5/Kconfig.in

@@ -805,3 +805,10 @@ config BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX
 config BT_LE_RXBUF_OPT_ENABLED
     bool "Enable rxbuf optimization feature"
     default y
+
+config BT_LE_CTRL_FAST_CONN_DATA_TX_EN
+    bool "Enable fast sending of connection data"
+    default y
+    help
+        If this option is enabled, The Controller will continue to
+        Send an empty PDU after sending valid connection data within an interval.

components/bt/controller/esp32c5/bt.c

@@ -67,7 +67,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20240422
+#define EXT_FUNC_VERSION             0x20250415
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -98,14 +98,17 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
-    void (* _esp_reset_rpa_moudle)(void);
     uint32_t magic;
 };
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
-#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
+#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 /* External functions or variables
  ************************************************************************
  */
@@ -182,7 +185,6 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
-static void esp_reset_rpa_moudle(void);
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -459,15 +461,9 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
-    ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
-static void IRAM_ATTR esp_reset_rpa_moudle(void)
-{
-
-}
-
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {
@@ -1419,20 +1415,22 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }

components/bt/controller/esp32c5/esp_bt_cfg.h

@@ -192,6 +192,12 @@ extern "C" {
 #define DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX (0)
 #endif
 
+#if defined(CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#else
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0)
+#endif
+
 #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #else

components/bt/controller/esp32c6/Kconfig.in

@@ -839,3 +839,10 @@ config BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX
 config BT_LE_RXBUF_OPT_ENABLED
     bool "Enable rxbuf optimization feature"
     default y
+
+config BT_LE_CTRL_FAST_CONN_DATA_TX_EN
+    bool "Enable fast sending of connection data"
+    default y
+    help
+        If this option is enabled, The Controller will continue to
+        Send an empty PDU after sending valid connection data within an interval.

components/bt/controller/esp32c6/bt.c

@@ -58,6 +58,7 @@
 
 #include "hal/efuse_hal.h"
 #include "soc/rtc.h"
+#include "modem/modem_syscon_struct.h"
 
 #if CONFIG_BT_BLE_LOG_SPI_OUT_ENABLED
 #include "ble_log/ble_log_spi_out.h"
@@ -70,7 +71,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20240422
+#define EXT_FUNC_VERSION             0x20250415
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -101,17 +102,29 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
-    void (* _esp_reset_rpa_moudle)(void);
+#if CONFIG_IDF_TARGET_ESP32C6
+    void (* _esp_reset_modem)(uint8_t mdl_opts, uint8_t start);
+#endif // CONFIG_IDF_TARGET_ESP32C6
     uint32_t magic;
 };
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
 /* External functions or variables
  ************************************************************************
  */
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+extern void coex_hw_timer_set(uint8_t idx,uint8_t src, uint8_t pti,uint32_t latency, uint32_t perioidc);
+extern void coex_hw_timer_enable(uint8_t idx);
+extern void coex_hw_timer_disable(uint8_t idx);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
 extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
 extern int r_ble_controller_init(esp_bt_controller_config_t *cfg);
 extern void esp_ble_controller_info_capture(uint32_t cycle_times);
@@ -185,7 +198,9 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
-static void esp_reset_rpa_moudle(void);
+#if CONFIG_IDF_TARGET_ESP32C6
+static void esp_reset_modem(uint8_t mdl_opts,uint8_t start);
+#endif // CONFIG_IDF_TARGET_ESP32C6
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -463,15 +478,34 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
-    ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
+#if CONFIG_IDF_TARGET_ESP32C6
+    ._esp_reset_modem = esp_reset_modem,
+#endif // CONFIG_IDF_TARGET_ESP32C6
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
-static void IRAM_ATTR esp_reset_rpa_moudle(void)
+#if CONFIG_IDF_TARGET_ESP32C6
+static void IRAM_ATTR esp_reset_modem(uint8_t mdl_opts,uint8_t start)
 {
+    if (mdl_opts == 0x05) {
+        if (start) {
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            coex_hw_timer_set(0x04, 0x02, 15, 0, 5000);
+            coex_hw_timer_enable(0x04);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            MODEM_SYSCON.modem_rst_conf.val |= (BIT(16) | BIT(18));
+            MODEM_SYSCON.modem_rst_conf.val &= ~(BIT(16) | BIT(18));
+        } else {
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            coex_hw_timer_disable(0x04);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+        }
 
+    }
 }
 
+#endif // CONFIG_IDF_TARGET_ESP32C6
+
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {
@@ -1452,20 +1486,22 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }

components/bt/controller/esp32c6/esp_bt_cfg.h

@@ -195,6 +195,12 @@ extern "C" {
 #define DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX (0)
 #endif
 
+#if defined(CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#else
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0)
+#endif
+
 #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #else

components/bt/controller/esp32h2/Kconfig.in

@@ -843,3 +843,10 @@ config BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX
 config BT_LE_RXBUF_OPT_ENABLED
     bool "Enable rxbuf optimization feature"
     default y
+
+config BT_LE_CTRL_FAST_CONN_DATA_TX_EN
+    bool "Enable fast sending of connection data"
+    default y
+    help
+        If this option is enabled, The Controller will continue to
+        Send an empty PDU after sending valid connection data within an interval.

components/bt/controller/esp32h2/bt.c

@@ -66,7 +66,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20240422
+#define EXT_FUNC_VERSION             0x20250415
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -97,12 +97,16 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
-    void (* _esp_reset_rpa_moudle)(void);
     uint32_t magic;
 };
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 /* External functions or variables
  ************************************************************************
@@ -183,7 +187,6 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
-static void esp_reset_rpa_moudle(void);
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -460,15 +463,9 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
-    ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
-static void IRAM_ATTR esp_reset_rpa_moudle(void)
-{
-
-}
-
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {
@@ -1412,20 +1409,22 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }

components/bt/controller/esp32h2/esp_bt_cfg.h

@@ -192,6 +192,12 @@ extern "C" {
 #define DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX (0)
 #endif
 
+#if defined(CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#else
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0)
+#endif
+
 #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #else

components/bt/esp_ble_mesh/core/ext_adv.c

@@ -303,6 +303,7 @@ static uint32_t received_adv_evts_handle(uint32_t recv_evts)
 CONFIG_BLE_MESH_GATT_PROXY_SERVER
             if (unlikely(i == BLE_MESH_ADV_PROXY_INS)) {
                 BT_DBG("Mesh Proxy Advertising auto stop");
+                bt_mesh_proxy_server_adv_flag_set(false);
             } else
 #endif
             {
@@ -366,7 +367,7 @@ void bt_mesh_adv_update(void)
 {
 #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_SERVER
-    BT_WARN("Mesh Proxy Advertising stopped manually");
+    BT_DBG("Mesh Proxy Advertising stopped manually");
     bt_mesh_proxy_server_adv_stop();
     if (adv_insts[BLE_MESH_ADV_PROXY_INS].busy) {
         ble_mesh_adv_task_wakeup(ADV_TASK_PROXY_ADV_UPD_EVT);

components/bt/esp_ble_mesh/core/proxy_server.c

@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -170,6 +170,11 @@ static void proxy_sar_timeout(struct k_work *work)
     bt_mesh_gatts_disconnect(client->conn, 0x13);
 }
 
+void bt_mesh_proxy_server_adv_flag_set(bool enable)
+{
+    proxy_adv_enabled = enable;
+}
+
 #if CONFIG_BLE_MESH_GATT_PROXY_SERVER
 /**
  * The following callbacks are used to notify proper information
@@ -853,7 +858,9 @@ static void proxy_connected(struct bt_mesh_conn *conn, uint8_t err)
     conn_count++;
 
     /* Since we use ADV_OPT_ONE_TIME */
-    proxy_adv_enabled = false;
+#if !CONFIG_BLE_MESH_USE_BLE_50
+    bt_mesh_proxy_server_adv_flag_set(false);
+#endif
 
 #if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX
     /* Before re-enabling advertising, stop advertising
@@ -1498,7 +1505,7 @@ static int node_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1529,7 +1536,7 @@ static int net_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1592,7 +1599,7 @@ static int private_node_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1636,7 +1643,7 @@ static int private_net_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1902,7 +1909,7 @@ int32_t bt_mesh_proxy_server_adv_start(void)
                             prov_sd, prov_sd_len) == 0) {
 #endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
-            proxy_adv_enabled = true;
+            bt_mesh_proxy_server_adv_flag_set(true);
 
             /* Advertise 60 seconds using fast interval */
             if (prov_fast_adv) {
@@ -1959,7 +1966,7 @@ int bt_mesh_proxy_server_adv_stop(void)
         return -EINVAL;
     }
 
-    proxy_adv_enabled = false;
+    bt_mesh_proxy_server_adv_flag_set(false);
     return 0;
 }
 
@@ -2022,7 +2029,7 @@ int bt_mesh_proxy_server_deinit(void)
     proxy_adv_inst = BLE_MESH_ADV_INS_UNUSED;
 #endif
 
-    proxy_adv_enabled = false;
+    bt_mesh_proxy_server_adv_flag_set(false);
     gatt_svc = MESH_GATT_NONE;
 
 #if CONFIG_BLE_MESH_GATT_PROXY_SERVER

components/bt/esp_ble_mesh/core/proxy_server.h

@@ -118,6 +118,7 @@ void bt_mesh_proxy_server_identity_stop(struct bt_mesh_subnet *sub);
 
 bool bt_mesh_proxy_server_relay(struct net_buf_simple *buf, uint16_t dst);
 void bt_mesh_proxy_server_addr_add(struct net_buf_simple *buf, uint16_t addr);
+void bt_mesh_proxy_server_adv_flag_set(bool enable);
 
 int bt_mesh_proxy_server_init(void);
 int bt_mesh_proxy_server_deinit(void);

components/bt/host/bluedroid/api/esp_gap_ble_api.c

@@ -300,83 +300,17 @@ esp_err_t esp_ble_gap_config_local_privacy (bool privacy_enable)
 
 esp_err_t esp_ble_gap_config_local_icon (uint16_t icon)
 {
-    esp_err_t ret;
     btc_msg_t msg = {0};
     btc_ble_gap_args_t arg;
 
     ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
 
-    switch (icon) {
-    case ESP_BLE_APPEARANCE_GENERIC_PHONE:
-    case ESP_BLE_APPEARANCE_GENERIC_COMPUTER:
-    case ESP_BLE_APPEARANCE_GENERIC_REMOTE:
-    case ESP_BLE_APPEARANCE_GENERIC_THERMOMETER:
-    case ESP_BLE_APPEARANCE_THERMOMETER_EAR:
-    case ESP_BLE_APPEARANCE_GENERIC_HEART_RATE:
-    case ESP_BLE_APPEARANCE_HEART_RATE_BELT:
-    case ESP_BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE:
-    case ESP_BLE_APPEARANCE_BLOOD_PRESSURE_ARM:
-    case ESP_BLE_APPEARANCE_BLOOD_PRESSURE_WRIST:
-    case ESP_BLE_APPEARANCE_GENERIC_PULSE_OXIMETER:
-    case ESP_BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP:
-    case ESP_BLE_APPEARANCE_PULSE_OXIMETER_WRIST:
-    case ESP_BLE_APPEARANCE_GENERIC_GLUCOSE:
-    case ESP_BLE_APPEARANCE_GENERIC_WEIGHT:
-    case ESP_BLE_APPEARANCE_GENERIC_WALKING:
-    case ESP_BLE_APPEARANCE_WALKING_IN_SHOE:
-    case ESP_BLE_APPEARANCE_WALKING_ON_SHOE:
-    case ESP_BLE_APPEARANCE_WALKING_ON_HIP:
-    case ESP_BLE_APPEARANCE_GENERIC_WATCH:
-    case ESP_BLE_APPEARANCE_SPORTS_WATCH:
-    case ESP_BLE_APPEARANCE_GENERIC_EYEGLASSES:
-    case ESP_BLE_APPEARANCE_GENERIC_DISPLAY:
-    case ESP_BLE_APPEARANCE_GENERIC_MEDIA_PLAYER:
-    case ESP_BLE_APPEARANCE_GENERIC_BARCODE_SCANNER:
-    case ESP_BLE_APPEARANCE_HID_BARCODE_SCANNER:
-    case ESP_BLE_APPEARANCE_GENERIC_HID:
-    case ESP_BLE_APPEARANCE_HID_KEYBOARD:
-    case ESP_BLE_APPEARANCE_HID_MOUSE:
-    case ESP_BLE_APPEARANCE_HID_JOYSTICK:
-    case ESP_BLE_APPEARANCE_HID_GAMEPAD:
-    case ESP_BLE_APPEARANCE_HID_DIGITIZER_TABLET:
-    case ESP_BLE_APPEARANCE_HID_CARD_READER:
-    case ESP_BLE_APPEARANCE_HID_DIGITAL_PEN:
-    case ESP_BLE_APPEARANCE_UNKNOWN:
-    case ESP_BLE_APPEARANCE_GENERIC_CLOCK:
-    case ESP_BLE_APPEARANCE_GENERIC_TAG:
-    case ESP_BLE_APPEARANCE_GENERIC_KEYRING:
-    case ESP_BLE_APPEARANCE_GENERIC_CYCLING:
-    case ESP_BLE_APPEARANCE_CYCLING_COMPUTER:
-    case ESP_BLE_APPEARANCE_CYCLING_SPEED:
-    case ESP_BLE_APPEARANCE_CYCLING_CADENCE:
-    case ESP_BLE_APPEARANCE_CYCLING_POWER:
-    case ESP_BLE_APPEARANCE_CYCLING_SPEED_CADENCE:
-    case ESP_BLE_APPEARANCE_GENERIC_PERSONAL_MOBILITY_DEVICE:
-    case ESP_BLE_APPEARANCE_POWERED_WHEELCHAIR:
-    case ESP_BLE_APPEARANCE_MOBILITY_SCOOTER:
-    case ESP_BLE_APPEARANCE_GENERIC_CONTINUOUS_GLUCOSE_MONITOR:
-    case ESP_BLE_APPEARANCE_GENERIC_INSULIN_PUMP:
-    case ESP_BLE_APPEARANCE_INSULIN_PUMP_DURABLE_PUMP:
-    case ESP_BLE_APPEARANCE_INSULIN_PUMP_PATCH_PUMP:
-    case ESP_BLE_APPEARANCE_INSULIN_PEN:
-    case ESP_BLE_APPEARANCE_GENERIC_MEDICATION_DELIVERY:
-    case ESP_BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS:
-    case ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION:
-    case ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_AND_NAV:
-    case ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_POD:
-    case ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_POD_AND_NAV:
-    case ESP_BLE_APPEARANCE_STANDALONE_SPEAKER:
-        msg.sig = BTC_SIG_API_CALL;
-        msg.pid = BTC_PID_GAP_BLE;
-        msg.act = BTC_GAP_BLE_ACT_CONFIG_LOCAL_ICON;
-        arg.cfg_local_icon.icon = icon;
-        ret = (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gap_args_t), NULL, NULL) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
-        break;
-    default:
-        ret = ESP_ERR_INVALID_ARG;
-        break;
-    }
-    return ret;
+    msg.sig = BTC_SIG_API_CALL;
+    msg.pid = BTC_PID_GAP_BLE;
+    msg.act = BTC_GAP_BLE_ACT_CONFIG_LOCAL_ICON;
+    arg.cfg_local_icon.icon = icon;
+
+    return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gap_args_t), NULL, NULL) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
 }
 
 esp_err_t esp_ble_gap_update_whitelist(bool add_remove, esp_bd_addr_t remote_bda, esp_ble_wl_addr_type_t wl_addr_type)

components/bt/host/bluedroid/api/esp_gatts_api.c

@@ -260,6 +260,11 @@ esp_err_t esp_ble_gatts_stop_service(uint16_t service_handle)
 esp_err_t esp_ble_gatts_send_indicate(esp_gatt_if_t gatts_if, uint16_t conn_id, uint16_t attr_handle,
                                       uint16_t value_len, uint8_t *value, bool need_confirm)
 {
+    if (value_len > ESP_GATT_MAX_ATTR_LEN) {
+        LOG_ERROR("%s, value_len > ESP_GATT_MAX_ATTR_LEN.", __func__);
+        return ESP_ERR_INVALID_SIZE;
+    }
+
     btc_msg_t msg = {0};
     btc_ble_gatts_args_t arg;
 
@@ -272,7 +277,7 @@ esp_err_t esp_ble_gatts_send_indicate(esp_gatt_if_t gatts_if, uint16_t conn_id,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 

components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h

@@ -2040,15 +2040,19 @@ esp_err_t esp_ble_gap_clear_rand_addr(void);
 esp_err_t esp_ble_gap_config_local_privacy (bool privacy_enable);
 
 /**
- * @brief           set local gap appearance icon
+ * @brief           Set the local GAP appearance icon.
  *
+ * @note            This API does not restrict the input icon value.
+ *                  If an undefined or incorrect icon value is used, the device icon may not display properly.
  *
- * @param[in]       icon   - External appearance value, these values are defined by the Bluetooth SIG, please refer to
+ *                  For a complete list of valid appearance values, please refer to "2.6.2 Appearance Category ranges" at:
  *                  https://www.bluetooth.com/specifications/assigned-numbers/
  *
+ * @param[in]       icon   - External appearance value (16-bit), as defined by the Bluetooth SIG.
+ *
  * @return
- *                  - ESP_OK : success
- *                  - other  : failed
+ *                  - ESP_OK   : Success
+ *                  - ESP_FAIL : Internal failure
  *
  */
 esp_err_t esp_ble_gap_config_local_icon (uint16_t icon);
@@ -2726,15 +2730,17 @@ esp_err_t esp_ble_gap_periodic_adv_stop(uint8_t instance);
 esp_err_t esp_ble_gap_set_ext_scan_params(const esp_ble_ext_scan_params_t *params);
 
 /**
-* @brief           This function is used to enable scanning.
+* @brief           Enables extended scanning.
 *
-* @param[in]       duration  Scan duration time, where Time = N * 10 ms. Range: 0x0001 to 0xFFFF.
-* @param[in]       period    Time interval from when the Controller started its last Scan Duration until it begins the subsequent Scan Duration.
-*                            Time = N * 1.28 sec. Range: 0x0001 to 0xFFFF.
+* @param[in]       duration  Scan duration in units of 10 ms.
+*                            - Range: 0x0001 to 0xFFFF (Time = N * 10 ms).
+*                            - 0x0000: Scan continuously until explicitly disabled.
 *
+* @param[in]       period    Time interval between the start of consecutive scan durations, in units of 1.28 seconds.
+*                            - Range: 0x0001 to 0xFFFF (Time = N * 1.28 sec).
+*                            - 0x0000: Scan continuously.
 * @return            - ESP_OK : success
 *                    - other  : failed
-*
 */
 esp_err_t esp_ble_gap_start_ext_scan(uint32_t duration, uint16_t period);
 

components/bt/host/bluedroid/api/include/api/esp_gatt_defs.h

@@ -478,7 +478,7 @@ typedef uint8_t esp_gatt_char_prop_t;
  *
  * This definition specifies the maximum number of bytes that a GATT attribute can hold.
  */
-#define ESP_GATT_MAX_ATTR_LEN   512 /*!< As same as GATT_MAX_ATTR_LEN. */
+#define ESP_GATT_MAX_ATTR_LEN   517 /*!< As same as GATT_MAX_ATTR_LEN. */
 
 /**
  * @brief Enumerates the possible sources of a GATT service discovery.

components/bt/host/bluedroid/common/include/common/bt_trace.h

@@ -223,12 +223,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 #if (BT_BLE_LOG_SPI_OUT_HOST_ENABLED && !CLASSIC_BT_INCLUDED)
 
 #define BTM_TRACE_ERROR(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_ERROR, "BT_BTM", fmt, ## args); \
     if (btm_cb.trace_level >= BT_TRACE_LEVEL_ERROR && BT_LOG_LEVEL_CHECK(BTM, ERROR)) BT_PRINT_E("BT_BTM", fmt, ## args); \
 }
 
 #define BTM_TRACE_WARNING(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_WARN, "BT_BTM", fmt, ## args); \
     if (btm_cb.trace_level >= BT_TRACE_LEVEL_WARNING && BT_LOG_LEVEL_CHECK(BTM, WARNING)) BT_PRINT_W("BT_BTM", fmt, ## args); \
 }
 
@@ -243,7 +241,6 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 }
 
 #define BTM_TRACE_DEBUG(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_BTM", fmt, ## args); \
     if (btm_cb.trace_level >= BT_TRACE_LEVEL_DEBUG && BT_LOG_LEVEL_CHECK(BTM, DEBUG)) BT_PRINT_D("BT_BTM", fmt, ## args); \
 }
 
@@ -262,12 +259,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 #if (BT_BLE_LOG_SPI_OUT_HOST_ENABLED && !CLASSIC_BT_INCLUDED)
 
 #define L2CAP_TRACE_ERROR(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_ERROR, "BT_L2CAP", fmt, ## args); \
     if (l2cb.l2cap_trace_level >= BT_TRACE_LEVEL_ERROR && BT_LOG_LEVEL_CHECK(L2CAP, ERROR)) BT_PRINT_E("BT_L2CAP", fmt, ## args); \
 }
 
 #define L2CAP_TRACE_WARNING(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_WARN, "BT_L2CAP", fmt, ## args); \
     if (l2cb.l2cap_trace_level >= BT_TRACE_LEVEL_WARNING && BT_LOG_LEVEL_CHECK(L2CAP, WARNING)) BT_PRINT_W("BT_L2CAP", fmt, ## args); \
 }
 
@@ -277,12 +272,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 }
 
 #define L2CAP_TRACE_EVENT(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_L2CAP", fmt, ## args); \
     if (l2cb.l2cap_trace_level >= BT_TRACE_LEVEL_EVENT && BT_LOG_LEVEL_CHECK(L2CAP, EVENT)) BT_PRINT_D("BT_L2CAP", fmt, ## args); \
 }
 
 #define L2CAP_TRACE_DEBUG(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_L2CAP", fmt, ## args); \
     if (l2cb.l2cap_trace_level >= BT_TRACE_LEVEL_DEBUG && BT_LOG_LEVEL_CHECK(L2CAP, DEBUG)) BT_PRINT_D("BT_L2CAP", fmt, ## args); \
 }
 
@@ -317,12 +310,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 #if (BT_BLE_LOG_SPI_OUT_HOST_ENABLED && !CLASSIC_BT_INCLUDED)
 
 #define GAP_TRACE_ERROR(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_ERROR, "BT_GAP", fmt, ## args); \
     if (gap_cb.trace_level >= BT_TRACE_LEVEL_ERROR && BT_LOG_LEVEL_CHECK(GAP, ERROR)) BT_PRINT_E("BT_GAP", fmt, ## args); \
 }
 
 #define GAP_TRACE_WARNING(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_WARN, "BT_GAP", fmt, ## args); \
     if (gap_cb.trace_level >= BT_TRACE_LEVEL_WARNING && BT_LOG_LEVEL_CHECK(GAP, WARNING)) BT_PRINT_W("BT_GAP", fmt, ## args); \
 }
 
@@ -332,7 +323,6 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 }
 
 #define GAP_TRACE_EVENT(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_GAP", fmt, ## args); \
     if (gap_cb.trace_level >= BT_TRACE_LEVEL_EVENT && BT_LOG_LEVEL_CHECK(GAP, EVENT)) BT_PRINT_D("BT_GAP", fmt, ## args); \
 }
 
@@ -450,12 +440,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 #if (BT_BLE_LOG_SPI_OUT_HOST_ENABLED && !CLASSIC_BT_INCLUDED)
 
 #define GATT_TRACE_ERROR(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_ERROR, "BT_GATT", fmt, ## args); \
     if (gatt_cb.trace_level >= BT_TRACE_LEVEL_ERROR && BT_LOG_LEVEL_CHECK(GATT, ERROR)) BT_PRINT_E("BT_GATT", fmt, ## args); \
 }
 
 #define GATT_TRACE_WARNING(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_WARN, "BT_GATT", fmt, ## args); \
     if (gatt_cb.trace_level >= BT_TRACE_LEVEL_WARNING && BT_LOG_LEVEL_CHECK(GATT, WARNING)) BT_PRINT_W("BT_GATT", fmt, ## args); \
 }
 
@@ -465,12 +453,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 }
 
 #define GATT_TRACE_EVENT(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_GATT", fmt, ## args); \
     if (gatt_cb.trace_level >= BT_TRACE_LEVEL_EVENT && BT_LOG_LEVEL_CHECK(GATT, EVENT)) BT_PRINT_D("BT_GATT", fmt, ## args); \
 }
 
 #define GATT_TRACE_DEBUG(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_GATT", fmt, ## args); \
     if (gatt_cb.trace_level >= BT_TRACE_LEVEL_DEBUG && BT_LOG_LEVEL_CHECK(GATT, DEBUG)) BT_PRINT_D("BT_GATT", fmt, ## args); \
 }
 
@@ -489,12 +475,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 #if (BT_BLE_LOG_SPI_OUT_HOST_ENABLED && !CLASSIC_BT_INCLUDED)
 
 #define SMP_TRACE_ERROR(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_ERROR, "BT_SMP", fmt, ## args); \
     if (smp_cb.trace_level >= BT_TRACE_LEVEL_ERROR && BT_LOG_LEVEL_CHECK(SMP, ERROR)) BT_PRINT_E("BT_SMP", fmt, ## args); \
 }
 
 #define SMP_TRACE_WARNING(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_WARN, "BT_SMP", fmt, ## args); \
     if (smp_cb.trace_level >= BT_TRACE_LEVEL_WARNING && BT_LOG_LEVEL_CHECK(SMP, WARNING)) BT_PRINT_W("BT_SMP", fmt, ## args); \
 }
 
@@ -504,12 +488,10 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 }
 
 #define SMP_TRACE_EVENT(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_SMP", fmt, ## args); \
     if (smp_cb.trace_level >= BT_TRACE_LEVEL_EVENT && BT_LOG_LEVEL_CHECK(SMP, EVENT)) BT_PRINT_D("BT_SMP", fmt, ## args); \
 }
 
 #define SMP_TRACE_DEBUG(fmt, args...) { \
-    ble_log_spi_out_printf_enh(BLE_LOG_SPI_OUT_SOURCE_BLUEDROID, BLE_LOG_SPI_OUT_LEVEL_DEBUG, "BT_SMP", fmt, ## args); \
     if (smp_cb.trace_level >= BT_TRACE_LEVEL_DEBUG && BT_LOG_LEVEL_CHECK(SMP, DEBUG)) BT_PRINT_D("BT_SMP", fmt, ## args); \
 }
 

components/bt/host/bluedroid/stack/include/stack/gatt_api.h

@@ -139,7 +139,7 @@ typedef UINT16 tGATT_DISCONN_REASON;
 /* max length of an attribute value
 */
 #ifndef GATT_MAX_ATTR_LEN
-#define GATT_MAX_ATTR_LEN                   512
+#define GATT_MAX_ATTR_LEN                   GATT_MAX_MTU_SIZE
 #endif
 
 /* default GATT MTU size over LE link

components/bt/host/nimble/Kconfig.in

@@ -156,7 +156,7 @@ config BT_NIMBLE_ROLE_BROADCASTER
     depends on BT_NIMBLE_ENABLED
     default y
     help
-                Enables broadcaster role
+            Enables broadcaster role
 
 config BT_NIMBLE_ROLE_OBSERVER
     bool "Enable BLE Observer role"
@@ -165,6 +165,20 @@ config BT_NIMBLE_ROLE_OBSERVER
     help
             Enables observer role
 
+config BT_NIMBLE_GATT_CLIENT
+    bool "Enable BLE GATT Client support"
+    depends on BT_NIMBLE_ROLE_CENTRAL
+    default y
+    help
+            Enables support for GATT Client
+
+config BT_NIMBLE_GATT_SERVER
+    bool "Enable BLE GATT Server support"
+    depends on BT_NIMBLE_ROLE_PERIPHERAL
+    default y
+    help
+            Enables support for GATT Server
+
 config BT_NIMBLE_NVS_PERSIST
     bool "Persist the BLE Bonding keys in NVS"
     depends on BT_NIMBLE_ENABLED
@@ -237,6 +251,13 @@ config BT_NIMBLE_SM_SC_ONLY
     help
         Enable Secure Connections Only Mode
 
+config BT_NIMBLE_PRINT_ERR_NAME
+    bool "Enable feature to print Error description"
+    depends on BT_NIMBLE_ENABLED
+    default y
+    help
+        Enable feature to give useful explanation for HCI errors
+
 config BT_NIMBLE_DEBUG
     bool "Enable extra runtime asserts and host debugging"
     default n
@@ -274,6 +295,13 @@ config BT_NIMBLE_ATT_PREFERRED_MTU
         This is the default value of ATT MTU indicated by the device during an ATT MTU exchange.
         This value can be changed using API ble_att_set_preferred_mtu()
 
+config BT_NIMBLE_ATT_MAX_PREP_ENTRIES
+    int "Max Prepare write entries"
+    depends on BT_NIMBLE_ENABLED
+    default 64
+    help
+        This is the default value of ATT Maximum prepare entries
+
 config BT_NIMBLE_SVC_GAP_APPEARANCE
     hex "External appearance of the device"
     depends on BT_NIMBLE_ENABLED
@@ -384,7 +412,7 @@ config BT_NIMBLE_GATT_MAX_PROCS
 
 config BT_NIMBLE_HS_FLOW_CTRL
     bool "Enable Host Flow control"
-    depends on BT_NIMBLE_ENABLED
+    depends on BT_NIMBLE_ENABLED && !SOC_ESP_NIMBLE_CONTROLLER
     default y if IDF_TARGET_ESP32
     default n
     help
@@ -600,6 +628,13 @@ if BT_NIMBLE_50_FEATURE_SUPPORT
             will be supported from BLE 5.0 onwards.
 
     if BT_NIMBLE_EXT_ADV
+        config BT_NIMBLE_EXT_ADV_V2
+            bool "Enable support for extended adv v2"
+            default n
+            depends on BT_NIMBLE_EXT_ADV
+            help
+                Enable this option to use Extended Adv V2 command instead of V1.
+
         config BT_NIMBLE_MAX_EXT_ADV_INSTANCES
             int "Maximum number of extended advertising instances."
             range 0 4
@@ -708,6 +743,19 @@ menuconfig BT_NIMBLE_GATT_CACHING
     select BT_NIMBLE_DYNAMIC_SERVICE
     help
         Enable GATT caching
+config BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES
+    bool "Include services in GATT caching"
+    depends on BT_NIMBLE_GATT_CACHING
+    default n
+    help
+        Enable this option to include *included services* (e.g., services referenced by other services)
+        in the GATT database cache. Disabling this will skip caching of included service entries.
+config BT_NIMBLE_INCL_SVC_DISCOVERY
+    bool "Enable Included service discovery"
+    default y if BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES
+    default n
+    help
+        Enable this option to start discovery for included service.
 config BT_NIMBLE_GATT_CACHING_MAX_CONNS
     int "Maximum connections to be cached"
     depends on BT_NIMBLE_GATT_CACHING
@@ -720,6 +768,12 @@ config BT_NIMBLE_GATT_CACHING_MAX_SVCS
     default 64
     help
         Set this option to set the upper limit on number of services per connection to be cached.
+config BT_NIMBLE_GATT_CACHING_MAX_INCL_SVCS
+    int "Maximum number of included services per connection"
+    depends on BT_NIMBLE_GATT_CACHING
+    default 64
+    help
+        Set this option to set the upper limit on number of included services per connection to be cached.
 config BT_NIMBLE_GATT_CACHING_MAX_CHRS
     int "Maximum number of characteristics per connection"
     depends on BT_NIMBLE_GATT_CACHING
@@ -781,8 +835,172 @@ config BT_NIMBLE_BLE_GATT_BLOB_TRANSFER
         This option is used when data to be sent is more than 512 bytes. For peripheral role,
         BT_NIMBLE_MSYS_1_BLOCK_COUNT needs to be increased according to the need.
 
-menu "GAP Service"
+menu "BLE Services"
+    depends on BT_NIMBLE_GATT_SERVER
+
+    config BT_NIMBLE_PROX_SERVICE
+        bool "Proximity service"
+        default y
+        help
+            Enable Proximity Service support
+
+    config BT_NIMBLE_ANS_SERVICE
+        bool "Alert Notification service"
+        default y
+        help
+            Enable Alert Notification Service support
+
+    config BT_NIMBLE_CTS_SERVICE
+        bool "Current Time Service"
+        default y
+        help
+            Enable Current Time Service support
+
+    config BT_NIMBLE_HTP_SERVICE
+        bool "Health Thermometer service"
+        default y
+        help
+            Enable Health Thermometer Service support
+
+    config BT_NIMBLE_IPSS_SERVICE
+        bool "Internet Protocol Support service"
+        default y
+        help
+            Enable Internet Protocol Service support
+
+    config BT_NIMBLE_TPS_SERVICE
+        bool "Tx Power service"
+        default y
+        help
+            Enable Tx Power Service support
+
+    config BT_NIMBLE_IAS_SERVICE
+        bool "Immediate Alert service"
+        default y
+        help
+            Enable Immediate Alert Service support
+
+    config BT_NIMBLE_LLS_SERVICE
+        bool "Link Loss service"
+        default y
+        help
+            Enable Link Loss Service support
+
+    config BT_NIMBLE_SPS_SERVICE
+        bool "Serial Port service"
+        default y
+        help
+            Enable Serial Port Service support
+
+    config BT_NIMBLE_HR_SERVICE
+        bool "Heart Rate service"
+        default y
+        help
+            Enable HeartRate Service support
+
+    menuconfig BT_NIMBLE_HID_SERVICE
+        bool "HID service"
+        default n
+        help
+            Enable HID service support
+
+    config BT_NIMBLE_SVC_HID_MAX_INSTANCES
+        depends on BT_NIMBLE_HID_SERVICE
+        int "Maximum HID service instances"
+        default 2
+        help
+            Defines maximum number of HID service instances
+
+    config BT_NIMBLE_SVC_HID_MAX_RPTS
+        depends on BT_NIMBLE_HID_SERVICE
+        int "Maximum HID Report characteristics per service instance"
+        default 3
+        help
+            Defines maximum number of report characteristics per service instance
+
+    menuconfig BT_NIMBLE_BAS_SERVICE
+        bool "Battery service"
+        default y
+        help
+            Enable Battery service support
+
+    config BT_NIMBLE_SVC_BAS_BATTERY_LEVEL_NOTIFY
+        depends on BT_NIMBLE_BAS_SERVICE
+        bool "BAS Battery Level NOTIFY permission"
+        help
+            Enable/Disable notifications on BAS Battery Level Characteristic
+
+    menuconfig BT_NIMBLE_DIS_SERVICE
+        bool "DIS service"
+        default y
+        help
+            Enable DIS service support
+
+    config BT_NIMBLE_SVC_DIS_MANUFACTURER_NAME
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "Manufacturer Name"
+        default n
+        help
+                Enable the DIS characteristic Manufacturer Name String characteristic
+
+    config BT_NIMBLE_SVC_DIS_SERIAL_NUMBER
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "Serial Number"
+        default n
+        help
+                Enable the DIS Serial Number characteristic
+
+    config BT_NIMBLE_SVC_DIS_HARDWARE_REVISION
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "Hardware Revision"
+        default n
+        help
+                Enable the DIS Hardware Revision characteristic
+
+    config BT_NIMBLE_SVC_DIS_FIRMWARE_REVISION
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "Firmware Revision"
+        default n
+        help
+                Enable the DIS Firmware Revision characteristic
+
+    config BT_NIMBLE_SVC_DIS_SOFTWARE_REVISION
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "Software Revision"
+        default n
+        help
+                Enable the DIS Software Revision characteristic
+
+    config BT_NIMBLE_SVC_DIS_SYSTEM_ID
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "System ID"
+        default n
+        help
+                Enable the DIS System ID characteristic
+
+    config BT_NIMBLE_SVC_DIS_PNP_ID
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "PnP ID"
+        default n
+        help
+                Enable the DIS PnP ID characteristic
+
+    config BT_NIMBLE_SVC_DIS_INCLUDED
+        depends on BT_NIMBLE_DIS_SERVICE
+        bool "DIS as an Included Service"
+        default n
+        help
+                Use DIS as an included service
+
+    menuconfig BT_NIMBLE_GAP_SERVICE
+        bool "GAP Service"
+        default y
+        help
+            Enable GAP Service support
+
     menu "GAP Appearance write permissions"
+        depends on BT_NIMBLE_GAP_SERVICE
+
         config BT_NIMBLE_SVC_GAP_APPEAR_WRITE
             bool "Write"
             default n
@@ -792,14 +1010,12 @@ menu "GAP Service"
         config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC
             depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE
             bool "Write with encryption"
-            default n
             help
                 Enable write with encryption permission (BLE_GATT_CHR_F_WRITE_ENC)
 
         config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN
             depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE
             bool "Write with authentication"
-            default n
             help
                 Enable write with authentication permission (BLE_GATT_CHR_F_WRITE_AUTHEN)
 
@@ -809,48 +1025,49 @@ menu "GAP Service"
             default n
             help
                 Enable write with authorisation permission (BLE_GATT_CHR_F_WRITE_AUTHOR)
+
+        config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM
+            int
+            default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE
+            default 8 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE
+
+        config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ENC
+            int
+            default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC
+            default 4096 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC
+
+        config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHN
+            int
+            default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN
+            default 8192 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN
+
+        config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHR
+            int
+            default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR
+            default 16384 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR
     endmenu
 
-    config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM
-        int
-        default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE
-        default 8 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE
-
-    config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ENC
-        int
-        default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC
-        default 4096 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC
-
-    config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHN
-        int
-        default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN
-        default 8192 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN
-
-    config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHR
-        int
-        default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR
-        default 16384 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR
-
     choice BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION
         prompt "GAP Characteristic - Central Address Resolution"
+        depends on BT_NIMBLE_GAP_SERVICE
         default BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP
         help
-            Weather or not Central Address Resolution characteristic is supported on
-            the device, and if supported, weather or not Central Address Resolution
-            is supported.
+                Weather or not Central Address Resolution characteristic is supported on
+                the device, and if supported, weather or not Central Address Resolution
+                is supported.
 
-            - Central Address Resolution characteristic not supported
-            - Central Address Resolution not supported
-            - Central Address Resolution supported
+                - Central Address Resolution characteristic not supported
+                - Central Address Resolution not supported
+                - Central Address Resolution supported
 
-        config BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP
-            bool "Characteristic not supported"
+            config BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP
+                bool "Characteristic not supported"
 
-        config BT_NIMBLE_SVC_GAP_CAR_NOT_SUPP
-            bool "Central Address Resolution not supported"
+            config BT_NIMBLE_SVC_GAP_CAR_NOT_SUPP
+                bool "Central Address Resolution not supported"
 
-        config BT_NIMBLE_SVC_GAP_CAR_SUPP
-            bool "Central Address Resolution supported"
+            config BT_NIMBLE_SVC_GAP_CAR_SUPP
+                bool "Central Address Resolution supported"
     endchoice
 
     config BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION
@@ -859,7 +1076,9 @@ menu "GAP Service"
         default 0 if BT_NIMBLE_SVC_GAP_CAR_NOT_SUPP
         default 1 if BT_NIMBLE_SVC_GAP_CAR_SUPP
 
+
     menu "GAP device name write permissions"
+        depends on BT_NIMBLE_GAP_SERVICE
         config BT_NIMBLE_SVC_GAP_NAME_WRITE
             bool "Write"
             default n
@@ -888,6 +1107,40 @@ menu "GAP Service"
                 Enable write with authorisation permission (BLE_GATT_CHR_F_WRITE_AUTHOR)
     endmenu
 
+    menu "PPCP settings"
+        depends on BT_NIMBLE_GAP_SERVICE
+        config BT_NIMBLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL
+            int "PPCP Connection Interval Max (Unit: 1.25 ms)"
+            depends on BT_NIMBLE_ROLE_PERIPHERAL && BT_NIMBLE_GAP_SERVICE
+            default 0
+            help
+                Peripheral Preferred Connection Parameter: Connection Interval maximum value
+                Interval Max = value * 1.25 ms
+
+        config BT_NIMBLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL
+            int "PPCP Connection Interval Min (Unit: 1.25 ms)"
+            depends on BT_NIMBLE_ROLE_PERIPHERAL && BT_NIMBLE_GAP_SERVICE
+            default 0
+            help
+                Peripheral Preferred Connection Parameter: Connection Interval minimum value
+                Interval Min = value * 1.25 ms
+
+        config BT_NIMBLE_SVC_GAP_PPCP_SLAVE_LATENCY
+            int "PPCP Slave Latency"
+            depends on BT_NIMBLE_GAP_SERVICE
+            default 0
+            help
+                Peripheral Preferred Connection Parameter: Slave Latency
+
+        config BT_NIMBLE_SVC_GAP_PPCP_SUPERVISION_TMO
+            int "PPCP Supervision Timeout (Uint: 10 ms)"
+            depends on BT_NIMBLE_GAP_SERVICE
+            default 0
+            help
+                Peripheral Preferred Connection Parameter: Supervision Timeout
+                Timeout = Value * 10 ms
+    endmenu
+
     config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM
         int
         default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE
@@ -908,35 +1161,6 @@ menu "GAP Service"
         default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR
         default 16384 if BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR
 
-    config BT_NIMBLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL
-        int "PPCP Connection Interval Max (Unit: 1.25 ms)"
-        depends on BT_NIMBLE_ROLE_PERIPHERAL
-        default 0
-        help
-            Peripheral Preferred Connection Parameter: Connection Interval maximum value
-            Interval Max = value * 1.25 ms
-
-    config BT_NIMBLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL
-        int "PPCP Connection Interval Min (Unit: 1.25 ms)"
-        depends on BT_NIMBLE_ROLE_PERIPHERAL
-        default 0
-        help
-            Peripheral Preferred Connection Parameter: Connection Interval minimum value
-            Interval Min = value * 1.25 ms
-
-    config BT_NIMBLE_SVC_GAP_PPCP_SLAVE_LATENCY
-        int "PPCP Slave Latency"
-        default 0
-        help
-            Peripheral Preferred Connection Parameter: Slave Latency
-
-    config BT_NIMBLE_SVC_GAP_PPCP_SUPERVISION_TMO
-        int "PPCP Supervision Timeout (Uint: 10 ms)"
-        default 0
-        help
-            Peripheral Preferred Connection Parameter: Supervision Timeout
-            Timeout = Value * 10 ms
-
     config BT_NIMBLE_SVC_GAP_GATT_SECURITY_LEVEL
         bool "LE GATT Security Level Characteristic"
         default n
@@ -951,94 +1175,6 @@ menu "GAP Service"
 
 endmenu
 
-menu "BLE Services"
-    menuconfig BT_NIMBLE_HID_SERVICE
-        bool "HID service"
-        depends on BT_NIMBLE_ENABLED
-        default n
-        help
-            Enable HID service support
-
-    config BT_NIMBLE_SVC_HID_MAX_INSTANCES
-        depends on BT_NIMBLE_HID_SERVICE
-        int "Maximum HID service instances"
-        default 2
-        help
-            Defines maximum number of HID service instances
-
-    config BT_NIMBLE_SVC_HID_MAX_RPTS
-        depends on BT_NIMBLE_HID_SERVICE
-        int "Maximum HID Report characteristics per service instance"
-        default 3
-        help
-            Defines maximum number of report characteristics per service instance
-
-    config BT_NIMBLE_SVC_BAS_BATTERY_LEVEL_NOTIFY
-        depends on BT_NIMBLE_ENABLED
-        bool "BAS Battery Level NOTIFY permission"
-        default n
-        help
-            Enable/Disable notifications on BAS Battery Level Characteristic
-
-    menu "Device Information Service"
-        config BT_NIMBLE_SVC_DIS_MANUFACTURER_NAME
-            depends on BT_NIMBLE_ENABLED
-            bool "Manufacturer Name"
-            default n
-            help
-                Enable the DIS characteristic Manufacturer Name String characteristic
-
-        config BT_NIMBLE_SVC_DIS_SERIAL_NUMBER
-            depends on BT_NIMBLE_ENABLED
-            bool "Serial Number"
-            default n
-            help
-                Enable the DIS Serial Number characteristic
-
-        config BT_NIMBLE_SVC_DIS_HARDWARE_REVISION
-            depends on BT_NIMBLE_ENABLED
-            bool "Hardware Revision"
-            default n
-            help
-                Enable the DIS Hardware Revision characteristic
-
-        config BT_NIMBLE_SVC_DIS_FIRMWARE_REVISION
-            depends on BT_NIMBLE_ENABLED
-            bool "Firmware Revision"
-            default n
-            help
-                Enable the DIS Firmware Revision characteristic
-
-        config BT_NIMBLE_SVC_DIS_SOFTWARE_REVISION
-            depends on BT_NIMBLE_ENABLED
-            bool "Software Revision"
-            default n
-            help
-                Enable the DIS Software Revision characteristic
-
-        config BT_NIMBLE_SVC_DIS_SYSTEM_ID
-            depends on BT_NIMBLE_ENABLED
-            bool "System ID"
-            default n
-            help
-                Enable the DIS System ID characteristic
-
-        config BT_NIMBLE_SVC_DIS_PNP_ID
-            depends on BT_NIMBLE_ENABLED
-            bool "PnP ID"
-            default n
-            help
-                Enable the DIS PnP ID characteristic
-
-        config BT_NIMBLE_SVC_DIS_INCLUDED
-            depends on BT_NIMBLE_ENABLED
-            bool "DIS as an Included Service"
-            default n
-            help
-                Use DIS as an included service
-    endmenu
-endmenu
-
 config BT_NIMBLE_VS_SUPPORT
     bool "Enable support for VSC and VSE"
     help
@@ -1075,8 +1211,7 @@ config BT_NIMBLE_HIGH_DUTY_ADV_ITVL
 
 config BT_NIMBLE_HOST_ALLOW_CONNECT_WITH_SCAN
     bool "Allow Connections with scanning in progress"
-    depends on BT_NIMBLE_ENABLED
-    depends on (!SOC_ESP_NIMBLE_CONTROLLER || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2)
+    depends on BT_NIMBLE_ENABLED && !(IDF_TARGET_ESP32C2)
     help
         This enables support for user to initiate a new connection with scan in progress
 

components/bt/host/nimble/port/include/esp_nimble_cfg.h

@@ -98,6 +98,14 @@
 #define MYNEWT_VAL_BLE_EXT_ADV (CONFIG_BT_NIMBLE_EXT_ADV)
 #endif
 
+#ifndef MYNEWT_VAL_BLE_EXT_ADV_V2
+#ifdef CONFIG_BT_NIMBLE_EXT_ADV_V2
+#define MYNEWT_VAL_BLE_EXT_ADV_V2  (CONFIG_BT_NIMBLE_EXT_ADV_V2)
+#else
+#define MYNEWT_VAL_BLE_EXT_ADV_V2  (0)
+#endif
+#endif
+
 #ifndef CONFIG_BT_NIMBLE_EXT_ADV_MAX_SIZE
 #define MYNEWT_VAL_BLE_EXT_ADV_MAX_SIZE (31)
 #else
@@ -129,11 +137,27 @@
 #define MYNEWT_VAL_BLE_MAX_PERIODIC_ADVERTISER_LIST (CONFIG_BT_NIMBLE_MAX_PERIODIC_ADVERTISER_LIST)
 #endif
 
+#ifndef MYNEWT_VAL_BLE_INCL_SVC_DISCOVERY
+#ifdef CONFIG_BT_NIMBLE_INCL_SVC_DISCOVERY
+#define MYNEWT_VAL_BLE_INCL_SVC_DISCOVERY (CONFIG_BT_NIMBLE_INCL_SVC_DISCOVERY)
+#else
+#define MYNEWT_VAL_BLE_INCL_SVC_DISCOVERY (0)
+#endif
+#endif
+
 #ifndef CONFIG_BT_NIMBLE_GATT_CACHING
 #define MYNEWT_VAL_BLE_GATT_CACHING (0)
 #else
 #define MYNEWT_VAL_BLE_GATT_CACHING           (CONFIG_BT_NIMBLE_GATT_CACHING)
 
+#ifndef MYNEWT_VAL_BLE_GATT_CACHING_INCLUDE_SERVICES
+#ifdef CONFIG_BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES
+#define MYNEWT_VAL_BLE_GATT_CACHING_INCLUDE_SERVICES (CONFIG_BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES)
+#else
+#define MYNEWT_VAL_BLE_GATT_CACHING_INCLUDE_SERVICES (0)
+#endif
+#endif
+
 #ifdef CONFIG_BT_NIMBLE_GATT_CACHING_MAX_CONNS
 #define MYNEWT_VAL_BLE_GATT_CACHING_MAX_CONNS (CONFIG_BT_NIMBLE_GATT_CACHING_MAX_CONNS)
 #else
@@ -146,6 +170,14 @@
 #define MYNEWT_VAL_BLE_GATT_CACHING_MAX_SVCS  (0)
 #endif
 
+#ifndef MYNEWT_VAL_BLE_GATT_CACHING_MAX_INCL_SVCS
+#ifdef CONFIG_BT_NIMBLE_GATT_CACHING_MAX_INCL_SVCS
+#define MYNEWT_VAL_BLE_GATT_CACHING_MAX_INCL_SVCS  (CONFIG_BT_NIMBLE_GATT_CACHING_MAX_INCL_SVCS)
+#else
+#define MYNEWT_VAL_BLE_GATT_CACHING_MAX_INCL_SVCS  (0)
+#endif
+#endif
+
 #ifdef CONFIG_BT_NIMBLE_GATT_CACHING_MAX_CHRS
 #define MYNEWT_VAL_BLE_GATT_CACHING_MAX_CHRS  (CONFIG_BT_NIMBLE_GATT_CACHING_MAX_CHRS)
 #else
@@ -212,6 +244,18 @@
 #define MYNEWT_VAL_BLE_ROLE_PERIPHERAL (CONFIG_BT_NIMBLE_ROLE_PERIPHERAL)
 #endif
 
+#ifndef CONFIG_BT_NIMBLE_GATT_CLIENT
+#define MYNEWT_VAL_BLE_GATTC     (0)
+#else
+#define MYNEWT_VAL_BLE_GATTC     (CONFIG_BT_NIMBLE_GATT_CLIENT)
+#endif
+
+#ifndef CONFIG_BT_NIMBLE_GATT_SERVER
+#define MYNEWT_VAL_BLE_GATTS     (0)
+#else
+#define MYNEWT_VAL_BLE_GATTS     (CONFIG_BT_NIMBLE_GATT_SERVER)
+#endif
+
 #ifndef MYNEWT_VAL_BLE_WHITELIST
 #define MYNEWT_VAL_BLE_WHITELIST (1)
 #endif
@@ -552,7 +596,7 @@
 #endif
 
 #ifndef MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES
-#define MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES (64)
+#define MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES CONFIG_BT_NIMBLE_ATT_MAX_PREP_ENTRIES
 #endif
 
 #ifndef MYNEWT_VAL_BLE_ATT_SVR_NOTIFY
@@ -2032,4 +2076,16 @@
 #endif
 #endif
 
+#ifndef MYNEWT_VAL_BLE_ERR_CHECK
+#ifdef CONFIG_BT_NIMBLE_PRINT_ERR_NAME
+#define MYNEWT_VAL_BLE_ERR_CHECK CONFIG_BT_NIMBLE_PRINT_ERR_NAME
+#else
+#define MYNEWT_VAL_BLE_ERR_CHECK (0)
+#endif
+#endif
+
+#ifndef MYNEWT_VAL_BLE_USED_IN_IDF
+#define MYNEWT_VAL_BLE_USED_IN_IDF (1)
+#endif
+
 #endif

components/bt/include/esp32c3/include/esp_bt.h

@@ -30,7 +30,7 @@ extern "C" {
 *
 * @note Please do not modify this value
 */
-#define ESP_BT_CTRL_CONFIG_VERSION      0x02502230
+#define ESP_BT_CTRL_CONFIG_VERSION      0x02505080
 
 /**
 * @brief Internal use only
@@ -268,7 +268,7 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
 #define BT_CTRL_RUN_IN_FLASH_ONLY  (0)
 #endif
 
-#if (BT_CTRL_RUN_IN_FLASH_ONLY == 1)
+
 
 #if defined(CONFIG_BT_CTRL_DTM_ENABLE)
 #define BT_CTRL_DTM_ENABLE  CONFIG_BT_CTRL_DTM_ENABLE
@@ -288,20 +288,11 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
 #define BT_CTRL_BLE_TEST  (0)
 #endif
 
-#if defined (CONFIG_BT_NIMBLE_SECURITY_ENABLE) || defined (CONFIG_BT_BLE_SMP_ENABLE)
-#ifdef CONFIG_BT_NIMBLE_SECURITY_ENABLE
-#define BLE_SECURITY_ENABLE  (CONFIG_BT_NIMBLE_SECURITY_ENABLE)
-#endif //CONFIG_BT_NIMBLE_SECURITY_ENABLE
-#ifdef CONFIG_BT_BLE_SMP_ENABLE
-#define BLE_SECURITY_ENABLE  (CONFIG_BT_BLE_SMP_ENABLE)
-#endif //CONFIG_BT_BLE_SMP_ENABLE
-#else
 #if defined (CONFIG_BT_CTRL_BLE_SECURITY_ENABLE)
 #define BLE_SECURITY_ENABLE  (CONFIG_BT_CTRL_BLE_SECURITY_ENABLE)
 #else
 #define BLE_SECURITY_ENABLE  (0)
 #endif
-#endif // (CONFIG_BT_NIMBLE_SECURITY_ENABLE) || (CONFIG_BT_BLE_SMP_ENABLE)
 
 #if defined (CONFIG_BT_CTRL_BLE_SCAN)
 #define BT_CTRL_BLE_SCAN    CONFIG_BT_CTRL_BLE_SCAN
@@ -309,13 +300,11 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
 #define BT_CTRL_BLE_SCAN    (0)
 #endif
 
+#if defined (CONFIG_BT_CTRL_BLE_ADV)
+#define BT_CTRL_BLE_ADV    CONFIG_BT_CTRL_BLE_ADV
 #else
-#define BT_CTRL_BLE_MASTER   (1)
-#define BT_CTRL_DTM_ENABLE   (1)
-#define BT_CTRL_BLE_TEST     (1)
-#define BLE_SECURITY_ENABLE  (1)
-#define BT_CTRL_BLE_SCAN     (1)
-#endif // (BT_CTRL_RUN_IN_FLASH_ONLY == 1)
+#define BT_CTRL_BLE_ADV    (0)
+#endif
 
 #ifdef CONFIG_BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
 #define BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED CONFIG_BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
@@ -384,11 +373,12 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
     .dtm_en = BT_CTRL_DTM_ENABLE,                                          \
     .enc_en = BLE_SECURITY_ENABLE,                                         \
     .qa_test = BT_CTRL_BLE_TEST,                                           \
-    .master_en = BT_CTRL_BLE_MASTER,                                       \
+    .connect_en = BT_CTRL_BLE_MASTER,                                      \
     .scan_en = BT_CTRL_BLE_SCAN,                                           \
     .ble_aa_check = BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED,     \
     .ble_log_mode_en = BLE_LOG_MODE_EN,                                    \
     .ble_log_level = BLE_LOG_LEVEL,                                        \
+    .adv_en = BT_CTRL_BLE_ADV,                                             \
 }
 
 #else
@@ -508,14 +498,15 @@ typedef struct {
     uint8_t ble_llcp_disc_flag;             /*!< Flag indicating whether the Controller disconnects after Instant Passed (0x28) error occurs. Configurable in menuconfig.
                                                 - The Controller does not disconnect after Instant Passed (0x28) by default. */
     bool run_in_flash;                      /*!< True if the Controller code is in flash (flash model); false otherwise (default). Configurable in menuconfig. */
-    bool dtm_en;                            /*!< In the flash mode, True if the DTM feature is enabled; false otherwise (default). Configurable in menuconfig. */
-    bool enc_en;                            /*!< In the flash mode, True if the encryption feature is enabled (default); false otherwise. Configurable in menuconfig. */
-    bool qa_test;                           /*!< In the flash mode, True if the QA test feature is enabled; false otherwise (default). Configurable in menuconfig.*/
-    bool master_en;                         /*!< In the flash mode, True if the master feature is enabled (default); false otherwise. Configurable in menuconfig.*/
-    bool scan_en;                           /*!< In the flash mode, True if the scan feature is enabled (default); false otherwise. Configurable in menuconfig.*/
+    bool dtm_en;                            /*!< True if the DTM feature is enabled; false otherwise (default). Configurable in menuconfig. */
+    bool enc_en;                            /*!< True if the encryption feature is enabled (default); false otherwise. Configurable in menuconfig. */
+    bool qa_test;                           /*!< True if the QA test feature is enabled; false otherwise (default). Configurable in menuconfig.*/
+    bool connect_en;                        /*!< True if the connection feature is enabled (default); false otherwise. Configurable in menuconfig.*/
+    bool scan_en;                           /*!< True if the scan feature is enabled (default); false otherwise. Configurable in menuconfig.*/
     bool ble_aa_check;                      /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */
     uint32_t ble_log_mode_en;               /*!< BLE log mode enable */
     uint8_t ble_log_level;                  /*!< BLE log level */
+    bool adv_en;                            /*!< True if the ADV feature is enabled (default); false otherwise. Configurable in menuconfig.*/
 } esp_bt_controller_config_t;
 
 /**

components/bt/include/esp32c5/include/esp_bt.h

@@ -159,7 +159,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
  */
 esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
 
-#define CONFIG_VERSION  0x20250310
+#define CONFIG_VERSION  0x20250513
 #define CONFIG_MAGIC    0x5A5AA5A5
 
 /**
@@ -226,6 +226,11 @@ typedef struct {
                                                         - 1 - Enable */
     uint8_t vhci_enabled;                            /*!< VHCI mode is enabled */
     uint8_t ptr_check_enabled;                       /*!< Enable boundary check for internal memory. */
+    uint8_t ble_adv_tx_options;                     /*!< The options for Extended advertising sending. */
+    uint8_t skip_unnecessary_checks_en;             /*!< The option to skip non-fatal state checks and perform extra handling for fatal checks. */
+    uint8_t fast_conn_data_tx_en;                   /*!< The option for fast transmission of connection data
+                                                        - 0 - Disable
+                                                        - 1 - Enable (default) */
     uint32_t config_magic;                           /*!< Magic number for configuration validation */
 } esp_bt_controller_config_t;
 
@@ -281,6 +286,9 @@ typedef struct {
     .ble_data_lenth_zero_aux    = DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX,          \
     .vhci_enabled               = DEFAULT_BT_LE_VHCI_ENABLED,                           \
     .ptr_check_enabled          = DEFAULT_BT_LE_PTR_CHECK_ENABLED,                      \
+    .ble_adv_tx_options         = 0,                                                    \
+    .skip_unnecessary_checks_en = 0,                                                    \
+    .fast_conn_data_tx_en       = DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN,              \
     .config_magic = CONFIG_MAGIC,                                                       \
 }
 

components/bt/include/esp32c6/include/esp_bt.h

@@ -156,7 +156,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
  */
 esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
 
-#define CONFIG_VERSION  0x20250310
+#define CONFIG_VERSION  0x20250513
 #define CONFIG_MAGIC    0x5A5AA5A5
 
 /**
@@ -226,6 +226,11 @@ typedef struct {
                                                         - 1 - Enable */
     uint8_t vhci_enabled;                            /*!< VHCI mode is enabled */
     uint8_t ptr_check_enabled;                       /*!< Enable boundary check for internal memory. */
+    uint8_t ble_adv_tx_options;                      /*!< The options for Extended advertising sending. */
+    uint8_t skip_unnecessary_checks_en;              /*!< The option to skip non-fatal state checks and perform extra handling for fatal checks. */
+    uint8_t fast_conn_data_tx_en;                    /*!< The option for fast transmission of connection data
+                                                        - 0 - Disable
+                                                        - 1 - Enable (default) */
     uint32_t config_magic;                           /*!< Magic number for configuration validation */
 } esp_bt_controller_config_t;
 
@@ -284,6 +289,9 @@ typedef struct {
     .ble_data_lenth_zero_aux    = DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX,          \
     .vhci_enabled               = DEFAULT_BT_LE_VHCI_ENABLED,                           \
     .ptr_check_enabled          = DEFAULT_BT_LE_PTR_CHECK_ENABLED,                      \
+    .ble_adv_tx_options         = 0,                                                    \
+    .skip_unnecessary_checks_en = 0,                                                    \
+    .fast_conn_data_tx_en       = DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN,              \
     .config_magic = CONFIG_MAGIC,                                                       \
 }
 #elif CONFIG_IDF_TARGET_ESP32C61
@@ -339,6 +347,9 @@ typedef struct {
     .ble_data_lenth_zero_aux    = DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX,          \
     .vhci_enabled               = DEFAULT_BT_LE_VHCI_ENABLED,                           \
     .ptr_check_enabled          = DEFAULT_BT_LE_PTR_CHECK_ENABLED,                      \
+    .ble_adv_tx_options         = 0,                                                    \
+    .skip_unnecessary_checks_en = 0,                                                    \
+    .fast_conn_data_tx_en       = DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN,              \
     .config_magic = CONFIG_MAGIC,                                                       \
 }
 #endif

components/bt/include/esp32h2/include/esp_bt.h

@@ -161,7 +161,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
  */
 esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
 
-#define CONFIG_VERSION  0x20250310
+#define CONFIG_VERSION  0x20250513
 #define CONFIG_MAGIC    0x5A5AA5A5
 
 /**
@@ -226,8 +226,13 @@ typedef struct {
     uint8_t ble_data_lenth_zero_aux;                /*!< Enable / disable auxiliary packets when the extended ADV data length is zero. Configurable in menuconfig.
                                                         - 0 - Disable (default)
                                                         - 1 - Enable */
-    uint8_t vhci_enabled;                           /*!< VHCI is enabled  */
+    uint8_t vhci_enabled;                           /*!< VHCI is enabled */
     uint8_t ptr_check_enabled;                      /*!< Enable boundary check for internal memory. */
+    uint8_t ble_adv_tx_options;                     /*!< The options for Extended advertising sending. */
+    uint8_t skip_unnecessary_checks_en;             /*!< The option to skip non-fatal state checks and perform extra handling for fatal checks. */
+    uint8_t fast_conn_data_tx_en;                   /*!< The option for fast transmission of connection data
+                                                        - 0 - Disable
+                                                        - 1 - Enable (default) */
     uint32_t config_magic;                          /*!< Configuration magic value */
 } esp_bt_controller_config_t;
 
@@ -284,6 +289,9 @@ typedef struct {
     .ble_data_lenth_zero_aux    = DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX,          \
     .vhci_enabled               = DEFAULT_BT_LE_VHCI_ENABLED,                           \
     .ptr_check_enabled          = DEFAULT_BT_LE_PTR_CHECK_ENABLED,                      \
+    .ble_adv_tx_options         = 0,                                                    \
+    .skip_unnecessary_checks_en = 0,                                                    \
+    .fast_conn_data_tx_en       = DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN,              \
     .config_magic = CONFIG_MAGIC,                                                       \
 }
 

components/driver/twai/twai.c

@@ -100,8 +100,10 @@ typedef struct twai_obj_t {
     SemaphoreHandle_t alert_semphr;
     uint32_t alerts_enabled;
     uint32_t alerts_triggered;
+#ifdef CONFIG_PM_ENABLE
     //Power Management Lock
     esp_pm_lock_handle_t pm_lock;
+#endif
     portMUX_TYPE spinlock;
 } twai_obj_t;
 

components/efuse/esp32c61/esp_efuse_table.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table af9aaa79feb0970d90f35360a5113f03
+// md5_digest_table 0edc6a5b20a41c88fdc0cf51a810c53e
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -231,6 +231,34 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLOCK2,
 };
 
+static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBG,
+};
+
+static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LP_HP_DBIAS_VOL_GAP,
+};
+
 static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
 };
@@ -368,43 +396,43 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
 };
 
 static const esp_efuse_desc_t DIS_ICACHE[] = {
-    {EFUSE_BLK0, 39, 1}, 	 // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled,
+    {EFUSE_BLK0, 39, 1}, 	 // [] Represents whether cache is disabled. 1: Disabled 0: Enabled.,
 };
 
 static const esp_efuse_desc_t DIS_USB_JTAG[] = {
-    {EFUSE_BLK0, 40, 1}, 	 // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled,
+    {EFUSE_BLK0, 40, 1}, 	 // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
-    {EFUSE_BLK0, 42, 1}, 	 // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled,
+    {EFUSE_BLK0, 42, 1}, 	 // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled,
 };
 
 static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
-    {EFUSE_BLK0, 43, 1}, 	 // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled,
+    {EFUSE_BLK0, 43, 1}, 	 // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled,
 };
 
 static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
-    {EFUSE_BLK0, 44, 1}, 	 // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled,
+    {EFUSE_BLK0, 44, 1}, 	 // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled,
 };
 
 static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
-    {EFUSE_BLK0, 45, 1}, 	 // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled,
+    {EFUSE_BLK0, 45, 1}, 	 // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
-    {EFUSE_BLK0, 46, 1}, 	 // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled,
+    {EFUSE_BLK0, 46, 1}, 	 // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled,
 };
 
 static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
-    {EFUSE_BLK0, 51, 1}, 	 // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged,
+    {EFUSE_BLK0, 51, 1}, 	 // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged,
 };
 
 static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
-    {EFUSE_BLK0, 52, 1}, 	 // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned,
+    {EFUSE_BLK0, 52, 1}, 	 // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned,
 };
 
 static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
-    {EFUSE_BLK0, 53, 2}, 	 // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16,
+    {EFUSE_BLK0, 53, 2}, 	 // [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)),
 };
 
 static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
@@ -452,11 +480,11 @@ static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
-    {EFUSE_BLK0, 90, 1}, 	 // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled,
+    {EFUSE_BLK0, 90, 1}, 	 // [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    {EFUSE_BLK0, 91, 1}, 	 // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled,
+    {EFUSE_BLK0, 91, 1}, 	 // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable,
 };
 
 static const esp_efuse_desc_t FLASH_TPUW[] = {
@@ -464,23 +492,23 @@ static const esp_efuse_desc_t FLASH_TPUW[] = {
 };
 
 static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 96, 1}, 	 // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable,
+    {EFUSE_BLK0, 96, 1}, 	 // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable,
 };
 
 static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
-    {EFUSE_BLK0, 97, 1}, 	 // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable,
+    {EFUSE_BLK0, 97, 1}, 	 // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable,
 };
 
 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
-    {EFUSE_BLK0, 98, 1}, 	 // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable,
+    {EFUSE_BLK0, 98, 1}, 	 // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable,
 };
 
 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 99, 1}, 	 // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable,
+    {EFUSE_BLK0, 99, 1}, 	 // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable,
 };
 
 static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
-    {EFUSE_BLK0, 100, 1}, 	 // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable,
+    {EFUSE_BLK0, 100, 1}, 	 // [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable,
 };
 
 static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
@@ -500,27 +528,47 @@ static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
 };
 
 static const esp_efuse_desc_t HYS_EN_PAD[] = {
-    {EFUSE_BLK0, 121, 1}, 	 // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled,
+    {EFUSE_BLK0, 121, 1}, 	 // [] Set bits to enable hysteresis function of PAD0~27,
 };
 
 static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = {
-    {EFUSE_BLK0, 122, 1}, 	 // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable,
+    {EFUSE_BLK0, 122, 1}, 	 // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable.,
 };
 
 static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = {
-    {EFUSE_BLK0, 123, 2}, 	 // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration,
+    {EFUSE_BLK0, 123, 2}, 	 // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled,
 };
 
 static const esp_efuse_desc_t DIS_WIFI6[] = {
-    {EFUSE_BLK0, 125, 1}, 	 // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.,
+    {EFUSE_BLK0, 125, 1}, 	 // [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled,
 };
 
 static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = {
-    {EFUSE_BLK0, 126, 1}, 	 // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable,
+    {EFUSE_BLK0, 126, 1}, 	 // [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled,
 };
 
 static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = {
-    {EFUSE_BLK0, 127, 1}, 	 // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable,
+    {EFUSE_BLK0, 127, 1}, 	 // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable,
+};
+
+static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = {
+    {EFUSE_BLK0, 128, 4}, 	 // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader,
+};
+
+static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_EN[] = {
+    {EFUSE_BLK0, 132, 1}, 	 // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled,
+};
+
+static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = {
+    {EFUSE_BLK0, 133, 1}, 	 // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable,
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR[] = {
+    {EFUSE_BLK0, 134, 12}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t REPEAT_DATA4[] = {
+    {EFUSE_BLK0, 160, 24}, 	 // [] Reserved,
 };
 
 static const esp_efuse_desc_t MAC[] = {
@@ -580,6 +628,34 @@ static const esp_efuse_desc_t PKG_VERSION[] = {
     {EFUSE_BLK1, 90, 3}, 	 // [] Package version,
 };
 
+static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK1, 93, 4}, 	 // [] Active HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK1, 97, 4}, 	 // [] Active LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LSLP_HP_DBG[] = {
+    {EFUSE_BLK1, 101, 2}, 	 // [] LSLP HP DBG of fixed voltage,
+};
+
+static const esp_efuse_desc_t LSLP_HP_DBIAS[] = {
+    {EFUSE_BLK1, 103, 4}, 	 // [] LSLP HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_LP_DBG[] = {
+    {EFUSE_BLK1, 107, 4}, 	 // [] DSLP LP DBG of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK1, 111, 5}, 	 // [] DSLP LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK1, 116, 5}, 	 // [] DBIAS gap between LP and HP,
+};
+
 static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
 };
@@ -950,6 +1026,41 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
+    &WR_DIS_ACTIVE_HP_DBIAS[0],    		// [] wr_dis of ACTIVE_HP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
+    &WR_DIS_ACTIVE_LP_DBIAS[0],    		// [] wr_dis of ACTIVE_LP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = {
+    &WR_DIS_LSLP_HP_DBG[0],    		// [] wr_dis of LSLP_HP_DBG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = {
+    &WR_DIS_LSLP_HP_DBIAS[0],    		// [] wr_dis of LSLP_HP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = {
+    &WR_DIS_DSLP_LP_DBG[0],    		// [] wr_dis of DSLP_LP_DBG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
+    &WR_DIS_DSLP_LP_DBIAS[0],    		// [] wr_dis of DSLP_LP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
+    &WR_DIS_LP_HP_DBIAS_VOL_GAP[0],    		// [] wr_dis of LP_HP_DBIAS_VOL_GAP
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
     NULL
@@ -1121,52 +1232,52 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
-    &DIS_ICACHE[0],    		// [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled
+    &DIS_ICACHE[0],    		// [] Represents whether cache is disabled. 1: Disabled 0: Enabled.
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
-    &DIS_USB_JTAG[0],    		// [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled
+    &DIS_USB_JTAG[0],    		// [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
-    &DIS_FORCE_DOWNLOAD[0],    		// [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled
+    &DIS_FORCE_DOWNLOAD[0],    		// [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
-    &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled
+    &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
-    &JTAG_SEL_ENABLE[0],    		// [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled
+    &JTAG_SEL_ENABLE[0],    		// [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
-    &DIS_PAD_JTAG[0],    		// [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled
+    &DIS_PAD_JTAG[0],    		// [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
-    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled
+    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
-    &USB_EXCHG_PINS[0],    		// [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged
+    &USB_EXCHG_PINS[0],    		// [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
-    &VDD_SPI_AS_GPIO[0],    		// [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned
+    &VDD_SPI_AS_GPIO[0],    		// [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
-    &WDT_DELAY_SEL[0],    		// [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16
+    &WDT_DELAY_SEL[0],    		// [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1))
     NULL
 };
 
@@ -1226,12 +1337,12 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
-    &SECURE_BOOT_EN[0],    		// [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled
+    &SECURE_BOOT_EN[0],    		// [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled
+    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable
     NULL
 };
 
@@ -1241,27 +1352,27 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
-    &DIS_DOWNLOAD_MODE[0],    		// [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable
+    &DIS_DOWNLOAD_MODE[0],    		// [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
-    &DIS_DIRECT_BOOT[0],    		// [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable
+    &DIS_DIRECT_BOOT[0],    		// [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
-    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable
+    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
-    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable
+    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
-    &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable
+    &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable
     NULL
 };
 
@@ -1286,32 +1397,57 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = {
-    &HYS_EN_PAD[0],    		// [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled
+    &HYS_EN_PAD[0],    		// [] Set bits to enable hysteresis function of PAD0~27
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = {
-    &XTS_DPA_CLK_ENABLE[0],    		// [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable
+    &XTS_DPA_CLK_ENABLE[0],    		// [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable.
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = {
-    &XTS_DPA_PSEUDO_LEVEL[0],    		// [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration
+    &XTS_DPA_PSEUDO_LEVEL[0],    		// [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[] = {
-    &DIS_WIFI6[0],    		// [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.
+    &DIS_WIFI6[0],    		// [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = {
-    &ECDSA_DISABLE_P192[0],    		// [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable
+    &ECDSA_DISABLE_P192[0],    		// [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = {
-    &ECC_FORCE_CONST_TIME[0],    		// [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable
+    &ECC_FORCE_CONST_TIME[0],    		// [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = {
+    &BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[0],    		// [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[] = {
+    &BOOTLOADER_ANTI_ROLLBACK_EN[0],    		// [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = {
+    &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0],    		// [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_REPEAT_DATA4[] = {
+    &REPEAT_DATA4[0],    		// [] Reserved
     NULL
 };
 
@@ -1385,6 +1521,41 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
+    &ACTIVE_HP_DBIAS[0],    		// [] Active HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
+    &ACTIVE_LP_DBIAS[0],    		// [] Active LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = {
+    &LSLP_HP_DBG[0],    		// [] LSLP HP DBG of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = {
+    &LSLP_HP_DBIAS[0],    		// [] LSLP HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = {
+    &DSLP_LP_DBG[0],    		// [] DSLP LP DBG of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
+    &DSLP_LP_DBIAS[0],    		// [] DSLP LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = {
+    &LP_HP_DBIAS_VOL_GAP[0],    		// [] DBIAS gap between LP and HP
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
     &OPTIONAL_UNIQUE_ID[0],    		// [] Optional unique 128-bit ID
     NULL

components/efuse/esp32c61/esp_efuse_table.csv

@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f05ff9d292b10d2360200fae1d15e8d
+# This file was generated by regtools.py based on the efuses.yaml file with the version: d435ade68d90ef96b0522478b2d8ba75
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -65,6 +65,13 @@ WR_DIS.PSRAM_VENDOR,                             EFUSE_BLK0,  20,   1, [] wr_dis
 WR_DIS.TEMP,                                     EFUSE_BLK0,  20,   1, [] wr_dis of TEMP
 WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
 WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
+WR_DIS.ACTIVE_HP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_HP_DBIAS
+WR_DIS.ACTIVE_LP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_LP_DBIAS
+WR_DIS.LSLP_HP_DBG,                              EFUSE_BLK0,  20,   1, [] wr_dis of LSLP_HP_DBG
+WR_DIS.LSLP_HP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of LSLP_HP_DBIAS
+WR_DIS.DSLP_LP_DBG,                              EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_LP_DBG
+WR_DIS.DSLP_LP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_LP_DBIAS
+WR_DIS.LP_HP_DBIAS_VOL_GAP,                      EFUSE_BLK0,  20,   1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
 WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
 WR_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  21,   1, [] wr_dis of TEMPERATURE_SENSOR
 WR_DIS.OCODE,                                    EFUSE_BLK0,  21,   1, [] wr_dis of OCODE
@@ -99,16 +106,16 @@ RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.K
 RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
 RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
 RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
-DIS_ICACHE,                                      EFUSE_BLK0,  39,   1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
-DIS_USB_JTAG,                                    EFUSE_BLK0,  40,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
-DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  42,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
-SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  43,   1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
-JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  44,   1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
-DIS_PAD_JTAG,                                    EFUSE_BLK0,  45,   1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  46,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\
-USB_EXCHG_PINS,                                  EFUSE_BLK0,  51,   1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\
-VDD_SPI_AS_GPIO,                                 EFUSE_BLK0,  52,   1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  53,   2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\
+DIS_ICACHE,                                      EFUSE_BLK0,  39,   1, [] Represents whether cache is disabled. 1: Disabled 0: Enabled.
+DIS_USB_JTAG,                                    EFUSE_BLK0,  40,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled
+DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  42,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled
+SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  43,   1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled
+JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  44,   1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled
+DIS_PAD_JTAG,                                    EFUSE_BLK0,  45,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled
+DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  46,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled
+USB_EXCHG_PINS,                                  EFUSE_BLK0,  51,   1, [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged
+VDD_SPI_AS_GPIO,                                 EFUSE_BLK0,  52,   1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned
+WDT_DELAY_SEL,                                   EFUSE_BLK0,  53,   2, [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1))
 SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  55,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
 SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  58,   1, [] Revoke 1st secure boot key
 SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  59,   1, [] Revoke 2nd secure boot key
@@ -120,24 +127,29 @@ KEY_PURPOSE_3,                                   EFUSE_BLK0,  76,   4, [KEY3_PUR
 KEY_PURPOSE_4,                                   EFUSE_BLK0,  80,   4, [KEY4_PURPOSE] Represents the purpose of Key4
 KEY_PURPOSE_5,                                   EFUSE_BLK0,  84,   4, [KEY5_PURPOSE] Represents the purpose of Key5
 SEC_DPA_LEVEL,                                   EFUSE_BLK0,  88,   2, [] Represents the spa secure level by configuring the clock random divide mode
-SECURE_BOOT_EN,                                  EFUSE_BLK0,  90,   1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
-SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0,  91,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\
+SECURE_BOOT_EN,                                  EFUSE_BLK0,  90,   1, [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable
+SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0,  91,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable
 FLASH_TPUW,                                      EFUSE_BLK0,  92,   4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0,  96,   1, [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\
-DIS_DIRECT_BOOT,                                 EFUSE_BLK0,  97,   1, [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable\\
-DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0,  98,   1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable\\
-DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0,  99,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 100,   1, [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\
+DIS_DOWNLOAD_MODE,                               EFUSE_BLK0,  96,   1, [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable
+DIS_DIRECT_BOOT,                                 EFUSE_BLK0,  97,   1, [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable
+DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0,  98,   1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable
+DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0,  99,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable
+ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 100,   1, [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable
 UART_PRINT_CONTROL,                              EFUSE_BLK0, 101,   2, [] Represents the types of UART printing
 FORCE_SEND_RESUME,                               EFUSE_BLK0, 103,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot
 SECURE_VERSION,                                  EFUSE_BLK0, 104,  16, [] Represents the version used by ESP-IDF anti-rollback feature
 SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 120,   1, [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable
-HYS_EN_PAD,                                      EFUSE_BLK0, 121,   1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\
-XTS_DPA_CLK_ENABLE,                              EFUSE_BLK0, 122,   1, [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable\\
-XTS_DPA_PSEUDO_LEVEL,                            EFUSE_BLK0, 123,   2, [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration\\
-DIS_WIFI6,                                       EFUSE_BLK0, 125,   1, [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.\\
-ECDSA_DISABLE_P192,                              EFUSE_BLK0, 126,   1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable
-ECC_FORCE_CONST_TIME,                            EFUSE_BLK0, 127,   1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable
+HYS_EN_PAD,                                      EFUSE_BLK0, 121,   1, [] Set bits to enable hysteresis function of PAD0~27
+XTS_DPA_CLK_ENABLE,                              EFUSE_BLK0, 122,   1, [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable.
+XTS_DPA_PSEUDO_LEVEL,                            EFUSE_BLK0, 123,   2, [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled
+DIS_WIFI6,                                       EFUSE_BLK0, 125,   1, [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled
+ECDSA_DISABLE_P192,                              EFUSE_BLK0, 126,   1, [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled
+ECC_FORCE_CONST_TIME,                            EFUSE_BLK0, 127,   1, [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable
+BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION,         EFUSE_BLK0, 128,   4, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader
+BOOTLOADER_ANTI_ROLLBACK_EN,                     EFUSE_BLK0, 132,   1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled
+BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM,          EFUSE_BLK0, 133,   1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable
+RECOVERY_BOOTLOADER_FLASH_SECTOR,                EFUSE_BLK0, 134,  12, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+REPEAT_DATA4,                                    EFUSE_BLK0, 160,  24, [] Reserved
 MAC,                                             EFUSE_BLK1,  40,   8, [MAC_FACTORY] MAC address
 ,                                                EFUSE_BLK1,  32,   8, [MAC_FACTORY] MAC address
 ,                                                EFUSE_BLK1,  24,   8, [MAC_FACTORY] MAC address
@@ -156,6 +168,13 @@ PSRAM_CAP,                                       EFUSE_BLK1,  83,   3, [] PSRAM
 PSRAM_VENDOR,                                    EFUSE_BLK1,  86,   2, [] PSRAM vendor
 TEMP,                                            EFUSE_BLK1,  88,   2, [] Temperature
 PKG_VERSION,                                     EFUSE_BLK1,  90,   3, [] Package version
+ACTIVE_HP_DBIAS,                                 EFUSE_BLK1,  93,   4, [] Active HP DBIAS of fixed voltage
+ACTIVE_LP_DBIAS,                                 EFUSE_BLK1,  97,   4, [] Active LP DBIAS of fixed voltage
+LSLP_HP_DBG,                                     EFUSE_BLK1, 101,   2, [] LSLP HP DBG of fixed voltage
+LSLP_HP_DBIAS,                                   EFUSE_BLK1, 103,   4, [] LSLP HP DBIAS of fixed voltage
+DSLP_LP_DBG,                                     EFUSE_BLK1, 107,   4, [] DSLP LP DBG of fixed voltage
+DSLP_LP_DBIAS,                                   EFUSE_BLK1, 111,   5, [] DSLP LP DBIAS of fixed voltage
+LP_HP_DBIAS_VOL_GAP,                             EFUSE_BLK1, 116,   5, [] DBIAS gap between LP and HP
 OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
 TEMPERATURE_SENSOR,                              EFUSE_BLK2, 128,   9, [] Temperature calibration data
 OCODE,                                           EFUSE_BLK2, 137,   8, [] ADC OCode calibration

components/efuse/esp32c61/include/esp_efuse_table.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table af9aaa79feb0970d90f35360a5113f03
+// md5_digest_table 0edc6a5b20a41c88fdc0cf51a810c53e
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -78,6 +78,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
@@ -174,6 +181,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_REPEAT_DATA4[];
 extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
 #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
 extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
@@ -188,6 +200,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
 extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];

components/efuse/esp32h21/esp_efuse_fields.c

@@ -10,7 +10,6 @@
 #include "stdlib.h"
 #include "esp_types.h"
 #include "assert.h"
-#include "hal/efuse_ll.h"
 #include "esp_err.h"
 #include "esp_log.h"
 #include "soc/efuse_periph.h"
@@ -52,40 +51,3 @@ esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
     }
     return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
 }
-
-#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
-bool esp_efuse_is_ecdsa_p192_curve_supported(void)
-{
-    uint32_t current_curve = efuse_ll_get_ecdsa_curve_mode();
-    return (current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT || current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT);
-}
-
-esp_err_t esp_efuse_enable_ecdsa_p192_curve_mode(void)
-{
-    esp_err_t err;
-    uint8_t current_curve, next_curve;
-
-    current_curve = efuse_ll_get_ecdsa_curve_mode();
-    // Check if already in desired state
-    if (current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT || current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT) {
-        ESP_EARLY_LOGD(TAG, "ECDSA P-192 curve mode is already enabled");
-        return ESP_OK;
-    }
-
-    // Check if write is disabled or already locked to P256
-    if (esp_efuse_read_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE) || current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED) {
-        ESP_EARLY_LOGE(TAG, "ECDSA curve mode is locked, cannot enable P-192 curve");
-        return ESP_FAIL;
-    }
-
-    // Attempt to write new curve mode
-    next_curve = ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT;
-    err = esp_efuse_write_field_blob(ESP_EFUSE_ECDSA_CURVE_MODE, &next_curve, ESP_EFUSE_ECDSA_CURVE_MODE[0]->bit_count);
-    if (err != ESP_OK) {
-        ESP_EARLY_LOGE(TAG, "Failed to enable ECDSA P-192 curve %d", err);
-        return err;
-    }
-
-    return ESP_OK;
-}
-#endif /* SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED */

components/efuse/esp32h21/include/esp_efuse_chip.h

@@ -77,13 +77,6 @@ typedef enum {
     ESP_EFUSE_KEY_PURPOSE_MAX,                              /**< MAX PURPOSE */
 } esp_efuse_purpose_t;
 
-typedef enum {
-    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT = 0,
-    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT = 1,
-    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT = 2,
-    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED = 3,
-} esp_efuse_ecdsa_curve_mode_t;
-
 #ifdef __cplusplus
 }
 #endif

components/efuse/include/esp_efuse.h

@@ -806,7 +806,7 @@ esp_err_t esp_efuse_check_errors(void);
  */
 esp_err_t esp_efuse_destroy_block(esp_efuse_block_t block);
 
-#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+#if SOC_ECDSA_SUPPORTED
 /**
  * @brief Checks if 192-bit ECDSA curve operations are supported.
  *
@@ -814,6 +814,22 @@ esp_err_t esp_efuse_destroy_block(esp_efuse_block_t block);
 */
 bool esp_efuse_is_ecdsa_p192_curve_supported(void);
 
+/**
+ * @brief Checks if 256-bit ECDSA curve operations are supported.
+ *
+ * This function checks if the current eFuse configuration supports 256-bit ECDSA curve operations.
+*/
+bool esp_efuse_is_ecdsa_p256_curve_supported(void);
+#endif /* SOC_ECDSA_SUPPORTED*/
+
+#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+typedef enum {
+    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT = 0,
+    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT = 1,
+    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT = 2,
+    ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED = 3,
+} esp_efuse_ecdsa_curve_mode_t;
+
 /**
  * @brief Enables 192-bit ECDSA curve operations by setting the appropriate eFuse value.
  *

components/efuse/src/esp_efuse_fields.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +16,13 @@
 #include "esp_log.h"
 #include "soc/efuse_periph.h"
 #include "sys/param.h"
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include "hal/efuse_hal.h"
+
+#ifdef SOC_ECDSA_SUPPORTED
+#include "hal/ecdsa_ll.h"
+#endif /* SOC_ECDSA_SUPPORTED */
 
 static __attribute__((unused)) const char *TAG = "efuse";
 
@@ -81,3 +88,66 @@ esp_err_t esp_efuse_update_secure_version(uint32_t secure_version)
     }
     return ESP_OK;
 }
+
+#if SOC_ECDSA_SUPPORTED
+bool esp_efuse_is_ecdsa_p192_curve_supported(void)
+{
+#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        uint32_t current_curve = efuse_hal_get_ecdsa_curve_mode();
+        return (current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT || current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT);
+    } else {
+        return true;
+    }
+#else
+    return true;
+#endif /* SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED */
+}
+
+bool esp_efuse_is_ecdsa_p256_curve_supported(void)
+{
+#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        uint32_t current_curve = efuse_hal_get_ecdsa_curve_mode();
+        return (current_curve != ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT);
+    } else {
+        return true;
+    }
+#else
+    return true;
+#endif /* SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED */
+}
+#endif /* SOC_ECDSA_SUPPORTED */
+
+#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+esp_err_t esp_efuse_enable_ecdsa_p192_curve_mode(void)
+{
+
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        esp_err_t err;
+        uint8_t current_curve, next_curve;
+
+        current_curve = efuse_hal_get_ecdsa_curve_mode();
+        // Check if already in desired state
+        if (current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT || current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P192_BIT) {
+            ESP_EARLY_LOGD(TAG, "ECDSA P-192 curve mode is already enabled");
+            return ESP_OK;
+        }
+
+        // Check if write is disabled or already locked to P256
+        if (esp_efuse_read_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE) || current_curve == ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED) {
+            ESP_EARLY_LOGE(TAG, "ECDSA curve mode is locked, cannot enable P-192 curve");
+            return ESP_FAIL;
+        }
+
+        // Attempt to write new curve mode
+        next_curve = ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_BOTH_P192_P256_BIT;
+        err = esp_efuse_write_field_blob(ESP_EFUSE_ECDSA_CURVE_MODE, &next_curve, ESP_EFUSE_ECDSA_CURVE_MODE[0]->bit_count);
+        if (err != ESP_OK) {
+            ESP_EARLY_LOGE(TAG, "Failed to enable ECDSA P-192 curve %d", err);
+            return err;
+        }
+    }
+    return ESP_OK;
+}
+#endif /* SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED */

components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -92,6 +92,20 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
 #endif
 #if SOC_EFUSE_ECDSA_KEY
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
+#endif
+#if SOC_EFUSE_ECDSA_KEY_P192
+            purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
+#endif
+#if SOC_EFUSE_ECDSA_KEY_P384
+            purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
+            purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
+#endif
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
+            purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
+#endif
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
+            purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
+            purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
 #endif
             purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
             purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG ||
@@ -111,7 +125,8 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
 
     TEST_ASSERT_EQUAL(purpose, esp_efuse_get_key_purpose(num_key));
     esp_efuse_purpose_t purpose2 = 0;
-    TEST_ESP_OK(esp_efuse_read_field_blob(esp_efuse_get_purpose_field(num_key), &purpose2, 4));
+    const esp_efuse_desc_t** key_purpose = esp_efuse_get_purpose_field(num_key);
+    TEST_ESP_OK(esp_efuse_read_field_blob(key_purpose, &purpose2, key_purpose[0]->bit_count));
     TEST_ASSERT_EQUAL(purpose, purpose2);
     TEST_ASSERT_TRUE(esp_efuse_get_keypurpose_dis_write(num_key));
     return ESP_OK;

components/esp_adc/adc_continuous.c

@@ -264,9 +264,11 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
         adc_ll_reset_register();
     }
 
+#if CONFIG_PM_ENABLE
     if (handle->pm_lock) {
         ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(handle->pm_lock), ADC_TAG, "acquire pm_lock failed");
     }
+#endif
 
     handle->fsm = ADC_FSM_STARTED;
     sar_periph_ctrl_adc_continuous_power_acquire();
@@ -369,10 +371,12 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
     }
     sar_periph_ctrl_adc_continuous_power_release();
 
+#if CONFIG_PM_ENABLE
     //release power manager lock
     if (handle->pm_lock) {
         ESP_RETURN_ON_ERROR(esp_pm_lock_release(handle->pm_lock), ADC_TAG, "release pm_lock failed");
     }
+#endif
 
     ANALOG_CLOCK_DISABLE();
 
@@ -422,9 +426,11 @@ esp_err_t adc_continuous_deinit(adc_continuous_handle_t handle)
         free(handle->ringbuf_struct);
     }
 
+#if CONFIG_PM_ENABLE
     if (handle->pm_lock) {
         esp_pm_lock_delete(handle->pm_lock);
     }
+#endif
 
     free(handle->rx_dma_buf);
     free(handle->hal.rx_desc);

components/esp_adc/adc_continuous_internal.h

@@ -89,7 +89,9 @@ struct adc_continuous_ctx_t {
     adc_hal_digi_ctrlr_cfg_t        hal_digi_ctrlr_cfg;         //Hal digital controller configuration
     adc_continuous_evt_cbs_t        cbs;                        //Callbacks
     void                            *user_data;                 //User context
+#if CONFIG_PM_ENABLE
     esp_pm_lock_handle_t            pm_lock;                    //For power management
+#endif
     struct {
         uint32_t flush_pool: 1;     //Flush the internal pool when the pool is full. With this flag, the `on_pool_ovf` event will not happen.
     } flags;

components/esp_common/include/esp_attr.h

@@ -19,15 +19,21 @@ extern "C" {
 //and all variables in shared RAM. These macros can be used to redirect
 //particular functions/variables to other memory regions.
 
-// Forces code into IRAM instead of flash
+// Places code into IRAM instead of flash
 #define IRAM_ATTR _SECTION_ATTR_IMPL(".iram1", __COUNTER__)
 
+// Forces code into IRAM instead of flash
+#define FORCE_IRAM_ATTR _SECTION_FORCE_ATTR_IMPL(".iram1", __COUNTER__)
+
 // Forces data into DRAM instead of flash
 #define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
 
-// Forces code into TCM instead of flash
+// Places code into TCM instead of flash
 #define TCM_IRAM_ATTR _SECTION_ATTR_IMPL(".tcm.text", __COUNTER__)
 
+// Forces code into TCM instead of flash
+#define FORCE_TCM_IRAM_ATTR _SECTION_FORCE_ATTR_IMPL(".tcm.text", __COUNTER__)
+
 // Forces data into TCM instead of L2MEM
 #define TCM_DRAM_ATTR _SECTION_ATTR_IMPL(".tcm.data", __COUNTER__)
 
@@ -189,11 +195,13 @@ FORCE_INLINE_ATTR TYPE& operator<<=(TYPE& a, int b) { a = a << b; return a; }
 // data with a custom section type set
 #ifndef CONFIG_IDF_TARGET_LINUX
 #define _SECTION_ATTR_IMPL(SECTION, COUNTER) __attribute__((section(SECTION "." _COUNTER_STRINGIFY(COUNTER))))
+#define _SECTION_FORCE_ATTR_IMPL(SECTION, COUNTER) __attribute__((noinline, section(SECTION "." _COUNTER_STRINGIFY(COUNTER))))
 #define _COUNTER_STRINGIFY(COUNTER) #COUNTER
 #else
 // Custom section attributes are generally not used in the port files for Linux target, but may be found
 // in the common header files. Don't declare custom sections in that case.
 #define _SECTION_ATTR_IMPL(SECTION, COUNTER)
+#define _SECTION_FORCE_ATTR_IMPL(SECTION, COUNTER)
 #endif
 
 /* Use IDF_DEPRECATED attribute to mark anything deprecated from use in

components/esp_driver_ana_cmpr/ana_cmpr.c

@@ -27,12 +27,21 @@ struct ana_cmpr_t {
     uint32_t                    intr_mask;          /*!< Interrupt mask */
     int                         intr_priority;      /*!< Interrupt priority */
     uint32_t                    src_clk_freq_hz;    /*!< Source clock frequency of the Analog Comparator unit */
+#if CONFIG_PM_ENABLE
     esp_pm_lock_handle_t        pm_lock;            /*!< The Power Management lock that used to avoid unexpected power down of the clock domain */
+#endif
 };
 
 /* Helper macros */
 #define ANA_CMPR_NULL_POINTER_CHECK(p)      ESP_RETURN_ON_FALSE((p), ESP_ERR_INVALID_ARG, TAG, "input parameter '" #p "' is NULL")
-#define ANA_CMPR_NULL_POINTER_CHECK_ISR(p)  ESP_RETURN_ON_FALSE_ISR((p), ESP_ERR_INVALID_ARG, TAG, "input parameter '" #p "' is NULL")
+#define ANA_CMPR_NULL_POINTER_CHECK_SAFE(p) \
+do {                                        \
+    if (unlikely(!(p))) {                   \
+        ESP_EARLY_LOGE(TAG, "input parameter '" #p "' is NULL");  \
+        return ESP_ERR_INVALID_ARG;         \
+    }                                       \
+} while(0)
+
 #define ANA_CMPR_UNIT_CHECK(unit)           ESP_RETURN_ON_FALSE((unit) >= 0 && (unit) < SOC_ANA_CMPR_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid unit number")
 
 /* Global static object of the Analog Comparator unit */
@@ -80,9 +89,11 @@ static esp_err_t s_ana_cmpr_init_gpio(ana_cmpr_handle_t cmpr, bool is_external_r
 
 static void ana_cmpr_destroy_unit(ana_cmpr_handle_t cmpr)
 {
+#if CONFIG_PM_ENABLE
     if (cmpr->pm_lock) {
         esp_pm_lock_delete(cmpr->pm_lock);
     }
+#endif
     if (cmpr->intr_handle) {
         esp_intr_free(cmpr->intr_handle);
     }
@@ -190,10 +201,12 @@ esp_err_t ana_cmpr_del_unit(ana_cmpr_handle_t cmpr)
 
 esp_err_t ana_cmpr_set_internal_reference(ana_cmpr_handle_t cmpr, const ana_cmpr_internal_ref_config_t *ref_cfg)
 {
-    ANA_CMPR_NULL_POINTER_CHECK_ISR(cmpr);
-    ANA_CMPR_NULL_POINTER_CHECK_ISR(ref_cfg);
-    ESP_RETURN_ON_FALSE_ISR(cmpr->ref_src == ANA_CMPR_REF_SRC_INTERNAL, ESP_ERR_INVALID_STATE,
-                            TAG, "the reference voltage does not come from internal");
+    ANA_CMPR_NULL_POINTER_CHECK_SAFE(cmpr);
+    ANA_CMPR_NULL_POINTER_CHECK_SAFE(ref_cfg);
+    if (unlikely(cmpr->ref_src != ANA_CMPR_REF_SRC_INTERNAL)) {
+        ESP_EARLY_LOGE(TAG, "the reference voltage does not come from internal");
+        return ESP_ERR_INVALID_STATE;
+    }
 
     // the underlying register may be accessed by different threads at the same time, so use spin lock to protect it
     portENTER_CRITICAL_SAFE(&s_spinlock);
@@ -205,8 +218,8 @@ esp_err_t ana_cmpr_set_internal_reference(ana_cmpr_handle_t cmpr, const ana_cmpr
 
 esp_err_t ana_cmpr_set_debounce(ana_cmpr_handle_t cmpr, const ana_cmpr_debounce_config_t *dbc_cfg)
 {
-    ANA_CMPR_NULL_POINTER_CHECK_ISR(cmpr);
-    ANA_CMPR_NULL_POINTER_CHECK_ISR(dbc_cfg);
+    ANA_CMPR_NULL_POINTER_CHECK_SAFE(cmpr);
+    ANA_CMPR_NULL_POINTER_CHECK_SAFE(dbc_cfg);
 
     /* Transfer the time to clock cycles */
     uint32_t wait_cycle = dbc_cfg->wait_us * (cmpr->src_clk_freq_hz / 1000000);
@@ -227,9 +240,11 @@ esp_err_t ana_cmpr_set_cross_type(ana_cmpr_handle_t cmpr, ana_cmpr_cross_type_t
     (void)cross_type;
     return ESP_ERR_NOT_SUPPORTED;
 #else
-    ANA_CMPR_NULL_POINTER_CHECK_ISR(cmpr);
-    ESP_RETURN_ON_FALSE_ISR(cross_type >= ANA_CMPR_CROSS_DISABLE && cross_type <= ANA_CMPR_CROSS_ANY,
-                            ESP_ERR_INVALID_ARG, TAG, "invalid cross type");
+    ANA_CMPR_NULL_POINTER_CHECK_SAFE(cmpr);
+    if (unlikely(cross_type < ANA_CMPR_CROSS_DISABLE || cross_type > ANA_CMPR_CROSS_ANY)) {
+        ESP_EARLY_LOGE(TAG, "invalid cross type");
+        return ESP_ERR_INVALID_ARG;
+    }
 
     portENTER_CRITICAL_SAFE(&s_spinlock);
     analog_cmpr_ll_set_intr_cross_type(cmpr->dev, cross_type);
@@ -274,9 +289,11 @@ esp_err_t ana_cmpr_enable(ana_cmpr_handle_t cmpr)
     ANA_CMPR_NULL_POINTER_CHECK(cmpr);
     ana_cmpr_fsm_t expected_fsm = ANA_CMPR_FSM_INIT;
     if (atomic_compare_exchange_strong(&cmpr->fsm, &expected_fsm, ANA_CMPR_FSM_WAIT)) {
+#if CONFIG_PM_ENABLE
         if (cmpr->pm_lock) {
             esp_pm_lock_acquire(cmpr->pm_lock);
         }
+#endif
 
         // the underlying register may be accessed by different threads at the same time, so use spin lock to protect it
         portENTER_CRITICAL(&s_spinlock);
@@ -305,9 +322,11 @@ esp_err_t ana_cmpr_disable(ana_cmpr_handle_t cmpr)
         analog_cmpr_ll_enable(cmpr->dev, false);
         portEXIT_CRITICAL(&s_spinlock);
 
+#if CONFIG_PM_ENABLE
         if (cmpr->pm_lock) {
             esp_pm_lock_release(cmpr->pm_lock);
         }
+#endif
 
         // switch the state machine to init state
         atomic_store(&cmpr->fsm, ANA_CMPR_FSM_INIT);

components/esp_driver_ana_cmpr/ana_cmpr_etm.c

@@ -23,13 +23,11 @@ static esp_err_t ana_cmpr_del_etm_event(esp_etm_event_handle_t base_event)
 
 esp_err_t ana_cmpr_new_etm_event(ana_cmpr_handle_t cmpr, const ana_cmpr_etm_event_config_t *config, esp_etm_event_handle_t *ret_event)
 {
-    esp_err_t ret = ESP_OK;
-    ana_cmpr_etm_event_t *event = NULL;
     ana_cmpr_unit_t unit = ana_cmpr_get_unit_id(cmpr);
     ESP_RETURN_ON_FALSE(((int)unit) >= 0, ESP_ERR_INVALID_ARG, TAG, "invalid analog comparator handle");
     ESP_RETURN_ON_FALSE(config && ret_event, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
-    event = heap_caps_calloc(1, sizeof(ana_cmpr_etm_event_t), ETM_MEM_ALLOC_CAPS);
-    ESP_GOTO_ON_FALSE(event, ESP_ERR_NO_MEM, err, TAG, "no mem for analog comparator event");
+    ana_cmpr_etm_event_t *event = heap_caps_calloc(1, sizeof(ana_cmpr_etm_event_t), ETM_MEM_ALLOC_CAPS);
+    ESP_RETURN_ON_FALSE(event, ESP_ERR_NO_MEM, TAG, "no mem for analog comparator event");
 
     uint32_t event_id = ANALOG_CMPR_LL_ETM_SOURCE(unit, config->event_type);
     event->base.del = ana_cmpr_del_etm_event;
@@ -38,11 +36,4 @@ esp_err_t ana_cmpr_new_etm_event(ana_cmpr_handle_t cmpr, const ana_cmpr_etm_even
     ESP_LOGD(TAG, "new event @%p, event_id=%"PRIu32", unit_id=%d", event, event_id, unit);
     *ret_event = &event->base;
     return ESP_OK;
-
-err:
-    if (event) {
-        free(event);
-        event = NULL;
-    }
-    return ret;
 }

components/esp_driver_ana_cmpr/include/driver/ana_cmpr.h

@@ -29,9 +29,6 @@ typedef struct {
     ana_cmpr_cross_type_t   cross_type;         /*!< The crossing types that can trigger interrupt */
     int                     intr_priority;      /*!< The interrupt priority, range 1~3.
                                                      If set to 0, the driver will automatically select a relative low priority (1,2,3) */
-    struct {
-        uint32_t            io_loop_back: 1;    /*!< Deprecated. For debug/test, a signal output from other peripheral can work as comparator input. */
-    } flags;                                    /*!< Analog comparator driver flags */
 } ana_cmpr_config_t;
 
 /**

components/esp_driver_ana_cmpr/test_apps/analog_comparator/CMakeLists.txt

@@ -14,7 +14,7 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
                       --elf-file ${CMAKE_BINARY_DIR}/test_ana_cmpr.elf
                       find-refs
                       --from-sections=.iram0.text
-                      --to-sections=.flash.text
+                      --to-sections=.flash.text,.flash.rodata
                       --exit-code
                       DEPENDS ${elf}
                       )

components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt

@@ -13,5 +13,5 @@ endif()
 
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS "."
-                       PRIV_REQUIRES unity esp_driver_gpio esp_driver_ana_cmpr esp_driver_gptimer esp_pm
+                       PRIV_REQUIRES unity esp_driver_gpio esp_driver_ana_cmpr esp_driver_gptimer esp_pm esp_psram
                        WHOLE_ARCHIVE)

components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.ci.cache_safe

@@ -1,6 +1,5 @@
 CONFIG_COMPILER_DUMP_RTL_FILES=y
 CONFIG_ANA_CMPR_ISR_CACHE_SAFE=y
-CONFIG_ANA_CMPR_CTRL_FUNC_IN_IRAM=y
 CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y
 CONFIG_COMPILER_OPTIMIZATION_NONE=y
 # place non-ISR FreeRTOS functions in Flash

components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.defaults

@@ -1,2 +1,2 @@
 CONFIG_FREERTOS_HZ=1000
-CONFIG_ESP_TASK_WDT=n
+CONFIG_ESP_TASK_WDT_EN=n

components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.defaults.esp32p4

@@ -0,0 +1,3 @@
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_HEX=y
+CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0

components/esp_driver_bitscrambler/include/driver/bitscrambler.h

@@ -50,6 +50,9 @@ typedef struct {
 /**
  * @brief Allocate BitScrambler handle for a hardware channel
  *
+ * @note This function can only be used to create a single direction BitScrambler handle.
+ *       If you need a loopback BitScrambler, call bitscrambler_loopback_create() instead.
+ *
  * @param config Configuration for requested BitScrambler
  * @param[out] handle BitScrambler controller handle
  *

components/esp_driver_bitscrambler/src/bitscrambler.c

@@ -5,6 +5,7 @@
  */
 #include <string.h>
 #include <stdatomic.h>
+#include "soc/soc_caps.h"
 #include "esp_log.h"
 #include "esp_heap_caps.h"
 #include "driver/bitscrambler.h"
@@ -20,6 +21,13 @@ static const char *TAG = "bitscrambler";
 #define BITSCRAMBLER_MEM_ALLOC_CAPS  MALLOC_CAP_DEFAULT
 #endif
 
+#if !SOC_RCC_IS_INDEPENDENT
+// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
+#define BS_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define BS_RCC_ATOMIC()
+#endif
+
 #define BITSCRAMBLER_BINARY_VER 1 //max version we're compatible with
 #define BITSCRAMBLER_HW_REV 0
 
@@ -54,38 +62,66 @@ typedef struct {
 atomic_flag tx_in_use = ATOMIC_FLAG_INIT;
 atomic_flag rx_in_use = ATOMIC_FLAG_INIT;
 
-// Claim both TX and RX channels for loopback use
-// Returns true on success, false if any of the two directions already is claimed.
-static bool claim_channel_loopback(void)
-{
-    bool old_val_tx = atomic_flag_test_and_set(&tx_in_use);
-    if (old_val_tx) {
-        return false;
-    }
-    bool old_val_rx = atomic_flag_test_and_set(&rx_in_use);
-    if (old_val_rx) {
-        atomic_flag_clear(&tx_in_use);
-        return false;
-    }
-    return true;
-}
+// This is a reference count for the BitScrambler module. It is used to keep track of how many clients are using the module.
+atomic_int group_ref_count = 0;
 
 // Claim a channel using the direction it indicated.
 // Returns true on success, false if the direction already is claimed
 static bool claim_channel(bitscrambler_direction_t dir)
 {
+    int old_use_count = atomic_fetch_add(&group_ref_count, 1);
+    if (old_use_count == 0) {
+        BS_RCC_ATOMIC() {
+            // This is the first client using the module, so we need to enable the sys clock
+            bitscrambler_ll_set_bus_clock_sys_enable(true);
+            bitscrambler_ll_reset_sys();
+            // also power on the memory
+            bitscrambler_ll_mem_power_by_pmu();
+        }
+    }
     if (dir == BITSCRAMBLER_DIR_TX) {
         bool old_val = atomic_flag_test_and_set(&tx_in_use);
         if (old_val) {
-            return false;
+            goto err;
+        } else {
+            BS_RCC_ATOMIC() {
+                bitscrambler_ll_set_bus_clock_tx_enable(true);
+                bitscrambler_ll_reset_tx();
+            }
         }
-    } else if (dir == BITSCRAMBLER_DIR_RX) {
+    } else {
         bool old_val = atomic_flag_test_and_set(&rx_in_use);
         if (old_val) {
-            return false;
+            goto err;
+        } else {
+            BS_RCC_ATOMIC() {
+                bitscrambler_ll_set_bus_clock_rx_enable(true);
+                bitscrambler_ll_reset_rx();
+            }
         }
     }
     return true;
+err:
+    atomic_fetch_sub(&group_ref_count, 1);
+    return false;
+}
+
+// Release the channel using the direction it indicated.
+static void release_channel(bitscrambler_direction_t dir)
+{
+    if (dir == BITSCRAMBLER_DIR_TX) {
+        atomic_flag_clear(&tx_in_use);
+    } else if (dir == BITSCRAMBLER_DIR_RX) {
+        atomic_flag_clear(&rx_in_use);
+    }
+    int old_use_count = atomic_fetch_sub(&group_ref_count, 1);
+    if (old_use_count == 1) {
+        // This is the last client using the module, so we need to disable the sys clock
+        BS_RCC_ATOMIC() {
+            bitscrambler_ll_set_bus_clock_sys_enable(false);
+            bitscrambler_ll_mem_force_power_off();
+        }
+    }
 }
 
 //Initialize the BitScrambler object and hardware using the given config.
@@ -96,53 +132,22 @@ static esp_err_t init_from_config(bitscrambler_t *bs, const bitscrambler_config_
     return ESP_OK;
 }
 
-static void enable_clocks(bitscrambler_t *bs)
-{
-    PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_BITSCRAMBLER_MODULE, ref_count) {
-        if (ref_count == 0) { //we're the first to enable the BitScrambler module
-            bitscrambler_ll_set_bus_clock_sys_enable(1);
-            bitscrambler_ll_reset_sys();
-            bitscrambler_ll_mem_power_by_pmu();
-        }
-        if (bs->cfg.dir == BITSCRAMBLER_DIR_RX || bs->loopback) {
-            bitscrambler_ll_set_bus_clock_rx_enable(1);
-            bitscrambler_ll_reset_rx();
-        }
-        if (bs->cfg.dir == BITSCRAMBLER_DIR_TX || bs->loopback) {
-            bitscrambler_ll_set_bus_clock_tx_enable(1);
-            bitscrambler_ll_reset_tx();
-        }
-    }
-}
-
-static void disable_clocks(bitscrambler_t *bs)
-{
-    PERIPH_RCC_RELEASE_ATOMIC(PERIPH_BITSCRAMBLER_MODULE, ref_count) {
-        if (bs->cfg.dir == BITSCRAMBLER_DIR_RX || bs->loopback) {
-            bitscrambler_ll_set_bus_clock_rx_enable(0);
-        }
-        if (bs->cfg.dir == BITSCRAMBLER_DIR_TX || bs->loopback) {
-            bitscrambler_ll_set_bus_clock_tx_enable(0);
-        }
-        if (ref_count == 0) { //we're the last to disable the BitScrambler module
-            bitscrambler_ll_set_bus_clock_sys_enable(0);
-            bitscrambler_ll_mem_force_power_off();
-        }
-    }
-}
-
-//Private function: init an existing BitScrambler object as a loopback BitScrambler.
+// init an existing BitScrambler object as a loopback BitScrambler, only used by the bitscrambler loopback driver
 esp_err_t bitscrambler_init_loopback(bitscrambler_handle_t handle, const bitscrambler_config_t *config)
 {
-    if (!claim_channel_loopback()) {
+    // claim the TX channel first
+    if (!claim_channel(BITSCRAMBLER_DIR_TX)) {
+        return ESP_ERR_NOT_FOUND;
+    }
+    // claim the RX channel, if it fails, release the TX channel
+    if (!claim_channel(BITSCRAMBLER_DIR_RX)) {
+        release_channel(BITSCRAMBLER_DIR_TX);
         return ESP_ERR_NOT_FOUND;
     }
 
-    assert(config->dir == BITSCRAMBLER_DIR_TX);
+    // mark the BitScrambler object as a loopback BitScrambler
     handle->loopback = true;
-    enable_clocks(handle);
-    esp_err_t r = init_from_config(handle, config);
-    return r;
+    return init_from_config(handle, config);
 }
 
 esp_err_t bitscrambler_new(const bitscrambler_config_t *config, bitscrambler_handle_t *handle)
@@ -165,7 +170,6 @@ esp_err_t bitscrambler_new(const bitscrambler_config_t *config, bitscrambler_han
         return ESP_ERR_NOT_FOUND;
     }
 
-    enable_clocks(bs);
     // Do initialization of BS object.
     esp_err_t r = init_from_config(bs, config);
     if (r != ESP_OK) {
@@ -303,14 +307,11 @@ void bitscrambler_free(bitscrambler_handle_t handle)
     if (!handle) {
         return;
     }
-    disable_clocks(handle);
     if (handle->loopback) {
-        atomic_flag_clear(&tx_in_use);
-        atomic_flag_clear(&rx_in_use);
-    } else if (handle->cfg.dir == BITSCRAMBLER_DIR_TX) {
-        atomic_flag_clear(&tx_in_use);
-    } else if (handle->cfg.dir == BITSCRAMBLER_DIR_RX) {
-        atomic_flag_clear(&rx_in_use);
+        release_channel(BITSCRAMBLER_DIR_TX);
+        release_channel(BITSCRAMBLER_DIR_RX);
+    } else {
+        release_channel(handle->cfg.dir);
     }
     if (handle->extra_clean_up) {
         handle->extra_clean_up(handle, handle->clean_up_user_ctx);

components/esp_driver_cam/CMakeLists.txt

@@ -34,3 +34,7 @@ idf_component_register(SRCS ${srcs}
                        REQUIRES ${requires}
                        PRIV_REQUIRES ${priv_requires}
                       )
+
+if(CONFIG_PM_ENABLE)
+    idf_component_optional_requires(PRIVATE esp_pm)
+endif()

components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -210,6 +210,10 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_
     };
     ESP_GOTO_ON_ERROR(dw_gdma_channel_register_event_callbacks(csi_dma_chan, &csi_dma_cbs, ctlr), err, TAG, "failed to register dwgdma callback");
 
+#if CONFIG_PM_ENABLE
+    ESP_GOTO_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "cam_csi_ctlr", &ctlr->pm_lock), err, TAG, "failed to create pm lock");
+#endif //CONFIG_PM_ENABLE
+
     ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
     ctlr->csi_fsm = CSI_FSM_INIT;
     ctlr->base.del = s_ctlr_del;
@@ -237,6 +241,12 @@ esp_err_t s_del_csi_ctlr(csi_controller_t *ctlr)
     ESP_RETURN_ON_FALSE(ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
     ESP_RETURN_ON_FALSE(ctlr->csi_fsm == CSI_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state");
 
+#if CONFIG_PM_ENABLE
+    if (ctlr->pm_lock) {
+        ESP_RETURN_ON_ERROR(esp_pm_lock_delete(ctlr->pm_lock), TAG, "delete pm_lock failed");
+    }
+#endif // CONFIG_PM_ENABLE
+
     if (ctlr->dma_chan) {
         ESP_RETURN_ON_ERROR(dw_gdma_del_channel(ctlr->dma_chan), TAG, "failed to delete dwgdma channel");
     }
@@ -400,6 +410,11 @@ esp_err_t s_csi_ctlr_enable(esp_cam_ctlr_handle_t handle)
 
     portENTER_CRITICAL(&ctlr->spinlock);
     ctlr->csi_fsm = CSI_FSM_ENABLED;
+#if CONFIG_PM_ENABLE
+    if (ctlr->pm_lock) {
+        ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(ctlr->pm_lock), TAG, "acquire pm_lock failed");
+    }
+#endif // CONFIG_PM_ENABLE
     portEXIT_CRITICAL(&ctlr->spinlock);
 
     return ESP_OK;
@@ -413,6 +428,11 @@ esp_err_t s_csi_ctlr_disable(esp_cam_ctlr_handle_t handle)
 
     portENTER_CRITICAL(&ctlr->spinlock);
     ctlr->csi_fsm = CSI_FSM_INIT;
+#if CONFIG_PM_ENABLE
+    if (ctlr->pm_lock) {
+        ESP_RETURN_ON_ERROR(esp_pm_lock_release(ctlr->pm_lock), TAG, "release pm_lock failed");
+    }
+#endif // CONFIG_PM_ENABLE
     portEXIT_CRITICAL(&ctlr->spinlock);
 
     return ESP_OK;

components/esp_driver_cam/csi/src/esp_cam_ctlr_csi_internal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,10 @@
 #include "soc/soc_caps.h"
 #include "esp_private/dw_gdma.h"
 
+#if CONFIG_PM_ENABLE
+#include "esp_pm.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -62,6 +66,9 @@ struct csi_controller_t {
     void                        *cbs_user_data;     //callback userdata
     dw_gdma_channel_handle_t    dma_chan;           //dwgdma channel handle
     size_t                      csi_transfer_size;  //csi transfer size for dwgdma
+#if CONFIG_PM_ENABLE
+    esp_pm_lock_handle_t        pm_lock;            //Power management lock
+#endif
     esp_cam_ctlr_t base;
 };