add function to start spi transaction from isr

Previously security eFuses were only burnt if the flash was not encrypted
yet.
To enhance robustness of the security eFuse settings their correct setup
should be verified on each bootup. Else it would be possible for an
already encrypted ESP to be reflashed with firmware containing updated,
more restrictive eFuse settings without them ever being applied.
Additionally this change enables easy, secure use of ESPs with host sidee
flash preencryption. Flash preencryption by the host computer performing
the programming procedure can speed up the programming process by a great
deal since the flash no longer needs to be read, erased and written again
by the bootloader self-encryption routines. Additionally it avoids
bricking of ESPs through interruption of the self-ecnryption procedure.
Without this change the host would have to set up all fuses in the ESP
correctly by itself, duplicating the fuse configuration code already
present in the bootloader and creating additional maintenance burden for
the host software if anything about the fuse setup logic changes.
This commit changes the security eFuse configuration logic to always burn
any configured security eFuses on bootup, regardless of current flash
encryption status.

.github/workflows/release_zips.yml

@@ -11,7 +11,8 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
       - name: Create a recursive clone source zip
-        uses: espressif/github-actions/release_zips@master
-        env:
-            RELEASE_PROJECT_NAME: ESP-IDF
-            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        uses: espressif/release-zips-action@v1
+        with:
+          github_token: ${{ secrets.GITHUB_TOKEN }}
+          release_project_name: ESP-IDF
+          git_extra_args: --shallow-since="1 year ago"

.gitignore

@@ -37,6 +37,7 @@ components/**/build/
 components/**/build_*_*/
 components/**/sdkconfig
 components/**/sdkconfig.old
+components/**/test_apps/wifi_nvs_config/nvs_data_suffix.csv
 
 # Example project files
 examples/**/build/

.gitlab/ci/build.yml

@@ -231,13 +231,18 @@ pytest_build_system_macos:
     - .after_script:build:macos:upload-failed-job-logs:ccache-show-stats
     - .rules:build:macos
   tags:
-    - macos_shell
+    - macos
   parallel: 3
   variables:
     PYENV_VERSION: "3.9"
     # CCACHE_DIR: "/cache/idf_ccache". On macOS, you cannot write to this folder due to insufficient permissions.
     CCACHE_DIR: "" # ccache will use "$HOME/Library/Caches/ccache".
     CCACHE_MAXSIZE: "5G" # To preserve the limited Macbook storage. CCACHE automatically prunes old caches to fit the set limit.
+    # Workaround for a bug in Parallels executor where CI_PROJECT_DIR is not an absolute path,
+    # but a relative path to the build directory (builds/espressif/esp-idf instead of ~/builds/espressif/esp-idf.
+    # GitLab sets the project dir to this template `<builds_dir>/<namespace>/<project_name>`
+    IDF_PATH: "/Users/espressif/builds/espressif/esp-idf"
+
 build_docker:
   extends:
     - .before_script:minimal

.gitlab/ci/common.yml

@@ -40,7 +40,7 @@ variables:
   GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
   # we're using .cache folder for caches
   GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.5-dev
+  LATEST_GIT_TAG: v6.0-dev
 
   SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
   # by default we will fetch all submodules
@@ -140,6 +140,13 @@ variables:
   if [[ -n "$IDF_DONT_USE_MIRRORS" ]]; then
     export IDF_MIRROR_PREFIX_MAP=
   fi
+  # Optimize pip install
+  if echo "${CI_RUNNER_TAGS}" | grep "shiny"; then
+    export PIP_INDEX_URL="${PIP_INDEX_URL_SHINY}"
+  fi
+  if [[ "$(uname -m)" == "x86_64" ]] || [[ "$(uname -m)" == "aarch64" ]]; then
+    export IDF_PIP_WHEELS_URL=""
+  fi
 
   if [[ "${CI_JOB_STAGE}" != "target_test" ]]; then
     section_start "running_install_sh" "Running install.sh"
@@ -191,13 +198,21 @@ variables:
   fi
 
   # Custom OpenOCD
-  if [[ ! -z "$OOCD_DISTRO_URL" && "$CI_JOB_STAGE" == "target_test" ]]; then
-    echo "Using custom OpenOCD from ${OOCD_DISTRO_URL}"
-    wget $OOCD_DISTRO_URL
-    ARCH_NAME=$(basename $OOCD_DISTRO_URL)
-    tar -x -f $ARCH_NAME
-    export OPENOCD_SCRIPTS=$PWD/openocd-esp32/share/openocd/scripts
-    export PATH=$PWD/openocd-esp32/bin:$PATH
+  if [[ "$CI_JOB_STAGE" == "target_test" ]]; then
+    machine="$(uname -m)"
+    if [[ "$machine" == "armv7l" ]] ; then
+      OOCD_DISTRO_URL="$OOCD_DISTRO_URL_ARMHF"
+    elif [[ "$machine" == "aarch64" ]] ; then
+      OOCD_DISTRO_URL="$OOCD_DISTRO_URL_ARM64"
+    fi
+    if [[ ! -z "$OOCD_DISTRO_URL" ]]; then
+      echo "Using custom OpenOCD from ${OOCD_DISTRO_URL}"
+      wget $OOCD_DISTRO_URL
+      ARCH_NAME=$(basename $OOCD_DISTRO_URL)
+      tar -x -f $ARCH_NAME
+      export OPENOCD_SCRIPTS=$PWD/openocd-esp32/share/openocd/scripts
+      export PATH=$PWD/openocd-esp32/bin:$PATH
+    fi
   fi
 
   if [[ -n "$CI_PYTHON_TOOL_REPO" ]]; then
@@ -228,8 +243,6 @@ variables:
     # Ensure pyenv and PYENV_VERSION installed
     - eval "$(pyenv init -)"
     - *common-before_scripts
-    # On macOS, these tools need to be installed
-    - export IDF_TOOLS_PATH="${HOME}/.espressif_runner_${CI_RUNNER_ID}_${CI_CONCURRENT_ID}"
     # remove idf-env.json, since it may contains enabled "features"
     - rm -f $IDF_TOOLS_PATH/idf-env.json
     # This adds tools (compilers) and the version-specific Python environment to PATH

.gitlab/ci/default-build-test-rules.yml

@@ -16,6 +16,7 @@ bypass_check_test_targets:
   - esp32h21
   - esp32h4
   - esp32c5
+  - esp32c61
 
 #
 # These lines would

.gitlab/ci/dependencies/dependencies.yml

@@ -91,4 +91,4 @@
   specific_rules:
     - if-schedule-test-build-system-windows
   patterns:
-    - build_system
+    - build_system_win

.gitlab/ci/deploy.yml

@@ -3,7 +3,6 @@
   image: $ESP_ENV_IMAGE
   tags: [ deploy ]
 
-# Check this before push_to_github
 check_submodule_sync:
   extends:
     - .deploy_job_template
@@ -31,8 +30,9 @@ push_to_github:
   extends:
     - .deploy_job_template
     - .before_script:minimal
-    - .rules:push_to_github
+    - .rules:protected:deploy
   needs:
+    # submodule must be synced before pushing to github
     - check_submodule_sync
   tags: [ brew, github_sync ]
   variables:
@@ -45,12 +45,16 @@ push_to_github:
     - git remote remove github &>/dev/null || true
     - git remote add github git@github.com:espressif/esp-idf.git
     - tools/ci/push_to_github.sh
+  environment:
+    name: push_to_github_production
+    deployment_tier: production
+    url: "https://github.com/espressif/esp-idf"
 
 deploy_update_SHA_in_esp-dockerfiles:
   extends:
     - .deploy_job_template
     - .before_script:minimal
-    - .rules:protected-no_label-always
+    - .rules:protected:deploy
   dependencies: []
   variables:
     GIT_DEPTH: 2
@@ -59,3 +63,6 @@ deploy_update_SHA_in_esp-dockerfiles:
     - 'curl --header "PRIVATE-TOKEN: ${ESPCI_SCRIPTS_TOKEN}" -o create_MR_in_esp_dockerfile.sh $GITLAB_HTTP_SERVER/api/v4/projects/1260/repository/files/create_MR_in_esp_dockerfile%2Fcreate_MR_in_esp_dockerfile.sh/raw\?ref\=master'
     - chmod +x create_MR_in_esp_dockerfile.sh
     - ./create_MR_in_esp_dockerfile.sh
+  environment:
+    name: eploy_update_SHA_in_esp-dockerfiles_production
+    deployment_tier: production

.gitlab/ci/docs.yml

@@ -4,10 +4,10 @@
   - "**/*.rst"
   - "CONTRIBUTING.rst"
   - "**/soc_caps.h"
+  - "**/Kconfig*"
 
 .patterns-docs-partial: &patterns-docs-partial
   - "components/**/*.h"
-  - "components/**/Kconfig*"
   - "components/**/CMakeList.txt"
   - "components/**/sdkconfig*"
   - "tools/tools.json"
@@ -19,12 +19,9 @@
 .patterns-docs-preview: &patterns-docs-preview
   - "docs/**/*"
 
-.if-protected: &if-protected
+.if-protected-check: &if-protected-check
   if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/)'
 
-.if-protected-no_label: &if-protected-no_label
-  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && $BOT_TRIGGER_WITH_LABEL == null'
-
 .if-qa-test-tag: &if-qa-test-tag
   if: '$CI_COMMIT_TAG =~ /^qa-test/'
 
@@ -41,7 +38,7 @@
   rules:
     - <<: *if-qa-test-tag
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build_docs
     - <<: *if-label-docs_full
     - <<: *if-dev-push
@@ -64,7 +61,7 @@ check_readme_links:
   tags: ["build", "amd64", "internet"]
   allow_failure: true
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-dev-push
       changes: *patterns-example-readme
   script:
@@ -96,7 +93,7 @@ check_docs_lang_sync:
   parallel:
     matrix:
       - DOCLANG: ["en", "zh_CN"]
-        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c61", "esp32c5","esp32h2", "esp32h21", "esp32p4"]
+        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c61", "esp32c5", "esp32h2", "esp32h4", "esp32h21", "esp32p4"]
 
 check_docs_gh_links:
   image: $ESP_IDF_DOC_ENV_IMAGE
@@ -182,14 +179,17 @@ deploy_docs_preview:
     DOCS_DEPLOY_SERVER_USER: "$DOCS_SERVER_USER"
     DOCS_DEPLOY_PATH: "$DOCS_PATH"
     DOCS_DEPLOY_URL_BASE: "https://$DOCS_PREVIEW_SERVER_URL/docs/esp-idf"
+  environment:
+    name: deploy_docs_preview
+    deployment_tier: staging
+    url: "https://$DOCS_PREVIEW_SERVER_URL/docs/esp-idf"
 
 # stage: post_deploy
 deploy_docs_production:
   # The DOCS_PROD_* variables used by this job are "Protected" so these branches must all be marked "Protected" in Gitlab settings
   extends:
     - .deploy_docs_template
-  rules:
-    - <<: *if-protected-no_label
+    - .rules:protected:deploy
   stage: post_deploy
   dependencies:  # set dependencies to null to avoid missing artifacts issue
   needs: # ensure runs after push_to_github succeeded
@@ -204,12 +204,15 @@ deploy_docs_production:
     DOCS_DEPLOY_PATH: "$DOCS_PROD_PATH"
     DOCS_DEPLOY_URL_BASE: "https://docs.espressif.com/projects/esp-idf"
     DEPLOY_STABLE: 1
+  environment:
+    name: deploy_docs_production
+    deployment_tier: production
+    url: "https://docs.espressif.com/projects/esp-idf"
 
 check_doc_links:
   extends:
     - .build_docs_template
-  rules:
-    - <<: *if-protected-no_label
+    - .rules:protected:deploy
   stage: post_deploy
   needs:
     - job: deploy_docs_production

.gitlab/ci/host-test.yml

@@ -113,7 +113,8 @@ test_cli_installer:
   script:
     # Tools must be downloaded for testing
     # We could use "idf_tools.py download all", but we don't want to install clang because of its huge size
-    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa cmake
+    #                                                                      cmake@version that is supported
+    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa cmake cmake@3.16.3
     - cd ${IDF_PATH}/tools/test_idf_tools
     - python3 -m pip install jsonschema
     - python3 ./test_idf_tools.py -v
@@ -348,7 +349,7 @@ test_pytest_macos:
     - .host_test_template
     - .before_script:build:macos
   tags:
-    - macos_shell
+    - macos
   artifacts:
     paths:
       - XUNIT_RESULT.xml
@@ -359,18 +360,22 @@ test_pytest_macos:
   variables:
     PYENV_VERSION: "3.9"
     PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
+    # Workaround for a bug in Parallels executor where CI_PROJECT_DIR is not an absolute path,
+    # but a relative path to the build directory (builds/espressif/esp-idf instead of ~/builds/espressif/esp-idf.
+    # GitLab sets the project dir to this template `<builds_dir>/<namespace>/<project_name>`
+    IDF_PATH: "/Users/espressif/builds/espressif/esp-idf"
   script:
     - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -v
       --target linux
       --pytest-apps
-      -m \"host_test and macos_shell\"
+      -m \"host_test and macos\"
       --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
       --modified-components ${MR_MODIFIED_COMPONENTS}
       --modified-files ${MR_MODIFIED_FILES}
     - python tools/ci/get_known_failure_cases_file.py
     - run_cmd pytest
       --target linux
-      -m \"host_test and macos_shell\"
+      -m \"host_test and macos\"
       --junitxml=XUNIT_RESULT.xml
       --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
       --app-info-filepattern \"list_job_*.txt\"

.gitlab/ci/post_deploy.yml

@@ -1,11 +1,15 @@
-generate_failed_jobs_report:
+.post_deploy_template:
   stage: post_deploy
-  tags: [build, shiny]
   image: $ESP_ENV_IMAGE
+
+generate_failed_jobs_report:
+  extends:
+    - .post_deploy_template
+  tags: [build, shiny]
   when: always
   dependencies: []  # Do not download artifacts from the previous stages
   artifacts:
-    expire_in: 1 week
+    expire_in: 2 week
     when: always
     paths:
       - job_report.html
@@ -13,12 +17,16 @@ generate_failed_jobs_report:
     - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type job
 
 sync_support_status:
-  stage: post_deploy
   extends:
-    - .rules:sync_support_status
+    - .post_deploy_template
+    - .rules:master:push
+  tags: [ brew, github_sync ]
   needs:
     - push_to_github
-  image: $ESP_ENV_IMAGE
-  tags: [ brew, github_sync ]
+  cache: []
+  before_script: []
   script:
     - curl --fail --request POST --form token="$IDF_STATUS_TRIG_TOKEN" --form ref="$IDF_STATUS_BRANCH" --form "variables[UPLOAD_TO_S3]=true" "$IDF_STATUS_TRIG_URL"
+  environment:
+    name: sync_support_status_production
+    deployment_tier: production

.gitlab/ci/pre_check.yml

@@ -10,7 +10,7 @@ check_version:
   # esp_idf_version.h in a branch before tagging the next version.
   extends:
     - .pre_check_template
-    - .rules:protected
+    - .rules:protected:check
   tags: [ brew, github_sync ]
   variables:
     # need a full clone to get the latest tag
@@ -165,6 +165,8 @@ pipeline_variables:
       if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
         echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
       fi
+    - echo "OOCD_DISTRO_URL_ARMHF=$OOCD_DISTRO_URL_ARMHF" >> pipeline.env
+    - echo "OOCD_DISTRO_URL_ARM64=$OOCD_DISTRO_URL_ARM64" >> pipeline.env
     - python tools/ci/ci_process_description.py
     - cat pipeline.env
     - python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report

.gitlab/ci/rules.yml

@@ -56,6 +56,9 @@
   - "tools/ci/ci_build_apps.py"
   - "tools/test_build_system/**/*"
 
+.patterns-build_system_win: &patterns-build_system_win
+  - "tools/test_build_system/**/*"
+
 .patterns-build_macos: &patterns-build_macos
   - "tools/ci/test_configure_ci_environment.sh"
 
@@ -167,22 +170,19 @@
 ##############
 # if anchors #
 ##############
-.if-ref-master: &if-ref-master
-  if: '$CI_COMMIT_REF_NAME == "master"'
+.if-master-push: &if-master-push
+  if: '$CI_COMMIT_REF_NAME == "master" && $CI_PIPELINE_SOURCE == "push"'
 
-.if-ref-master-no_label: &if-ref-master-no_label
-  if: '$CI_COMMIT_REF_NAME == "master" && $BOT_TRIGGER_WITH_LABEL == null'
-
-.if-tag-release: &if-tag-release
+.if-release-tag: &if-release-tag
   if: '$CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/'
 
-.if-protected: &if-protected
+.if-protected-check: &if-protected-check
   if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) || $CI_COMMIT_TAG =~ /^qa-test/'
 
-.if-protected-no_label: &if-protected-no_label
-  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && $BOT_TRIGGER_WITH_LABEL == null'
+.if-protected-deploy: &if-protected-deploy
+  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && ($CI_PIPELINE_SOURCE == "push" || $CI_PIPELINE_SOURCE == "api")'
 
-.if-protected-ref-push: &if-protected-ref-push
+.if-protected-branch-push: &if-protected-branch-push
   # rules:changes always evaluates to true for new branch pipelines or when there is no Git push event
   if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/) && $CI_PIPELINE_SOURCE == "push"'
 
@@ -192,9 +192,6 @@
 .if-dev-push: &if-dev-push
   if: '$CI_COMMIT_REF_NAME != "master" && $CI_COMMIT_BRANCH !~ /^release\/v/ && $CI_COMMIT_TAG !~ /^v\d+\.\d+(\.\d+)?($|-)/ && $CI_COMMIT_TAG !~ /^qa-test/ && ($CI_PIPELINE_SOURCE == "push" || $CI_PIPELINE_SOURCE == "merge_request_event")'
 
-.if-schedule: &if-schedule
-  if: '$CI_PIPELINE_SOURCE == "schedule"'
-
 .if-schedule-nightly: &if-schedule-nightly
   if: '$CI_PIPELINE_SOURCE == "schedule" && $INCLUDE_NIGHTLY_RUN == "1"'
 
@@ -214,51 +211,41 @@
 # Rules #
 #########
 ### Branches ###
-.rules:protected:
+.rules:protected:check:
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
 
-.rules:push_to_github:
+.rules:protected:deploy:
   rules:
     - <<: *if-qa-test-tag
       when: never
-    - <<: *if-protected-no_label
+    - <<: *if-protected-deploy
 
-# Not uploading on release branches
-.rules:sync_support_status:
+.rules:master:push:
   rules:
-    - <<: *if-ref-master-no_label
-
-.rules:protected-no_label-always:
-  rules:
-    - <<: *if-qa-test-tag
-      when: never
-    - <<: *if-protected-no_label
-      when: always
+    - <<: *if-master-push
 
 .rules:tag:release:
   rules:
-    - <<: *if-tag-release
+    - <<: *if-release-tag
 
 .rules:dev-push:
   rules:
     - <<: *if-dev-push
 
-# Do not upload caches on dev branches by default
 .rules:upload-python-cache:
   rules:
-    - <<: *if-tag-release
+    - <<: *if-release-tag
     - <<: *if-schedule-nightly
-    - <<: *if-protected-ref-push
+    - <<: *if-protected-branch-push
       changes: *patterns-python-cache
     - <<: *if-label-upload_cache
       when: manual
 
 .rules:upload-submodule-cache:
   rules:
-    # Needn't upload submodule cache in schedule pipeline
-    - <<: *if-tag-release
-    - <<: *if-protected-ref-push
+    - <<: *if-release-tag
+    - <<: *if-protected-branch-push
       changes: *patterns-submodule
     - <<: *if-label-upload_cache
       when: manual
@@ -266,11 +253,10 @@
 ### Patterns ###
 .rules:patterns:clang_tidy:
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-dev-push
       changes: *patterns-c-files
 
-
 #.rules:patterns:static-code-analysis-preview:
 #  rules:
 #    - <<: *if-dev-push
@@ -282,7 +268,7 @@
 
 .rules:patterns:idf-pytest-plugin:
   rules:
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-dev-push
       changes: *patterns-idf-pytest-plugin
 
@@ -326,7 +312,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-dev-push
       changes: *patterns-build_components
@@ -339,7 +325,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-dev-push
       changes: *patterns-build_check
@@ -354,7 +340,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-label-docker
     - <<: *if-dev-push
@@ -370,7 +356,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-label-macos
     - <<: *if-label-macos_test
@@ -385,7 +371,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build
     - <<: *if-dev-push
       changes: *patterns-build_components
@@ -409,13 +395,13 @@
     - <<: *if-schedule-test-build-system-windows
     - <<: *if-label-windows
     - <<: *if-dev-push
-      changes: *patterns-build_system
+      changes: *patterns-build_system_win
 
 .rules:test:host_test:
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build-only
       when: never
     - <<: *if-label-host_test
@@ -426,7 +412,7 @@
   rules:
     - <<: *if-revert-branch
       when: never
-    - <<: *if-protected
+    - <<: *if-protected-check
     - <<: *if-label-build-only
       when: never
     - <<: *if-label-submodule

.gitlab/ci/static-code-analysis.yml

@@ -85,7 +85,7 @@ clang_tidy_check:
 #code_quality_report:
 #  extends:
 #    - .sonar_scan_template
-#    - .rules:protected
+#    - .rules:protected:check
 #  allow_failure: true  # it's using exit code to indicate the code analysis result,
 #                       # we don't want to block ci when critical issues founded
 #  script:

.gitlab/ci/test-win.yml

@@ -18,9 +18,12 @@
   after_script: []
 
 test_cli_installer_win:
+  rules:
+    - when: never
   extends:
     - .host_test_win_template
     - .rules:labels:windows_pytest_build_system
+  allow_failure: true
   artifacts:
     when: on_failure
     paths:
@@ -32,7 +35,8 @@ test_cli_installer_win:
   timeout: 3h
   script:
     # Tools must be downloaded for testing
-    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa cmake
+    #                                                                     cmake@version that is supported
+    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa cmake cmake@3.16.3
     - cd ${IDF_PATH}\tools\test_idf_tools
     - python -m pip install jsonschema
     - python .\test_idf_tools.py

.gitmodules

@@ -54,8 +54,10 @@
 	sbom-supplier = Person: Dave Gamble
 	sbom-url = https://github.com/DaveGamble/cJSON
 	sbom-description = Ultralightweight JSON parser in ANSI C
-	sbom-hash = acc76239bee01d8e9c858ae2cab296704e52d916
+	sbom-hash = 8f2beb57ddad1f94bed899790b00f46df893ccac
 	sbom-cve-exclude-list = CVE-2024-31755 Resolved in v1.7.18
+	sbom-cve-exclude-list = CVE-2023-26819 Resolved in commit a328d65ad490b64da8c87523cbbfe16050ba5bf6
+	sbom-cve-exclude-list = CVE-2023-53154 Resolved in v1.7.18
 
 [submodule "components/mbedtls/mbedtls"]
 	path = components/mbedtls/mbedtls

.pre-commit-config.yaml

@@ -212,7 +212,7 @@ repos:
       - id: check-copyright
         args: ['--ignore', 'tools/ci/check_copyright_ignore.txt', '--config', 'tools/ci/check_copyright_config.yaml']
   - repo: https://github.com/espressif/conventional-precommit-linter
-    rev: v1.7.0
+    rev: v1.10.0
     hooks:
       - id: conventional-precommit-linter
         stages: [commit-msg]

COMPATIBILITY.md

@@ -8,9 +8,9 @@ This document describes the compatibility between ESP-IDF releases and Espressif
 
 NOTE: This document on release branches may be out-of-date. Check the [Compatibility file on master](https://github.com/espressif/esp-idf/blob/master/COMPATIBILITY.md) for the most accurate information.
 
-See [Compatibility Advisory for Chip Revision Numbering Scheme](https://www.espressif.com.cn/sites/default/files/advisory_downloads/AR2022-005%20Compatibility%20Advisory%20for%20Chip%20Revision%20Numbering%20%20Scheme.pdf) on the versioning of Espressif SoC revisions.
+See [Compatibility Advisory for Chip Revision Numbering Scheme](https://www.espressif.com/sites/default/files/advisory_downloads/AR2022-005%20Compatibility%20Advisory%20for%20Chip%20Revision%20Numbering%20%20Scheme.pdf) on the versioning of Espressif SoC revisions.
 
-You can run `esptool chip_id` to detect the series and revision of an SoC. See [SoC Errata](https://www.espressif.com.cn/en/support/documents/technical-documents?keys=errata) for more on how to distinguish between chip revisions, and the improvements provided by chip revisions. And run `idf.py --version` to know the version of current ESP-IDF.
+You can run `esptool chip_id` to detect the series and revision of an SoC. See [SoC Errata](https://www.espressif.com/en/support/documents/technical-documents?keys=errata) for more on how to distinguish between chip revisions, and the improvements provided by chip revisions. And run `idf.py --version` to know the version of current ESP-IDF.
 
 ## ESP-IDF Support for Different Chip Revisions
 

Kconfig

@@ -118,8 +118,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32c5"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
-        # TODO: [ESPTOOL-1044] remove when stub supported
-        select IDF_ENV_BRINGUP
 
     config IDF_TARGET_ESP32P4
         bool
@@ -143,13 +141,11 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32h21"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_FPGA
         select IDF_ENV_BRINGUP
 
     config IDF_TARGET_ESP32H4
         bool
         default "y" if IDF_TARGET="esp32h4"
-        select FREERTOS_UNICORE  # TODO: [ESP32H4] IDF-12319, need remove
         select IDF_TARGET_ARCH_RISCV
         select IDF_ENV_FPGA
         select IDF_ENV_BRINGUP
@@ -650,7 +646,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
 
         choice COMPILER_ORPHAN_SECTIONS
             prompt "Orphan sections handling"
-            default COMPILER_ORPHAN_SECTIONS_WARNING
+            default COMPILER_ORPHAN_SECTIONS_ERROR
             depends on !IDF_TARGET_LINUX
             help
                 If the linker finds orphan sections, it attempts to place orphan sections after sections of the same
@@ -658,6 +654,11 @@ mainmenu "Espressif IoT Development Framework Configuration"
                 That means that orphan sections could placed between sections defined in IDF linker scripts.
                 This could lead to corruption of the binary image. Configure the linker action here.
 
+            config COMPILER_ORPHAN_SECTIONS_ERROR
+                bool "Fail if orphan sections found"
+                help
+                    Fails the link step with an error if orphan sections are detected.
+
             config COMPILER_ORPHAN_SECTIONS_WARNING
                 bool "Place with warning"
                 help
@@ -707,3 +708,4 @@ mainmenu "Espressif IoT Development Framework Configuration"
             - CONFIG_ESP_WIFI_ENABLE_ROAMING_APP
             - CONFIG_USB_HOST_EXT_PORT_RESET_ATTEMPTS
             - CONFIG_LIBC_PICOLIBC
+            - CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION

components/app_trace/app_trace_membufs_proto.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -92,7 +92,7 @@ static esp_err_t esp_apptrace_membufs_swap(esp_apptrace_membufs_proto_data_t *pr
     // switch to new block
     proto->state.in_block++;
 
-    proto->hw->swap(new_block_num);
+    proto->hw->swap(new_block_num, proto->state.markers[prev_block_num]);
 
     // handle data from host
     esp_hostdata_hdr_t *hdr = (esp_hostdata_hdr_t *)proto->blocks[new_block_num].start;
@@ -148,6 +148,18 @@ static esp_err_t esp_apptrace_membufs_swap_waitus(esp_apptrace_membufs_proto_dat
         if (res != ESP_OK) {
             break;
         }
+#if CONFIG_IDF_TARGET_ESP32S3
+        /*
+        * ESP32S3 has a serious data corruption issue with the transferred data to host.
+        * This delay helps reduce the failure rate by temporarily reducing heavy memory writes
+        * from RTOS-level tracing and giving OpenOCD more time to read trace memory before
+        * the current thread continues execution. While this doesn't completely prevent
+        * memory access from other threads/cores/ISRs, it has shown to significantly improve
+        * reliability when combined with CRC checks in OpenOCD. In practice, this reduces the
+        * number of retries needed to read an entire block without corruption.
+        */
+        esp_rom_delay_us(100);
+#endif
     }
     return res;
 }
@@ -339,7 +351,7 @@ uint8_t *esp_apptrace_membufs_up_buffer_get(esp_apptrace_membufs_proto_data_t *p
 esp_err_t esp_apptrace_membufs_up_buffer_put(esp_apptrace_membufs_proto_data_t *proto, uint8_t *ptr, esp_apptrace_tmo_t *tmo)
 {
     esp_apptrace_membufs_pkt_end(ptr);
-    // TODO: mark block as busy in order not to re-use it for other tracing calls until it is completely written
+    // TODO: mark block as busy in order not to reuse it for other tracing calls until it is completely written
     // TODO: avoid potential situation when all memory is consumed by low prio tasks which can not complete writing due to
     // higher prio tasks and the latter can not allocate buffers at all
     // this is abnormal situation can be detected on host which will receive only uncompleted buffers

components/app_trace/port/riscv/port.c

@@ -50,7 +50,7 @@ static uint8_t *esp_apptrace_riscv_down_buffer_get(esp_apptrace_riscv_data_t *hw
 static esp_err_t esp_apptrace_riscv_down_buffer_put(esp_apptrace_riscv_data_t *hw_data, uint8_t *ptr, esp_apptrace_tmo_t *tmo);
 static bool esp_apptrace_riscv_host_is_connected(esp_apptrace_riscv_data_t *hw_data);
 static esp_err_t esp_apptrace_riscv_buffer_swap_start(uint32_t curr_block_id);
-static esp_err_t esp_apptrace_riscv_buffer_swap(uint32_t new_block_id);
+static esp_err_t esp_apptrace_riscv_buffer_swap(uint32_t new_block_id, uint32_t prev_block_len);
 static esp_err_t esp_apptrace_riscv_buffer_swap_end(uint32_t new_block_id, uint32_t prev_block_len);
 static bool esp_apptrace_riscv_host_data_pending(void);
 
@@ -353,7 +353,7 @@ static esp_err_t esp_apptrace_riscv_buffer_swap_end(uint32_t new_block_id, uint3
     return ESP_OK;
 }
 
-static esp_err_t esp_apptrace_riscv_buffer_swap(uint32_t new_block_id)
+static esp_err_t esp_apptrace_riscv_buffer_swap(uint32_t new_block_id, uint32_t prev_block_len)
 {
     /* do nothing */
     return ESP_OK;

components/app_trace/port/xtensa/port.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -12,7 +12,7 @@
 // ======================
 
 // Xtensa has useful feature: TRAX debug module. It allows recording program execution flow at run-time without disturbing CPU.
-// Exectution flow data are written to configurable Trace RAM block. Besides accessing Trace RAM itself TRAX module also allows to read/write
+// Execution flow data are written to configurable Trace RAM block. Besides accessing Trace RAM itself TRAX module also allows to read/write
 // trace memory via its registers by means of JTAG, APB or ERI transactions.
 // ESP32 has two Xtensa cores with separate TRAX modules on them and provides two special memory regions to be used as trace memory.
 // Chip allows muxing access to those trace memory blocks in such a way that while one block is accessed by CPUs another one can be accessed by host
@@ -47,7 +47,7 @@
 // 2. TRAX Registers layout
 // ========================
 
-// This module uses two TRAX HW registers to communicate with host SW (OpenOCD).
+// This module uses two TRAX HW registers and one Performance Monitor register to communicate with host SW (OpenOCD).
 //  - Control register uses TRAX_DELAYCNT as storage. Only lower 24 bits of TRAX_DELAYCNT are writable. Control register has the following bitfields:
 //   | 31..XXXXXX..24 | 23 .(host_connect). 23| 22..(block_id)..15 | 14..(block_len)..0 |
 //    14..0  bits - actual length of user data in trace memory block. Target updates it every time it fills memory block and exposes it to host.
@@ -55,9 +55,15 @@
 //    21..15 bits - trace memory block transfer ID. Block counter. It can overflow. Updated by target, host should not modify it. Actually can be 2 bits;
 //    22     bit  - 'host data present' flag. If set to one there is data from host, otherwise - no host data;
 //    23     bit  - 'host connected' flag. If zero then host is not connected and tracing module works in post-mortem mode, otherwise in streaming mode;
-// - Status register uses TRAX_TRIGGERPC as storage. If this register is not zero then current CPU is changing TRAX registers and
-//   this register holds address of the instruction which application will execute when it finishes with those registers modifications.
-//   See 'Targets Connection' setion for details.
+//  - Status register uses TRAX_TRIGGERPC as storage. If this register is not zero then current CPU is changing TRAX registers and
+//    this register holds address of the instruction which application will execute when it finishes with those registers modifications.
+//    See 'Targets Connection' section for details.
+//  - CRC16 register uses ERI_PERFMON_PM1 as storage. This register is used to store CRC16 checksum of the exposed trace memory block.
+//    The register has the following format:
+//    | 31..16 (CRC indicator) | 15..0 (CRC16 value) |
+//    CRC indicator (0xA55A) is used to distinguish valid CRC values from other data that might be in the register.
+//    CRC16 is calculated over the entire exposed block and is updated every time a block is exposed to the host.
+//    This allows the host to verify data integrity of the received trace data.
 
 // 3. Modes of operation
 // =====================
@@ -127,7 +133,7 @@
 
 // Access to internal module's data is synchronized with custom mutex. Mutex is a wrapper for portMUX_TYPE and uses almost the same sync mechanism as in
 // vPortCPUAcquireMutex/vPortCPUReleaseMutex. The mechanism uses S32C1I Xtensa instruction to implement exclusive access to module's data from tasks and
-// ISRs running on both cores. Also custom mutex allows specifying timeout for locking operation. Locking routine checks underlaying mutex in cycle until
+// ISRs running on both cores. Also custom mutex allows specifying timeout for locking operation. Locking routine checks underlying mutex in cycle until
 // it gets its ownership or timeout expires. The differences of application tracing module's mutex implementation from vPortCPUAcquireMutex/vPortCPUReleaseMutex are:
 // - Support for timeouts.
 // - Local IRQs for CPU which owns the mutex are disabled till the call to unlocking routine. This is made to avoid possible task's prio inversion.
@@ -142,9 +148,9 @@
 
 // Timeout mechanism is based on xthal_get_ccount() routine and supports timeout values in microseconds.
 // There are two situations when task/ISR can be delayed by tracing API call. Timeout mechanism takes into account both conditions:
-// - Trace data are locked by another task/ISR. When wating on trace data lock.
+// - Trace data are locked by another task/ISR. When waiting on trace data lock.
 // - Current TRAX memory input block is full when working in streaming mode (host is connected). When waiting for host to complete previous block reading.
-// When wating for any of above conditions xthal_get_ccount() is called periodically to calculate time elapsed from trace API routine entry. When elapsed
+// When waiting for any of above conditions xthal_get_ccount() is called periodically to calculate time elapsed from trace API routine entry. When elapsed
 // time exceeds specified timeout value operation is canceled and ESP_ERR_TIMEOUT code is returned.
 #include "sdkconfig.h"
 #include "soc/soc.h"
@@ -159,11 +165,15 @@
 #include "esp_log.h"
 #include "esp_app_trace_membufs_proto.h"
 #include "esp_app_trace_port.h"
+#include "esp_rom_crc.h"
 
 // TRAX is disabled, so we use its registers for our own purposes
 // | 31..XXXXXX..24 | 23 .(host_connect). 23 | 22 .(host_data). 22| 21..(block_id)..15 | 14..(block_len)..0 |
 #define ESP_APPTRACE_TRAX_CTRL_REG              ERI_TRAX_DELAYCNT
 #define ESP_APPTRACE_TRAX_STAT_REG              ERI_TRAX_TRIGGERPC
+#define ESP_APPTRACE_TRAX_CRC16_REG             ERI_PERFMON_PM1
+
+#define ESP_APPTRACE_CRC_INDICATOR              (0xA55AU << 16)
 
 #define ESP_APPTRACE_TRAX_BLOCK_LEN_MSK         0x7FFFUL
 #define ESP_APPTRACE_TRAX_BLOCK_LEN(_l_)        ((_l_) & ESP_APPTRACE_TRAX_BLOCK_LEN_MSK)
@@ -198,7 +208,7 @@ static uint8_t *esp_apptrace_trax_down_buffer_get(esp_apptrace_trax_data_t *hw_d
 static esp_err_t esp_apptrace_trax_down_buffer_put(esp_apptrace_trax_data_t *hw_data, uint8_t *ptr, esp_apptrace_tmo_t *tmo);
 static bool esp_apptrace_trax_host_is_connected(esp_apptrace_trax_data_t *hw_data);
 static esp_err_t esp_apptrace_trax_buffer_swap_start(uint32_t curr_block_id);
-static esp_err_t esp_apptrace_trax_buffer_swap(uint32_t new_block_id);
+static esp_err_t esp_apptrace_trax_buffer_swap(uint32_t new_block_id, uint32_t prev_block_len);
 static esp_err_t esp_apptrace_trax_buffer_swap_end(uint32_t new_block_id, uint32_t prev_block_len);
 static bool esp_apptrace_trax_host_data_pending(void);
 
@@ -498,7 +508,8 @@ static esp_err_t esp_apptrace_trax_buffer_swap_start(uint32_t curr_block_id)
         uint32_t acked_block = ESP_APPTRACE_TRAX_BLOCK_ID_GET(ctrl_reg);
         uint32_t host_to_read = ESP_APPTRACE_TRAX_BLOCK_LEN_GET(ctrl_reg);
         if (host_to_read != 0 || acked_block != (curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK)) {
-            ESP_APPTRACE_LOGD("HC[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32, esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
+            ESP_APPTRACE_LOGD("HC[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32,
+                esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
                 curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK, curr_block_id);
             res = ESP_ERR_NO_MEM;
             goto _on_err;
@@ -514,14 +525,22 @@ static esp_err_t esp_apptrace_trax_buffer_swap_end(uint32_t new_block_id, uint32
 {
     uint32_t ctrl_reg = eri_read(ESP_APPTRACE_TRAX_CTRL_REG);
     uint32_t host_connected = ESP_APPTRACE_TRAX_HOST_CONNECT & ctrl_reg;
+
     eri_write(ESP_APPTRACE_TRAX_CTRL_REG, ESP_APPTRACE_TRAX_BLOCK_ID(new_block_id) |
               host_connected | ESP_APPTRACE_TRAX_BLOCK_LEN(prev_block_len));
     esp_apptrace_trax_buffer_swap_unlock();
     return ESP_OK;
 }
 
-static esp_err_t esp_apptrace_trax_buffer_swap(uint32_t new_block_id)
+static esp_err_t esp_apptrace_trax_buffer_swap(uint32_t new_block_id, uint32_t prev_block_len)
 {
+    /* Before switching to the new block, calculate CRC16 of the current block */
+    if (prev_block_len > 0) {
+        const uint8_t *prev_block_start = s_trax_blocks[!((new_block_id % 2))];
+        uint16_t crc16 = esp_rom_crc16_le(0, prev_block_start, prev_block_len);
+        eri_write(ESP_APPTRACE_TRAX_CRC16_REG, crc16 | ESP_APPTRACE_CRC_INDICATOR);
+        ESP_APPTRACE_LOGD("CRC16:%x %d @%x", crc16, prev_block_len, prev_block_start);
+    }
     esp_apptrace_trax_select_memory_block(new_block_id);
     return ESP_OK;
 }

components/app_trace/private_include/esp_app_trace_membufs_proto.h

@@ -29,7 +29,7 @@ typedef struct {
 
 typedef struct {
     esp_err_t (*swap_start)(uint32_t curr_block_id);
-    esp_err_t (*swap)(uint32_t new_block_id);
+    esp_err_t (*swap)(uint32_t new_block_id, uint32_t prev_block_len);
     esp_err_t (*swap_end)(uint32_t new_block_id, uint32_t prev_block_len);
     bool (*host_data_pending)(void);
 } esp_apptrace_membufs_proto_hw_t;

components/app_trace/sys_view/Sample/FreeRTOSV10.4/SEGGER_SYSVIEW_FreeRTOS.c

@@ -108,7 +108,7 @@ static void _cbSendTaskList(void) {
 *    Called from SystemView when asked by the host, returns the
 *    current system time in micro seconds.
 */
-static U64 _cbGetTime(void) {
+__attribute__((unused)) static U64 _cbGetTime(void) {
   U64 Time;
 
   Time = xTaskGetTickCountFromISR();
@@ -260,7 +260,10 @@ void SYSVIEW_SendTaskInfo(U32 TaskID, const char* sName, unsigned Prio, U32 Stac
 */
 // Callbacks provided to SYSTEMVIEW by FreeRTOS
 const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI = {
-  _cbGetTime,
+  /* Callback _cbGetTime locks xKernelLock inside xTaskGetTickCountFromISR, this can cause deadlock on multi-core.
+     To prevent deadlock, always lock xKernelLock before s_sys_view_lock. Omitting the callback here results in sending
+     SYSVIEW_EVTID_SYSTIME_CYCLES events instead of SYSVIEW_EVTID_SYSTIME_US */
+  NULL,
   _cbSendTaskList,
 };
 

components/app_update/esp_ota_ops.c

@@ -33,7 +33,7 @@
 #include "esp_flash.h"
 #include "esp_flash_internal.h"
 
-#define SUB_TYPE_ID(i) (i & 0x0F)
+#define OTA_SLOT(i) (i & 0x0F)
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
 /* Partial_data is word aligned so no reallocation is necessary for encrypted flash write */
@@ -539,6 +539,69 @@ static esp_err_t rewrite_ota_seq(esp_ota_select_entry_t *two_otadata, uint32_t s
     }
 }
 
+/**
+ * @brief Calculate the next OTA sequence number that will boot the given OTA slot.
+ *
+ * Based on the ESP-IDF OTA boot scheme, the system selects the OTA slot to boot by:
+ *   boot_slot = (seq - 1) % ota_app_count
+ *
+ * This function determines the required seq value that would cause the given ota_slot_idx
+ * to be selected on next boot.
+ *
+ * @param current_seq     Current active OTA sequence number
+ * @param ota_slot_idx    Target OTA slot index (0-based)
+ * @param ota_app_count   Total number of OTA slots
+ *
+ * @return New sequence number that will result in booting ota_slot_idx
+ */
+static uint32_t compute_ota_seq_for_target_slot(uint32_t current_seq, uint32_t ota_slot_idx, uint8_t ota_app_count)
+{
+    if (ota_app_count == 0) {
+        return 0;
+    }
+    /* ESP-IDF stores OTA boot information in the OTA data partition, which consists of two sectors.
+     * Each sector holds an esp_ota_select_entry_t structure: otadata[0] and otadata[1].
+     * These structures record the OTA sequence number (ota_seq) used to determine the current boot partition.
+     *
+     * Boot selection logic:
+     * - If both otadata[0].ota_seq and otadata[1].ota_seq are 0xFFFFFFFF (invalid), it is the initial state:
+     *     → Boot the factory app, if it exists.
+     *     → Otherwise, fall back to booting ota[0].
+     *
+     * - If both otadata entries have valid sequence numbers and CRCs:
+     *     → Choose the higher sequence number (max_seq).
+     *     → Determine the OTA partition for boot (or running partition) using:
+     *          running_ota_slot = (max_seq - 1) % ota_app_count
+     *       where ota_app_count is the total number of OTA app partitions.
+     *
+     * Example:
+     *     otadata[0].ota_seq = 4
+     *     otadata[1].ota_seq = 5
+     *     ota_app_count = 8 (available OTA slots: ota_0 to ota_7)
+     *     → max_seq = 5
+     *     → running slot = (5 - 1) % 8 = 4
+     *     → So ota_4 is currently running
+     *
+     * If you want to switch to boot a different OTA slot (e.g., ota_7):
+     *     → You need to compute a new sequence number such that:
+     *          (new_seq - 1) % ota_app_count == 7
+     *       while ensuring new_seq > current_seq.
+     *
+     * General formula:
+     *         x = current OTA slot ID
+     *         ota_slot_idx = desired OTA slot ID
+     *         seq = current ota_seq
+     *
+     *     To find the next ota_seq that will boot ota_y, use:
+     *         new_seq = ((ota_slot_idx + 1) % ota_app_count) + ota_app_count * i;
+     *         // where i is the smallest non-negative integer such that new_seq > seq
+     */
+    uint32_t i = 0;
+    uint32_t base = (ota_slot_idx + 1) % ota_app_count;
+    while (current_seq > (base + i * ota_app_count)) { i++; };
+    return base + i * ota_app_count;
+}
+
 uint8_t esp_ota_get_app_partition_count(void)
 {
     uint16_t ota_app_count = 0;
@@ -549,6 +612,30 @@ uint8_t esp_ota_get_app_partition_count(void)
     return ota_app_count;
 }
 
+/**
+ * @brief Update the OTA data partition to set the given OTA app subtype as the next boot target.
+ *
+ * ESP-IDF uses the OTA data partition to track which OTA app should boot.
+ * This partition contains two entries (otadata[0] and otadata[1]), each storing an esp_ota_select_entry_t struct,
+ * which includes the OTA sequence number (ota_seq).
+ *
+ * On boot, the chip determines the current running OTA slot using:
+ *     current_slot = (max(ota_seq) - 1) % ota_app_count
+ *
+ * This function updates the OTA data to switch the next boot to the partition with the given subtype.
+ *
+ * Behavior:
+ * - If the currently selected OTA slot already matches the requested subtype,
+ *   only the state field is updated (e.g., to mark the app as newly downloaded).
+ * - Otherwise, it calculates the next valid ota_seq that will cause the bootloader to select
+ *   the requested OTA slot on reboot, and writes it to the inactive OTA data sector.
+ *
+ * @param subtype The OTA partition subtype (e.g., ESP_PARTITION_SUBTYPE_APP_OTA_0, ..._OTA_1, ...)
+ * @return
+ *     - ESP_OK if update was successful
+ *     - ESP_ERR_NOT_FOUND if OTA data partition not found
+ *     - ESP_ERR_INVALID_ARG if subtype is out of range
+ */
 static esp_err_t esp_rewrite_ota_data(esp_partition_subtype_t subtype)
 {
     esp_ota_select_entry_t otadata[2];
@@ -558,42 +645,31 @@ static esp_err_t esp_rewrite_ota_data(esp_partition_subtype_t subtype)
     }
 
     uint8_t ota_app_count = esp_ota_get_app_partition_count();
-    if (SUB_TYPE_ID(subtype) >= ota_app_count) {
+    if (OTA_SLOT(subtype) >= ota_app_count) {
         return ESP_ERR_INVALID_ARG;
     }
-
-    //esp32_idf use two sector for store information about which partition is running
-    //it defined the two sector as ota data partition,two structure esp_ota_select_entry_t is saved in the two sector
-    //named data in first sector as otadata[0], second sector data as otadata[1]
-    //e.g.
-    //if otadata[0].ota_seq == otadata[1].ota_seq == 0xFFFFFFFF,means ota info partition is in init status
-    //so it will boot factory application(if there is),if there's no factory application,it will boot ota[0] application
-    //if otadata[0].ota_seq != 0 and otadata[1].ota_seq != 0,it will choose a max seq ,and get value of max_seq%max_ota_app_number
-    //and boot a subtype (mask 0x0F) value is (max_seq - 1)%max_ota_app_number,so if want switch to run ota[x],can use next formulas.
-    //for example, if otadata[0].ota_seq = 4, otadata[1].ota_seq = 5, and there are 8 ota application,
-    //current running is (5-1)%8 = 4,running ota[4],so if we want to switch to run ota[7],
-    //we should add otadata[0].ota_seq (is 4) to 4 ,(8-1)%8=7,then it will boot ota[7]
-    //if      A=(B - C)%D
-    //then    B=(A + C)%D + D*n ,n= (0,1,2...)
-    //so current ota app sub type id is x , dest bin subtype is y,total ota app count is n
-    //seq will add (x + n*1 + 1 - seq)%n
-
     int active_otadata = bootloader_common_get_active_otadata(otadata);
+    int next_otadata;
+    uint32_t new_seq;
     if (active_otadata != -1) {
-        uint32_t seq = otadata[active_otadata].ota_seq;
-        uint32_t i = 0;
-        while (seq > (SUB_TYPE_ID(subtype) + 1) % ota_app_count + i * ota_app_count) {
-            i++;
+        uint32_t ota_slot = (otadata[active_otadata].ota_seq - 1) % ota_app_count;
+        if (ota_slot == OTA_SLOT(subtype)) {
+            // ota_data is already valid and points to the correct OTA slot.
+            // So after reboot the requested partition will be selected for boot.
+            // Only update the ota_state of the requested partition.
+            next_otadata = active_otadata;
+            new_seq = otadata[active_otadata].ota_seq;
+        } else {
+            next_otadata = (~active_otadata) & 1; // if 0 -> will be next 1. and if 1 -> will be next 0.
+            new_seq = compute_ota_seq_for_target_slot(otadata[active_otadata].ota_seq, OTA_SLOT(subtype), ota_app_count);
         }
-        int next_otadata = (~active_otadata)&1; // if 0 -> will be next 1. and if 1 -> will be next 0.
-        otadata[next_otadata].ota_state = set_new_state_otadata();
-        return rewrite_ota_seq(otadata, (SUB_TYPE_ID(subtype) + 1) % ota_app_count + i * ota_app_count, next_otadata, otadata_partition);
     } else {
         /* Both OTA slots are invalid, probably because unformatted... */
-        int next_otadata = 0;
-        otadata[next_otadata].ota_state = set_new_state_otadata();
-        return rewrite_ota_seq(otadata, SUB_TYPE_ID(subtype) + 1, next_otadata, otadata_partition);
+        next_otadata = 0;
+        new_seq = OTA_SLOT(subtype) + 1;
     }
+    otadata[next_otadata].ota_state = set_new_state_otadata();
+    return rewrite_ota_seq(otadata, new_seq, next_otadata, otadata_partition);
 }
 
 esp_err_t esp_ota_set_boot_partition(const esp_partition_t *partition)

components/app_update/test_apps/test_app_update/.build-test-rules.yml

@@ -7,6 +7,7 @@ components/app_update/test_apps:
     - if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_XIP_SUPPORTED == 1
     # S2 doesn't have ROM for flash
     - if: CONFIG_NAME == "xip_psram_with_rom_impl" and (SOC_SPIRAM_XIP_SUPPORTED == 1 and IDF_TARGET != "esp32s2")
+    - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1
   disable:
     - if: IDF_TARGET in ["esp32h21", "esp32h4"]
       temporary: true
@@ -14,3 +15,7 @@ components/app_update/test_apps:
     - if: IDF_TARGET == "esp32c61" and CONFIG_NAME == "xip_psram_with_rom_impl"
       temporary: true
       reason: not supported yet  # TODO: [ESP32C61] IDF-12784
+  disable_test:
+    - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1 and IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runners  # TODO: [ESP32C61] IDF-13165

components/app_update/test_apps/test_app_update/main/CMakeLists.txt

@@ -1,4 +1,15 @@
-idf_component_register(SRC_DIRS "."
-                       PRIV_INCLUDE_DIRS "."
-                       PRIV_REQUIRES cmock test_utils app_update bootloader_support nvs_flash driver spi_flash esp_psram
-                      WHOLE_ARCHIVE)
+idf_component_register(
+    SRC_DIRS "."
+    PRIV_INCLUDE_DIRS "."
+    PRIV_REQUIRES
+        cmock
+        test_utils
+        app_update
+        bootloader_support
+        nvs_flash
+        driver
+        spi_flash
+        esp_psram
+        efuse
+    WHOLE_ARCHIVE
+)

components/app_update/test_apps/test_app_update/main/test_bootloader_update.c

@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Tests bootloader update.
+ */
+
+#include "unity.h"
+#include "esp_log.h"
+#include "esp_efuse.h"
+#include "esp_flash_internal.h"
+#include "esp_rom_sys.h"
+#include "utils_update.h"
+#include "sdkconfig.h"
+
+#define BOOT_COUNT_NAMESPACE "boot_count"
+
+static __attribute__((unused)) const char *TAG = "btldr_update";
+
+#if CONFIG_BOOTLOADER_RECOVERY_ENABLE
+
+/* @brief Checks and prepares the partition so that the factory app is launched after that.
+ */
+static void start_test(void)
+{
+    ESP_LOGI(TAG, "boot count 1 - reset");
+    set_boot_count_in_nvs(1);
+    erase_ota_data();
+    ESP_LOGI(TAG, "ota_data erased");
+    ESP_LOGI(TAG, "Bootloader offset: 0x%x", esp_rom_get_bootloader_offset());
+    reboot_as_deep_sleep();
+}
+
+static void test_flow1(void)
+{
+    uint8_t boot_count = get_boot_count_from_nvs();
+    boot_count++;
+    set_boot_count_in_nvs(boot_count);
+    ESP_LOGI(TAG, "boot count %d", boot_count);
+
+    ESP_LOGI(TAG, "Bootloader offset: 0x%x", esp_rom_get_bootloader_offset());
+
+    const esp_partition_t *primary_bootloader;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader));
+    const esp_partition_t *recovery_bootloader;
+    TEST_ESP_OK(esp_partition_register_external(NULL, CONFIG_BOOTLOADER_RECOVERY_OFFSET, ESP_BOOTLOADER_SIZE, "RecoveryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_RECOVERY, &recovery_bootloader));
+    ESP_LOGI(TAG, "Bootloaders are registered");
+
+    // Remove write protection for the bootloader
+    esp_flash_set_dangerous_write_protection(esp_flash_default_chip, false);
+    switch (boot_count) {
+        case 2:
+            TEST_ASSERT_EQUAL_HEX32(ESP_PRIMARY_BOOTLOADER_OFFSET, esp_rom_get_bootloader_offset());
+
+            TEST_ESP_OK(esp_partition_erase_range(recovery_bootloader, 0, recovery_bootloader->size));
+            ESP_LOGI(TAG, "Erase recovery bootloader");
+
+            TEST_ESP_OK(esp_efuse_set_recovery_bootloader_offset(CONFIG_BOOTLOADER_RECOVERY_OFFSET));
+
+            ESP_LOGI(TAG, "Backup, copy <%s> -> <%s>", primary_bootloader->label, recovery_bootloader->label);
+            TEST_ESP_OK(esp_partition_copy(recovery_bootloader, 0, primary_bootloader, 0, primary_bootloader->size));
+
+            TEST_ESP_OK(esp_partition_erase_range(primary_bootloader, 0, primary_bootloader->size));
+            ESP_LOGI(TAG, "Erase primary bootloader");
+            reboot_as_deep_sleep();
+            break;
+        case 3:
+            TEST_ASSERT_EQUAL_HEX32(CONFIG_BOOTLOADER_RECOVERY_OFFSET, esp_rom_get_bootloader_offset());
+
+            ESP_LOGI(TAG, "Return to primary bootloader...");
+            ESP_LOGI(TAG, "Copy <%s> -> <%s>", recovery_bootloader->label, primary_bootloader->label);
+            TEST_ESP_OK(esp_partition_copy(primary_bootloader, 0, recovery_bootloader, 0, primary_bootloader->size));
+
+            TEST_ESP_OK(esp_partition_erase_range(recovery_bootloader, 0, recovery_bootloader->size));
+            ESP_LOGI(TAG, "Erase recovery bootloader");
+            break;
+        default:
+            TEST_FAIL_MESSAGE("Unexpected stage");
+            break;
+    }
+}
+
+TEST_CASE_MULTIPLE_STAGES("Recovery bootloader feature", "[recovery_bootloader][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", start_test, test_flow1, test_flow1);
+
+#endif // CONFIG_BOOTLOADER_RECOVERY_ENABLE

components/app_update/test_apps/test_app_update/main/test_switch_ota.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,314 +7,16 @@
  * Tests for switching between partitions: factory, OTAx, test.
  */
 
-#include <esp_types.h>
-#include <stdio.h>
-#include "string.h"
-#include <inttypes.h>
-#include "sdkconfig.h"
-
-#include "esp_rom_spiflash.h"
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "freertos/queue.h"
-#include "unity.h"
-
+#include "esp_system.h"
 #include "bootloader_common.h"
 #include "../bootloader_flash/include/bootloader_flash_priv.h"
-
-#include "esp_err.h"
 #include "esp_log.h"
-#include "esp_ota_ops.h"
-#include "esp_partition.h"
-#include "esp_flash_partitions.h"
-#include "esp_image_format.h"
-#include "nvs_flash.h"
-
-#include "driver/gpio.h"
-#include "esp_sleep.h"
-#include "test_utils.h"
-
-#define BOOT_COUNT_NAMESPACE "boot_count"
+#include "unity.h"
+#include "utils_update.h"
+#include "sdkconfig.h"
 
 static const char *TAG = "ota_test";
 
-static void set_boot_count_in_nvs(uint8_t boot_count)
-{
-    nvs_handle_t boot_count_handle;
-    esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle);
-    if (err != ESP_OK) {
-        TEST_ESP_OK(nvs_flash_erase());
-        TEST_ESP_OK(nvs_flash_init());
-        TEST_ESP_OK(nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle));
-    }
-    TEST_ESP_OK(nvs_set_u8(boot_count_handle, "boot_count", boot_count));
-    TEST_ESP_OK(nvs_commit(boot_count_handle));
-    nvs_close(boot_count_handle);
-}
-
-static uint8_t get_boot_count_from_nvs(void)
-{
-    nvs_handle_t boot_count_handle;
-    esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READONLY, &boot_count_handle);
-    if (err == ESP_ERR_NVS_NOT_FOUND) {
-        set_boot_count_in_nvs(0);
-    }
-    uint8_t boot_count;
-    TEST_ESP_OK(nvs_get_u8(boot_count_handle, "boot_count", &boot_count));
-    nvs_close(boot_count_handle);
-    return boot_count;
-}
-
-/* @brief Copies a current app to next partition using handle.
- *
- * @param[in] update_handle - Handle of API ota.
- * @param[in] cur_app - Current app.
- */
-static void copy_app_partition(esp_ota_handle_t update_handle, const esp_partition_t *curr_app)
-{
-    const void *partition_bin = NULL;
-    esp_partition_mmap_handle_t data_map;
-    ESP_LOGI(TAG, "start the copy process");
-    TEST_ESP_OK(esp_partition_mmap(curr_app, 0, curr_app->size, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map));
-    TEST_ESP_OK(esp_ota_write(update_handle, (const void *)partition_bin, curr_app->size));
-    esp_partition_munmap(data_map);
-    ESP_LOGI(TAG, "finish the copy process");
-}
-
-/* @brief Copies a current app to next partition using handle.
- *
- * @param[in] update_handle - Handle of API ota.
- * @param[in] cur_app - Current app.
- */
-static void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app)
-{
-    const void *partition_bin = NULL;
-    esp_partition_mmap_handle_t  data_map;
-    ESP_LOGI(TAG, "start the copy process");
-    uint32_t offset = 0, bytes_to_write = curr_app->size;
-    uint32_t write_bytes;
-    while (bytes_to_write > 0) {
-        write_bytes = (bytes_to_write > (4 * 1024)) ? (4 * 1024) : bytes_to_write;
-        TEST_ESP_OK(esp_partition_mmap(curr_app, offset, write_bytes, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map));
-        TEST_ESP_OK(esp_ota_write_with_offset(update_handle, (const void *)partition_bin, write_bytes, offset));
-        esp_partition_munmap(data_map);
-        bytes_to_write -= write_bytes;
-        offset += write_bytes;
-    }
-    ESP_LOGI(TAG, "finish the copy process");
-}
-
-/* @brief Get the next partition of OTA for the update.
- *
- * @return The next partition of OTA(OTA0-15).
- */
-static const esp_partition_t * get_next_update_partition(void)
-{
-    const esp_partition_t *update_partition = esp_ota_get_next_update_partition(NULL);
-    TEST_ASSERT_NOT_EQUAL(NULL, update_partition);
-    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, update_partition->subtype, update_partition->address);
-    return update_partition;
-}
-
-/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition.
- *
- * @param[in] cur_app_partition - Current app.
- * @param[in] next_app_partition - Next app for boot.
- */
-static void copy_current_app_to_next_part(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition)
-{
-    esp_ota_get_next_update_partition(NULL);
-    TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition);
-    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address);
-
-    esp_ota_handle_t update_handle = 0;
-    TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle));
-
-    copy_app_partition(update_handle, cur_app_partition);
-
-    TEST_ESP_OK(esp_ota_end(update_handle));
-    TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition));
-}
-
-/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition.
- *
- * @param[in] cur_app_partition - Current app.
- * @param[in] next_app_partition - Next app for boot.
- */
-static void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition)
-{
-    esp_ota_get_next_update_partition(NULL);
-    TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition);
-    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address);
-
-    esp_ota_handle_t update_handle = 0;
-    TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle));
-
-    copy_app_partition_with_offset(update_handle, cur_app_partition);
-
-    TEST_ESP_OK(esp_ota_end(update_handle));
-    TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition));
-}
-
-/* @brief Erase otadata partition
- */
-static void erase_ota_data(void)
-{
-    const esp_partition_t *data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL);
-    TEST_ASSERT_NOT_EQUAL(NULL, data_partition);
-    TEST_ESP_OK(esp_partition_erase_range(data_partition, 0, 2 * data_partition->erase_size));
-}
-
-/* @brief Reboots ESP using mode deep sleep. This mode guaranty that RTC_DATA_ATTR variables is not reset.
- */
-static void reboot_as_deep_sleep(void)
-{
-    ESP_LOGI(TAG, "reboot as deep sleep");
-    esp_deep_sleep(20000);
-    TEST_FAIL_MESSAGE("Should never be reachable except when sleep is rejected, abort");
-}
-
-/* @brief Copies a current app to next partition (OTA0-15), after that ESP is rebooting and run this (the next) OTAx.
- */
-static void copy_current_app_to_next_part_and_reboot(void)
-{
-    const esp_partition_t *cur_app = esp_ota_get_running_partition();
-    ESP_LOGI(TAG, "copy current app to next part");
-    copy_current_app_to_next_part(cur_app, get_next_update_partition());
-    reboot_as_deep_sleep();
-}
-
-/* @brief Copies a current app to next partition (OTA0-15) using esp_ota_write_with_offest(), after that ESP is rebooting and run this (the next) OTAx.
- */
-static void copy_current_app_to_next_part_with_offset_and_reboot(void)
-{
-    const esp_partition_t *cur_app = esp_ota_get_running_partition();
-    ESP_LOGI(TAG, "copy current app to next part");
-    copy_current_app_to_next_part_with_offset(cur_app, get_next_update_partition());
-    reboot_as_deep_sleep();
-}
-
-/* @brief Get running app.
- *
- * @return The next partition of OTA(OTA0-15).
- */
-static const esp_partition_t* get_running_firmware(void)
-{
-    const esp_partition_t *configured = esp_ota_get_boot_partition();
-    const esp_partition_t *running = esp_ota_get_running_partition();
-    ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08"PRIx32")",
-            running->type, running->subtype, running->address);
-    ESP_LOGI(TAG, "Configured partition type %d subtype %d (offset 0x%08"PRIx32")",
-            configured->type, configured->subtype, configured->address);
-    TEST_ASSERT_NOT_EQUAL(NULL, configured);
-    TEST_ASSERT_NOT_EQUAL(NULL, running);
-    if (running->subtype != ESP_PARTITION_SUBTYPE_APP_TEST) {
-        TEST_ASSERT_EQUAL_PTR(running, configured);
-    }
-    return running;
-}
-
-// type of a corrupt ota_data
-typedef enum {
-    CORR_CRC_1_SECTOR_OTA_DATA       = (1 << 0),   /*!< Corrupt CRC only 1 sector of ota_data */
-    CORR_CRC_2_SECTOR_OTA_DATA       = (1 << 1),   /*!< Corrupt CRC only 2 sector of ota_data */
-} corrupt_ota_data_t;
-
-/* @brief Get two copies ota_data from otadata partition.
- *
- * @param[in] otadata_partition - otadata partition.
- * @param[out] ota_data_0 - First copy from otadata_partition.
- * @param[out] ota_data_1 - Second copy from otadata_partition.
- */
-static void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data_0, esp_ota_select_entry_t *ota_data_1)
-{
-    uint32_t offset = otadata_partition->address;
-    uint32_t size   = otadata_partition->size;
-    if (offset != 0) {
-        const esp_ota_select_entry_t *ota_select_map;
-        ota_select_map = bootloader_mmap(offset, size);
-        TEST_ASSERT_NOT_EQUAL(NULL, ota_select_map);
-
-        memcpy(ota_data_0, ota_select_map, sizeof(esp_ota_select_entry_t));
-        memcpy(ota_data_1, (uint8_t *)ota_select_map + otadata_partition->erase_size, sizeof(esp_ota_select_entry_t));
-        bootloader_munmap(ota_select_map);
-    }
-}
-
-/* @brief Writes a ota_data into required sector of otadata_partition.
- *
- * @param[in] otadata_partition - Partition information otadata.
- * @param[in] ota_data - otadata structure.
- * @param[in] sec_id - Sector number 0 or 1.
- */
-static void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id)
-{
-    esp_partition_write(otadata_partition, otadata_partition->erase_size * sec_id, &ota_data[sec_id], sizeof(esp_ota_select_entry_t));
-}
-
-/* @brief Makes a corrupt of ota_data.
- * @param[in] err - type error
- */
-static void corrupt_ota_data(corrupt_ota_data_t err)
-{
-    esp_ota_select_entry_t ota_data[2];
-
-    const esp_partition_t *otadata_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL);
-    TEST_ASSERT_NOT_EQUAL(NULL, otadata_partition);
-    get_ota_data(otadata_partition, &ota_data[0], &ota_data[1]);
-
-    if (err & CORR_CRC_1_SECTOR_OTA_DATA) {
-        ota_data[0].crc = 0;
-    }
-    if (err & CORR_CRC_2_SECTOR_OTA_DATA) {
-        ota_data[1].crc = 0;
-    }
-    TEST_ESP_OK(esp_partition_erase_range(otadata_partition, 0, otadata_partition->size));
-    write_ota_data(otadata_partition, &ota_data[0], 0);
-    write_ota_data(otadata_partition, &ota_data[1], 1);
-}
-
-#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST)
-/* @brief Sets the pin number to output and sets output level as low. After reboot (deep sleep) this pin keep the same level.
- *
- * The output level of the pad will be force locked and can not be changed.
- * Power down or call gpio_hold_dis will disable this function.
- *
- * @param[in] num_pin - Pin number
- */
-static void set_output_pin(uint32_t num_pin)
-{
-    TEST_ESP_OK(gpio_hold_dis(num_pin));
-
-    gpio_config_t io_conf;
-    io_conf.intr_type = GPIO_INTR_DISABLE;
-    io_conf.mode = GPIO_MODE_OUTPUT;
-    io_conf.pin_bit_mask = (1ULL << num_pin);
-    io_conf.pull_down_en = 0;
-    io_conf.pull_up_en = 0;
-    TEST_ESP_OK(gpio_config(&io_conf));
-
-    TEST_ESP_OK(gpio_set_level(num_pin, 0));
-    TEST_ESP_OK(gpio_hold_en(num_pin));
-}
-
-/* @brief Unset the pin number hold function.
- */
-static void reset_output_pin(uint32_t num_pin)
-{
-    TEST_ESP_OK(gpio_hold_dis(num_pin));
-    TEST_ESP_OK(gpio_reset_pin(num_pin));
-}
-#endif
-
-static void mark_app_valid(void)
-{
-#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
-    TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
-#endif
-}
 
 /* @brief Checks and prepares the partition so that the factory app is launched after that.
  */
@@ -546,20 +248,6 @@ static void test_flow5(void)
 TEST_CASE_MULTIPLE_STAGES("Switching between factory, test, factory", "[app_update][timeout=90][reset=SW_CPU_RESET, SW_CPU_RESET, DEEPSLEEP_RESET]", start_test, test_flow5, test_flow5, test_flow5);
 #endif
 
-static const esp_partition_t* app_update(void)
-{
-    const esp_partition_t *cur_app = get_running_firmware();
-    const esp_partition_t* update_partition = esp_ota_get_next_update_partition(NULL);
-    TEST_ASSERT_NOT_NULL(update_partition);
-    esp_ota_handle_t update_handle = 0;
-    TEST_ESP_OK(esp_ota_begin(update_partition, OTA_SIZE_UNKNOWN, &update_handle));
-    copy_app_partition(update_handle, cur_app);
-    TEST_ESP_OK(esp_ota_end(update_handle));
-    TEST_ESP_OK(esp_ota_set_boot_partition(update_partition));
-    return update_partition;
-}
-
-
 static void test_rollback1(void)
 {
     uint8_t boot_count = get_boot_count_from_nvs();
@@ -930,3 +618,51 @@ static void test_rollback3_1(void)
 }
 
 TEST_CASE_MULTIPLE_STAGES("Test rollback. Updated partition invalidated after esp_ota_begin", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET, DEEPSLEEP_RESET, SW_CPU_RESET]", start_test, test_rollback3, test_rollback3, test_rollback3, test_rollback3_1);
+
+static void test_rollback4(void)
+{
+    uint8_t boot_count = get_boot_count_from_nvs();
+    boot_count++;
+    set_boot_count_in_nvs(boot_count);
+    ESP_LOGI(TAG, "boot count %d", boot_count);
+    const esp_partition_t *cur_app = get_running_firmware();
+    switch (boot_count) {
+        case 2:
+            ESP_LOGI(TAG, "Factory");
+            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_FACTORY, cur_app->subtype);
+            app_update();
+            reboot_as_deep_sleep();
+            break;
+        case 3:
+            ESP_LOGI(TAG, "OTA0");
+            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_0, cur_app->subtype);
+            TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
+            app_update();
+
+            // Do not reboot and call app_update again.
+            // This will not change the running partition since we haven't rebooted.
+            // The esp_rewrite_otadata() will update the otadata for the non-running partition only.
+            app_update();
+#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
+            // The last call to esp_rewrite_otadata should have updated the otadata for the non-running partition only.
+            // Therefore, calling esp_ota_get_state_partition on the running partition should succeed and not return ESP_ERR_NOT_FOUND
+            const esp_partition_t* running_partition;
+            running_partition = esp_ota_get_running_partition();
+            esp_ota_img_states_t ota_state;
+            TEST_ESP_OK(esp_ota_get_state_partition(running_partition, &ota_state));
+#endif
+            reboot_as_deep_sleep();
+            break;
+        case 4:
+            ESP_LOGI(TAG, "OTA1");
+            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_1, cur_app->subtype);
+            TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
+            break;
+        default:
+            erase_ota_data();
+            TEST_FAIL_MESSAGE("Unexpected stage");
+            break;
+    }
+}
+
+TEST_CASE_MULTIPLE_STAGES("Test esp_rewrite_otadata. Updated sequence number for non-running partition always", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET, DEEPSLEEP_RESET, SW_CPU_RESET]", start_test, test_rollback4, test_rollback4, test_rollback4);

components/app_update/test_apps/test_app_update/main/utils_update.c

@@ -0,0 +1,307 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_rom_spiflash.h"
+#include "driver/gpio.h"
+#include "nvs_flash.h"
+#include "esp_partition.h"
+#include "esp_flash_partitions.h"
+#include "esp_image_format.h"
+#include "../bootloader_flash/include/bootloader_flash_priv.h"
+#include "esp_sleep.h"
+#include "esp_ota_ops.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "test_utils.h"
+#include "utils_update.h"
+#include "unity.h"
+#include "sdkconfig.h"
+
+#define BOOT_COUNT_NAMESPACE "boot_count"
+
+static const char *TAG = "ota_test";
+
+
+void set_boot_count_in_nvs(uint8_t boot_count)
+{
+    nvs_handle_t boot_count_handle;
+    esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle);
+    if (err != ESP_OK) {
+        TEST_ESP_OK(nvs_flash_erase());
+        TEST_ESP_OK(nvs_flash_init());
+        TEST_ESP_OK(nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle));
+    }
+    TEST_ESP_OK(nvs_set_u8(boot_count_handle, "boot_count", boot_count));
+    TEST_ESP_OK(nvs_commit(boot_count_handle));
+    nvs_close(boot_count_handle);
+}
+
+uint8_t get_boot_count_from_nvs(void)
+{
+    nvs_handle_t boot_count_handle;
+    esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READONLY, &boot_count_handle);
+    if (err == ESP_ERR_NVS_NOT_FOUND) {
+        set_boot_count_in_nvs(0);
+    }
+    uint8_t boot_count;
+    TEST_ESP_OK(nvs_get_u8(boot_count_handle, "boot_count", &boot_count));
+    nvs_close(boot_count_handle);
+    return boot_count;
+}
+
+/* @brief Copies a current app to next partition using handle.
+ *
+ * @param[in] update_handle - Handle of API ota.
+ * @param[in] cur_app - Current app.
+ */
+void copy_app_partition(esp_ota_handle_t update_handle, const esp_partition_t *curr_app)
+{
+    const void *partition_bin = NULL;
+    esp_partition_mmap_handle_t data_map;
+    ESP_LOGI(TAG, "start the copy process");
+    TEST_ESP_OK(esp_partition_mmap(curr_app, 0, curr_app->size, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map));
+    TEST_ESP_OK(esp_ota_write(update_handle, (const void *)partition_bin, curr_app->size));
+    esp_partition_munmap(data_map);
+    ESP_LOGI(TAG, "finish the copy process");
+}
+
+/* @brief Copies a current app to next partition using handle.
+ *
+ * @param[in] update_handle - Handle of API ota.
+ * @param[in] cur_app - Current app.
+ */
+void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app)
+{
+    const void *partition_bin = NULL;
+    esp_partition_mmap_handle_t  data_map;
+    ESP_LOGI(TAG, "start the copy process");
+    uint32_t offset = 0, bytes_to_write = curr_app->size;
+    uint32_t write_bytes;
+    while (bytes_to_write > 0) {
+        write_bytes = (bytes_to_write > (4 * 1024)) ? (4 * 1024) : bytes_to_write;
+        TEST_ESP_OK(esp_partition_mmap(curr_app, offset, write_bytes, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map));
+        TEST_ESP_OK(esp_ota_write_with_offset(update_handle, (const void *)partition_bin, write_bytes, offset));
+        esp_partition_munmap(data_map);
+        bytes_to_write -= write_bytes;
+        offset += write_bytes;
+    }
+    ESP_LOGI(TAG, "finish the copy process");
+}
+
+/* @brief Get the next partition of OTA for the update.
+ *
+ * @return The next partition of OTA(OTA0-15).
+ */
+const esp_partition_t * get_next_update_partition(void)
+{
+    const esp_partition_t *update_partition = esp_ota_get_next_update_partition(NULL);
+    TEST_ASSERT_NOT_EQUAL(NULL, update_partition);
+    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, update_partition->subtype, update_partition->address);
+    return update_partition;
+}
+
+/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition.
+ *
+ * @param[in] cur_app_partition - Current app.
+ * @param[in] next_app_partition - Next app for boot.
+ */
+void copy_current_app_to_next_part(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition)
+{
+    esp_ota_get_next_update_partition(NULL);
+    TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition);
+    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address);
+
+    esp_ota_handle_t update_handle = 0;
+    TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle));
+
+    copy_app_partition(update_handle, cur_app_partition);
+
+    TEST_ESP_OK(esp_ota_end(update_handle));
+    TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition));
+}
+
+/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition.
+ *
+ * @param[in] cur_app_partition - Current app.
+ * @param[in] next_app_partition - Next app for boot.
+ */
+void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition)
+{
+    esp_ota_get_next_update_partition(NULL);
+    TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition);
+    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address);
+
+    esp_ota_handle_t update_handle = 0;
+    TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle));
+
+    copy_app_partition_with_offset(update_handle, cur_app_partition);
+
+    TEST_ESP_OK(esp_ota_end(update_handle));
+    TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition));
+}
+
+/* @brief Erase otadata partition
+ */
+void erase_ota_data(void)
+{
+    const esp_partition_t *data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL);
+    TEST_ASSERT_NOT_EQUAL(NULL, data_partition);
+    TEST_ESP_OK(esp_partition_erase_range(data_partition, 0, 2 * data_partition->erase_size));
+}
+
+/* @brief Reboots ESP using mode deep sleep. This mode guaranty that RTC_DATA_ATTR variables is not reset.
+ */
+void reboot_as_deep_sleep(void)
+{
+    ESP_LOGI(TAG, "reboot as deep sleep");
+    esp_deep_sleep(20000);
+    TEST_FAIL_MESSAGE("Should never be reachable except when sleep is rejected, abort");
+}
+
+/* @brief Copies a current app to next partition (OTA0-15), after that ESP is rebooting and run this (the next) OTAx.
+ */
+void copy_current_app_to_next_part_and_reboot(void)
+{
+    const esp_partition_t *cur_app = esp_ota_get_running_partition();
+    ESP_LOGI(TAG, "copy current app to next part");
+    copy_current_app_to_next_part(cur_app, get_next_update_partition());
+    reboot_as_deep_sleep();
+}
+
+/* @brief Copies a current app to next partition (OTA0-15) using esp_ota_write_with_offest(), after that ESP is rebooting and run this (the next) OTAx.
+ */
+void copy_current_app_to_next_part_with_offset_and_reboot(void)
+{
+    const esp_partition_t *cur_app = esp_ota_get_running_partition();
+    ESP_LOGI(TAG, "copy current app to next part");
+    copy_current_app_to_next_part_with_offset(cur_app, get_next_update_partition());
+    reboot_as_deep_sleep();
+}
+
+/* @brief Get running app.
+ *
+ * @return The next partition of OTA(OTA0-15).
+ */
+const esp_partition_t* get_running_firmware(void)
+{
+    const esp_partition_t *configured = esp_ota_get_boot_partition();
+    const esp_partition_t *running = esp_ota_get_running_partition();
+    // If a reboot hasn't occurred after app_update(), the configured and running partitions may differ
+    ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08"PRIx32")",
+            running->type, running->subtype, running->address);
+    ESP_LOGI(TAG, "Configured partition type %d subtype %d (offset 0x%08"PRIx32")",
+            configured->type, configured->subtype, configured->address);
+    TEST_ASSERT_NOT_EQUAL(NULL, configured);
+    TEST_ASSERT_NOT_EQUAL(NULL, running);
+    return running;
+}
+
+/* @brief Get two copies ota_data from otadata partition.
+ *
+ * @param[in] otadata_partition - otadata partition.
+ * @param[out] ota_data_0 - First copy from otadata_partition.
+ * @param[out] ota_data_1 - Second copy from otadata_partition.
+ */
+void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data_0, esp_ota_select_entry_t *ota_data_1)
+{
+    uint32_t offset = otadata_partition->address;
+    uint32_t size   = otadata_partition->size;
+    if (offset != 0) {
+        const esp_ota_select_entry_t *ota_select_map;
+        ota_select_map = bootloader_mmap(offset, size);
+        TEST_ASSERT_NOT_EQUAL(NULL, ota_select_map);
+
+        memcpy(ota_data_0, ota_select_map, sizeof(esp_ota_select_entry_t));
+        memcpy(ota_data_1, (uint8_t *)ota_select_map + otadata_partition->erase_size, sizeof(esp_ota_select_entry_t));
+        bootloader_munmap(ota_select_map);
+    }
+}
+
+/* @brief Writes a ota_data into required sector of otadata_partition.
+ *
+ * @param[in] otadata_partition - Partition information otadata.
+ * @param[in] ota_data - otadata structure.
+ * @param[in] sec_id - Sector number 0 or 1.
+ */
+void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id)
+{
+    esp_partition_write(otadata_partition, otadata_partition->erase_size * sec_id, &ota_data[sec_id], sizeof(esp_ota_select_entry_t));
+}
+
+/* @brief Makes a corrupt of ota_data.
+ * @param[in] err - type error
+ */
+void corrupt_ota_data(corrupt_ota_data_t err)
+{
+    esp_ota_select_entry_t ota_data[2];
+
+    const esp_partition_t *otadata_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL);
+    TEST_ASSERT_NOT_EQUAL(NULL, otadata_partition);
+    get_ota_data(otadata_partition, &ota_data[0], &ota_data[1]);
+
+    if (err & CORR_CRC_1_SECTOR_OTA_DATA) {
+        ota_data[0].crc = 0;
+    }
+    if (err & CORR_CRC_2_SECTOR_OTA_DATA) {
+        ota_data[1].crc = 0;
+    }
+    TEST_ESP_OK(esp_partition_erase_range(otadata_partition, 0, otadata_partition->size));
+    write_ota_data(otadata_partition, &ota_data[0], 0);
+    write_ota_data(otadata_partition, &ota_data[1], 1);
+}
+
+#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST)
+/* @brief Sets the pin number to output and sets output level as low. After reboot (deep sleep) this pin keep the same level.
+ *
+ * The output level of the pad will be force locked and can not be changed.
+ * Power down or call gpio_hold_dis will disable this function.
+ *
+ * @param[in] num_pin - Pin number
+ */
+void set_output_pin(uint32_t num_pin)
+{
+    TEST_ESP_OK(gpio_hold_dis(num_pin));
+
+    gpio_config_t io_conf;
+    io_conf.intr_type = GPIO_INTR_DISABLE;
+    io_conf.mode = GPIO_MODE_OUTPUT;
+    io_conf.pin_bit_mask = (1ULL << num_pin);
+    io_conf.pull_down_en = 0;
+    io_conf.pull_up_en = 0;
+    TEST_ESP_OK(gpio_config(&io_conf));
+
+    TEST_ESP_OK(gpio_set_level(num_pin, 0));
+    TEST_ESP_OK(gpio_hold_en(num_pin));
+}
+
+/* @brief Unset the pin number hold function.
+ */
+void reset_output_pin(uint32_t num_pin)
+{
+    TEST_ESP_OK(gpio_hold_dis(num_pin));
+    TEST_ESP_OK(gpio_reset_pin(num_pin));
+}
+#endif
+
+void mark_app_valid(void)
+{
+#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
+    TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback());
+#endif
+}
+
+const esp_partition_t* app_update(void)
+{
+    const esp_partition_t *cur_app = get_running_firmware();
+    const esp_partition_t* update_partition = esp_ota_get_next_update_partition(NULL);
+    TEST_ASSERT_NOT_NULL(update_partition);
+    esp_ota_handle_t update_handle = 0;
+    TEST_ESP_OK(esp_ota_begin(update_partition, OTA_SIZE_UNKNOWN, &update_handle));
+    copy_app_partition(update_handle, cur_app);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+    TEST_ESP_OK(esp_ota_set_boot_partition(update_partition));
+    return update_partition;
+}

components/app_update/test_apps/test_app_update/main/utils_update.h

@@ -0,0 +1,148 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_ota_ops.h"
+#include "esp_partition.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Enumeration for specifying which OTA data sectors' CRCs to corrupt.
+ */
+typedef enum {
+    CORR_CRC_1_SECTOR_OTA_DATA       = (1 << 0),   /*!< Corrupt CRC only 1 sector of ota_data */
+    CORR_CRC_2_SECTOR_OTA_DATA       = (1 << 1),   /*!< Corrupt CRC only 2 sector of ota_data */
+} corrupt_ota_data_t;
+
+/**
+ * @brief Set boot count value in NVS.
+ * @param boot_count Value to set.
+ */
+void set_boot_count_in_nvs(uint8_t boot_count);
+
+/**
+ * @brief Get boot count value from NVS.
+ * @return Boot count value.
+ */
+uint8_t get_boot_count_from_nvs(void);
+
+/**
+ * @brief Copy current app to next partition using OTA handle.
+ * @param update_handle OTA update handle.
+ * @param curr_app Current app partition.
+ */
+void copy_app_partition(esp_ota_handle_t update_handle, const esp_partition_t *curr_app);
+
+/**
+ * @brief Copy current app to next partition using OTA handle with offset.
+ * @param update_handle OTA update handle.
+ * @param curr_app Current app partition.
+ */
+void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app);
+
+/**
+ * @brief Get the next OTA update partition.
+ * @return Pointer to next OTA partition.
+ */
+const esp_partition_t * get_next_update_partition(void);
+
+/**
+ * @brief Copy current app to next partition and set boot partition.
+ * @param cur_app_partition Current app partition.
+ * @param next_app_partition Next app partition.
+ */
+void copy_current_app_to_next_part(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition);
+
+/**
+ * @brief Copy current app to next partition with offset and set boot partition.
+ * @param cur_app_partition Current app partition.
+ * @param next_app_partition Next app partition.
+ */
+void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition);
+
+/**
+ * @brief Erase OTA data partition.
+ */
+void erase_ota_data(void);
+
+/**
+ * @brief Reboot ESP using deep sleep mode.
+ */
+void reboot_as_deep_sleep(void);
+
+/**
+ * @brief Copy current app to next partition and reboot.
+ */
+void copy_current_app_to_next_part_and_reboot(void);
+
+/**
+ * @brief Copy current app to next partition with offset and reboot.
+ */
+void copy_current_app_to_next_part_with_offset_and_reboot(void);
+
+/**
+ * @brief Get running firmware partition.
+ * @return Pointer to running firmware partition.
+ */
+const esp_partition_t* get_running_firmware(void);
+
+/**
+ * @brief Get two OTA data copies from OTA data partition.
+ * @param otadata_partition OTA data partition.
+ * @param ota_data_0 First OTA data copy.
+ * @param ota_data_1 Second OTA data copy.
+ */
+void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data_0, esp_ota_select_entry_t *ota_data_1);
+
+/**
+ * @brief Write OTA data into required sector of OTA data partition.
+ * @param otadata_partition OTA data partition.
+ * @param ota_data OTA data structure.
+ * @param sec_id Sector number (0 or 1).
+ */
+void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id);
+
+/**
+ * @brief Corrupt OTA data for testing.
+ * @param err Type of corruption.
+ */
+void corrupt_ota_data(corrupt_ota_data_t err);
+
+#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST)
+/**
+ * @brief Set output pin to low and hold state.
+ * @param num_pin Pin number.
+ */
+void set_output_pin(uint32_t num_pin);
+
+/**
+ * @brief Reset output pin hold function.
+ * @param num_pin Pin number.
+ */
+void reset_output_pin(uint32_t num_pin);
+#endif
+
+/**
+ * @brief Mark app as valid and cancel rollback.
+ */
+void mark_app_valid(void);
+
+/**
+ * @brief Perform app update and set new boot partition.
+ * @return Pointer to updated partition.
+ */
+const esp_partition_t* app_update(void);
+
+#ifdef __cplusplus
+}
+#endif

components/app_update/test_apps/test_app_update/pytest_app_update_ut.py

@@ -20,7 +20,7 @@ TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_app_update(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
 
 
 @pytest.mark.generic
@@ -33,7 +33,7 @@ def test_app_update(dut: Dut) -> None:
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_app_update_xip_psram(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
 
 
 @pytest.mark.generic
@@ -46,7 +46,7 @@ def test_app_update_xip_psram(dut: Dut) -> None:
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
 
 
 @pytest.mark.generic
@@ -59,4 +59,19 @@ def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
 )
 @idf_parametrize('target', ['esp32', 'esp32c3', 'esp32s3', 'esp32p4'], indirect=['target'])
 def test_app_update_with_rollback(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)
+    dut.run_all_single_board_cases(timeout=180)
+
+
+@pytest.mark.recovery_bootloader
+@pytest.mark.parametrize(
+    'config',
+    ['recovery_bootloader'],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32c5'], indirect=['target'])
+def test_recovery_bootloader_update(dut: Dut) -> None:
+    try:
+        dut.run_all_single_board_cases(group='recovery_bootloader', timeout=90)
+    finally:
+        # Erase recovery bootloader after test because it may interfere with other tests using this runner
+        dut.serial.erase_flash()

components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader

@@ -0,0 +1,3 @@
+CONFIG_BOOTLOADER_RECOVERY_ENABLE=y
+CONFIG_BOOTLOADER_RECOVERY_OFFSET=0x3F0000
+CONFIG_PARTITION_TABLE_OFFSET=0x9000

components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c5

@@ -0,0 +1,2 @@
+# ESP32C5 supports the Recovery bootloader feature in ROM starting from v1.0 (ECO2)
+CONFIG_IDF_TARGET="esp32c5"

components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c61

@@ -0,0 +1,2 @@
+# ESP32C61 supports the Recovery bootloader feature in ROM starting from v1.0 (ECO3)
+CONFIG_IDF_TARGET="esp32c61"

components/bootloader/Kconfig.bootloader_rollback

@@ -1,8 +1,37 @@
-menu "Bootloader Rollback"
+menu "Recovery Bootloader and Rollback"
+
+    config BOOTLOADER_RECOVERY_ENABLE
+        bool "Enable Recovery Bootloader"
+        depends on SOC_RECOVERY_BOOTLOADER_SUPPORTED
+        default n
+        help
+            The recovery bootloader feature is implemented in the ROM bootloader. It is required for safe OTA
+            updates of the bootloader. The feature is activated when the eFuse field
+            (ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR) is set, which defines the flash address of the
+            recovery bootloader. If activated and the primary bootloader fails to load, the ROM bootloader
+            will attempt to load the recovery bootloader from the address specified in eFuse.
+
+    config BOOTLOADER_RECOVERY_OFFSET
+        hex "Recovery Bootloader Flash Offset"
+        depends on BOOTLOADER_RECOVERY_ENABLE
+        default 0x3F0000
+        range 0x0 0xFFE000
+        help
+            Flash address where the recovery bootloader is stored.
+            This value must be written to the eFuse field (ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR)
+            to activate the recovery bootloader in the ROM bootloader. The eFuse can be programmed
+            using espefuse.py or in the user application with the API esp_efuse_set_recovery_bootloader_offset().
+            Setting this value in the config allows parttool.py to verify that it does not overlap with existing
+            partitions in the partition table.
+
+            The address must be a multiple of the flash sector size (0x1000 bytes).
+            The eFuse field stores the offset in sectors.
+            If the feature is no longer needed or unused, you can burn the 0xFFF value to disable this feature in
+            the ROM bootloader.
 
     config BOOTLOADER_ANTI_ROLLBACK_ENABLE
         bool "Enable bootloader rollback support"
-        depends on SOC_RECOVERY_BOOTLOADER_SUPPORTED
+        depends on BOOTLOADER_RECOVERY_ENABLE
         default n
         help
             This option prevents rollback to previous bootloader image with lower security version.

components/bootloader/Kconfig.log.settings

@@ -21,6 +21,7 @@ menu "Settings"
         config BOOTLOADER_LOG_MODE_BINARY
             bool "Binary Log Mode"
             select BOOTLOADER_LOG_MODE_BINARY_EN
+            depends on BOOTLOADER_LOG_VERSION_2
             help
                 Enables binary logging with host-side format string expansion. In this mode, the
                 format argument of ESP_LOGx, ESP_EARLY_LOG, and ESP_DRAM_LOG macros is stored in a

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -136,7 +136,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 #if ESP_TEE_BUILD
 #include "esp_fault.h"
 #include "esp_flash_partitions.h"
-#include "esp32c6/rom/spi_flash.h"
+#include "rom/spi_flash.h"
 
 extern bool esp_tee_flash_check_paddr_in_active_tee_part(size_t paddr);
 #endif

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -55,7 +55,8 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
+    mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -52,7 +52,8 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
-    mspi_ll_fast_set_hs_divider(6);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
+    mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,6 +18,7 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 #include "hal/mspi_ll.h"
+#include "hal/clk_tree_ll.h"
 #include "soc/pcr_reg.h"
 
 static const char *TAG = "boot.esp32h21";
@@ -80,7 +81,9 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 
 static void IRAM_ATTR bootloader_flash_clock_init(void)
 {
-    // At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed
+    // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
+    // (FPGA image fixed MSPI0/1 clock to 64MHz)
+    clk_ll_xtal_x2_enable();
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
 }
 

components/bootloader_support/private_include/bootloader_soc.h

@@ -25,12 +25,11 @@ void bootloader_ana_super_wdt_reset_config(bool enable);
 void bootloader_ana_clock_glitch_reset_config(bool enable);
 
 /**
- * @brief Configure analog power glitch reset & glitch reset dref
+ * @brief Configure analog power glitch reset
  *
  * @param enable Boolean to enable or disable power glitch reset
- * @param dref voltage threshold
  */
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
+void bootloader_power_glitch_reset_config(bool enable);
 
 #ifdef __cplusplus
 }

components/bootloader_support/src/bootloader_clock_init.c

@@ -18,7 +18,7 @@
 #include "soc/pmu_reg.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32
 #include "hal/clk_tree_ll.h"
 #endif
 #include "esp_rom_sys.h"

components/bootloader_support/src/bootloader_common_loader.c

@@ -28,6 +28,7 @@
 
 #define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
 #define IS_FIELD_SET(rev_full) (((rev_full) != 65535) && ((rev_full) != 0))
+#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
 static const char* TAG = "boot_comm";
 
@@ -264,7 +265,10 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
 #if ESP_ROM_HAS_LP_ROM
     #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW)
 #else
-    #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t))
+    /* Since the structure containing the retain_mem_t is aligned on 8 by the linker, make sure we align this
+     * structure size here too */
+    #define RETAIN_MEM_SIZE     ALIGN_UP(sizeof(rtc_retain_mem_t), 8)
+    #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE)
 #endif //ESP_ROM_HAS_LP_ROM
     static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR;
     return s_bootloader_retain_mem;

components/bootloader_support/src/bootloader_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,6 +19,7 @@
 #include "hal/wdt_hal.h"
 #include "hal/efuse_hal.h"
 #include "esp_bootloader_desc.h"
+#include "esp_rom_sys.h"
 
 static const char *TAG = "boot";
 
@@ -34,7 +35,12 @@ void bootloader_clear_bss_section(void)
 esp_err_t bootloader_read_bootloader_header(void)
 {
     /* load bootloader image header */
-    if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) {
+#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
+    const uint32_t bootloader_flash_offset = esp_rom_get_bootloader_offset();
+#else
+    const uint32_t bootloader_flash_offset = ESP_PRIMARY_BOOTLOADER_OFFSET;
+#endif
+    if (bootloader_flash_read(bootloader_flash_offset, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) {
         ESP_EARLY_LOGE(TAG, "failed to load bootloader image header!");
         return ESP_FAIL;
     }

components/bootloader_support/src/bootloader_mem.c

@@ -25,20 +25,19 @@ void bootloader_init_mem(void)
      * So, at boot disabling these filters. They will enable as per the
      * use case by TEE initialization code.
      */
-#ifdef SOC_APM_CTRL_FILTER_SUPPORTED
-    apm_hal_apm_ctrl_filter_enable_all(false);
-    /* [APM] On power-up, only the HP CPU starts in TEE mode; others default to REE2.
-     * APM blocks REE0–REE2 access by default. C5 ECO2 adds per-peripheral control
-     * (default REEx blocking), but config support is pending. As a workaround,
-     * all masters are set to TEE mode.
+#if SOC_APM_CTRL_FILTER_SUPPORTED
+    apm_hal_enable_ctrl_filter_all(false);
+    /* [APM] On power-up, only the HP CPU starts in TEE mode; others
+     * default to REE2. APM blocks REE0–REE2 access by default.
+     * Thus, all masters are set to TEE mode.
      */
 #if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
-    apm_tee_hal_set_master_secure_mode_all(APM_LL_SECURE_MODE_TEE);
+    apm_hal_set_master_sec_mode_all(APM_SEC_MODE_TEE);
 #endif // SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
 #endif // SOC_APM_CTRL_FILTER_SUPPORTED
 #endif
 
-#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
+#if CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
     // protect memory region
     esp_cpu_configure_region_protection();
 #endif

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;

components/bootloader_support/src/bootloader_random_esp32c6.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_2;

components/bootloader_support/src/bootloader_random_esp32c61.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;

components/bootloader_support/src/bootloader_random_esp32h2.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.atten = ADC_ATTEN_DB_2_5;

components/bootloader_support/src/bootloader_random_esp32p4.c

@@ -1,108 +1,72 @@
 /*
  * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+#include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "soc/soc.h"
-#include "soc/adc_reg.h"
-#include "soc/pmu_reg.h"
-#include "soc/regi2c_saradc.h"
-#include "soc/hp_sys_clkrst_reg.h"
-#include "soc/lp_adc_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "esp_rom_regi2c.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
 
-// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
+#include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 
 #define I2C_SAR_ADC_INIT_CODE_VAL 2166
 
-typedef struct {
-    int atten;
-    int channel;
-} pattern_item;
-
-typedef struct {
-    pattern_item item[4];
-} pattern_table;
-
-static void adc1_fix_initcode_set(uint32_t initcode_value)
-{
-    uint32_t msb = initcode_value >> 8;
-    uint32_t lsb = initcode_value & 0xff;
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
-}
-
-//total 4 tables
-static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
-{
-    uint32_t wdata = 0;
-    wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
-            table.item[1].channel << 14|table.item[1].atten << 12 |
-            table.item[2].channel << 8 |table.item[2].atten << 6 |
-            table.item[3].channel << 2 |table.item[3].atten);
-    WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
-}
-
 void bootloader_random_enable(void)
 {
-    pattern_table sar1_table[4] = {};
-    uint32_t pattern_len = 0;
+    _adc_ll_reset_register();
+    _adc_ll_enable_bus_clock(true);
 
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(0, 0, 0);
 
-    SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
-
-    uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
-
-    SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_enable();
+#else
+    regi2c_ctrl_ll_i2c_sar_periph_enable();
+#endif
 
     // enable analog i2c master clock for RNG runtime
     ANALOG_CLOCK_ENABLE();
 
-    adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_regi2c_init();
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
 
-    //  cfg pattern table
-    sar1_table[0].item[0].channel = 10; //rand() % 6;
-    sar1_table[0].item[0].atten = 3;
-    sar1_table[0].item[1].channel = 10;
-    sar1_table[0].item[1].atten = 3;
-    sar1_table[0].item[2].channel = 10;
-    sar1_table[0].item[2].atten = 3;
-    sar1_table[0].item[3].channel = 10;
-    sar1_table[0].item[3].atten = 3;
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.unit = ADC_UNIT_1;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_10;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 1, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 2, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 3, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
 
-    hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
+    adc_ll_digi_set_power_manage(ADC_UNIT_1, ADC_LL_POWER_SW_ON);
 
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
-
-    CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
-    SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
-    SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
-
-    while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
-
-    SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(100);
+    adc_ll_digi_trigger_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_regi2c_adc_deinit();
+
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_disable();
+#endif
+
     // disable analog i2c master clock
     ANALOG_CLOCK_DISABLE();
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
 }

components/bootloader_support/src/bootloader_utility.c

@@ -717,7 +717,25 @@ static void load_image(const esp_image_metadata_t *image_data)
      */
     ESP_LOGI(TAG, "Checking flash encryption...");
     bool flash_encryption_enabled = esp_flash_encrypt_state();
-    if (!flash_encryption_enabled) {
+    if (flash_encryption_enabled) {
+#if BOOTLOADER_BUILD
+        /* Ensure security eFuses are burnt */
+        esp_efuse_batch_write_begin();
+        esp_err_t err = esp_flash_encryption_enable_secure_features();
+        if (err != ESP_OK) {
+            ESP_LOGE(TAG, "Error setting security eFuses (err=0x%x).", err);
+            esp_efuse_batch_write_cancel();
+            return;
+        }
+
+        err = esp_efuse_batch_write_commit();
+        if (err != ESP_OK) {
+            ESP_LOGE(TAG, "Error programming security eFuses (err=0x%x).", err);
+            return;
+        }
+        ESP_LOGI(TAG, "Security eFuses are burnt");
+#endif // BOOTLOADER_BUILD
+    } else {
 #ifdef CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED
         ESP_LOGE(TAG, "flash encryption is not enabled, and SECURE_FLASH_REQUIRE_ALREADY_ENABLED is set, refusing to boot.");
         return;

components/bootloader_support/src/esp32/bootloader_esp32.c

@@ -167,7 +167,7 @@ esp_err_t bootloader_init(void)
 
 #if XCHAL_ERRATUM_572
     uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
-    WSR(MEMCTL, memctl);
+    WSR(XT_REG_MEMCTL, memctl);
 #endif // XCHAL_ERRATUM_572
 
 // In RAM_APP, memory will be initialized in `call_start_cpu0`

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -86,7 +86,6 @@ static void bootloader_super_wdt_auto_feed(void)
 static inline void bootloader_hardware_init(void)
 {
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
-    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 
@@ -94,11 +93,7 @@ static inline void bootloader_ana_reset_config(void)
 {
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
-    if (efuse_hal_chip_revision() == 0) {
-        // decrease power glitch reset voltage to avoid start the glitch reset
-        uint8_t power_glitch_dref = 0;
-        bootloader_power_glitch_reset_config(true, power_glitch_dref);
-    }
+    bootloader_power_glitch_reset_config(true);
 }
 
 esp_err_t bootloader_init(void)

components/bootloader_support/src/esp32c5/bootloader_soc.c

@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
     (void)enable;
 }
 
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+void bootloader_power_glitch_reset_config(bool enable)
 {
-    assert(dref < 8);
-    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    //only detect VDDPST POWER GLITCH
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_XTAL, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
+
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO1
     if (enable) {
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
-        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO1
     } else {
         REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
     }

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -87,7 +87,6 @@ static void bootloader_super_wdt_auto_feed(void)
 static inline void bootloader_hardware_init(void)
 {
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
-    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 
@@ -95,8 +94,7 @@ static inline void bootloader_ana_reset_config(void)
 {
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
-    uint8_t power_glitch_dref = 0;
-    bootloader_power_glitch_reset_config(true, power_glitch_dref);
+    bootloader_power_glitch_reset_config(true);
 }
 
 esp_err_t bootloader_init(void)

components/bootloader_support/src/esp32c61/bootloader_soc.c

@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
     (void)enable;
 }
 
-void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+void bootloader_power_glitch_reset_config(bool enable)
 {
-    assert(dref < 8);
-    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    //only detect VDDPST POWER GLITCH
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
+
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO2
     if (enable) {
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
-        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
-        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO2
     } else {
         REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
     }

components/bootloader_support/src/esp32h2/secure_boot_secure_features.c

@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <strings.h>
+#include "hal/ecdsa_ll.h"
 #include "esp_flash_encrypt.h"
 #include "esp_secure_boot.h"
 #include "esp_efuse.h"
@@ -36,6 +37,12 @@ esp_err_t esp_secure_boot_enable_secure_features(void)
     ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
 #endif
 
+#ifdef SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
+    }
+#endif
+
 #ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
     ESP_LOGI(TAG, "Disable hardware & software JTAG...");
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);

components/bootloader_support/src/esp32h21/bootloader_esp32h21.c

@@ -89,8 +89,7 @@ static inline void bootloader_hardware_init(void)
     CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
 
-    //TODO: [ESP32H21] IDF-11550, regi2c atomic clock
-    regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_configure_clock();
 }
 

components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

@@ -144,7 +144,7 @@ esp_err_t bootloader_init(void)
 
 #if XCHAL_ERRATUM_572
     uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
-    WSR(MEMCTL, memctl);
+    WSR(XT_REG_MEMCTL, memctl);
 #endif // XCHAL_ERRATUM_572
 
     bootloader_ana_reset_config();

components/bootloader_support/src/esp_image_format.c

@@ -23,6 +23,7 @@
 #include "soc/soc_caps.h"
 #include "hal/cache_ll.h"
 #include "spi_flash_mmap.h"
+#include "hal/efuse_hal.h"
 
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
@@ -119,11 +120,26 @@ void esp_image_bootloader_offset_set(const uint32_t offset)
 {
     s_bootloader_partition_offset = offset;
     ESP_LOGI(TAG, "Bootloader offsets for PRIMARY: 0x%x, Secondary: 0x%" PRIx32, ESP_PRIMARY_BOOTLOADER_OFFSET, s_bootloader_partition_offset);
+#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
+    uint32_t recovery_offset = efuse_hal_get_recovery_bootloader_address();
+    if (efuse_hal_recovery_bootloader_enabled()) {
+        ESP_LOGI(TAG, "Bootloader offset for RECOVERY: 0x%" PRIx32, recovery_offset);
+    } else if (recovery_offset == 0) {
+        ESP_LOGI(TAG, "Bootloader offset for RECOVERY: has not been set yet");
+    } else {
+        ESP_LOGI(TAG, "Bootloader offset for RECOVERY: is disabled");
+    }
+#endif
 }
 
 static bool is_bootloader(uint32_t offset)
 {
-    return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET) || (offset == s_bootloader_partition_offset));
+    return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET)
+         || (offset == s_bootloader_partition_offset)
+#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
+         || (efuse_hal_recovery_bootloader_enabled() ? offset == efuse_hal_get_recovery_bootloader_address() : false)
+#endif
+    );
 }
 
 static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data)
@@ -796,20 +812,27 @@ static esp_err_t verify_segment_header(int index, const esp_image_segment_header
     bool map_segment = should_map(load_addr);
 
 #if SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    esp_err_t err = ESP_FAIL;
+
     /* ESP APP descriptor is present in the DROM segment #0 */
     if (index == 0 && !is_bootloader(metadata->start_addr)) {
-        const esp_app_desc_t *app_desc = (const esp_app_desc_t *)bootloader_mmap(segment_data_offs, sizeof(esp_app_desc_t));
-        if (!app_desc || app_desc->magic_word != ESP_APP_DESC_MAGIC_WORD) {
+        uint32_t mmu_page_size = 0, magic_word = 0;
+        const uint32_t mmu_page_size_offset = segment_data_offs + offsetof(esp_app_desc_t, mmu_page_size);
+        CHECK_ERR(bootloader_flash_read(segment_data_offs, &magic_word, sizeof(uint32_t), true));
+        CHECK_ERR(bootloader_flash_read(mmu_page_size_offset, &mmu_page_size, sizeof(uint32_t), true));
+        // Extract only the lowest byte from mmu_page_size (as per image format)
+        mmu_page_size &= 0xFF;
+
+        if (magic_word != ESP_APP_DESC_MAGIC_WORD) {
             ESP_LOGE(TAG, "Failed to fetch app description header!");
             return ESP_FAIL;
         }
 
         // Convert from log base 2 number to actual size while handling legacy image case (value 0)
-        metadata->mmu_page_size = (app_desc->mmu_page_size > 0) ? (1UL << app_desc->mmu_page_size) : SPI_FLASH_MMU_PAGE_SIZE;
+        metadata->mmu_page_size = (mmu_page_size > 0) ? (1UL << mmu_page_size) : SPI_FLASH_MMU_PAGE_SIZE;
         if (metadata->mmu_page_size != SPI_FLASH_MMU_PAGE_SIZE) {
             ESP_LOGI(TAG, "MMU page size mismatch, configured: 0x%x, found: 0x%"PRIx32, SPI_FLASH_MMU_PAGE_SIZE, metadata->mmu_page_size);
         }
-        bootloader_munmap(app_desc);
     } else if (index == 0 && is_bootloader(metadata->start_addr)) {
         // Bootloader always uses the default MMU page size
         metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
@@ -836,6 +859,10 @@ static esp_err_t verify_segment_header(int index, const esp_image_segment_header
     }
 
     return ESP_OK;
+#if SOC_MMU_PAGE_SIZE_CONFIGURABLE
+err:
+    return err;
+#endif
 }
 
 static bool should_map(uint32_t load_addr)

components/bootloader_support/src/secure_boot.c

@@ -12,6 +12,10 @@
 #include "esp_secure_boot.h"
 #include "hal/efuse_hal.h"
 
+#ifdef SOC_ECDSA_SUPPORTED
+#include "hal/ecdsa_ll.h"
+#endif
+
 #ifndef BOOTLOADER_BUILD
 static __attribute__((unused)) const char *TAG = "secure_boot";
 
@@ -341,15 +345,17 @@ bool esp_secure_boot_cfg_verify_release_mode(void)
     }
 
 #ifdef SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
-    secure = esp_efuse_read_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
-    if (!secure) {
-        uint8_t current_curve;
-        esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_ECDSA_CURVE_MODE, &current_curve, ESP_EFUSE_ECDSA_CURVE_MODE[0]->bit_count);
-        if (err == ESP_OK) {
-            if (current_curve != ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED) {
-                // If not P256 mode
-                result &= secure;
-                ESP_LOGW(TAG, "Not write disabled ECDSA curve mode (set WR_DIS_ECDSA_CURVE_MODE->1)");
+    if (ecdsa_ll_is_configurable_curve_supported()) {
+        secure = esp_efuse_read_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
+        if (!secure) {
+            uint8_t current_curve;
+            esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_ECDSA_CURVE_MODE, &current_curve, ESP_EFUSE_ECDSA_CURVE_MODE[0]->bit_count);
+            if (err == ESP_OK) {
+                if (current_curve != ESP_EFUSE_ECDSA_CURVE_MODE_ALLOW_ONLY_P256_BIT_LOCKED) {
+                    // If not P256 mode
+                    result &= secure;
+                    ESP_LOGW(TAG, "Not write disabled ECDSA curve mode (set WR_DIS_ECDSA_CURVE_MODE->1)");
+                }
             }
         }
     }

components/bt/CMakeLists.txt

@@ -29,7 +29,6 @@ set(common_include_dirs
 
 set(ble_mesh_include_dirs
     "esp_ble_mesh/common/include"
-    "esp_ble_mesh/common/tinycrypt/include"
     "esp_ble_mesh/core"
     "esp_ble_mesh/core/include"
     "esp_ble_mesh/core/storage"
@@ -42,6 +41,10 @@ set(ble_mesh_include_dirs
     "esp_ble_mesh/api"
 )
 
+set(ble_mesh_tinycrypt_dirs
+    "esp_ble_mesh/common/tinycrypt/include"
+)
+
 set(ble_mesh_v11_include_dirs
     "esp_ble_mesh/lib/include"
     "esp_ble_mesh/v1.1/api/core/include"
@@ -500,21 +503,6 @@ if(CONFIG_BT_ENABLED)
                     "esp_ble_mesh/btc/btc_ble_mesh_prov.c"
                     "esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c"
                     "esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c"
-                    "esp_ble_mesh/common/tinycrypt/src/aes_decrypt.c"
-                    "esp_ble_mesh/common/tinycrypt/src/aes_encrypt.c"
-                    "esp_ble_mesh/common/tinycrypt/src/cbc_mode.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ccm_mode.c"
-                    "esp_ble_mesh/common/tinycrypt/src/cmac_mode.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ctr_mode.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ctr_prng.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ecc_dh.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ecc_dsa.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ecc_platform_specific.c"
-                    "esp_ble_mesh/common/tinycrypt/src/ecc.c"
-                    "esp_ble_mesh/common/tinycrypt/src/hmac_prng.c"
-                    "esp_ble_mesh/common/tinycrypt/src/hmac.c"
-                    "esp_ble_mesh/common/tinycrypt/src/sha256.c"
-                    "esp_ble_mesh/common/tinycrypt/src/utils.c"
                     "esp_ble_mesh/common/atomic.c"
                     "esp_ble_mesh/common/buf.c"
                     "esp_ble_mesh/common/common.c"
@@ -565,6 +553,26 @@ if(CONFIG_BT_ENABLED)
                     "esp_ble_mesh/models/server/state_binding.c"
                     "esp_ble_mesh/models/server/state_transition.c"
                     "esp_ble_mesh/models/server/time_scene_server.c")
+
+        if(NOT CONFIG_BLE_MESH_USE_UNIFIED_CRYPTO)
+            list(APPEND include_dirs ${ble_mesh_tinycrypt_dirs})
+                list(APPEND srcs
+                    "esp_ble_mesh/common/tinycrypt/src/aes_decrypt.c"
+                    "esp_ble_mesh/common/tinycrypt/src/aes_encrypt.c"
+                    "esp_ble_mesh/common/tinycrypt/src/cbc_mode.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ccm_mode.c"
+                    "esp_ble_mesh/common/tinycrypt/src/cmac_mode.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ctr_mode.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ctr_prng.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ecc_dh.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ecc_dsa.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ecc_platform_specific.c"
+                    "esp_ble_mesh/common/tinycrypt/src/ecc.c"
+                    "esp_ble_mesh/common/tinycrypt/src/hmac_prng.c"
+                    "esp_ble_mesh/common/tinycrypt/src/hmac.c"
+                    "esp_ble_mesh/common/tinycrypt/src/sha256.c"
+                    "esp_ble_mesh/common/tinycrypt/src/utils.c")
+        endif()
         if(CONFIG_BLE_MESH_V11_SUPPORT)
             list(APPEND include_dirs ${ble_mesh_v11_include_dirs})
 

components/bt/common/Kconfig.in

@@ -48,7 +48,7 @@ config BT_BLE_LOG_SPI_OUT_LL_TASK_BUF_SIZE
     depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
     default 1024
     help
-        SPI transaction buffer size for upper layer task logs.
+        SPI transaction buffer size for lower layer task logs.
         There will be 2 SPI DMA buffers with the same size.
 
 config BT_BLE_LOG_SPI_OUT_LL_ISR_BUF_SIZE
@@ -56,9 +56,17 @@ config BT_BLE_LOG_SPI_OUT_LL_ISR_BUF_SIZE
     depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
     default 512
     help
-        SPI transaction buffer size for upper layer ISR logs.
+        SPI transaction buffer size for lower layer ISR logs.
         There will be 2 SPI DMA buffers with the same size.
 
+config BT_BLE_LOG_SPI_OUT_LL_HCI_BUF_SIZE
+    int "SPI transaction buffer size for lower layer HCI logs"
+    depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
+    default 512
+    help
+        SPI transaction buffer size for upper layer HCI logs.
+        There will be 2 SPI DMA buffers with the same size
+
 config BT_BLE_LOG_SPI_OUT_MOSI_IO_NUM
     int "GPIO number of SPI MOSI"
     depends on BT_BLE_LOG_SPI_OUT_ENABLED
@@ -94,6 +102,13 @@ config BT_BLE_LOG_SPI_OUT_SYNC_IO_NUM
     help
         GPIO number of SYNC IO
 
+config BT_BLE_LOG_SPI_OUT_TS_SYNC_SLEEP_SUPPORT
+    bool "Enable ble log & logic analyzer log time sync sleep support"
+    depends on BT_BLE_LOG_SPI_OUT_LL_ENABLED
+    default n
+    help
+        Enable ble log & logic analyzer log time sync sleep support
+
 config BT_BLE_LOG_SPI_OUT_FLUSH_TIMER_ENABLED
     bool "Enable periodic buffer flush out"
     depends on BT_BLE_LOG_SPI_OUT_ENABLED
@@ -108,3 +123,18 @@ config BT_BLE_LOG_SPI_OUT_FLUSH_TIMEOUT
     default 1000
     help
         Buffer flush out period in unit of ms
+
+config BT_BLE_LOG_SPI_OUT_LE_AUDIO_ENABLED
+    bool "Enable LE Audio log output to SPI"
+    depends on BT_BLE_LOG_SPI_OUT_ENABLED
+    default n
+    help
+        Enable LE Audio log output to SPI
+
+config BT_BLE_LOG_SPI_OUT_LE_AUDIO_BUF_SIZE
+    int "SPI transaction buffer size for LE Audio logs"
+    depends on BT_BLE_LOG_SPI_OUT_LE_AUDIO_ENABLED
+    default 1024
+    help
+        SPI transaction buffer size for LE Audio logs.
+        There will be 2 SPI DMA buffers with the same size.

components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h

@@ -14,27 +14,33 @@
 #include "esp_log.h"
 #include "freertos/semphr.h"
 
-// Public typedefs
-#define BLE_LOG_SPI_OUT_SOURCE_ESP 0
-#define BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY 1
-#define BLE_LOG_SPI_OUT_SOURCE_BLUEDROID 2
-#define BLE_LOG_SPI_OUT_SOURCE_NIMBLE 3
-#define BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM 4
-#define BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM 5
-#define BLE_LOG_SPI_OUT_SOURCE_ESP_ISR 6
-#define BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY_ISR 7
-#define BLE_LOG_SPI_OUT_SOURCE_USER 0x10
-#define BLE_LOG_SPI_OUT_SOURCE_SYNC 0xFE
-#define BLE_LOG_SPI_OUT_SOURCE_LOSS 0xFF
+// Public enums
+enum {
+    BLE_LOG_SPI_OUT_SOURCE_ESP = 0,
+    BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY,
+    BLE_LOG_SPI_OUT_SOURCE_BLUEDROID,
+    BLE_LOG_SPI_OUT_SOURCE_NIMBLE,
+    BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM,
+    BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM,
+    BLE_LOG_SPI_OUT_SOURCE_ESP_ISR,
+    BLE_LOG_SPI_OUT_SOURCE_ESP_LEGACY_ISR,
+    BLE_LOG_SPI_OUT_SOURCE_LL_HCI,
+    BLE_LOG_SPI_OUT_SOURCE_LE_AUDIO,
+    BLE_LOG_SPI_OUT_SOURCE_USER = 0x10,
+    BLE_LOG_SPI_OUT_SOURCE_SSC = 0xFD,
+    BLE_LOG_SPI_OUT_SOURCE_SYNC,
+    BLE_LOG_SPI_OUT_SOURCE_LOSS,
+};
 
-// SPI Log Level Definitions
-#define BLE_LOG_SPI_OUT_LEVEL_NONE      0  /*!< No log output */
-#define BLE_LOG_SPI_OUT_LEVEL_ERROR     1  /*!< Critical errors that SPI driver cannot recover from */
-#define BLE_LOG_SPI_OUT_LEVEL_WARN      2  /*!< Recoverable error conditions in SPI communication */
-#define BLE_LOG_SPI_OUT_LEVEL_INFO      3  /*!< Informational messages about SPI transactions */
-#define BLE_LOG_SPI_OUT_LEVEL_DEBUG     4  /*!< Detailed debug information, such as SPI register values */
-#define BLE_LOG_SPI_OUT_LEVEL_VERBOSE   5  /*!< Very detailed debugging logs, potentially flooding output */
-#define BLE_LOG_SPI_OUT_LEVEL_MAX       6  /*!< Number of SPI log levels supported */
+enum {
+    BLE_LOG_SPI_OUT_LEVEL_NONE = 0,
+    BLE_LOG_SPI_OUT_LEVEL_ERROR,
+    BLE_LOG_SPI_OUT_LEVEL_WARN,
+    BLE_LOG_SPI_OUT_LEVEL_INFO,
+    BLE_LOG_SPI_OUT_LEVEL_DEBUG,
+    BLE_LOG_SPI_OUT_LEVEL_VERBOSE,
+    BLE_LOG_SPI_OUT_LEVEL_MAX,
+};
 
 // Public functions
 int ble_log_spi_out_init(void);
@@ -50,5 +56,8 @@ int ble_log_spi_out_printf(uint8_t source, const char *format, ...);
 int ble_log_spi_out_printf_enh(uint8_t source, uint8_t level, const char *tag, const char *format, ...);
 int ble_log_spi_out_write_with_ts(uint8_t source, const uint8_t *addr, uint16_t len);
 void ble_log_spi_out_dump_all(void);
+void ble_log_spi_out_enable(bool enable);
+void ble_log_spi_out_flush(void);
+void ble_log_spi_out_le_audio_write(const uint8_t *addr, uint16_t len);
 
 #endif // __BT_SPI_OUT_H__

components/bt/common/btc/core/btc_task.c

@@ -490,10 +490,10 @@ static bt_status_t btc_init_mem(void) {
 #endif
 
 #if BTC_HF_INCLUDED == TRUE && HFP_DYNAMIC_MEMORY == TRUE
-    if ((hf_local_param_ptr = (hf_local_param_t *)osi_malloc(BTC_HF_NUM_CB * sizeof(hf_local_param_t))) == NULL) {
+    if ((hf_local_param_ptr = (hf_local_param_t *)osi_malloc(sizeof(hf_local_param_t))) == NULL) {
         goto error_exit;
     }
-    memset((void *)hf_local_param_ptr, 0, BTC_HF_NUM_CB * sizeof(hf_local_param_t));
+    memset((void *)hf_local_param_ptr, 0, sizeof(hf_local_param_t));
 #endif
 
 #if BTC_HF_CLIENT_INCLUDED == TRUE && HFP_DYNAMIC_MEMORY == TRUE

components/bt/controller/esp32/bt.c

@@ -965,7 +965,7 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles)
     assert(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US);
     // allow a maximum time uncertainty to be about 488ppm(1/2048) at least as clock drift
     // and set the timer in advance
-    uint32_t uncertainty = (us_to_sleep >> 11);
+    uint32_t uncertainty = (us_to_sleep / 1000);
     if (uncertainty < BTDM_MIN_TIMER_UNCERTAINTY_US) {
         uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US;
     }
@@ -1701,6 +1701,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 #if CONFIG_BT_BLE_LOG_SPI_OUT_ENABLED
     if (ble_log_spi_out_init() != 0) {
         ESP_LOGE(BTDM_LOG_TAG, "BLE Log SPI output init failed");
+        err = ESP_ERR_NO_MEM;
         goto error;
     }
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_ENABLED

components/bt/controller/esp32/hli_vectors.S

@@ -57,17 +57,17 @@ xt_highint4:
     wsr     a0, CCOMPARE2
 
     /* Enable Timer 2 interrupt */
-    rsr     a0, INTENABLE
+    rsr     a0, XT_REG_INTENABLE
     extui   a0, a0, 16, 1
     bnez    a0, 1f
     movi    a0, 0
-    xsr     a0, INTENABLE     /* disable all interrupts */
+    xsr     a0, XT_REG_INTENABLE     /* disable all interrupts */
     /* And a0 with (1 << 16) for Timer 2 interrupt mask */
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
-    wsr     a0, INTENABLE    /* Enable Timer 2 */
+    wsr     a0, XT_REG_INTENABLE    /* Enable Timer 2 */
 1:
 #endif
 
@@ -76,37 +76,37 @@ xt_highint4:
     s32i    a1, a0, 4
     s32i    a2, a0, 8
     s32i    a3, a0, 12
-    rsr     a2, EXCSAVE_4  /* holds the value of a0 */
+    rsr     a2, XT_REG_EXCSAVE_4  /* holds the value of a0 */
     s32i    a2, a0, 0
 
     /* Save special registers */
     addi    a0, a0, SPECREG_OFFSET
-    rsr     a2, WINDOWBASE
+    rsr     a2, XT_REG_WINDOWBASE
     s32i    a2, a0, 0
-    rsr     a2, WINDOWSTART
+    rsr     a2, XT_REG_WINDOWSTART
     s32i    a2, a0, 4
-    rsr     a2, SAR
+    rsr     a2, XT_REG_SAR
     s32i    a2, a0, 8
-    rsr     a2, LBEG
+    rsr     a2, XT_REG_LBEG
     s32i    a2, a0, 12
-    rsr     a2, LEND
+    rsr     a2, XT_REG_LEND
     s32i    a2, a0, 16
-    rsr     a2, LCOUNT
+    rsr     a2, XT_REG_LCOUNT
     s32i    a2, a0, 20
     rsr     a2, EPC1
     s32i    a2, a0, 24
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
     movi    a0, 0
-    xsr     a0, INTENABLE     /* disable all interrupts */
+    xsr     a0, XT_REG_INTENABLE     /* disable all interrupts */
     movi    a2, ~(1<<16)
     and     a0, a2, a0
-    wsr     a0, INTENABLE
+    wsr     a0, XT_REG_INTENABLE
 #endif
 
     /* disable exception mode, window overflow */
     movi    a0, PS_INTLEVEL(5) | PS_EXCM
-    wsr     a0, PS
+    wsr     a0, XT_REG_PS
     rsync
 
     /* Save the remaining physical registers.
@@ -153,12 +153,12 @@ xt_highint4:
     /* a0 still points to _l4_save_ctx */
 
     /* Can clear WINDOWSTART now, all registers are saved */
-    rsr     a2, WINDOWBASE
+    rsr     a2, XT_REG_WINDOWBASE
     /* WINDOWSTART = (1 << WINDOWBASE) */
     movi    a3, 1
     ssl     a2
     sll     a3, a3
-    wsr     a3, WINDOWSTART
+    wsr     a3, XT_REG_WINDOWSTART
 
 _highint4_stack_switch:
     movi    a0, 0
@@ -169,7 +169,7 @@ _highint4_stack_switch:
 
     /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
     movi    a6, PS_INTLEVEL(4) | PS_UM | PS_WOE
-    wsr     a6, PS
+    wsr     a6, XT_REG_PS
     rsync
 
     /* Call C handler */
@@ -180,7 +180,7 @@ _highint4_stack_switch:
 
     /* Done with C handler; re-enable exception mode, disabling window overflow */
     movi    a2, PS_INTLEVEL(5) | PS_EXCM    /* TOCHECK */
-    wsr     a2, PS
+    wsr     a2, XT_REG_PS
     rsync
 
     /* Restore the special registers.
@@ -188,13 +188,13 @@ _highint4_stack_switch:
      */
     movi    a0, _l4_save_ctx + SPECREG_OFFSET
     l32i    a2, a0, 8
-    wsr     a2, SAR
+    wsr     a2, XT_REG_SAR
     l32i    a2, a0, 12
-    wsr     a2, LBEG
+    wsr     a2, XT_REG_LBEG
     l32i    a2, a0, 16
-    wsr     a2, LEND
+    wsr     a2, XT_REG_LEND
     l32i    a2, a0, 20
-    wsr     a2, LCOUNT
+    wsr     a2, XT_REG_LCOUNT
     l32i    a2, a0, 24
     wsr     a2, EPC1
 
@@ -247,12 +247,12 @@ _highint4_stack_switch:
     movi    a0, _l4_save_ctx
 
     l32i    a2, a0, SPECREG_OFFSET + 4
-    wsr     a2, WINDOWSTART
+    wsr     a2, XT_REG_WINDOWSTART
 
     l32i    a1, a0, 4
     l32i    a2, a0, 8
     l32i    a3, a0, 12
-    rsr     a0, EXCSAVE_4  /* holds the value of a0 before the interrupt handler */
+    rsr     a0, XT_REG_EXCSAVE_4  /* holds the value of a0 before the interrupt handler */
 
     /* Return from the interrupt, restoring PS from EPS_4 */
     rfi     4

components/bt/controller/esp32c2/Kconfig.in

@@ -584,7 +584,7 @@ config BT_LE_CCA_RSSI_THRESH
     int "CCA RSSI threshold value"
     depends on BT_LE_TX_CCA_ENABLED
     range 20 100
-    default 20
+    default 65
     help
         Power threshold of CCA in unit of -1 dBm.
 

components/bt/controller/esp32c2/bt.c

@@ -119,6 +119,11 @@ struct ext_funcs_t {
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
 /* External functions or variables
@@ -411,20 +416,22 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }

components/bt/controller/esp32c3/Kconfig.in

@@ -231,7 +231,7 @@ config BT_CTRL_DFT_TX_POWER_LEVEL_EFF
 
 config BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP
     bool "BLE adv report flow control supported"
-    depends on (!BT_CTRL_RUN_IN_FLASH_ONLY) || (BT_CTRL_RUN_IN_FLASH_ONLY && BT_CTRL_BLE_SCAN)
+    depends on BT_CTRL_BLE_SCAN
     default y
     help
         The function is mainly used to enable flow control for advertising reports. When it is enabled,
@@ -530,30 +530,31 @@ config BT_CTRL_RUN_IN_FLASH_ONLY
         impact on Bluetooth performance.
 
 config BT_CTRL_DTM_ENABLE
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
     bool "Enable direct test mode feature"
-    default n
-
-config BT_CTRL_BLE_MASTER
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
-    bool "Enable BLE master role feature"
     default y
 
+config BT_CTRL_BLE_MASTER
+    bool "Enable BLE connection feature"
+    default y
+    help
+        If this option is disabled, it is not recommended to use connectable ADV.
+
 config BT_CTRL_BLE_TEST
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
-    bool "Enable BLE QA test feature"
+    bool "Enable BLE QA test feature (Not Used)"
     default n
 
 config BT_CTRL_BLE_SCAN
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
     bool "Enable BLE scan feature"
     default y
 
 config BT_CTRL_BLE_SECURITY_ENABLE
-    depends on BT_CTRL_RUN_IN_FLASH_ONLY
     bool "Enable BLE security feature"
     default y
 
+config BT_CTRL_BLE_ADV
+    bool "Enable BLE ADV feature"
+    default y
+
 config BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
     bool "Enable enhanced Access Address check in CONNECT_IND"
     default n

components/bt/controller/esp32c3/bt.c

@@ -312,6 +312,17 @@ extern void advFilter_stack_enableDupExcListVsCmd(bool en);
 extern void chanSel_stack_enableSetCsaVsCmd(bool en);
 #endif // (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
 
+extern void ble_dtm_funcs_reset(void);
+extern void ble_scan_funcs_reset(void);
+extern void ble_42_adv_funcs_reset(void);
+extern void ble_init_funcs_reset(void);
+extern void ble_con_funcs_reset(void);
+extern void ble_cca_funcs_reset(void);
+extern void ble_ext_adv_funcs_reset(void);
+extern void ble_ext_scan_funcs_reset(void);
+extern void ble_base_funcs_reset(void);
+extern void ble_enc_funcs_reset(void);
+
 extern uint32_t _bt_bss_start;
 extern uint32_t _bt_bss_end;
 extern uint32_t _bt_controller_bss_start;
@@ -1265,6 +1276,46 @@ static void btdm_funcs_table_ready_wrapper(void)
 #if BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED
     btdm_aa_check_enhance_enable();
 #endif
+#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
+    // do nothing
+#else
+    ESP_LOGI(BT_LOG_TAG, "Feature Config, ADV:%d, BLE_50:%d, DTM:%d, SCAN:%d, CCA:%d, SMP:%d, CONNECT:%d",
+                        BT_CTRL_BLE_ADV, BT_CTRL_50_FEATURE_SUPPORT, BT_CTRL_DTM_ENABLE, BT_CTRL_BLE_SCAN,
+                        BT_BLE_CCA_MODE, BLE_SECURITY_ENABLE, BT_CTRL_BLE_MASTER);
+
+    ble_base_funcs_reset();
+#if CONFIG_BT_CTRL_BLE_ADV
+    ble_42_adv_funcs_reset();
+#if (BT_CTRL_50_FEATURE_SUPPORT == 1)
+    ble_ext_adv_funcs_reset();
+#endif //
+#endif // CONFIG_BT_CTRL_BLE_ADV
+
+#if CONFIG_BT_CTRL_DTM_ENABLE
+    ble_dtm_funcs_reset();
+#endif // CONFIG_BT_CTRL_DTM_ENABLE
+
+#if CONFIG_BT_CTRL_BLE_SCAN
+    ble_scan_funcs_reset();
+#if (BT_CTRL_50_FEATURE_SUPPORT == 1)
+    ble_ext_scan_funcs_reset();
+#endif // (BT_CTRL_50_FEATURE_SUPPORT == 1)
+#endif // CONFIG_BT_CTRL_BLE_SCAN
+
+#if (BT_BLE_CCA_MODE != 0)
+    ble_cca_funcs_reset();
+#endif // (BT_BLE_CCA_MODE != 0)
+
+#if CONFIG_BT_CTRL_BLE_SECURITY_ENABLE
+    ble_enc_funcs_reset();
+#endif // CONFIG_BT_CTRL_BLE_SECURITY_ENABLE
+
+#if CONFIG_BT_CTRL_BLE_MASTER
+    ble_init_funcs_reset();
+    ble_con_funcs_reset();
+#endif // CONFIG_BT_CTRL_BLE_MASTER
+
+#endif // CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
 }
 
 bool bt_async_wakeup_request(void)

components/bt/controller/esp32c5/Kconfig.in

@@ -681,7 +681,7 @@ config BT_LE_CCA_RSSI_THRESH
     int "CCA RSSI threshold value"
     depends on BT_LE_TX_CCA_ENABLED
     range 20 100
-    default 20
+    default 65
     help
         Power threshold of CCA in unit of -1 dBm.
 
@@ -805,3 +805,10 @@ config BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX
 config BT_LE_RXBUF_OPT_ENABLED
     bool "Enable rxbuf optimization feature"
     default y
+
+config BT_LE_CTRL_FAST_CONN_DATA_TX_EN
+    bool "Enable fast sending of connection data"
+    default y
+    help
+        If this option is enabled, The Controller will continue to
+        Send an empty PDU after sending valid connection data within an interval.

components/bt/controller/esp32c5/bt.c

@@ -67,7 +67,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20240422
+#define EXT_FUNC_VERSION             0x20250415
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -98,14 +98,17 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
-    void (* _esp_reset_rpa_moudle)(void);
     uint32_t magic;
 };
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
-#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
+#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 /* External functions or variables
  ************************************************************************
  */
@@ -182,7 +185,6 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
-static void esp_reset_rpa_moudle(void);
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -459,15 +461,9 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
-    ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
-static void IRAM_ATTR esp_reset_rpa_moudle(void)
-{
-
-}
-
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {
@@ -1419,20 +1415,22 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }
@@ -1675,7 +1673,7 @@ int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
 #endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
 
 int IRAM_ATTR
-ble_capture_info_user_handler(uint8_t type, uint32_t reason)
+ble_capture_info_user_handler(uint8_t type, uint32_t reason, uint32_t param1, uint32_t param2)
 {
     int i;
 

components/bt/controller/esp32c5/esp_bt_cfg.h

@@ -192,6 +192,12 @@ extern "C" {
 #define DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX (0)
 #endif
 
+#if defined(CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#else
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0)
+#endif
+
 #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #else

components/bt/controller/esp32c6/Kconfig.in

@@ -721,7 +721,7 @@ config BT_LE_CCA_RSSI_THRESH
     int "CCA RSSI threshold value"
     depends on BT_LE_TX_CCA_ENABLED
     range 20 100
-    default 20
+    default 65
     help
         Power threshold of CCA in unit of -1 dBm.
 
@@ -839,3 +839,10 @@ config BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX
 config BT_LE_RXBUF_OPT_ENABLED
     bool "Enable rxbuf optimization feature"
     default y
+
+config BT_LE_CTRL_FAST_CONN_DATA_TX_EN
+    bool "Enable fast sending of connection data"
+    default y
+    help
+        If this option is enabled, The Controller will continue to
+        Send an empty PDU after sending valid connection data within an interval.

components/bt/controller/esp32c6/bt.c

@@ -58,6 +58,7 @@
 
 #include "hal/efuse_hal.h"
 #include "soc/rtc.h"
+#include "modem/modem_syscon_struct.h"
 
 #if CONFIG_BT_BLE_LOG_SPI_OUT_ENABLED
 #include "ble_log/ble_log_spi_out.h"
@@ -70,7 +71,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20240422
+#define EXT_FUNC_VERSION             0x20250415
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -101,17 +102,29 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
-    void (* _esp_reset_rpa_moudle)(void);
+#if CONFIG_IDF_TARGET_ESP32C6
+    void (* _esp_reset_modem)(uint8_t mdl_opts, uint8_t start);
+#endif // CONFIG_IDF_TARGET_ESP32C6
     uint32_t magic;
 };
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
 /* External functions or variables
  ************************************************************************
  */
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+extern void coex_hw_timer_set(uint8_t idx,uint8_t src, uint8_t pti,uint32_t latency, uint32_t perioidc);
+extern void coex_hw_timer_enable(uint8_t idx);
+extern void coex_hw_timer_disable(uint8_t idx);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
 extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
 extern int r_ble_controller_init(esp_bt_controller_config_t *cfg);
 extern void esp_ble_controller_info_capture(uint32_t cycle_times);
@@ -185,7 +198,9 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
-static void esp_reset_rpa_moudle(void);
+#if CONFIG_IDF_TARGET_ESP32C6
+static void esp_reset_modem(uint8_t mdl_opts,uint8_t start);
+#endif // CONFIG_IDF_TARGET_ESP32C6
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -463,15 +478,34 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
-    ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
+#if CONFIG_IDF_TARGET_ESP32C6
+    ._esp_reset_modem = esp_reset_modem,
+#endif // CONFIG_IDF_TARGET_ESP32C6
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
-static void IRAM_ATTR esp_reset_rpa_moudle(void)
+#if CONFIG_IDF_TARGET_ESP32C6
+static void IRAM_ATTR esp_reset_modem(uint8_t mdl_opts,uint8_t start)
 {
+    if (mdl_opts == 0x05) {
+        if (start) {
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            coex_hw_timer_set(0x04, 0x02, 15, 0, 5000);
+            coex_hw_timer_enable(0x04);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            MODEM_SYSCON.modem_rst_conf.val |= (BIT(16) | BIT(18));
+            MODEM_SYSCON.modem_rst_conf.val &= ~(BIT(16) | BIT(18));
+        } else {
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            coex_hw_timer_disable(0x04);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+        }
 
+    }
 }
 
+#endif // CONFIG_IDF_TARGET_ESP32C6
+
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {
@@ -1452,20 +1486,22 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }
@@ -1708,7 +1744,7 @@ int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
 #endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
 
 int IRAM_ATTR
-ble_capture_info_user_handler(uint8_t type, uint32_t reason)
+ble_capture_info_user_handler(uint8_t type, uint32_t reason, uint32_t param1, uint32_t param2)
 {
     int i;
 

components/bt/controller/esp32c6/esp_bt_cfg.h

@@ -195,6 +195,12 @@ extern "C" {
 #define DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX (0)
 #endif
 
+#if defined(CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#else
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0)
+#endif
+
 #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #else

components/bt/controller/esp32h2/Kconfig.in

@@ -716,7 +716,7 @@ config BT_LE_CCA_RSSI_THRESH
     int "CCA RSSI threshold value"
     depends on BT_LE_TX_CCA_ENABLED
     range 20 100
-    default 20
+    default 65
     help
         Power threshold of CCA in unit of -1 dBm.
 
@@ -843,3 +843,10 @@ config BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX
 config BT_LE_RXBUF_OPT_ENABLED
     bool "Enable rxbuf optimization feature"
     default y
+
+config BT_LE_CTRL_FAST_CONN_DATA_TX_EN
+    bool "Enable fast sending of connection data"
+    default y
+    help
+        If this option is enabled, The Controller will continue to
+        Send an empty PDU after sending valid connection data within an interval.

components/bt/controller/esp32h2/bt.c

@@ -66,7 +66,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20240422
+#define EXT_FUNC_VERSION             0x20250415
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -97,12 +97,16 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
-    void (* _esp_reset_rpa_moudle)(void);
     uint32_t magic;
 };
 
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 /* External functions or variables
  ************************************************************************
@@ -183,7 +187,6 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
-static void esp_reset_rpa_moudle(void);
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -460,15 +463,9 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
-    ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
-static void IRAM_ATTR esp_reset_rpa_moudle(void)
-{
-
-}
-
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {
@@ -1412,20 +1409,22 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
 #if !CONFIG_BT_LE_CONTROLLER_LOG_SPI_OUT_ENABLED
 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
-    bool end = flag ? true : false;
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     esp_bt_controller_log_storage(len, addr, end);
 #else // !CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
-    for (int i = 0; i < len; i++) {
-        esp_rom_printf("%02x ", addr[i]);
-    }
 
-    if (end) {
-        esp_rom_printf("\n");
+    if (len && addr) {
+        for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
     }
+    if (len_append && addr_append) {
+        for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
+    }
+    if (end) { esp_rom_printf("\n"); }
+
     portEXIT_CRITICAL_SAFE(&spinlock);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
 }
@@ -1667,7 +1666,7 @@ int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
 #endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
 
 int IRAM_ATTR
-ble_capture_info_user_handler(uint8_t type, uint32_t reason)
+ble_capture_info_user_handler(uint8_t type, uint32_t reason, uint32_t param1, uint32_t param2)
 {
     int i;
 

components/bt/controller/esp32h2/esp_bt_cfg.h

@@ -192,6 +192,12 @@ extern "C" {
 #define DEFAULT_BT_LE_CTRL_ADV_DATA_LENGTH_ZERO_AUX (0)
 #endif
 
+#if defined(CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (CONFIG_BT_LE_CTRL_FAST_CONN_DATA_TX_EN)
+#else
+#define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0)
+#endif
+
 #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART
 #else

components/bt/esp_ble_mesh/Kconfig.in

@@ -22,10 +22,17 @@ if BLE_MESH
             for mesh packets. And this could help avoid collision of
             advertising packets.
 
+    config BLE_MESH_USE_UNIFIED_CRYPTO
+        bool "Use the unified BLE tinycrypt implementation"
+        depends on !BT_LE_CRYPTO_STACK_MBEDTLS && !BT_NIMBLE_CRYPTO_STACK_MBEDTLS
+        default n
+        help
+            Enable this option to use the unified BLE tinycrypt solution
+            instead of the default one in BLE Mesh stack.
+
     menuconfig BLE_MESH_USE_BLE_50
         bool "Support using BLE 5.0 APIs for BLE Mesh"
         depends on BLE_MESH_EXPERIMENTAL
-        depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
         select BT_NIMBLE_50_FEATURE_SUPPORT if BT_NIMBLE_ENABLED
         select BT_NIMBLE_EXT_ADV if BT_NIMBLE_ENABLED
         select BT_BLE_50_FEATURES_SUPPORTED if BT_BLUEDROID_ENABLED
@@ -477,7 +484,7 @@ if BLE_MESH
         int "Maximum capacity of solicitation replay protection list"
         depends on BLE_MESH_PROXY_SOLIC_PDU_RX
         default 2
-        range 1 255
+        range 1 65536
         help
             This option specifies the maximum capacity of the solicitation replay
             protection list. The solicitation replay protection list is used to

components/bt/esp_ble_mesh/core/adv.c

@@ -94,17 +94,16 @@ static inline int adv_send(struct net_buf *buf)
 #if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
         if (BLE_MESH_ADV(buf)->type == BLE_MESH_ADV_PROXY_SOLIC) {
             bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL);
-            struct bt_mesh_adv_data solic_ad[3] = {
-                BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_FLAGS, (BLE_MESH_AD_GENERAL | BLE_MESH_AD_NO_BREDR)),
+            struct bt_mesh_adv_data solic_ad[2] = {
                 BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_UUID16_ALL, 0x59, 0x18),
                 BLE_MESH_ADV_DATA(BLE_MESH_DATA_SVC_DATA16, buf->data, buf->len),
             };
 #if CONFIG_BLE_MESH_USE_BLE_50
             param.primary_phy = BLE_MESH_ADV_PHY_1M;
             param.secondary_phy = BLE_MESH_ADV_PHY_1M;
-            err = bt_le_ext_adv_start(CONFIG_BLE_MESH_ADV_INST_ID, &param, &ad, 3, NULL, 0);
+            err = bt_le_ext_adv_start(CONFIG_BLE_MESH_ADV_INST_ID, &param, solic_ad, ARRAY_SIZE(solic_ad), NULL, 0);
 #else /* CONFIG_BLE_MESH_USE_BLE_50 */
-            err = bt_le_adv_start(&param, &ad, 3, NULL, 0);
+            err = bt_le_adv_start(&param, solic_ad, ARRAY_SIZE(solic_ad), NULL, 0);
 #endif /* CONFIG_BLE_MESH_USE_BLE_50 */
         } else
 #endif

components/bt/esp_ble_mesh/core/adv_common.c

@@ -625,6 +625,9 @@ void bt_mesh_adv_common_init(void)
     bt_mesh_adv_type_init(BLE_MESH_ADV_DATA, &adv_queue, &adv_buf_pool, adv_alloc);
     bt_mesh_adv_type_init(BLE_MESH_ADV_BEACON, &adv_queue, &adv_buf_pool, adv_alloc);
     bt_mesh_adv_type_init(BLE_MESH_ADV_URI, &adv_queue, &adv_buf_pool, adv_alloc);
+#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
+    bt_mesh_adv_type_init(BLE_MESH_ADV_PROXY_SOLIC, &adv_queue, &adv_buf_pool, adv_alloc);
+#endif
 
 #if CONFIG_BLE_MESH_USE_BLE_50
     bt_mesh_adv_inst_init(BLE_MESH_ADV_INS, CONFIG_BLE_MESH_ADV_INST_ID);

components/bt/esp_ble_mesh/core/adv_common.h

@@ -140,6 +140,9 @@ enum bt_mesh_adv_type {
 #endif
     BLE_MESH_ADV_BEACON,
     BLE_MESH_ADV_URI,
+#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
+    BLE_MESH_ADV_PROXY_SOLIC,
+#endif
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
     BLE_MESH_ADV_BLE,
 #endif

components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c

@@ -667,7 +667,7 @@ int bt_le_ext_adv_start(const uint8_t inst_id,
         interval >>= 1;
         interval += (bt_mesh_get_rand() % (interval + 1));
 
-        BT_INFO("%u->%u", param->interval_min, interval);
+        BT_DBG("%u->%u", param->interval_min, interval);
     }
 #endif
 
@@ -2153,8 +2153,10 @@ static void bt_mesh_bta_gattc_cb(tBTA_GATTC_EVT event, tBTA_GATTC *p_data)
         for (i = 0; i < ARRAY_SIZE(bt_mesh_gattc_info); i++) {
             if (bt_mesh_gattc_info[i].conn.handle == handle) {
                 if (bt_mesh_gattc_info[i].wr_desc_done == false) {
-                    BT_DBG("Receive notification before finishing to write ccc");
+                    BT_WARN("Receive notification before finishing to write ccc");
+#if !CONFIG_BLE_MESH_BQB_TEST
                     return;
+#endif
                 }
 
                 conn = &bt_mesh_gattc_info[i].conn;

components/bt/esp_ble_mesh/core/ext_adv.c

@@ -70,6 +70,9 @@ static inline int adv_send(struct bt_mesh_adv_inst *inst, uint16_t *adv_duration
 #endif
 #if CONFIG_BLE_MESH_RELAY_ADV_BUF
     case BLE_MESH_ADV_RELAY_DATA:
+#endif
+#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
+    case BLE_MESH_ADV_PROXY_SOLIC:
 #endif
     case BLE_MESH_ADV_BEACON:
     case BLE_MESH_ADV_URI: {
@@ -96,9 +99,20 @@ static inline int adv_send(struct bt_mesh_adv_inst *inst, uint16_t *adv_duration
         param.primary_phy = BLE_MESH_ADV_PHY_1M;
         param.secondary_phy = BLE_MESH_ADV_PHY_1M;
 
-        bt_mesh_adv_buf_ref_debug(__func__, buf, 4U, BLE_MESH_BUF_REF_SMALL);
-
-        err = bt_le_ext_adv_start(inst->id, &param, &ad, 1, NULL, 0);
+#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
+        if (BLE_MESH_ADV(buf)->type == BLE_MESH_ADV_PROXY_SOLIC) {
+            bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL);
+            struct bt_mesh_adv_data solic_ad[2] = {
+                BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_UUID16_ALL, 0x59, 0x18),
+                BLE_MESH_ADV_DATA(BLE_MESH_DATA_SVC_DATA16, buf->data, buf->len),
+            };
+            err = bt_le_ext_adv_start(CONFIG_BLE_MESH_ADV_INST_ID, &param, solic_ad, ARRAY_SIZE(solic_ad), NULL, 0);
+        } else
+#endif
+        {
+            bt_mesh_adv_buf_ref_debug(__func__, buf, 4U, BLE_MESH_BUF_REF_SMALL);
+            err = bt_le_ext_adv_start(inst->id, &param, &ad, 1, NULL, 0);
+        }
         }
         break;
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
@@ -303,6 +317,7 @@ static uint32_t received_adv_evts_handle(uint32_t recv_evts)
 CONFIG_BLE_MESH_GATT_PROXY_SERVER
             if (unlikely(i == BLE_MESH_ADV_PROXY_INS)) {
                 BT_DBG("Mesh Proxy Advertising auto stop");
+                bt_mesh_proxy_server_adv_flag_set(false);
             } else
 #endif
             {
@@ -366,7 +381,7 @@ void bt_mesh_adv_update(void)
 {
 #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_SERVER
-    BT_WARN("Mesh Proxy Advertising stopped manually");
+    BT_DBG("Mesh Proxy Advertising stopped manually");
     bt_mesh_proxy_server_adv_stop();
     if (adv_insts[BLE_MESH_ADV_PROXY_INS].busy) {
         ble_mesh_adv_task_wakeup(ADV_TASK_PROXY_ADV_UPD_EVT);

components/bt/esp_ble_mesh/core/nimble_host/adapter.c

@@ -1223,7 +1223,7 @@ int bt_le_ext_adv_start(const uint8_t inst_id,
         interval >>= 1;
         interval += (bt_mesh_get_rand() % (interval + 1));
 
-        BT_INFO("%u->%u", param->interval_min, interval);
+        BT_DBG("%u->%u", param->interval_min, interval);
     }
 #endif
 

components/bt/esp_ble_mesh/core/proxy_client.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,7 +31,7 @@
 
 static struct bt_mesh_proxy_server {
     struct bt_mesh_conn *conn;
-
+    bt_mesh_addr_t addr;
     enum __attribute__((packed)) {
         CLI_NONE,
         CLI_PROV,
@@ -465,6 +465,7 @@ static void proxy_connected(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn, int
 
     server->conn = bt_mesh_conn_ref(conn);
     server->conn_type = CLI_NONE;
+    memcpy(&server->addr, addr, sizeof(bt_mesh_addr_t));
     net_buf_simple_reset(&server->buf);
 
 #if CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT
@@ -629,6 +630,12 @@ static ssize_t proxy_write_ccc(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn)
         return 0;
     }
 
+#if CONFIG_BLE_MESH_BQB_TEST
+    /* notify maybe received first */
+    if (server->conn_type == CLI_PROXY) {
+        return 0;
+    }
+#endif
     return -EINVAL;
 }
 
@@ -641,6 +648,16 @@ static ssize_t proxy_recv_ntf(struct bt_mesh_conn *conn, uint8_t *data, uint16_t
         return -ENOTCONN;
     }
 
+#if CONFIG_BLE_MESH_BQB_TEST
+    /* update conn type if notify received before write ccc */
+    if (server->conn_type == CLI_NONE) {
+        server->conn_type = CLI_PROXY;
+        if (proxy_client_connect_cb) {
+            proxy_client_connect_cb(&server->addr, server - servers, server->net_idx);
+        }
+    }
+#endif
+
     if (server->conn_type == CLI_PROXY) {
         return proxy_recv(conn, NULL, data, len, 0, 0);
     }

components/bt/esp_ble_mesh/core/proxy_server.c

@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -170,6 +170,11 @@ static void proxy_sar_timeout(struct k_work *work)
     bt_mesh_gatts_disconnect(client->conn, 0x13);
 }
 
+void bt_mesh_proxy_server_adv_flag_set(bool enable)
+{
+    proxy_adv_enabled = enable;
+}
+
 #if CONFIG_BLE_MESH_GATT_PROXY_SERVER
 /**
  * The following callbacks are used to notify proper information
@@ -853,7 +858,9 @@ static void proxy_connected(struct bt_mesh_conn *conn, uint8_t err)
     conn_count++;
 
     /* Since we use ADV_OPT_ONE_TIME */
-    proxy_adv_enabled = false;
+#if !CONFIG_BLE_MESH_USE_BLE_50
+    bt_mesh_proxy_server_adv_flag_set(false);
+#endif
 
 #if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX
     /* Before re-enabling advertising, stop advertising
@@ -1356,7 +1363,7 @@ int bt_mesh_proxy_server_segment_send(struct bt_mesh_conn *conn, uint8_t type,
     net_buf_simple_pull(msg, mtu);
 
     while (msg->len) {
-        if (msg->len + 1 < mtu) {
+        if (msg->len + 1 <= mtu) {
             net_buf_simple_push_u8(msg, BLE_MESH_PROXY_PDU_HDR(BLE_MESH_PROXY_SAR_LAST, type));
             proxy_send(conn, msg->data, msg->len);
             break;
@@ -1498,7 +1505,7 @@ static int node_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1529,7 +1536,7 @@ static int net_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1592,7 +1599,7 @@ static int private_node_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1636,7 +1643,7 @@ static int private_net_id_adv(struct bt_mesh_subnet *sub)
         return err;
     }
 
-    proxy_adv_enabled = true;
+    bt_mesh_proxy_server_adv_flag_set(true);
 
     return 0;
 }
@@ -1902,7 +1909,7 @@ int32_t bt_mesh_proxy_server_adv_start(void)
                             prov_sd, prov_sd_len) == 0) {
 #endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
-            proxy_adv_enabled = true;
+            bt_mesh_proxy_server_adv_flag_set(true);
 
             /* Advertise 60 seconds using fast interval */
             if (prov_fast_adv) {
@@ -1959,7 +1966,7 @@ int bt_mesh_proxy_server_adv_stop(void)
         return -EINVAL;
     }
 
-    proxy_adv_enabled = false;
+    bt_mesh_proxy_server_adv_flag_set(false);
     return 0;
 }
 
@@ -2022,7 +2029,7 @@ int bt_mesh_proxy_server_deinit(void)
     proxy_adv_inst = BLE_MESH_ADV_INS_UNUSED;
 #endif
 
-    proxy_adv_enabled = false;
+    bt_mesh_proxy_server_adv_flag_set(false);
     gatt_svc = MESH_GATT_NONE;
 
 #if CONFIG_BLE_MESH_GATT_PROXY_SERVER

components/bt/esp_ble_mesh/core/proxy_server.h

@@ -118,6 +118,7 @@ void bt_mesh_proxy_server_identity_stop(struct bt_mesh_subnet *sub);
 
 bool bt_mesh_proxy_server_relay(struct net_buf_simple *buf, uint16_t dst);
 void bt_mesh_proxy_server_addr_add(struct net_buf_simple *buf, uint16_t addr);
+void bt_mesh_proxy_server_adv_flag_set(bool enable);
 
 int bt_mesh_proxy_server_init(void);
 int bt_mesh_proxy_server_deinit(void);

components/bt/esp_ble_mesh/core/scan.c

@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -102,13 +102,14 @@ int bt_mesh_unprov_dev_info_query(uint8_t uuid[16], uint8_t addr[6],
 {
     uint8_t idx = 0;
     uint8_t cnt = 0;
+    uint8_t pair_num = unprov_dev_info_fifo.pair_num;
 
-    if (uuid == NULL || addr == NULL) {
+    if (uuid == NULL && addr == NULL) {
         BT_WARN("No available information to query");
         return -1;
     }
 
-    while (cnt < unprov_dev_info_fifo.pair_num) {
+    while (cnt < pair_num) {
         idx = (cnt + unprov_dev_info_fifo.start_idx) % BLE_MESH_STORE_UNPROV_INFO_MAX_NUM;
         if (query_type & BLE_MESH_STORE_UNPROV_INFO_QUERY_TYPE_UUID) {
             if (!memcmp(unprov_dev_info_fifo.info[idx].addr, addr, 6)) {
@@ -134,7 +135,7 @@ int bt_mesh_unprov_dev_info_query(uint8_t uuid[16], uint8_t addr[6],
         cnt++;
     }
 
-    if (cnt == unprov_dev_info_fifo.pair_num) {
+    if (cnt == pair_num) {
         return -1;
     }
 

components/bt/esp_ble_mesh/lib/ext.c

@@ -92,6 +92,9 @@ uint8_t __meshlib_var_BLE_MESH_ADV_RELAY_DATA = BLE_MESH_ADV_RELAY_DATA;
 #endif
 uint8_t __meshlib_var_BLE_MESH_ADV_BEACON = BLE_MESH_ADV_BEACON;
 uint8_t __meshlib_var_BLE_MESH_ADV_URI = BLE_MESH_ADV_URI;
+#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
+uint8_t __meshlib_var_BLE_MESH_ADV_PROXY_SOLIC = BLE_MESH_ADV_PROXY_SOLIC;
+#endif
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
 uint8_t __meshlib_var_BLE_MESH_ADV_BLE = BLE_MESH_ADV_BLE;
 #endif
@@ -1175,17 +1178,17 @@ uint8_t *bt_mesh_ext_net_get_dev_key_ca(void)
     return bt_mesh.dev_key_ca;
 }
 
-uint8_t bt_mesh_ext_net_get_rpl_count(void)
+uint16_t bt_mesh_ext_net_get_rpl_count(void)
 {
     return ARRAY_SIZE(bt_mesh.rpl);
 }
 
-uint16_t bt_mesh_ext_net_get_rpl_src(uint8_t index)
+uint16_t bt_mesh_ext_net_get_rpl_src(uint16_t index)
 {
     return bt_mesh.rpl[index].src;
 }
 
-void bt_mesh_ext_net_reset_rpl(uint8_t index)
+void bt_mesh_ext_net_reset_rpl(uint16_t index)
 {
     memset(&bt_mesh.rpl[index], 0, sizeof(bt_mesh.rpl[index]));
 }
@@ -3813,7 +3816,7 @@ void *bt_mesh_ext_brc_srv_get_bridge_table_entry(void *srv, uint8_t index)
 #endif /* CONFIG_BLE_MESH_BRC_SRV */
 }
 
-void *bt_mesh_ext_brc_srv_get_bridge_rpl(uint8_t index)
+void *bt_mesh_ext_brc_srv_get_bridge_rpl(uint16_t index)
 {
 #if CONFIG_BLE_MESH_BRC_SRV
     return &bridge_rpl[index];
@@ -4584,7 +4587,7 @@ typedef struct {
     uint16_t (*_bt_mesh_ext_sub_get_sbr_net_idx)(void *sub);
     void (*_bt_mesh_ext_sub_set_sbr_net_idx)(void *sub, uint16_t sbr_net_idx);
     void *(*_bt_mesh_ext_brc_srv_get_bridge_table_entry)(void *srv, uint8_t index);
-    void *(*_bt_mesh_ext_brc_srv_get_bridge_rpl)(uint8_t index);
+    void *(*_bt_mesh_ext_brc_srv_get_bridge_rpl)(uint16_t index);
 /* CONFIG_BLE_MESH_BRC_SRV */
 
 /* CONFIG_BLE_MESH_AGG_CLI */