fix(esp32) esp_secure_boot not compiling in C++

Merge branch 'contrib/github_pr_14339' into 'master'
Fix(pthread): Added linux port with empty functions to make pthread cxx example build. (GitHub PR) Closes IDFGH-13424 and IDFGH-13433 See merge request espressif/esp-idf!32785
2024-08-19 13:27:49 +02:00 · 2024-08-14 00:05:12 +08:00 · 2024-08-13 19:24:32 +08:00 · 2024-08-13 19:23:53 +08:00 · 2024-08-13 18:48:44 +08:00 · 2024-08-13 17:23:53 +08:00
4394 changed files with 149946 additions and 202501 deletions
@@ -1,4 +1,4 @@
 [codespell]
-skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart
+skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*,*.pem
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn
 write-changes = true
@@ -40,3 +40,5 @@ jobs:
            echo ""
            exit 1
          fi
+          # Run pre-commit for PowerShell scripts check
+          pre-commit run --hook-stage manual check-powershell-scripts --from-ref base_ref --to-ref pr_ref --show-diff-on-failure
@@ -96,6 +96,8 @@ dependencies.lock
 managed_components

 # pytest log
+pytest-embedded/
+# legacy one
 pytest_embedded_log/
 list_job*.txt
 size_info*.txt
@@ -30,4 +30,6 @@ include:
  - '.gitlab/ci/integration_test.yml'
  - '.gitlab/ci/host-test.yml'
  - '.gitlab/ci/deploy.yml'
+  - '.gitlab/ci/post_deploy.yml'
+  - '.gitlab/ci/retry_failed_jobs.yml'
  - '.gitlab/ci/test-win.yml'
@@ -119,6 +119,7 @@
 /components/fatfs/                    @esp-idf-codeowners/storage
 /components/freertos/                 @esp-idf-codeowners/system
 /components/hal/                      @esp-idf-codeowners/peripherals
+/components/hal/test_apps/crypto/     @esp-idf-codeowners/peripherals @esp-idf-codeowners/security
 /components/heap/                     @esp-idf-codeowners/system
 /components/http_parser/              @esp-idf-codeowners/app-utilities
 /components/idf_test/                 @esp-idf-codeowners/ci
@@ -139,6 +140,7 @@
 /components/protocomm/                @esp-idf-codeowners/app-utilities/provisioning
 /components/pthread/                  @esp-idf-codeowners/system
 /components/riscv/                    @esp-idf-codeowners/system
+/components/rt/                       @esp-idf-codeowners/system
 /components/sdmmc/                    @esp-idf-codeowners/storage
 /components/soc/                      @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
 /components/spi_flash/                @esp-idf-codeowners/peripherals
@@ -154,20 +156,22 @@
 /components/wpa_supplicant/           @esp-idf-codeowners/wifi @esp-idf-codeowners/app-utilities/mbedtls
 /components/xtensa/                   @esp-idf-codeowners/system

-/docs/                                   @esp-idf-codeowners/docs
-/docs/**/api-guides/tools/               @esp-idf-codeowners/tools
-/docs/en/api-guides/core_dump.rst        @esp-idf-codeowners/debugging
-/docs/en/api-guides/jtag-debugging/      @esp-idf-codeowners/debugging
-/docs/**/api-reference/bluetooth/        @esp-idf-codeowners/bluetooth
-/docs/**/api-reference/network/          @esp-idf-codeowners/network @esp-idf-codeowners/wifi
-/docs/**/api-reference/peripherals/      @esp-idf-codeowners/peripherals
-/docs/**/api-reference/peripherals/usb*  @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
-/docs/**/api-reference/protocols/        @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
-/docs/**/api-reference/provisioning/     @esp-idf-codeowners/app-utilities/provisioning
-/docs/**/api-reference/storage/          @esp-idf-codeowners/storage
-/docs/**/api-reference/system/           @esp-idf-codeowners/system
-/docs/**/security/                       @esp-idf-codeowners/security
-/docs/**/migration-guides/               @esp-idf-codeowners/docs @esp-idf-codeowners/all-maintainers
+/docs/                                      @esp-idf-codeowners/docs
+/docs/**/api-guides/tools/                  @esp-idf-codeowners/tools
+/docs/en/api-guides/core_dump.rst           @esp-idf-codeowners/debugging
+/docs/en/api-guides/jtag-debugging/         @esp-idf-codeowners/debugging
+/docs/**/api-reference/bluetooth/           @esp-idf-codeowners/bluetooth
+/docs/**/api-reference/network/             @esp-idf-codeowners/network @esp-idf-codeowners/wifi
+/docs/**/api-reference/peripherals/         @esp-idf-codeowners/peripherals
+/docs/**/api-reference/peripherals/usb*     @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
+/docs/**/api-reference/peripherals/usb*/    @esp-idf-codeowners/peripherals @esp-idf-codeowners/peripherals/usb
+/docs/**/api-reference/protocols/           @esp-idf-codeowners/network @esp-idf-codeowners/app-utilities
+/docs/**/api-reference/provisioning/        @esp-idf-codeowners/app-utilities/provisioning
+/docs/**/api-reference/storage/             @esp-idf-codeowners/storage
+/docs/**/api-reference/system/              @esp-idf-codeowners/system
+/docs/**/security/                          @esp-idf-codeowners/security
+/docs/**/migration-guides/                  @esp-idf-codeowners/docs @esp-idf-codeowners/all-maintainers
+/docs/**/contribute/install-pre-commit-hook.rst @esp-idf-codeowners/ci @esp-idf-codeowners/tools

 /examples/README.md           @esp-idf-codeowners/docs @esp-idf-codeowners/ci
 /examples/**/*.py             @esp-idf-codeowners/ci @esp-idf-codeowners/tools
@@ -56,7 +56,7 @@
  variables:
    IDF_TOOLCHAIN: clang
    TEST_BUILD_OPTS_EXTRA: ""
-    TEST_DIR: tools/test_apps/system/cxx_pthread_bluetooth
+    TEST_DIR: tools/test_apps/system/clang_build_test
  script:
    # CI specific options start from "--parallel-count xxx". could ignore when running locally
    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
@@ -112,6 +112,22 @@ fast_template_app:
    BUILD_COMMAND_ARGS: "-p"
 #------------------------------------------------------------------------------

+#######################
+# gnu_static_analyzer #
+#######################
+gcc_static_analyzer:
+  extends:
+    - .build_template_app_template
+    - .rules:build:target_test
+  stage: pre_check
+  tags: [build, shiny]
+  variables:
+    CI_CCACHE_DISABLE: 1
+    ANALYZING_APP: "examples/get-started/hello_world"
+  script:
+    - echo "CONFIG_COMPILER_STATIC_ANALYZER=y" >> ${ANALYZING_APP}/sdkconfig.defaults
+    - python -m idf_build_apps build -vv -p ${ANALYZING_APP} -t all
+
 ########################################
 # Clang Build Apps Without Tests Cases #
 ########################################
@@ -143,7 +159,7 @@ build_clang_test_apps_esp32s3:
    # For RISCV clang generates '.linker-options' sections of type 'llvm_linker_options' in asm files.
    # See (https://llvm.org/docs/Extensions.html#linker-options-section-linker-options).
    # Binutils gas ignores them with warning.
-    # TODO: LLVM-112, Use integrated assembler.
+    # TODO: LLVM-333, Use integrated assembler.
    TEST_BUILD_OPTS_EXTRA: "--ignore-warning-str 'Warning: unrecognized section type'"

 build_clang_test_apps_esp32c3:
@@ -164,11 +180,30 @@ build_clang_test_apps_esp32c6:
  extends:
    - .build_clang_test_apps_riscv
    - .rules:build
-  # TODO: c6 builds fail in master due to missing headers
-  allow_failure: true
  variables:
    IDF_TARGET: esp32c6

+build_clang_test_apps_esp32c5:
+  extends:
+    - .build_clang_test_apps_riscv
+    - .rules:build
+  variables:
+    IDF_TARGET: esp32c5
+
+build_clang_test_apps_esp32h2:
+  extends:
+    - .build_clang_test_apps_riscv
+    - .rules:build
+  variables:
+    IDF_TARGET: esp32h2
+
+build_clang_test_apps_esp32p4:
+  extends:
+    - .build_clang_test_apps_riscv
+    - .rules:build
+  variables:
+    IDF_TARGET: esp32p4
+
 ######################
 # Build System Tests #
 ######################
@@ -288,6 +323,7 @@ build_child_pipeline:
    MR_MODIFIED_FILES: $MR_MODIFIED_FILES
    PARENT_PIPELINE_ID: $CI_PIPELINE_ID
    BUILD_AND_TEST_ALL_APPS: $BUILD_AND_TEST_ALL_APPS
+    REPORT_EXIT_CODE: $REPORT_EXIT_CODE
  # https://gitlab.com/gitlab-org/gitlab/-/issues/214340
  inherit:
    variables: false
@@ -12,6 +12,7 @@ stages:
  - test_deploy
  - deploy
  - post_deploy
+  - retry_failed_jobs

 variables:
 # System environment
@@ -83,6 +84,12 @@ variables:
  # This is used only if CI_PYTHON_TOOL_REPO is not empty.
  CI_PYTHON_TOOL_BRANCH: ""

+  # Set this variable to Clang toolchain distro URL to be used.
+  # NOTE: We have separate toolchains for Xtensa and RISCV, therefore jobs for one arch will fail.
+  # This is OK as far as we use CI_CLANG_DISTRO_URL for pre-release tests purposes only.
+  # Keep the variable empty when not used.
+  CI_CLANG_DISTRO_URL: ""
+
  # Set this variable to specify the file name for the known failure cases.
  KNOWN_FAILURE_CASES_FILE_NAME: "master.txt"

@@ -96,6 +103,8 @@ variables:
  CCACHE_DIR: "/cache/idf_ccache"
  CCACHE_MAXSIZE: "50G"

+  FF_USE_NEW_BASH_EVAL_STRATEGY: "true"
+
 ################################################
 # `before_script` and `after_script` Templates #
 ################################################
@@ -152,7 +161,7 @@ variables:
  fi

  # Install esp-clang if necessary
-  if [[ "$IDF_TOOLCHAIN" == "clang" ]]; then
+  if [[ "$IDF_TOOLCHAIN" == "clang" && -z "$CI_CLANG_DISTRO_URL" ]]; then
    $IDF_PATH/tools/idf_tools.py --non-interactive install esp-clang
  fi

@@ -167,7 +176,7 @@ variables:

  source ./export.sh

-  # Custom clang
+  # Custom clang toolchain
  if [[ ! -z "$CI_CLANG_DISTRO_URL" ]]; then
    echo "Using custom clang from ${CI_CLANG_DISTRO_URL}"
    wget $CI_CLANG_DISTRO_URL
@@ -1,4 +1,4 @@
-# Extenal DangerJS
+# External DangerJS
 include:
  - project: espressif/shared-ci-dangerjs
    ref: master
@@ -10,7 +10,6 @@ run-danger-mr-linter:
    GIT_STRATEGY: none # no repo checkout
    ENABLE_CHECK_AREA_LABELS: 'true'
    ENABLE_CHECK_DOCS_TRANSLATION: 'true'
-    ENABLE_CHECK_RELEASE_NOTES_DESCRIPTION: 'true'
    ENABLE_CHECK_UPDATED_CHANGELOG: 'false'
  before_script: []
  cache: []
@@ -7,11 +7,10 @@
 #
 # This file should ONLY be used during bringup. Should be reset to empty after the bringup process
 extra_default_build_targets:
-  - esp32p4
  - esp32c5
+  - esp32c61

 bypass_check_test_targets:
-  - esp32c5
  - esp32c61
 #
 # These lines would
@@ -102,7 +102,7 @@ check_docs_lang_sync:
  parallel:
    matrix:
      - DOCLANG: ["en", "zh_CN"]
-        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c5","esp32h2", "esp32p4"]
+        DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32c61", "esp32c5","esp32h2", "esp32p4"]

 check_docs_gh_links:
  image: $ESP_IDF_DOC_ENV_IMAGE
@@ -171,6 +171,7 @@ build_docs_pdf:
    - job: fast_template_app
      artifacts: false
      optional: true
+  allow_failure: true # TODO IDFCI-2216
  artifacts:
    paths:
      - docs/_build/*/*/latex/*
@@ -182,6 +183,7 @@ build_docs_pdf_prod:
    - .build_docs_template
    - .doc-rules:build:docs-full-prod
  dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts
+  allow_failure: true # TODO IDFCI-2216
  artifacts:
    paths:
      - docs/_build/*/*/latex/*
@@ -133,7 +133,7 @@ test_cli_installer:
  script:
    # Tools must be downloaded for testing
    # We could use "idf_tools.py download all", but we don't want to install clang because of its huge size
-    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa
+    - python3 ${IDF_PATH}/tools/idf_tools.py download required qemu-riscv32 qemu-xtensa cmake
    - cd ${IDF_PATH}/tools/test_idf_tools
    - python3 -m pip install jsonschema
    - python3 ./test_idf_tools.py -v
@@ -228,6 +228,8 @@ test_tools:
    - pytest --noconftest test_idf_qemu.py     --junitxml=${IDF_PATH}/XUNIT_IDF_PY_QEMU.xml               || stat=1
    - cd ${IDF_PATH}/tools/test_mkdfu
    - pytest --noconftest test_mkdfu.py        --junitxml=${IDF_PATH}/XUNIT_MKDFU.xml                     || stat=1
+    - cd ${IDF_PATH}/tools/test_idf_size
+    - pytest --noconftest test_idf_size.py     --junitxml=${IDF_PATH}/XUNIT_IDF_SIZE.xml                  || stat=1
    - cd ${IDF_PATH}
    - shellcheck -s sh tools/detect_python.sh                                                             || stat=1
    - shellcheck -s bash tools/detect_python.sh                                                           || stat=1
@@ -296,17 +298,17 @@ test_pytest_qemu:
  artifacts:
    paths:
      - XUNIT_RESULT.xml
-      - pytest_embedded_log/
+      - pytest-embedded/
+      - "**/build*/*.bin"
    reports:
      junit: XUNIT_RESULT.xml
-  allow_failure: true # IDFCI-1752
  parallel:
    matrix:
      - IDF_TARGET: [esp32, esp32c3]
  variables:
    INSTALL_QEMU: 1
  script:
-    - run_cmd python tools/ci/ci_build_apps.py . -vv
+    - run_cmd python tools/ci/ci_build_apps.py . -v
      --target $IDF_TARGET
      --pytest-apps
      -m qemu
@@ -316,6 +318,7 @@ test_pytest_qemu:
    - python tools/ci/get_known_failure_cases_file.py
    - run_cmd pytest
      --target $IDF_TARGET
+      --log-cli-level DEBUG
      -m qemu
      --embedded-services idf,qemu
      --junitxml=XUNIT_RESULT.xml
@@ -330,12 +333,12 @@ test_pytest_linux:
  artifacts:
    paths:
      - XUNIT_RESULT.xml
-      - pytest_embedded_log/
+      - pytest-embedded/
      - "**/build*/build_log.txt"
    reports:
      junit: XUNIT_RESULT.xml
  script:
-    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -vv
+    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -v
      --target linux
      --pytest-apps
      -m host_test
@@ -346,6 +349,38 @@ test_pytest_linux:
    - run_cmd pytest
      --target linux
      -m host_test
+      --embedded-services idf
+      --junitxml=XUNIT_RESULT.xml
+      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
+      --app-info-filepattern \"list_job_*.txt\"
+
+test_pytest_macos:
+  extends:
+    - .host_test_template
+    - .before_script:build:macos
+  tags:
+    - macos_shell
+  artifacts:
+    paths:
+      - XUNIT_RESULT.xml
+      - pytest-embedded/
+      - "**/build*/build_log.txt"
+    reports:
+      junit: XUNIT_RESULT.xml
+  variables:
+    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
+  script:
+    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -vv
+      --target linux
+      --pytest-apps
+      -m \"host_test and macos_shell\"
+      --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt"
+      --modified-components ${MR_MODIFIED_COMPONENTS}
+      --modified-files ${MR_MODIFIED_FILES}
+    - python tools/ci/get_known_failure_cases_file.py
+    - run_cmd pytest
+      --target linux
+      -m \"host_test and macos_shell\"
      --junitxml=XUNIT_RESULT.xml
      --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
      --app-info-filepattern \"list_job_*.txt\"
@@ -360,5 +395,12 @@ test_idf_pytest_plugin:
    reports:
      junit: XUNIT_RESULT.xml
  script:
-    - cd tools/ci/idf_pytest
+    - cd ${IDF_PATH}/tools/ci/dynamic_pipelines/tests/test_report_generator
+    - python -m unittest test_report_generator.py
+    - cd ${IDF_PATH}/tools/ci/idf_pytest
    - pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
+
+test_idf_build_apps_load_soc_caps:
+  extends: .host_test_template
+  script:
+    - python tools/ci/check_soc_headers_load_in_idf_build_apps.py
@@ -0,0 +1,13 @@
+generate_failed_jobs_report:
+  stage: post_deploy
+  tags: [build, shiny]
+  image: $ESP_ENV_IMAGE
+  when: always
+  dependencies: []  # Do not download artifacts from the previous stages
+  artifacts:
+    expire_in: 1 week
+    when: always
+    paths:
+      - job_report.html
+  script:
+    - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type job
@@ -135,6 +135,7 @@ pipeline_variables:
    # MODIFIED_FILES is a list of files that changed, could be used everywhere
    - MODIFIED_FILES=$(echo "$GIT_DIFF_OUTPUT" | xargs)
    - echo "MODIFIED_FILES=$MODIFIED_FILES" >> pipeline.env
+    - echo "REPORT_EXIT_CODE=0" >> pipeline.env
    # MR_MODIFIED_FILES and MR_MODIFIED_COMPONENTS are semicolon separated lists that is used in MR only
    # for non MR pipeline, these are empty lists
    - |
@@ -157,6 +158,7 @@ pipeline_variables:
      if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
        echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
      fi
+    - python tools/ci/ci_process_description.py
    - cat pipeline.env
    - python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report
  artifacts:
@@ -45,3 +45,36 @@ check_pre_commit:
      paths:
        - .cache/submodule_archives
      policy: pull
+
+check_powershell:
+  extends:
+    - .before_script:minimal
+  stage: pre_check
+  image: docker:latest
+  services:
+    - docker:dind
+  tags:
+    - dind
+    - amd64
+  needs:
+    - pipeline_variables
+  variables:
+    # cache pre_commit
+    PRE_COMMIT_HOME: "$CI_PROJECT_DIR/.cache/pre-commit"
+  rules:
+    - changes:
+        - "*.ps1"
+  script:
+    - apk add python3
+    - apk add py3-pip
+    - pip install pre-commit --break-system-packages
+    - pre-commit run --hook-stage manual check-powershell-scripts --files $MODIFIED_FILES
+  cache:
+    - key: pre_commit-cache-${LATEST_GIT_TAG}
+      paths:
+        - .cache/pre-commit
+      policy: pull
+    - key: submodule-cache-${LATEST_GIT_TAG}
+      paths:
+        - .cache/submodule_archives
+      policy: pull
@@ -0,0 +1,14 @@
+retry_failed_jobs:
+  stage: retry_failed_jobs
+  tags: [shiny, fast_run]
+  image: $ESP_ENV_IMAGE
+  dependencies: null
+  before_script: []
+  cache: []
+  extends: []
+  script:
+    - echo "Retrieving and retrying all failed jobs for the pipeline..."
+    - python tools/ci/python_packages/gitlab_api.py retry_failed_jobs $CI_MERGE_REQUEST_PROJECT_ID --pipeline_id $CI_PIPELINE_ID
+  when: manual
+  needs:
+    - generate_failed_jobs_report
@@ -66,6 +66,8 @@
  - "tools/ci/check_esp_memory_utils_headers.sh"
  - "tools/ci/check_blobs.sh"
  - "tools/ci/check_public_headers.py"
+  - "tools/ci/check_register_rw_half_word.cmake"
+  - "tools/ci/check_register_rw_half_word.py"

 .patterns-host_test: &patterns-host_test
  - ".gitlab/ci/host-test.yml"
@@ -86,6 +88,7 @@
  - "tools/test_idf_py/**/*"

  - "tools/idf_size.py"
+  - "tools/test_idf_size/**/*"

  - "tools/tools.json"
  - "tools/tools_schema.json"
@@ -147,6 +150,7 @@

 .patterns-idf-pytest-plugin: &patterns-idf-pytest-plugin
  - "tools/ci/idf_pytest/**/*"
+  - "tools/ci/dynamic_pipelines/tests/**/*"

 ##############
 # if anchors #
@@ -31,7 +31,7 @@ test_cli_installer_win:
    IDF_PATH: "$CI_PROJECT_DIR"
  script:
    # Tools must be downloaded for testing
-    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa
+    - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa cmake
    - cd ${IDF_PATH}\tools\test_idf_tools
    - python -m pip install jsonschema
    - python .\test_idf_tools.py
@@ -13,3 +13,17 @@
 <!-- Either state release notes or write "No release notes" -->

 <!-- ## Breaking change notes --><!-- Optional -->
+
+<!-- ## Dynamic Pipeline Configuration
+```yaml
+Test Case Filters:
+    # Only run tests that match the given substring expression (modified files/components will be ignored):
+    # Please use a list of strings. 
+    # This will run the test cases filtered like `pytest -k "(<list_item_1>) or (<list_item_2>) or ...`
+    # The fast pipeline will fail at the final stage.
+    # For example:
+      - test_sdm and not sdmmc
+      - test_hello_world
+    # This example will include all tests containing 'test_hello_world' in the name,
+    # and include all tests containing 'test_sdm' but not 'sdmmc' in the name.
+``` --><!-- Optional -->
@@ -49,12 +49,13 @@
 [submodule "components/json/cJSON"]
 	path = components/json/cJSON
 	url = ../../DaveGamble/cJSON.git
-	sbom-version = 1.7.17
+	sbom-version = 1.7.18
 	sbom-cpe = cpe:2.3:a:cjson_project:cjson:{}:*:*:*:*:*:*:*
 	sbom-supplier = Person: Dave Gamble
 	sbom-url = https://github.com/DaveGamble/cJSON
 	sbom-description = Ultralightweight JSON parser in ANSI C
-	sbom-hash = 87d8f0961a01bf09bef98ff89bae9fdec42181ee
+	sbom-hash = acc76239bee01d8e9c858ae2cab296704e52d916
+	sbom-cve-exclude-list = CVE-2024-31755 Resolved in v1.7.18

 [submodule "components/mbedtls/mbedtls"]
 	path = components/mbedtls/mbedtls
@@ -53,7 +53,7 @@ repos:
              .*_pb2.py
          )$
  - repo: https://github.com/codespell-project/codespell
-    rev: v2.2.6
+    rev: v2.3.0
    hooks:
      - id: codespell
  - repo: local
@@ -103,10 +103,10 @@ repos:
        name: Check type annotations in python files
        entry: tools/ci/check_type_comments.py
        additional_dependencies:
-          - 'mypy==0.940'
-          - 'mypy-extensions==0.4.3'
-          - 'types-setuptools==57.4.14'
-          - 'types-PyYAML==0.1.9'
+          - 'mypy'
+          - 'mypy-extensions'
+          - 'types-setuptools'
+          - 'types-PyYAML'
          - 'types-requests'
        exclude: >
          (?x)^(
@@ -224,6 +224,11 @@ repos:
      name: shellcheck dash (export.sh)
      args: ['--shell', 'dash', '-x']
      files: 'export.sh'
+  - repo: https://github.com/espressif/esp-pwsh-check
+    rev: v1.0.1
+    hooks:
+    - id: check-powershell-scripts
+      stages: [manual]
  - repo: https://github.com/espressif/esp-idf-sbom.git
    rev: v0.13.0
    hooks:
@@ -236,6 +241,6 @@ repos:
        name: Lint rST files in docs folder using Sphinx Lint
        files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$
  - repo: https://github.com/espressif/esp-idf-kconfig.git
-    rev: v2.1.0
+    rev: v2.3.0
    hooks:
      - id: check-kconfig-files
@@ -96,7 +96,7 @@ if(CMAKE_C_COMPILER_ID MATCHES "Clang")
    list(APPEND compile_options "-Wno-pointer-bool-conversion")
    # mbedTLS md5.c triggers this warning in md5_test_buf (false positive)
    list(APPEND compile_options "-Wno-string-concatenation")
-    # multiple cases of implict convertions between unrelated enum types
+    # multiple cases of implicit conversions between unrelated enum types
    list(APPEND compile_options "-Wno-enum-conversion")
    # When IRAM_ATTR is specified both in function declaration and definition,
    # it produces different section names, since section names include __COUNTER__.
@@ -136,6 +136,10 @@ if(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE)
    list(APPEND compile_definitions "-DNDEBUG")
 endif()

+if(CONFIG_COMPILER_NO_MERGE_CONSTANTS)
+    list(APPEND compile_options "-fno-merge-constants")
+endif()
+
 if(CONFIG_COMPILER_STACK_CHECK_MODE_NORM)
    list(APPEND compile_options "-fstack-protector")
 elseif(CONFIG_COMPILER_STACK_CHECK_MODE_STRONG)
@@ -201,10 +205,18 @@ if(CONFIG_COMPILER_DISABLE_GCC13_WARNINGS)
                                    "-Wno-dangling-reference")
 endif()

+if(CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS)
+    if(NOT CMAKE_C_COMPILER_ID MATCHES "Clang")
+        idf_build_replace_option_from_property(COMPILE_OPTIONS "-Werror" "-Werror=all")
+    endif()
+endif()
+
 # GCC-specific options
 if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    list(APPEND compile_options "-fstrict-volatile-bitfields"
-                                )
+    list(APPEND compile_options "-fstrict-volatile-bitfields")
+    if(CONFIG_COMPILER_STATIC_ANALYZER)
+        list(APPEND compile_options "-fanalyzer")
+    endif()
 endif()

 if(CONFIG_ESP_SYSTEM_USE_EH_FRAME)
@@ -84,17 +84,18 @@ Supported since ESP-IDF v4.4.

 ### ESP32-C2 & ESP8684

-#### v1.0
+#### v1.0, v1.1

 Supported since ESP-IDF v5.0.

-#### v1.1
-
-To be added.
-
 #### v1.2

-To be added.
+| Release branch         | Recommended | Required |
+|------------------------|-------------|----------|
+| release/v5.0           | v5.0.7+     | v5.0     |
+| release/v5.1           | v5.1.4+     | v5.1     |
+| release/v5.2           | v5.2.2+     | v5.2     |
+| release/v5.3 and above | v5.3+       | v5.3     |

 ### ESP32-C6

@@ -84,17 +84,18 @@

 ### ESP32-C2 & ESP8684

-#### v1.0
+#### v1.0, v1.1

 从 ESP-IDF v5.0 开始支持。

-#### v1.1
-
-待更新。
-
 #### v1.2

-待更新。
+| 发布分支                | 推荐版本      | 需求版本  |
+|------------------------|-------------|----------|
+| release/v5.0           | v5.0.7+     | v5.0     |
+| release/v5.1           | v5.1.4+     | v5.1     |
+| release/v5.2           | v5.2.2+     | v5.1     |
+| release/v5.3 及以上     | v5.3+       | v5.3     |

 ### ESP32-C6

@@ -48,6 +48,10 @@ mainmenu "Espressif IoT Development Framework Configuration"
        bool
        default "y" if IDF_TOOLCHAIN="clang"

+    config IDF_TOOLCHAIN_GCC
+        bool
+        default "y" if IDF_TOOLCHAIN="gcc"
+
    config IDF_TARGET_ARCH_RISCV
        bool
        default "n"
@@ -75,10 +79,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
        string
        default "$IDF_INIT_VERSION"

-    config IDF_TARGET_LINUX
-        bool
-        default "y" if IDF_TARGET="linux"
-
    config IDF_TARGET_ESP32
        bool
        default "y" if IDF_TARGET="esp32"
@@ -119,28 +119,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV

-    # TODO: IDF-9197
-    choice IDF_TARGET_ESP32C5_VERSION
-        prompt "ESP32-C5 version"
-        depends on IDF_TARGET_ESP32C5
-        default IDF_TARGET_ESP32C5_MP_VERSION
-        help
-            ESP32-C5 will support two versions for a period.
-            This option is for internal use only.
-            Select the one that matches your chip model.
-
-        config IDF_TARGET_ESP32C5_BETA3_VERSION
-            bool
-            prompt "ESP32-C5 beta3"
-            select ESPTOOLPY_NO_STUB
-
-        config IDF_TARGET_ESP32C5_MP_VERSION
-            bool
-            prompt "ESP32-C5 MP"
-            select ESPTOOLPY_NO_STUB
-            select IDF_ENV_FPGA
-    endchoice
-
    config IDF_TARGET_ESP32P4
        bool
        default "y" if IDF_TARGET="esp32p4"
@@ -157,7 +135,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default "y" if IDF_TARGET="esp32c61"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_FPGA

    config IDF_TARGET_LINUX
        bool
@@ -173,8 +150,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default 0x000D if IDF_TARGET_ESP32C6
        default 0x0010 if IDF_TARGET_ESP32H2
        default 0x0012 if IDF_TARGET_ESP32P4
-        default 0x0011 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_BETA3_VERSION  # TODO: IDF-9197
-        default 0x0017 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_MP_VERSION     # TODO: IDF-9197
+        default 0x0017 if IDF_TARGET_ESP32C5
        default 0x0014 if IDF_TARGET_ESP32C61
        default 0xFFFF

@@ -533,6 +509,15 @@ mainmenu "Espressif IoT Development Framework Configuration"
            help
                Stack smashing protection.

+        config COMPILER_NO_MERGE_CONSTANTS
+            bool "Disable merging const sections"
+            depends on IDF_TOOLCHAIN_GCC
+            help
+                Disable merging identical constants (string/floating-point) across compilation units.
+                This helps in better size analysis of the application binary as the rodata section
+                distribution is more uniform across libraries. On downside, it may increase
+                the binary size and hence should be used during development phase only.
+
        config COMPILER_WARN_WRITE_STRINGS
            bool "Enable -Wwrite-strings warning flag"
            default "n"
@@ -559,6 +544,20 @@ mainmenu "Espressif IoT Development Framework Configuration"

                This option can be enabled for RISC-V targets only.

+        config COMPILER_DISABLE_DEFAULT_ERRORS
+            bool "Disable errors for default warnings"
+            default "y"
+            help
+                Enable this option if you do not want default warnings to be considered as errors,
+                especially when updating IDF.
+
+                This is a temporary flag that could help to allow upgrade while having
+                some time to address the warnings raised by those default warnings.
+                Alternatives are:
+                1) fix code (preferred),
+                2) remove specific warnings,
+                3) do not consider specific warnings as error.
+
        config COMPILER_DISABLE_GCC12_WARNINGS
            bool "Disable new warnings introduced in GCC 12"
            default "n"
@@ -607,6 +606,34 @@ mainmenu "Espressif IoT Development Framework Configuration"
            default "gcc" if COMPILER_RT_LIB_GCCLIB
            default "" if COMPILER_RT_LIB_HOST

+        choice COMPILER_ORPHAN_SECTIONS
+            prompt "Orphan sections handling"
+            default COMPILER_ORPHAN_SECTIONS_WARNING
+            depends on !IDF_TARGET_LINUX
+            help
+                If the linker finds orphan sections, it attempts to place orphan sections after sections of the same
+                attribute such as code vs data, loadable vs non-loadable, etc.
+                That means that orphan sections could placed between sections defined in IDF linker scripts.
+                This could lead to corruption of the binary image. Configure the linker action here.
+
+            config COMPILER_ORPHAN_SECTIONS_WARNING
+                bool "Place with warning"
+                help
+                    Places orphan sections without a warning message.
+
+            config COMPILER_ORPHAN_SECTIONS_PLACE
+                bool "Place silently"
+                help
+                    Places orphan sections without a warning/error message.
+        endchoice
+
+        config COMPILER_STATIC_ANALYZER
+            bool "Enable compiler static analyzer"
+            default "n"
+            depends on IDF_TOOLCHAIN_GCC
+            help
+                Enable compiler static analyzer. This may produce false-positive results and increases compile time.
+
    endmenu # Compiler Options

    menu "Component config"
@@ -15,17 +15,17 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li

 The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.

-|Chip         |          v4.4          |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
-|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
-|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
-|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
-|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
-|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |
+|Chip         |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
+|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
+|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
+|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
+|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
+|ESP32-C5     |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |

 [supported]: https://img.shields.io/badge/-supported-green "supported"
 [preview]: https://img.shields.io/badge/-preview-orange "preview"
@@ -15,17 +15,17 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux

 下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。

-|芯片         |          v4.4          |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
-|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
-|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
-|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
-|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/en/news/ESP32-P4)      |
-|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
+|芯片         |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
+|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
+|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
+|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
+|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) |
+|ESP32-C5     |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |

 [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
 [preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
@@ -122,7 +122,7 @@ ESP-IDF 中的子模块采用相对路径（[详见 .gitmodules 文件](.gitmodu

 * 最新版的文档：https://docs.espressif.com/projects/esp-idf/ ，该文档是由本仓库 [docs 目录](docs) 构建得到。

-* [初学者指南：主要概念和资源](https://www.bilibili.com/video/BV1114y1r7du/) 
+* [初学者指南：主要概念和资源](https://www.bilibili.com/video/BV1114y1r7du/)

 * 可以前往 [esp32.com 论坛](https://esp32.com/) 提问，挖掘社区资源。

@@ -14,6 +14,7 @@ menu "Application Level Tracing"

        config APPTRACE_DEST_NONE
            bool "None"
+
    endchoice

    config APPTRACE_DEST_UART
@@ -60,7 +61,7 @@ menu "Application Level Tracing"
    endchoice

    config APPTRACE_UART_TX_GPIO
-        int "UART TX on GPIO#"
+        int "UART TX on GPIO<num>"
        depends on APPTRACE_DEST_UART_NOUSB
        range 0 46
        default 12 if IDF_TARGET_ESP32
@@ -70,7 +71,7 @@ menu "Application Level Tracing"
            This GPIO is used for UART TX pin.

    config APPTRACE_UART_RX_GPIO
-        int "UART RX on GPIO#"
+        int "UART RX on GPIO<num>"
        depends on APPTRACE_DEST_UART_NOUSB
        range 0 46
        default 13 if IDF_TARGET_ESP32
@@ -213,7 +214,7 @@ menu "Application Level Tracing"
            depends on APPTRACE_SV_ENABLE
            default APPTRACE_SV_DEST_JTAG
            help
-                SystemView witt transfer data trough defined interface.
+                SystemView will transfer data through the defined interface.

            config APPTRACE_SV_DEST_JTAG
                bool "Data destination JTAG"
@@ -8,6 +8,6 @@ components/app_trace/test_apps:
    - driver
    - esp_hw_support
  disable:
-    - if: IDF_TARGET == "esp32c5"
+    - if: IDF_TARGET in ["esp32c5", "esp32c61"]
      temporary: true
-      reason: not support yet # TODO: [ESP32C5] IDF-8705
+      reason: not support yet # TODO: [ESP32C5] IDF-8705, [ESP32C61] IDF-9306
@@ -17,6 +17,7 @@
 #include "esp_image_format.h"
 #include "esp_secure_boot.h"
 #include "esp_flash_encrypt.h"
+#include "spi_flash_mmap.h"
 #include "sdkconfig.h"

 #include "esp_ota_ops.h"
@@ -116,6 +116,8 @@ esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp
 *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
 *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
 *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
+ *    - ESP_ERR_INVALID_SIZE: if write would go out of bounds of the partition
+ *    - or one of error codes from lower-level flash driver.
 */
 esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);

@@ -2,6 +2,6 @@

 components/app_update/test_apps:
  disable:
-    - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4", "esp32c5"]
+    - if: IDF_TARGET in ["esp32c5", "esp32c61"]
      temporary: true
-      reason: target esp32c6, esp32h2, esp32p4, esp32c5 is not supported yet # TODO: IDF-8068, [ESP32C5] IDF-8638
+      reason: target esp32c5 is not supported yet  # TODO: [ESP32C5] IDF-8640, IDF-10317, [ESP32C61] IDF-9245
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
@@ -841,8 +841,7 @@ static void test_flow6(void)
 // 3 Stage: run OTA0    -> check it -> erase OTA_DATA for next tests    -> PASS
 TEST_CASE_MULTIPLE_STAGES("Switching between factory, OTA0 using esp_ota_write_with_offset", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", start_test, test_flow6, test_flow6);

-//IDF-5145
-TEST_CASE("Test bootloader_common_get_sha256_of_partition returns ESP_ERR_IMAGE_INVALID when image is ivalid", "[partitions]")
+TEST_CASE("Test bootloader_common_get_sha256_of_partition returns ESP_ERR_IMAGE_INVALID when image is invalid", "[partitions]")
 {
    const esp_partition_t *cur_app = esp_ota_get_running_partition();
    ESP_LOGI(TAG, "copy current app to next part");
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 import re

@@ -19,14 +19,7 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:


@pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2', 'esp32p4'], reason='c6/h2/p4 support TBD')  # TODO: IDF-8959
+@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep')  # TODO: [ESP32C5] IDF-8640, IDF-10317
@pytest.mark.generic
 def test_app_update(dut: Dut) -> None:
-    extra_data = dut.parse_test_menu()
-    for test_case in extra_data:
-        if test_case.type != 'multi_stage':
-            dut.write(str(test_case.index))
-        else:
-            run_multiple_stages(dut, test_case.index, len(test_case.subcases))
-        dut.expect_unity_test_output(timeout=90)
-        dut.expect_exact("Enter next test, or 'enter' to see menu")
+    dut.run_all_single_board_cases(timeout=90)
@@ -14,5 +14,9 @@ CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_two_ota.csv"

 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_OFFSET=0x18000
+
+CONFIG_BOOTLOADER_FACTORY_RESET=y
+CONFIG_BOOTLOADER_APP_TEST=y
+CONFIG_BOOTLOADER_DATA_FACTORY_RESET=""
 CONFIG_BOOTLOADER_HOLD_TIME_GPIO=2
 CONFIG_BOOTLOADER_OTA_DATA_ERASE=y
@@ -1,7 +1,3 @@
 CONFIG_IDF_TARGET="esp32"
-CONFIG_BOOTLOADER_FACTORY_RESET=y
-CONFIG_BOOTLOADER_APP_TEST=y
-CONFIG_BOOTLOADER_DATA_FACTORY_RESET=""
 CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=32
 CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
-CONFIG_BOOTLOADER_HOLD_TIME_GPIO=2
@@ -3,3 +3,4 @@ CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_two_ota_2m.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_two_ota_2m.csv"
 CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
@@ -1,2 +1,3 @@
 CONFIG_IDF_TARGET="esp32c3"
 CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32c6"
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32h2"
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=22
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32p4"
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=19
@@ -1,2 +1,3 @@
 CONFIG_IDF_TARGET="esp32s2"
 CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32s3"
+CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=18
+CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4
@@ -0,0 +1,34 @@
+menu "Log"
+
+    choice BOOTLOADER_LOG_LEVEL
+        bool "Bootloader log verbosity"
+        default BOOTLOADER_LOG_LEVEL_INFO
+        help
+            Specify how much output to see in bootloader logs.
+
+        config BOOTLOADER_LOG_LEVEL_NONE
+            bool "No output"
+        config BOOTLOADER_LOG_LEVEL_ERROR
+            bool "Error"
+        config BOOTLOADER_LOG_LEVEL_WARN
+            bool "Warning"
+        config BOOTLOADER_LOG_LEVEL_INFO
+            bool "Info"
+        config BOOTLOADER_LOG_LEVEL_DEBUG
+            bool "Debug"
+        config BOOTLOADER_LOG_LEVEL_VERBOSE
+            bool "Verbose"
+    endchoice
+
+    config BOOTLOADER_LOG_LEVEL
+        int
+        default 0 if BOOTLOADER_LOG_LEVEL_NONE
+        default 1 if BOOTLOADER_LOG_LEVEL_ERROR
+        default 2 if BOOTLOADER_LOG_LEVEL_WARN
+        default 3 if BOOTLOADER_LOG_LEVEL_INFO
+        default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
+        default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
+
+    orsource "Kconfig.log.format"
+
+endmenu
@@ -0,0 +1,38 @@
+menu "Format"
+
+    config BOOTLOADER_LOG_COLORS
+        bool "Color"
+        default y
+        help
+            Use ANSI terminal colors in log output
+            Enable ANSI terminal color codes.
+            In order to view these, your terminal program must support ANSI color codes.
+
+    choice BOOTLOADER_LOG_TIMESTAMP_SOURCE
+        prompt "Timestamp"
+        default BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS
+        help
+            Choose what sort of timestamp is displayed in the log output:
+
+            - "None" - The log will only contain the actual log messages themselves
+              without any time-related information. Avoiding timestamps can help conserve
+              processing power and memory. It might useful when you
+              perform log analysis or debugging, sometimes it's more straightforward
+              to work with logs that lack timestamps, especially if the time of occurrence
+              is not critical for understanding the issues.
+              "I log_test: info message"
+
+            - "Milliseconds since boot" is calculated from the RTOS tick count multiplied
+              by the tick period. This time will reset after a software reboot.
+              "I (112500) log_test: info message"
+
+        config BOOTLOADER_LOG_TIMESTAMP_SOURCE_NONE
+            bool "None"
+            depends on NO_SYMBOL  # hide it now, turn it on final MR
+
+        config BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS
+            bool "Milliseconds Since Boot"
+
+    endchoice # BOOTLOADER_LOG_TIMESTAMP_SOURCE
+
+endmenu
@@ -38,34 +38,7 @@ menu "Bootloader config"

    endchoice

-    choice BOOTLOADER_LOG_LEVEL
-        bool "Bootloader log verbosity"
-        default BOOTLOADER_LOG_LEVEL_INFO
-        help
-            Specify how much output to see in bootloader logs.
-
-        config BOOTLOADER_LOG_LEVEL_NONE
-            bool "No output"
-        config BOOTLOADER_LOG_LEVEL_ERROR
-            bool "Error"
-        config BOOTLOADER_LOG_LEVEL_WARN
-            bool "Warning"
-        config BOOTLOADER_LOG_LEVEL_INFO
-            bool "Info"
-        config BOOTLOADER_LOG_LEVEL_DEBUG
-            bool "Debug"
-        config BOOTLOADER_LOG_LEVEL_VERBOSE
-            bool "Verbose"
-    endchoice
-
-    config BOOTLOADER_LOG_LEVEL
-        int
-        default 0 if BOOTLOADER_LOG_LEVEL_NONE
-        default 1 if BOOTLOADER_LOG_LEVEL_ERROR
-        default 2 if BOOTLOADER_LOG_LEVEL_WARN
-        default 3 if BOOTLOADER_LOG_LEVEL_INFO
-        default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
-        default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
+    orsource "Kconfig.log"

    menu "Serial Flash Configurations"
        config BOOTLOADER_SPI_CUSTOM_WP_PIN
@@ -127,9 +100,15 @@ menu "Bootloader config"
            help
                This is a helper config for 32bits address flash. Invisible for users.

+        config BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH
+            bool
+            default y if BOOTLOADER_FLASH_NEEDS_32BIT_FEAT && SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
+            help
+                This is a helper config for 32bits address quad flash. Invisible for users.
+
        config BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
            bool "Enable cache access to 32-bit-address (over 16MB) range of SPI Flash (READ DOCS FIRST)"
-            depends on BOOTLOADER_FLASH_NEEDS_32BIT_FEAT && IDF_TARGET_ESP32S3 && IDF_EXPERIMENTAL_FEATURES
+            depends on BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH && IDF_EXPERIMENTAL_FEATURES
            default n
            help
                Enabling this option allows the CPU to access 32-bit-address flash beyond 16M range.
@@ -166,7 +145,7 @@ menu "Bootloader config"

    config BOOTLOADER_FACTORY_RESET
        bool "GPIO triggers factory reset"
-        default N
+        default n
        select BOOTLOADER_RESERVE_RTC_MEM if SOC_RTC_FAST_MEM_SUPPORTED
        help
            Allows to reset the device to factory settings:
@@ -221,7 +200,7 @@ menu "Bootloader config"

    config BOOTLOADER_APP_TEST
        bool "GPIO triggers boot from test app partition"
-        default N
+        default n
        depends on !BOOTLOADER_APP_ANTI_ROLLBACK
        help
            Allows to run the test app from "TEST" partition.
@@ -269,6 +248,8 @@ menu "Bootloader config"
            Protects the unmapped memory regions of the entire address space from unintended accesses.
            This will ensure that an exception will be triggered whenever the CPU performs a memory
            operation on unmapped regions of the address space.
+            NOTE: Disabling this config on some targets (ESP32-C6, ESP32-H2, ESP32-C5) would not generate
+            an exception when reading from or writing to 0x0.

    config BOOTLOADER_WDT_ENABLE
        bool "Use RTC watchdog in start code"
@@ -381,9 +362,9 @@ menu "Bootloader config"
        # options, allowing to turn on "allow insecure options" and have secure boot with
        # "skip validation when existing deep sleep". Keeping this to avoid a breaking change,
        # but - as noted in help - it invalidates the integrity of Secure Boot checks
-        depends on SOC_RTC_FAST_MEM_SUPPORTED && ((SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT)
+        depends on ((SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT)
        default n
-        select BOOTLOADER_RESERVE_RTC_MEM
+        select BOOTLOADER_RESERVE_RTC_MEM if SOC_RTC_FAST_MEM_SUPPORTED
        help
            This option disables the normal validation of an image coming out of
            deep sleep (checksums, SHA256, and signature). This is a trade-off
@@ -782,7 +763,7 @@ menu "Security features"
    config SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
        bool "Enable Aggressive key revoke strategy"
        depends on SECURE_BOOT && SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
-        default N
+        default n
        help
            If this option is set, ROM bootloader will revoke the public key digest burned in efuse block
            if it fails to verify the signature of software bootloader with it.
@@ -798,7 +779,7 @@ menu "Security features"
    config SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT
        bool "Flash bootloader along with other artifacts when using the default flash command"
        depends on SECURE_BOOT_V2_ENABLED && SECURE_BOOT_BUILD_SIGNED_BINARIES
-        default N
+        default n
        help
            When Secure Boot V2 is enabled, by default the bootloader is not flashed along with other artifacts
            like the application and the partition table images, i.e. bootloader has to be separately flashed
@@ -838,7 +819,7 @@ menu "Security features"
    config SECURE_BOOT_INSECURE
        bool "Allow potentially insecure options"
        depends on SECURE_BOOT
-        default N
+        default n
        help
            You can disable some of the default protections offered by secure boot, in order to enable testing or a
            custom combination of security features.
@@ -849,7 +830,7 @@ menu "Security features"

    config SECURE_FLASH_ENC_ENABLED
        bool "Enable flash encryption on boot (READ DOCS FIRST)"
-        default N
+        default n
        select SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE
        help
            If this option is set, flash contents will be encrypted by the bootloader on first boot.
@@ -936,7 +917,7 @@ menu "Security features"
        config SECURE_BOOT_ALLOW_ROM_BASIC
            bool "Leave ROM BASIC Interpreter available on reset"
            depends on (SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT) && IDF_TARGET_ESP32
-            default N
+            default n
            help
                By default, the BASIC ROM Console starts on reset if no valid bootloader is
                read from the flash.
@@ -951,7 +932,7 @@ menu "Security features"
            bool "Allow JTAG Debugging"
            depends on SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
            select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
-            default N
+            default n
            help
                If not set (default), the bootloader will permanently disable JTAG (across entire chip) on first boot
                when either secure boot or flash encryption is enabled.
@@ -998,7 +979,7 @@ menu "Security features"
        config SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS
            bool "Leave unused digest slots available (not revoke)"
            depends on SECURE_BOOT_INSECURE && SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
-            default N
+            default n
            help
                If not set (default), during startup in the app all unused digest slots will be revoked.
                To revoke unused slot will be called esp_efuse_set_digest_revoke(num_digest) for each digest.
@@ -1017,7 +998,7 @@ menu "Security features"
            bool "Leave UART bootloader encryption enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
            select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
-            default N
+            default n
            help
                If not set (default), the bootloader will permanently disable UART bootloader encryption access on
                first boot. If set, the UART bootloader will still be able to access hardware encryption.
@@ -1027,7 +1008,7 @@ menu "Security features"
        config SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC
            bool "Leave UART bootloader decryption enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && IDF_TARGET_ESP32
-            default N
+            default n
            help
                If not set (default), the bootloader will permanently disable UART bootloader decryption access on
                first boot. If set, the UART bootloader will still be able to access hardware decryption.
@@ -1039,7 +1020,7 @@ menu "Security features"
            bool "Leave UART bootloader flash cache enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && \
                (IDF_TARGET_ESP32 || SOC_EFUSE_DIS_DOWNLOAD_ICACHE || SOC_EFUSE_DIS_DOWNLOAD_DCACHE) # NOERROR
-            default N
+            default n
            select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
            help
                If not set (default), the bootloader will permanently disable UART bootloader flash cache access on
@@ -1050,7 +1031,7 @@ menu "Security features"
        config SECURE_FLASH_REQUIRE_ALREADY_ENABLED
            bool "Require flash encryption to be already enabled"
            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
-            default N
+            default n
            help
                If not set (default), and flash encryption is not yet enabled in eFuses, the 2nd stage bootloader
                will enable flash encryption: generate the flash encryption key and program eFuses.
@@ -30,12 +30,6 @@ idf_build_get_property(project_dir PROJECT_DIR)
 if(CONFIG_SECURE_SIGNED_APPS)
    add_custom_target(gen_secure_boot_keys)

-    if(CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
-        set(secure_apps_signing_version "1")
-    elseif(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME)
-        set(secure_apps_signing_version "2")
-    endif()
-
    if(CONFIG_SECURE_BOOT_V1_ENABLED)
        # Check that the configuration is sane
        if((CONFIG_SECURE_BOOTLOADER_REFLASHABLE AND CONFIG_SECURE_BOOTLOADER_ONE_TIME_FLASH) OR
@@ -65,11 +59,10 @@ if(CONFIG_SECURE_SIGNED_APPS)
            # If the signing key is not found, create a phony gen_secure_boot_signing_key target that
            # fails the build. fail_at_build_time causes a cmake run next time
            # (to pick up a new signing key if one exists, etc.)
-            if(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME)
+            if(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
                fail_at_build_time(gen_secure_boot_signing_key
                    "Secure Boot Signing Key ${CONFIG_SECURE_BOOT_SIGNING_KEY} does not exist. Generate using:"
-                    "\tespsecure.py generate_signing_key --version ${secure_apps_signing_version} \
-                    ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
+                    "\tidf.py secure-generate-signing-key ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
            else()
                if(CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_192_BITS)
                    set(scheme "ecdsa192")
@@ -78,8 +71,7 @@ if(CONFIG_SECURE_SIGNED_APPS)
                endif()
                fail_at_build_time(gen_secure_boot_signing_key
                    "Secure Boot Signing Key ${CONFIG_SECURE_BOOT_SIGNING_KEY} does not exist. Generate using:"
-                    "\tespsecure.py generate_signing_key --version ${secure_apps_signing_version} \
-                    --scheme ${scheme} ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
+                    "\tidf.py secure-generate-signing-key --scheme ${scheme} ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
            endif()
        else()
            add_custom_target(gen_secure_boot_signing_key)
@@ -124,7 +116,7 @@ idf_build_get_property(sdkconfig SDKCONFIG)
 idf_build_get_property(python PYTHON)
 idf_build_get_property(extra_cmake_args EXTRA_CMAKE_ARGS)

-# We cannot pass lists are a parameter to the external project without modifying the ';' spearator
+# We cannot pass lists are a parameter to the external project without modifying the ';' separator
 string(REPLACE ";" "|" BOOTLOADER_IGNORE_EXTRA_COMPONENT "${BOOTLOADER_IGNORE_EXTRA_COMPONENT}")

 externalproject_add(bootloader
@@ -1,13 +1,7 @@
 idf_component_register(SRCS "bootloader_start.c"
                    REQUIRES bootloader bootloader_support)

-if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
-    set(target_folder "esp32c5/beta3")
-elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
-    set(target_folder "esp32c5/mp")
-else()
-    set(target_folder "${target}")
-endif()
+set(target_folder "${target}")

 idf_build_get_property(target IDF_TARGET)
 set(scripts "ld/${target_folder}/bootloader.ld")
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -119,6 +119,7 @@ SECTIONS

  .dram0.data : ALIGN(0x10)
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -144,6 +145,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /*  C++ constructor and destructor tables, properly ordered:  */
@@ -208,12 +210,55 @@ SECTIONS
   */
  .xt.prop 0 :
  {
-    KEEP (*(.xt.prop .gnu.linkonce.prop.*))
+    KEEP (*(.xt.prop .xt.prop.* .gnu.linkonce.prop.*))
  }

  .xt.lit 0 :
  {
-    KEEP (*(.xt.lit .gnu.linkonce.p.*))
+    KEEP (*(.xt.lit .xt.lit.* .gnu.linkonce.p.*))
  }

+  .xtensa.info 0: { *(.xtensa.info) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
 }
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -140,6 +140,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -165,6 +166,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -218,6 +220,57 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
 }

 /**
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -140,6 +140,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -165,6 +166,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -218,6 +220,58 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
 }


@@ -1,256 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/** Simplified memory map for the bootloader.
- *  Make sure the bootloader can load into main memory without overwriting itself.
- *
- *  TODO: [ESP32C5] IDF-9358 Check this file whether need update for MP ROM
- *  ESP32-C5 ROM static data usage is as follows:
- *  - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
- *  - 0x4087ebc0 - 0x40880000: ROM .bss and .data (not easily reclaimable)
- *
- *  The 2nd stage bootloader can take space up to the end of ROM shared
- *  buffers area (0x4087cbc0).
- */
-
-/* We consider 0x4087cbc0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
- * and work out iram_seg and iram_loader_seg addresses from there, backwards.
- */
-
-/* These lengths can be adjusted, if necessary: */
-bootloader_usable_dram_end = 0x4087cbc0;
-bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
-bootloader_dram_seg_len = 0x5000;
-bootloader_iram_loader_seg_len = 0x7000;
-bootloader_iram_seg_len = 0x2200;
-
-/* Start of the lower region is determined by region size and the end of the higher region */
-bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
-bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
-bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
-bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
-
-MEMORY
-{
-  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
-  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
-  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
-}
-
-/* The app may use RAM for static allocations up to the start of iram_loader_seg.
- * If you have changed something above and this assert fails:
- * 1. Check what the new value of bootloader_iram_loader_seg start is.
- * 2. Update the value in this assert.
- * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
- */
-ASSERT(bootloader_iram_loader_seg_start == 0x4086EBC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
-
-/* Default entry point: */
-ENTRY(call_start_cpu0);
-
-SECTIONS
-{
-
-  .iram_loader.text :
-  {
-    . = ALIGN (16);
-    _loader_text_start = ABSOLUTE(.);
-    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
-    *liblog.a:(.literal .text .literal.* .text.*)
-    /* we use either libgcc or compiler-rt, so put similar entries for them here */
-    *libgcc.a:(.literal .text .literal.* .text.*)
-    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
-    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
-    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
-    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
-    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
-    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
-    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
-    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
-    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
-    *libefuse.a:*.*(.literal .text .literal.* .text.*)
-    *(.fini.literal)
-    *(.fini)
-    *(.gnu.version)
-    _loader_text_end = ABSOLUTE(.);
-  } > iram_loader_seg
-
-  .iram.text :
-  {
-    . = ALIGN (16);
-    *(.entry.text)
-    *(.init.literal)
-    *(.init)
-  } > iram_seg
-
-
-  /* Shared RAM */
-  .dram0.bss (NOLOAD) :
-  {
-    . = ALIGN (8);
-    _dram_start = ABSOLUTE(.);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } > dram_seg
-
-  .dram0.bootdesc : ALIGN(0x10)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
-  } > dram_seg
-
-  .dram0.data :
-  {
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.gnu.linkonce.s2.*)
-    *(.jcr)
-    _data_end = ABSOLUTE(.);
-  } > dram_seg
-
-  .dram0.rodata :
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    *(.sdata2 .sdata2.* .srodata .srodata.*)
-    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
-    *(.xt_except_table)
-    *(.gcc_except_table)
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    *(.eh_frame)
-    . = (. + 3) & ~ 3;
-    /* C++ constructor and destructor tables, properly ordered: */
-    __init_array_start = ABSOLUTE(.);
-    KEEP (*crtbegin.*(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    __init_array_end = ABSOLUTE(.);
-    KEEP (*crtbegin.*(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    _rodata_end = ABSOLUTE(.);
-    /* Literals are also RO data. */
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-    . = ALIGN(4);
-    _dram_end = ABSOLUTE(.);
-  } > dram_seg
-
-  .iram.text :
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.iram .iram.*) /* catch stray IRAM_ATTR */
-    *(.fini.literal)
-    *(.fini)
-    *(.gnu.version)
-
-    /** CPU will try to prefetch up to 16 bytes of
-      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
-      * safe access to up to 16 bytes after the last real instruction, add
-      * dummy bytes to ensure this
-      */
-    . += 16;
-
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } > iram_seg
-
-}
-
-
-/**
- *  Appendix: Memory Usage of ROM bootloader
- *
- * 0x4086b2b8 ------------------> _dram0_0_start
- *            |               |
- *            |               |
- *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
- *            |               |
- *            |               |
- * 0x4087cbc0 ------------------> __stack_sentry
- *            |               |
- *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
- *            |               |
- * 0x4087ebc0 ------------------> __stack (pro cpu)
- *            |               |
- *            |               |
- *            |               |   3. Shared memory only used in startup code or nonos/early boot*
- *            |               |      (can be freed when IDF runs)
- *            |               |
- *            |               |
- * 0x4087fb14 ------------------> _dram0_rtos_reserved_start
- *            |               |
- *            |               |
- *            |               |   4. Shared memory used in startup code and when IDF runs
- *            |               |
- *            |               |
- * 0x4087fefc ------------------> _dram0_rtos_reserved_end
- *            |               |
- * 0x4087ffb8 ------------------> _data_start_interface
- *            |               |
- *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
- *            |               |
- * 0x40880000 ------------------> _data_end_interface
- */
@@ -138,6 +138,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -163,6 +164,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -216,6 +218,58 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
 }


@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -138,6 +138,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -163,6 +164,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -216,6 +218,58 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
 }


@@ -7,20 +7,20 @@
 *  Make sure the bootloader can load into main memory without overwriting itself.
 *
 *  ESP32-C61 ROM static data usage is as follows:
- *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
- *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *  - 0x4083ea70 - 0x4084ca70: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4084ca70 - 0x4084ea70: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4084ea70 - 0x40850000: ROM .bss and .data (not easily reclaimable)
 *
 *  The 2nd stage bootloader can take space up to the end of ROM shared
- *  buffers area (0x4087c610).
+ *  buffers area (0x4084ca70).
 */

-/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+/* We consider 0x4084ca70 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
 * and work out iram_seg and iram_loader_seg addresses from there, backwards.
 */

 /* These lengths can be adjusted, if necessary: */
-bootloader_usable_dram_end = 0x4084c9f0;
+bootloader_usable_dram_end = 0x4084ca70;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
 bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
@@ -45,7 +45,7 @@ MEMORY
 * 2. Update the value in this assert.
 * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c61/memory.ld.in to the same value.
 */
-ASSERT(bootloader_iram_loader_seg_start == 0x4083E9F0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+ASSERT(bootloader_iram_loader_seg_start == 0x4083ea70, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");

 /* Default entry point: */
 ENTRY(call_start_cpu0);
@@ -138,6 +138,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -163,6 +164,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -216,40 +218,92 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
 }


-/** TODO: [ESP32C61] IDF-9405, update after rom freeze
+/**
 *  Appendix: Memory Usage of ROM bootloader
 *
- * 0x4086ad08 ------------------> _dram0_0_start
+ * 0x4083ea70 ------------------> _dram0_0_start
 *            |               |
 *            |               |
 *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
 *            |               |
 *            |               |
- * 0x4087c610 ------------------> __stack_sentry
+ * 0x4084ca70 ------------------> __stack_sentry
 *            |               |
 *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
 *            |               |
- * 0x4087e610 ------------------> __stack (pro cpu)
+ * 0x4084ea70 ------------------> __stack (pro cpu)
 *            |               |
 *            |               |
 *            |               |   3. Shared memory only used in startup code or nonos/early boot*
 *            |               |      (can be freed when IDF runs)
 *            |               |
 *            |               |
- * 0x4087f564 ------------------> _dram0_rtos_reserved_start
+ * 0x4084f5d0 ------------------> _dram0_rtos_reserved_start
 *            |               |
 *            |               |
 *            |               |   4. Shared memory used in startup code and when IDF runs
 *            |               |
 *            |               |
- * 0x4087fab0 ------------------> _dram0_rtos_reserved_end
+ * 0x4084fc58 ------------------> _dram0_rtos_reserved_end
 *            |               |
- * 0x4087fce8 ------------------> _data_start_interface
+ * 0x4084fc6c ------------------> _data_start_interface
 *            |               |
 *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
 *            |               |
- * 0x40880000 ------------------> _data_end_interface
+ * 0x40850000 ------------------> _data_end_interface
 */
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -138,7 +138,7 @@ SECTIONS

  .dram0.data :
  {
-    _data_start = ABSOLUTE(.);
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -164,6 +164,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -217,6 +218,58 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
 }

 /**
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -131,9 +131,15 @@ SECTIONS
    _bss_end = ABSOLUTE(.);
  } > dram_seg

-  .dram0.data :
+  .dram0.bootdesc : ALIGN(0x10)
  {
    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -159,6 +165,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -212,6 +219,58 @@ SECTIONS
    _etext = .;
  } > iram_seg

+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
 }


@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -108,6 +108,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -133,6 +134,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /*  C++ constructor and destructor tables, properly ordered:  */
@@ -205,4 +207,48 @@ SECTIONS
    KEEP (*(.xt.lit .gnu.linkonce.p.*))
  }

+  .xtensa.info 0: { *(.xtensa.info) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
 }
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -142,6 +142,7 @@ SECTIONS

  .dram0.data :
  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
@@ -167,6 +168,7 @@ SECTIONS
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
+    *(.eh_frame_hdr)
    *(.eh_frame)
    . = (. + 3) & ~ 3;
    /* C++ constructor and destructor tables, properly ordered: */
@@ -239,6 +241,50 @@ SECTIONS
    KEEP (*(.xt.lit .gnu.linkonce.p.*))
  }

+  .xtensa.info 0: { *(.xtensa.info) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
 }

 /**
@@ -15,7 +15,7 @@ set(srcs
    "src/secure_boot.c"
    )

-if(NOT CONFIG_IDF_ENV_FPGA)
+if(NOT CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING)
    # For FPGA ENV, bootloader_random implementation is implemented in `bootloader_random.c`
    list(APPEND srcs "src/bootloader_random_${IDF_TARGET}.c")
 endif()
@@ -13,6 +13,9 @@
 #include "hal/efuse_ll.h"
 #include "hal/efuse_hal.h"

+#ifndef BOOTLOADER_BUILD
+#include "spi_flash_mmap.h"
+#endif
 #include "hal/spi_flash_ll.h"
 #include "rom/spi_flash.h"
 #if CONFIG_IDF_TARGET_ESP32
@@ -133,6 +136,8 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)

 #if CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/opi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/opi_flash.h"
 #endif
 static const char *TAG = "bootloader_flash";

@@ -14,11 +14,8 @@
 #include "esp32c5/rom/efuse.h"
 #include "soc/gpio_periph.h"
 #include "soc/io_mux_reg.h"
-// TODO: IDF-9197
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
 #include "esp_rom_efuse.h"
 #include "soc/efuse_reg.h"
-#endif
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -31,7 +28,7 @@
 #include "hal/mmu_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
-#include "hal/clk_tree_ll.h"
+#include "hal/mspi_timing_tuning_ll.h"

 void bootloader_flash_update_id()
 {
@@ -207,19 +204,11 @@ static void bootloader_spi_flash_resume(void)

 esp_err_t bootloader_init_spi_flash(void)
 {
-// TODO: IDF-9197
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // On ESP32C5, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
-    // Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
-    // 80MHz after the switch. PLL = 480MHz, so divider is 6.
-    clk_ll_mspi_fast_set_hs_divider(6);
-#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    /* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
-       need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
-       and we need to check flash freq before restart as well */
-    clk_ll_mspi_fast_set_divider(1);
-    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
-#endif
+    // Set source mspi pll clock as 80M in bootloader stage.
+    // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
+    // in this stage, set divider as 6
+    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    mspi_ll_fast_set_hs_divider(6);

    bootloader_init_flash_configure();
    bootloader_spi_flash_resume();
@@ -22,7 +22,7 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"

-void bootloader_flash_update_id()
+void IRAM_ATTR bootloader_flash_update_id()
 {
    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
    chip->device_id = bootloader_read_flash_id();
@@ -99,6 +99,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
    case ESP_IMAGE_FLASH_SIZE_16MB:
        size = 16;
        break;
+    case ESP_IMAGE_FLASH_SIZE_32MB:
+        size = 32;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_64MB:
+        size = 64;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_128MB:
+        size = 128;
+        break;
    default:
        size = 2;
    }
@@ -175,6 +184,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
    case ESP_IMAGE_FLASH_SIZE_16MB:
        str = "16MB";
        break;
+    case ESP_IMAGE_FLASH_SIZE_32MB:
+        str = "32MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_64MB:
+        str = "64MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_128MB:
+        str = "128MB";
+        break;
    default:
        str = "2MB";
        break;
@@ -203,6 +221,9 @@ esp_err_t bootloader_init_spi_flash(void)
 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
    bootloader_enable_qio_mode();
 #endif
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
+    bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
+#endif

    print_flash_info(&bootloader_image_hdr);

@@ -271,6 +292,10 @@ void bootloader_flash_hardware_init(void)
    bootloader_spi_flash_resume();
    bootloader_flash_unlock();

+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
+    bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
+#endif
+
    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
    update_flash_config(&hdr);
    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -10,6 +10,7 @@
 #include <stdbool.h>

 #include "soc/soc.h"
+#include "soc/ext_mem_defs.h"
 #include "soc/soc_caps.h"
 #include "sdkconfig.h"
 #include "esp_attr.h"
@@ -179,6 +180,31 @@ inline static bool esp_ptr_in_tcm(const void *p) {
 #endif  //#if SOC_MEM_TCM_SUPPORTED

 /** End of the common section that has to be in sync with esp_memory_utils.h **/
+
+/**
+ * @brief Check if the pointer is in PSRAM vaddr space
+ *
+ * @note This function is only used when in bootloader, where the PSRAM isn't initialised.
+ *       This function simply check if the pointer is the in the PSRAM vaddr space.
+ *       The PSRAM vaddr space is not always the same as the actual PSRAM vaddr range used in APP
+ *
+ * @param p pointer
+ *
+ * @return true: is in PSRAM; false: not in PSRAM
+ */
+__attribute__((always_inline))
+inline static bool esp_ptr_in_extram(const void *p) {
+    bool valid = false;
+#if SOC_IRAM_PSRAM_ADDRESS_LOW
+    valid |= ((intptr_t)p >= SOC_IRAM_PSRAM_ADDRESS_LOW && (intptr_t)p < SOC_IRAM_PSRAM_ADDRESS_HIGH);
+#endif
+
+#if SOC_DRAM_PSRAM_ADDRESS_LOW
+    valid |= ((intptr_t)p >= SOC_DRAM_PSRAM_ADDRESS_LOW && (intptr_t)p < SOC_DRAM_PSRAM_ADDRESS_HIGH);
+#endif
+    return valid;
+}
+
 /** Don't add new functions below **/

 #ifdef __cplusplus
@@ -8,8 +8,9 @@
 #include <inttypes.h>
 #include "esp_assert.h"

-// TODO: IDF-9197
-#include "sdkconfig.h"
+#ifdef __cplusplus
+extern "C" {
+#endif

 /**
 * @brief ESP chip ID
@@ -24,11 +25,7 @@ typedef enum {
    ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
    ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
    ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
-    ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
-#endif
+    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 */
    ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;

@@ -120,3 +117,7 @@ typedef struct {
 } esp_image_segment_header_t;

 #define ESP_IMAGE_MAX_SEGMENTS 16           /*!< Max count of segments in the image. */
+
+#ifdef __cplusplus
+}
+#endif
@@ -9,9 +9,6 @@
 #include "esp_attr.h"
 #include "esp_err.h"
 #include "soc/soc_caps.h"
-#ifndef BOOTLOADER_BUILD
-#include "spi_flash_mmap.h"
-#endif
 #include "hal/efuse_ll.h"
 #include "sdkconfig.h"

@@ -31,6 +31,10 @@
 #include "esp32h2/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C5
+#include "esp32c5/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C61
+#include "esp32c61/rom/secure_boot.h"
 #endif

 #ifdef CONFIG_SECURE_BOOT_V1_ENABLED
@@ -61,6 +65,42 @@ extern "C" {
 #include "esp_efuse_table.h"
 #endif

+/**
+ * @brief   Secure Boot Signature Block Version field
+ */
+typedef enum {
+    ESP_SECURE_BOOT_V1_ECDSA = 0,           /*!< Secure Boot v1 */
+    ESP_SECURE_BOOT_V2_RSA   = 2,           /*!< Secure Boot v2 with RSA key */
+    ESP_SECURE_BOOT_V2_ECDSA = 3,           /*!< Secure Boot v2 with ECDSA key */
+} esp_secure_boot_sig_scheme_t;
+
+#if CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME
+#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V1_ECDSA
+#elif CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME
+#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V2_RSA
+#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME
+#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V2_ECDSA
+#endif
+
+#if CONFIG_SECURE_BOOT || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT
+/** @brief Get the selected secure boot scheme key type
+ *
+ * @return key type for the selected secure boot scheme
+ */
+static inline const char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme)
+{
+    switch (scheme) {
+        case ESP_SECURE_BOOT_V2_RSA:
+            return "RSA";
+        case ESP_SECURE_BOOT_V1_ECDSA:
+        case ESP_SECURE_BOOT_V2_ECDSA:
+            return "ECDSA";
+        default:
+            return "Unknown";
+    }
+}
+#endif
+
 /** @brief Is secure boot currently enabled in hardware?
 *
 * This means that the ROM bootloader code will only boot
@@ -1,11 +1,15 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #pragma once

+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /**
 * @brief Initialize console output (UART or USB)
 */
@@ -21,3 +25,7 @@ void bootloader_console_deinit(void);
 * Only defined if USB CDC is used for console output.
 */
 void bootloader_console_write_char_usb(char c);
+
+#ifdef __cplusplus
+}
+#endif
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -8,6 +8,10 @@
 #include "esp_err.h"
 #include "esp_image_format.h"

+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /**@{*/
 /**
 * @brief labels from bootloader linker script: bootloader.ld
@@ -49,3 +53,7 @@ void bootloader_print_banner(void);
 *          ESP_FAIL - If the setting is not successful.
 */
 esp_err_t bootloader_init(void);
+
+#ifdef __cplusplus
+}
+#endif
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -16,6 +16,10 @@
 #include <stdlib.h>
 #include "esp_err.h"

+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef void *bootloader_sha256_handle_t;

 bootloader_sha256_handle_t bootloader_sha256_start(void);
@@ -23,3 +27,7 @@ bootloader_sha256_handle_t bootloader_sha256_start(void);
 void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len);

 void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest);
+
+#ifdef __cplusplus
+}
+#endif
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -25,6 +25,14 @@
 #include "esp32h2/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C5
+#include "esp32c5/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C61
+#include "esp32c61/rom/secure_boot.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
 #endif

 #if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
@@ -45,3 +53,7 @@ esp_err_t esp_secure_boot_verify_rsa_signature_block(const ets_secure_boot_signa
 #endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */

 #endif
+
+#ifdef __cplusplus
+}
+#endif
@@ -1,10 +1,15 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 #pragma once

+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /**
 * @brief Configure analog super WDT reset
 *
@@ -12,16 +17,13 @@
 */
 void bootloader_ana_super_wdt_reset_config(bool enable);

-/**
- * @brief Configure analog brownout reset
- *
- * @param enable Boolean to enable or disable brownout reset
- */
-void bootloader_ana_bod_reset_config(bool enable);
-
 /**
 * @brief Configure analog clock glitch reset
 *
 * @param enable Boolean to enable or disable clock glitch reset
 */
 void bootloader_ana_clock_glitch_reset_config(bool enable);
+
+#ifdef __cplusplus
+}
+#endif
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -9,6 +9,11 @@
 #include "esp_image_format.h"
 #include "bootloader_config.h"

+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /**
 * @brief Load partition table.
 *
@@ -16,7 +21,7 @@
 * OTA data partition, factory app partition, and test app partition.
 *
 * @param[out] bs Bootloader state structure used to save read data.
- * @return        Return true if the partition table was succesfully loaded and MD5 checksum is valid.
+ * @return        Return true if the partition table was successfully loaded and MD5 checksum is valid.
 */
 bool bootloader_utility_load_partition_table(bootloader_state_t* bs);

@@ -51,9 +56,14 @@ __attribute__((__noreturn__)) void bootloader_utility_load_boot_image(const boot
 /**
 * @brief Load that application which was worked before we go to the deep sleep.
 *
+ * If chip supports the RTC memory:
 * Checks the reboot reason if it is the deep sleep and has a valid partition in the RTC memory
 * then try to load the application which was worked before we go to the deep sleep.
 *
+ * If chip does not support the RTC memory:
+ * Checks the reboot reason if it is the deep sleep then the partition table is read
+ * to select and load an application which was worked before we go to the deep sleep.
+ *
 */
 void bootloader_utility_load_boot_image_from_deep_sleep(void);
 #endif
@@ -120,3 +130,7 @@ void bootloader_debug_buffer(const void *buffer, size_t length, const char *labe
 * @return ESP_OK if secure boot digest is generated successfully.
 */
 esp_err_t bootloader_sha256_flash_contents(uint32_t flash_offset, uint32_t len, uint8_t *digest);
+
+#ifdef __cplusplus
+}
+#endif
@@ -53,32 +53,29 @@ __attribute__((weak)) void bootloader_clock_configure(void)

        clk_cfg.cpu_freq_mhz = cpu_freq_mhz;

-#if CONFIG_IDF_TARGET_ESP32C5
-        // TODO: [ESP32C5] IDF-9009 Check whether SOC_RTC_SLOW_CLK_SRC_RC_SLOW can be used on C5 MP
-        // RC150K can't do calibrate on ESP32C5MPW so not use it
-        clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
-#else
        // Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
        // RTC_SLOW clock source will be switched according to Kconfig selection at application startup
        clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
        if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
            clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
        }
-#endif

-//TODO: [ESP32C61] IDF-9274, basic rtc support
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
-        // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
-        // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
-        clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
-#else
        // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader
        // RTC_FAST clock source will be switched to RC_FAST at application startup
        clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
        if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
        }
+
+#if CONFIG_IDF_TARGET_ESP32C6
+        if (efuse_hal_chip_revision() == 0) {
+            // Some of ESP32C6-ECO0 chip's SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue,
+            // which will cause the chip to be unable to capture the reset reason when it is reset.
+            // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
+            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
+        }
 #endif
+
        rtc_clk_init(clk_cfg);
    }

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -37,8 +37,8 @@ esp_comm_gpio_hold_t bootloader_common_check_long_hold_gpio(uint32_t num_pin, ui
 esp_comm_gpio_hold_t bootloader_common_check_long_hold_gpio_level(uint32_t num_pin, uint32_t delay_sec, bool level)
 {
    esp_rom_gpio_pad_select_gpio(num_pin);
-    if (GPIO_PIN_MUX_REG[num_pin]) {
-        PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[num_pin]);
+    if (((1ULL << num_pin) & SOC_GPIO_VALID_GPIO_MASK) != 0) {
+        gpio_ll_input_enable(&GPIO, num_pin);
    }
    esp_rom_gpio_pad_pullup_only(num_pin);
    uint32_t tm_start = esp_log_early_timestamp();
@@ -13,7 +13,7 @@
 #include "soc/gpio_periph.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/rtc.h"
-#include "hal/gpio_hal.h"
+#include "hal/gpio_ll.h"
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/usb/cdc_acm.h"
 #include "esp32s2/rom/usb/usb_common.h"
@@ -25,9 +25,6 @@
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_caps.h"
-#if CONFIG_IDF_TARGET_ESP32C5
-#include "soc/pcr_reg.h"
-#endif

 #ifdef CONFIG_ESP_CONSOLE_NONE
 void bootloader_console_init(void)
@@ -63,17 +60,17 @@ void bootloader_console_init(void)
            uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM ||
            uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) {
        // Change default UART pins back to GPIOs
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[UART_NUM_0_RXD_DIRECT_GPIO_NUM], PIN_FUNC_GPIO);
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[UART_NUM_0_TXD_DIRECT_GPIO_NUM], PIN_FUNC_GPIO);
+        gpio_ll_func_sel(&GPIO, UART_NUM_0_RXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO);
+        gpio_ll_func_sel(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO);
        // Route GPIO signals to/from pins
        const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX);
        const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX);
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[uart_rx_gpio], PIN_FUNC_GPIO);
-        PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[uart_rx_gpio]);
+        gpio_ll_func_sel(&GPIO, uart_rx_gpio, PIN_FUNC_GPIO);
+        gpio_ll_input_enable(&GPIO, uart_rx_gpio);
        esp_rom_gpio_pad_pullup_only(uart_rx_gpio);
        esp_rom_gpio_connect_out_signal(uart_tx_gpio, tx_idx, 0, 0);
        esp_rom_gpio_connect_in_signal(uart_rx_gpio, rx_idx, 0);
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[uart_tx_gpio], PIN_FUNC_GPIO);
+        gpio_ll_func_sel(&GPIO, uart_tx_gpio, PIN_FUNC_GPIO);
        // Enable the peripheral
        uart_ll_enable_bus_clock(uart_num, true);
        uart_ll_reset_register(uart_num);
@@ -88,13 +85,6 @@ void bootloader_console_init(void)
 #if ESP_ROM_UART_CLK_IS_XTAL
    clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
 #endif
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-#if CONFIG_IDF_ENV_FPGA
-    clock_hz = CONFIG_XTAL_FREQ * MHZ;
-#else
-    clock_hz = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_CLK_XTAL_FREQ) * MHZ;
-#endif  // CONFIG_IDF_ENV_FPGA
-#endif  // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
    esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 }
 #endif // CONFIG_ESP_CONSOLE_UART
@@ -14,7 +14,6 @@
 #include "bootloader_random.h"
 #include "bootloader_clock.h"
 #include "bootloader_common.h"
-#include "esp_flash_encrypt.h"
 #include "esp_cpu.h"
 #include "soc/rtc.h"
 #include "hal/wdt_hal.h"
@@ -16,12 +16,12 @@
 #include "hal/apm_hal.h"
 #endif

-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-8615 Remove the workaround when APM supported on C5!
+#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
 #include "soc/hp_apm_reg.h"
 #include "soc/lp_apm_reg.h"
-#include "soc/lp_apm0_reg.h"
 #endif

+
 void bootloader_init_mem(void)
 {

@@ -33,18 +33,20 @@ void bootloader_init_mem(void)
     * So, at boot disabling these filters. They will enable as per the
     * use case by TEE initialization code.
     */
+#ifdef SOC_APM_CTRL_FILTER_SUPPORTED
    apm_hal_apm_ctrl_filter_enable_all(false);
 #endif
+#endif

-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-8615 Remove the workaround when APM supported on C5!
+#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
    // disable apm filter
    REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
-    REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
    REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
 #endif

+
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
    // protect memory region
-    esp_cpu_configure_region_protection();  // TODO: [ESP32C5] IDF-8833 PSRAM support write
+    esp_cpu_configure_region_protection();
 #endif
 }
@@ -83,10 +83,10 @@
 }
 #endif // BOOTLOADER_BUILD

-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING
 static void s_non_functional(const char *func)
 {
-    ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func);
+    ESP_EARLY_LOGW("rand", "%s non-functional as RNG has not been supported yet", func);
 }

 void bootloader_random_enable()
@@ -98,4 +98,4 @@ void bootloader_random_disable()
 {
    s_non_functional(__func__);
 }
-#endif // CONFIG_IDF_ENV_FPGA
+#endif // CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING
@@ -4,20 +4,99 @@
 * SPDX-License-Identifier: Apache-2.0
 */
 #include "sdkconfig.h"
+#include "bootloader_random.h"
 #include "soc/soc.h"
 #include "soc/pcr_reg.h"
+#include "soc/apb_saradc_reg.h"
 #include "soc/pmu_reg.h"
 #include "hal/regi2c_ctrl.h"
+#include "soc/lpperi_reg.h"
+#include "soc/regi2c_saradc.h"
 #include "esp_log.h"

+static const uint32_t SAR2_CHANNEL = 9;
+static const uint32_t SAR1_CHANNEL = 7;
+static const uint32_t PATTERN_BIT_WIDTH = 6;
+static const uint32_t SAR1_ATTEN = 3;
+static const uint32_t SAR2_ATTEN = 3;
+
 void bootloader_random_enable(void)
 {
-// TODO: [ESP32C5] IDF-8626, IDF-9197
-    ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
+    // pull SAR ADC out of reset
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+
+    // enable SAR ADC APB clock
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
+
+    // pull APB register out of reset
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
+    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
+
+    // enable ADC_CTRL_CLK (SAR ADC function clock)
+    REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
+
+    // select XTAL clock (40 MHz) source for ADC_CTRL_CLK
+    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0); // 0: XTAL; 1: 80M(from bbpll); 2. FOSC
+
+    // set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
+    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
+
+    // some magic register poke from the digital team
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
+    // Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 1);
+
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x66);
+
+    // create patterns and set them in pattern table
+    uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
+    uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
+    uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
+    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
+
+    // set pattern length  (APB_SARADC_SARADC_SAR_PATT_LEN counts from 0)
+    REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
+
+    REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
+
+    // set timer expiry (timer is ADC_CTRL_CLK)
+    REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
+
+    // enable timer
+    REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+    CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
 }

 void bootloader_random_disable(void)
 {
-// TODO: [ESP32C5] IDF-8626, IDF-9197
-    ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
+    // disable timer
+    REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+
+    // Write reset value of this register
+    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
+
+    // Revert ADC I2C configuration and initial voltage source setting
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
+
+    // disable ADC_CTRL_CLK (SAR ADC function clock)
+    REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
+
+    // Set PCR_SARADC_CONF_REG to initial state
+    REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
 }
@@ -53,7 +53,7 @@ void bootloader_random_enable(void)

    // create patterns and set them in pattern table
    uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
-    uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
+    uint32_t pattern_two = (SAR2_CHANNEL << 2) | SAR1_ATTEN; // we want channel 9 with max attenuation
    uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);

@@ -88,9 +88,6 @@ void bootloader_random_disable(void)
    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);

-    // Revert PMU_RF_PWC_REG to it's initial value
-    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-
    // disable ADC_CTRL_CLK (SAR ADC function clock)
    REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);

@@ -0,0 +1,101 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "bootloader_random.h"
+#include "soc/soc.h"
+#include "soc/pcr_reg.h"
+#include "soc/apb_saradc_reg.h"
+#include "soc/pmu_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
+#include "esp_log.h"
+
+static const uint32_t SAR2_CHANNEL = 9;
+static const uint32_t SAR1_CHANNEL = 7;
+static const uint32_t PATTERN_BIT_WIDTH = 6;
+static const uint32_t SAR1_ATTEN = 3;
+static const uint32_t SAR2_ATTEN = 3;
+
+void bootloader_random_enable(void)
+{
+    // pull SAR ADC out of reset
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+
+    // enable SAR ADC APB clock
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
+
+    // pull APB register out of reset
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
+    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
+
+    // enable ADC_CTRL_CLK (SAR ADC function clock)
+    REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
+
+    // select XTAL clock (40 MHz) source for ADC_CTRL_CLK
+    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
+
+    // set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
+    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
+
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
+    // Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR   , 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
+
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
+
+    // create patterns and set them in pattern table
+    uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
+    uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
+    uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
+    REG_WRITE(SARADC_SAR_PATT_TAB1_REG, pattern_table);
+
+    // set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
+    REG_SET_FIELD(SARADC_CTRL_REG, SARADC_SAR_PATT_LEN, 1);
+
+    // Same as in C3
+    REG_SET_FIELD(SARADC_CTRL_REG, SARADC_SAR_CLK_DIV, 15);
+
+    // set timer expiry (timer is ADC_CTRL_CLK)
+    REG_SET_FIELD(SARADC_CTRL2_REG, SARADC_TIMER_TARGET, 200);
+
+    // enable timer
+    REG_SET_BIT(SARADC_CTRL2_REG, SARADC_TIMER_EN);
+}
+
+void bootloader_random_disable(void)
+{
+    // disable timer
+    REG_CLR_BIT(SARADC_CTRL2_REG, SARADC_TIMER_EN);
+
+    // Write reset value of this register
+    REG_WRITE(SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
+
+    // Revert ADC I2C configuration and initial voltage source setting
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
+
+    // disable ADC_CTRL_CLK (SAR ADC function clock)
+    REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
+
+    // Set PCR_SARADC_CONF_REG to initial state
+    REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
+}
@@ -9,7 +9,7 @@
 #include "soc/pmu_reg.h"
 #include "soc/regi2c_saradc.h"
 #include "soc/hp_sys_clkrst_reg.h"
-#include "soc/rtcadc_reg.h"
+#include "soc/lp_adc_reg.h"
 #include "esp_private/regi2c_ctrl.h"
 #include "esp_rom_regi2c.h"

@@ -25,6 +25,7 @@
 #include "soc/rtc_periph.h"
 #include "soc/timer_periph.h"
 #include "hal/mmu_hal.h"
+#include "hal/mmu_ll.h"
 #include "hal/cache_types.h"
 #include "hal/cache_ll.h"
 #include "hal/cache_hal.h"
@@ -34,6 +35,9 @@
 #include "esp_app_desc.h"
 #include "esp_secure_boot.h"
 #include "esp_flash_encrypt.h"
+#ifndef BOOTLOADER_BUILD
+#include "spi_flash_mmap.h"
+#endif
 #include "esp_flash_partitions.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_random.h"
@@ -43,6 +47,7 @@
 #include "bootloader_sha.h"
 #include "bootloader_console.h"
 #include "bootloader_soc.h"
+#include "bootloader_memory_utils.h"
 #include "esp_efuse.h"
 #include "esp_fault.h"

@@ -456,15 +461,33 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index)
 void bootloader_utility_load_boot_image_from_deep_sleep(void)
 {
    if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) {
+#if SOC_RTC_FAST_MEM_SUPPORTED
        esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition();
-        if (partition != NULL) {
+        esp_image_metadata_t image_data;
+        if (partition != NULL && bootloader_load_image_no_verify(partition, &image_data) == ESP_OK) {
+            ESP_LOGI(TAG, "Fast booting app from partition at offset 0x%"PRIx32, partition->offset);
+            bootloader_common_update_rtc_retain_mem(NULL, true);
+            load_image(&image_data);
+        }
+#else // !SOC_RTC_FAST_MEM_SUPPORTED
+        bootloader_state_t bs = {0};
+        if (bootloader_utility_load_partition_table(&bs)) {
+            int index_of_last_loaded_app = FACTORY_INDEX;
+            esp_ota_select_entry_t otadata[2];
+            if (bs.ota_info.size && bootloader_common_read_otadata(&bs.ota_info, otadata) == ESP_OK) {
+                int active_otadata = bootloader_common_get_active_otadata(otadata);
+                if (active_otadata != -1) {
+                    index_of_last_loaded_app = (otadata[active_otadata].ota_seq - 1) % bs.app_count;
+                }
+            }
+            esp_partition_pos_t partition = index_to_partition(&bs, index_of_last_loaded_app);
            esp_image_metadata_t image_data;
-            if (bootloader_load_image_no_verify(partition, &image_data) == ESP_OK) {
-                ESP_LOGI(TAG, "Fast booting app from partition at offset 0x%"PRIx32, partition->offset);
-                bootloader_common_update_rtc_retain_mem(NULL, true);
+            if (partition.size && bootloader_load_image_no_verify(&partition, &image_data) == ESP_OK) {
+                ESP_LOGI(TAG, "Fast booting app from partition at offset 0x%"PRIx32, partition.offset);
                load_image(&image_data);
            }
        }
+#endif // !SOC_RTC_FAST_MEM_SUPPORTED
        ESP_LOGE(TAG, "Fast booting is not successful");
        ESP_LOGI(TAG, "Try to load an app as usual with all validations");
    }
@@ -715,10 +738,20 @@ static void unpack_load_app(const esp_image_metadata_t *data)
    // Find DROM & IROM addresses, to configure MMU mappings
    for (int i = 0; i < data->image.segment_count; i++) {
        const esp_image_segment_header_t *header = &data->segments[i];
+        bool text_or_rodata = false;
+
        //`SOC_DROM_LOW` and `SOC_DROM_HIGH` are the same as `SOC_IROM_LOW` and `SOC_IROM_HIGH`, reasons are in above `note`
        if (header->load_addr >= SOC_DROM_LOW && header->load_addr < SOC_DROM_HIGH) {
+            text_or_rodata = true;
+        }
+#if SOC_MMU_PER_EXT_MEM_TARGET
+        if (header->load_addr >= SOC_EXTRAM_LOW && header->load_addr < SOC_EXTRAM_HIGH) {
+            text_or_rodata = true;
+        }
+#endif
+        if (text_or_rodata) {
            /**
-             * D/I are shared, but there should not be a third segment on flash
+             * D/I are shared, but there should not be a third segment on flash/psram
             */
            assert(rom_index < 2);
            rom_addr[rom_index] = data->segment_data[i];
@@ -785,6 +818,20 @@ static void unpack_load_app(const esp_image_metadata_t *data)
 }
 #endif  //#if SOC_MMU_DI_VADDR_SHARED

+//unused for esp32
+__attribute__((unused))
+static bool s_flash_seg_needs_map(uint32_t vaddr)
+{
+#if SOC_MMU_PER_EXT_MEM_TARGET
+    //For these chips, segments on PSRAM will be mapped in app
+    bool is_psram = esp_ptr_in_extram((void *)vaddr);
+    return !is_psram;
+#else
+    //For these chips, segments on Flash always need to be mapped
+    return true;
+#endif
+}
+
 static void set_cache_and_start_app(
    uint32_t drom_addr,
    uint32_t drom_load_addr,
@@ -822,8 +869,13 @@ static void set_cache_and_start_app(
    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
 #else
    uint32_t actual_mapped_len = 0;
-    mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
-    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
+    if (s_flash_seg_needs_map(drom_load_addr_aligned)) {
+        mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
+        ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
+    }
+    //we use the MMU_LL_END_DROM_ENTRY_ID mmu entry as a map page for app to find the boot partition
+    mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_LL_END_DROM_ENTRY_VADDR, drom_addr_aligned, CONFIG_MMU_PAGE_SIZE, &actual_mapped_len);
+    ESP_EARLY_LOGV(TAG, "mapped one page of the rodata, from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
 #endif

    //-----------------------MAP IROM--------------------------
@@ -840,8 +892,10 @@ static void set_cache_and_start_app(
    ESP_LOGV(TAG, "rc=%d", rc);
    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
 #else
-    mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
-    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
+    if (s_flash_seg_needs_map(irom_load_addr_aligned)) {
+        mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
+        ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
+    }
 #endif

    //----------------------Enable corresponding buses----------------
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -37,6 +37,7 @@
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
 #include "hal/rwdt_ll.h"
+#include "hal/brownout_ll.h"

 static const char *TAG = "boot.esp32c2";

@@ -81,8 +82,8 @@ static inline void bootloader_ana_reset_config(void)
 {
    //Enable super WDT reset.
    bootloader_ana_super_wdt_reset_config(true);
-    //Enable BOD reset
-    bootloader_ana_bod_reset_config(true);
+    //Enable BOD reset (mode1)
+    brownout_ll_ana_reset_enable(true);
 }

 esp_err_t bootloader_init(void)
@@ -138,7 +139,7 @@ esp_err_t bootloader_init(void)
    }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM

-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
    bootloader_check_wdt_reset();
    // config WDT
    bootloader_config_wdt();
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -18,17 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
    }
 }

-void bootloader_ana_bod_reset_config(bool enable)
-{
-    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
-
-    if (enable) {
-        REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
-    } else {
-        REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
-    }
-}
-
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -42,6 +42,7 @@
 #include "hal/cache_hal.h"
 #include "hal/efuse_hal.h"
 #include "hal/rwdt_ll.h"
+#include "hal/brownout_ll.h"

 static const char *TAG = "boot.esp32c3";

@@ -106,18 +107,18 @@ static inline void bootloader_ana_reset_config(void)
        case 0:
        case 1:
            //Disable BOD and GLITCH reset
-            bootloader_ana_bod_reset_config(false);
+            brownout_ll_ana_reset_enable(false);
            bootloader_ana_clock_glitch_reset_config(false);
            break;
        case 2:
            //Enable BOD reset. Disable GLITCH reset
-            bootloader_ana_bod_reset_config(true);
+            brownout_ll_ana_reset_enable(true);
            bootloader_ana_clock_glitch_reset_config(false);
            break;
        case 3:
        default:
            //Enable BOD, and GLITCH reset
-            bootloader_ana_bod_reset_config(true);
+            brownout_ll_ana_reset_enable(true);
            bootloader_ana_clock_glitch_reset_config(true);
            break;
    }
@@ -182,7 +183,7 @@ esp_err_t bootloader_init(void)
    }
 #endif  //#if !CONFIG_APP_BUILD_TYPE_RAM

-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
    bootloader_check_wdt_reset();
    // config WDT
    bootloader_config_wdt();
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -18,17 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
    }
 }

-void bootloader_ana_bod_reset_config(bool enable)
-{
-    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
-
-    if (enable) {
-        REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
-    } else {
-        REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
-    }
-}
-
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
@@ -38,13 +38,10 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
-#include "hal/clk_tree_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "modem/modem_lpcon_reg.h"
-#endif
+#include "hal/regi2c_ctrl_ll.h"

 static const char *TAG = "boot.esp32c5";

@@ -87,11 +84,9 @@ static void bootloader_super_wdt_auto_feed(void)

 static inline void bootloader_hardware_init(void)
 {
-    /* Enable analog i2c master clock */
-#if SOC_MODEM_CLOCK_SUPPORTED
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
-#endif
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
 }

 static inline void bootloader_ana_reset_config(void)
@@ -100,8 +95,8 @@ static inline void bootloader_ana_reset_config(void)
    //Enable super WDT reset.
    // bootloader_ana_super_wdt_reset_config(true);
    // TODO: [ESP32C5] IDF-8647
-    //Enable BOD reset
-    // bootloader_ana_bod_reset_config(true);
+    //Enable BOD reset TODO: [ESP32C5] IDF-8667
+    // brownout_ll_ana_reset_enable(true);
 }

 esp_err_t bootloader_init(void)
@@ -163,7 +158,7 @@ esp_err_t bootloader_init(void)
    }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM

-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
    bootloader_check_wdt_reset();
    // config WDT
    bootloader_config_wdt();
@@ -16,12 +16,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
    ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
 }

-void bootloader_ana_bod_reset_config(bool enable)
-{
-     // TODO: [ESP32C5] IDF-8667
-    ESP_EARLY_LOGW("bootloader", "bootloader_ana_bod_reset_config() has not been implemented on C5 yet");
-}
-
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
@@ -23,13 +23,12 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
 #endif

-// TODO: [ESP32C5] IDF-8623 check if the following code is still supported
-// #ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
-//     ESP_LOGI(TAG, "Disable UART bootloader cache...");
-//     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-// #else
-//     ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
-// #endif
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
+    ESP_LOGI(TAG, "Disable UART bootloader cache...");
+    esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
+#endif

 #ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
    ESP_LOGI(TAG, "Disable JTAG...");
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -43,7 +43,8 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/brownout_ll.h"

 static const char *TAG = "boot.esp32c6";

@@ -95,17 +96,16 @@ static inline void bootloader_hardware_init(void)
    esp_rom_spiflash_fix_dummylen(1, 1);
 #endif

-    /* Enable analog i2c master clock */
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
 }

 static inline void bootloader_ana_reset_config(void)
 {
    //Enable super WDT reset.
    bootloader_ana_super_wdt_reset_config(true);
-    //Enable BOD reset
-    bootloader_ana_bod_reset_config(true);
+    //Enable BOD mode1 hardware reset
+    brownout_ll_ana_reset_enable(true);
 }

 esp_err_t bootloader_init(void)
@@ -167,7 +167,7 @@ esp_err_t bootloader_init(void)
    }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM

-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
    bootloader_check_wdt_reset();
    // config WDT
    bootloader_config_wdt();
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -15,17 +15,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
 }

-void bootloader_ana_bod_reset_config(bool enable)
-{
-    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
-
-    if (enable) {
-        REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
-    } else {
-        REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
-    }
-}
-
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
@@ -39,10 +39,10 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
-#include "hal/clk_tree_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
+#include "hal/regi2c_ctrl_ll.h"

 static const char *TAG = "boot.esp32c61";

@@ -85,29 +85,17 @@ static void bootloader_super_wdt_auto_feed(void)

 static inline void bootloader_hardware_init(void)
 {
-    // In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here
-#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM
-    clk_ll_mspi_fast_set_hs_divider(6);
-    esp_rom_spiflash_config_clk(1, 0);
-    esp_rom_spiflash_config_clk(1, 1);
-    esp_rom_spiflash_fix_dummylen(0, 1);
-    esp_rom_spiflash_fix_dummylen(1, 1);
-#endif
-
-//TODO: [ESP32C61] IDF-9276
-#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-    ESP_EARLY_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
-#else
-    ESP_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
-#endif
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
 }

 static inline void bootloader_ana_reset_config(void)
 {
    //Enable super WDT reset.
    bootloader_ana_super_wdt_reset_config(true);
-    //Enable BOD reset
-    bootloader_ana_bod_reset_config(true);
+    //Enable BOD reset TODO: IDF-9254 BOD support
+    // brownout_ll_ana_reset_enable(true);
 }

 esp_err_t bootloader_init(void)
@@ -18,18 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
 }

-void bootloader_ana_bod_reset_config(bool enable)
-{
-    // lp_analog_peri_reg.h updated, now following registers
-    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
-
-    if (enable) {
-        REG_SET_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
-    } else {
-        REG_CLR_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
-    }
-}
-
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "secure_boot";
+
+esp_err_t esp_secure_boot_enable_secure_features(void)
+{
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Enabling Security download mode...");
+    esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not enable Security download mode...");
+        return err;
+    }
+#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Disable ROM Download mode...");
+    esp_err_t err = esp_efuse_disable_rom_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not disable ROM Download mode...");
+        return err;
+    }
+#else
+    ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable hardware & software JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+    // TODO in IDF-10694
+    // esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
+
+#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
+    bool rd_dis_now = true;
+#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
+    /* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
+       when Flash Encryption is being enabled */
+    rd_dis_now = esp_flash_encryption_enabled();
+#endif
+    if (rd_dis_now) {
+        ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
+        esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+    }
+#else
+    ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
+#endif
+
+    return ESP_OK;
+}
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -31,7 +31,6 @@
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/regi2c_lp_bias.h"
 #include "soc/regi2c_bias.h"
-#include "modem/modem_lpcon_reg.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"
@@ -43,7 +42,8 @@
 #include "soc/lp_wdt_reg.h"
 #include "soc/pmu_reg.h"
 #include "hal/efuse_hal.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/brownout_ll.h"

 static const char *TAG = "boot.esp32h2";

@@ -89,16 +89,17 @@ static inline void bootloader_hardware_init(void)
    /* Disable RF pll by default */
    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
-    /* Enable analog i2c master clock */
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
 }

 static inline void bootloader_ana_reset_config(void)
 {
    //Enable super WDT reset.
    bootloader_ana_super_wdt_reset_config(true);
-    //Enable BOD reset
-    bootloader_ana_bod_reset_config(true);
+    //Enable BOD reset (mode1)
+    brownout_ll_ana_reset_enable(true);
 }

 esp_err_t bootloader_init(void)
@@ -160,7 +161,7 @@ esp_err_t bootloader_init(void)
    }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM

-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
    bootloader_check_wdt_reset();
    // config WDT
    bootloader_config_wdt();
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -13,17 +13,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
 }

-void bootloader_ana_bod_reset_config(bool enable)
-{
-    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
-
-    if (enable) {
-        REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
-    } else {
-        REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
-    }
-}
-
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -29,6 +29,7 @@
 #include "bootloader_flash_config.h"
 #include "bootloader_mem.h"
 #include "esp_private/regi2c_ctrl.h"
+#include "soc/chip_revision.h"
 #include "soc/regi2c_lp_bias.h"
 #include "soc/regi2c_bias.h"
 #include "bootloader_console.h"
@@ -40,11 +41,15 @@
 #include "hal/cache_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/lpwdt_ll.h"
+#include "hal/spimem_flash_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "soc/regi2c_syspll.h"
 #include "soc/regi2c_cpll.h"
 #include "soc/regi2c_bias.h"
+#include "esp_private/periph_ctrl.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/brownout_ll.h"

 static const char *TAG = "boot.esp32p4";

@@ -89,25 +94,35 @@ static void bootloader_super_wdt_auto_feed(void)

 static inline void bootloader_hardware_init(void)
 {
-    // regi2c is enabled by default on ESP32P4, do nothing
+    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();

-    // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
-    // And we are fixing SPLL to be 480MHz at all runtime
-    // Suppose to fix the issue on ECO1, will check when chip comes back
-    // TODO: IDF-8939
-    REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
-    REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
-    esp_rom_delay_us(100);
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
+        // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
+        // And we are fixing SPLL to be 480MHz after app is up
+        REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
+        REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
+        esp_rom_delay_us(100);
+    }
    REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
    REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
+
+    // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
+    if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
+        spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
+        spimem_ctrlr_ll_set_core_clock(0, 6);
+    }
 }

 static inline void bootloader_ana_reset_config(void)
 {
    //Enable super WDT reset.
    bootloader_ana_super_wdt_reset_config(true);
-    //Enable BOD reset
-    bootloader_ana_bod_reset_config(true);
+    //Enable BOD reset (mode1)
+    brownout_ll_ana_reset_enable(true);
 }

 esp_err_t bootloader_init(void)
@@ -170,7 +185,7 @@ esp_err_t bootloader_init(void)
    }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM

-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
    bootloader_check_wdt_reset();
    // config WDT
    bootloader_config_wdt();
--- a/Show More
+++ b/Show More